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Jie Yang43250dd2009-02-18 17:24:15 -08001/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_HW_H_
23#define _ATL1C_HW_H_
24
25#include <linux/types.h>
26#include <linux/mii.h>
27
28struct atl1c_adapter;
29struct atl1c_hw;
30
31/* function prototype */
32void atl1c_phy_disable(struct atl1c_hw *hw);
33void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
34int atl1c_phy_reset(struct atl1c_hw *hw);
35int atl1c_read_mac_addr(struct atl1c_hw *hw);
36int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
37u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
38void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
39int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
40int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
41bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
42int atl1c_phy_init(struct atl1c_hw *hw);
43int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
44int atl1c_restart_autoneg(struct atl1c_hw *hw);
Jie Yang8f574b32010-06-01 00:28:12 -070045int atl1c_phy_power_saving(struct atl1c_hw *hw);
Jie Yang43250dd2009-02-18 17:24:15 -080046/* register definition */
47#define REG_DEVICE_CAP 0x5C
48#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
49#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
50
51#define REG_DEVICE_CTRL 0x60
52#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
53#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
54#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
56
57#define REG_LINK_CTRL 0x68
58#define LINK_CTRL_L0S_EN 0x01
59#define LINK_CTRL_L1_EN 0x02
Luis R. Rodriguez496c1852010-02-16 15:16:45 -080060#define LINK_CTRL_EXT_SYNC 0x80
Jie Yang43250dd2009-02-18 17:24:15 -080061
62#define REG_VPD_CAP 0x6C
63#define VPD_CAP_ID_MASK 0xff
64#define VPD_CAP_ID_SHIFT 0
65#define VPD_CAP_NEXT_PTR_MASK 0xFF
66#define VPD_CAP_NEXT_PTR_SHIFT 8
67#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
68#define VPD_CAP_VPD_ADDR_SHIFT 16
69#define VPD_CAP_VPD_FLAG 0x80000000
70
71#define REG_VPD_DATA 0x70
72
73#define REG_PCIE_UC_SEVERITY 0x10C
74#define PCIE_UC_SERVRITY_TRN 0x00000001
75#define PCIE_UC_SERVRITY_DLP 0x00000010
76#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
77#define PCIE_UC_SERVRITY_FCP 0x00002000
78#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
79#define PCIE_UC_SERVRITY_CA 0x00008000
80#define PCIE_UC_SERVRITY_UC 0x00010000
81#define PCIE_UC_SERVRITY_ROV 0x00020000
82#define PCIE_UC_SERVRITY_MLFP 0x00040000
83#define PCIE_UC_SERVRITY_ECRC 0x00080000
84#define PCIE_UC_SERVRITY_UR 0x00100000
85
86#define REG_DEV_SERIALNUM_CTRL 0x200
87#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
88#define REG_DEV_MAC_SEL_SHIFT 0
89#define REG_DEV_SERIAL_NUM_EN_MASK 0x1
90#define REG_DEV_SERIAL_NUM_EN_SHIFT 1
91
92#define REG_TWSI_CTRL 0x218
93#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
94#define TWSI_CTRL_LD_OFFSET_SHIFT 0
95#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
96#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
97#define TWSI_CTRL_SW_LDSTART 0x800
98#define TWSI_CTRL_HW_LDSTART 0x1000
99#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
100#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
101#define TWSI_CTRL_LD_EXIST 0x400000
102#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
103#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
104#define TWSI_CTRL_FREQ_SEL_100K 0
105#define TWSI_CTRL_FREQ_SEL_200K 1
106#define TWSI_CTRL_FREQ_SEL_300K 2
107#define TWSI_CTRL_FREQ_SEL_400K 3
108#define TWSI_CTRL_SMB_SLV_ADDR
109#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
110#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
111
112
113#define REG_PCIE_DEV_MISC_CTRL 0x21C
114#define PCIE_DEV_MISC_EXT_PIPE 0x2
115#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
116#define PCIE_DEV_MISC_SPIROM_EXIST 0x4
117#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
118#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
119
120#define REG_PCIE_PHYMISC 0x1000
121#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
122
Jie Yang8f574b32010-06-01 00:28:12 -0700123#define REG_PCIE_PHYMISC2 0x1004
124#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x3
125#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
126#define PCIE_PHYMISC2_SERDES_TH_MASK 0x3
127#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
128
Jie Yang43250dd2009-02-18 17:24:15 -0800129#define REG_TWSI_DEBUG 0x1108
130#define TWSI_DEBUG_DEV_EXIST 0x20000000
131
132#define REG_EEPROM_CTRL 0x12C0
133#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
134#define EEPROM_CTRL_DATA_HI_SHIFT 0
135#define EEPROM_CTRL_ADDR_MASK 0x3FF
136#define EEPROM_CTRL_ADDR_SHIFT 16
137#define EEPROM_CTRL_ACK 0x40000000
138#define EEPROM_CTRL_RW 0x80000000
139
140#define REG_EEPROM_DATA_LO 0x12C4
141
142#define REG_OTP_CTRL 0x12F0
143#define OTP_CTRL_CLK_EN 0x0002
144
145#define REG_PM_CTRL 0x12F8
146#define PM_CTRL_SDES_EN 0x00000001
147#define PM_CTRL_RBER_EN 0x00000002
148#define PM_CTRL_CLK_REQ_EN 0x00000004
149#define PM_CTRL_ASPM_L1_EN 0x00000008
150#define PM_CTRL_SERDES_L1_EN 0x00000010
151#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
152#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
153#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
154#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
155#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
156#define PM_CTRL_ASPM_L0S_EN 0x00001000
157#define PM_CTRL_CLK_SWH_L1 0x00002000
158#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
Jie Yang8f574b32010-06-01 00:28:12 -0700159#define PM_CTRL_RCVR_WT_TIMER 0x00008000
Jie Yang43250dd2009-02-18 17:24:15 -0800160#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
161#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
162#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
163#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
Jie Yang8f574b32010-06-01 00:28:12 -0700164#define PM_CTRL_LCKDET_TIMER_MASK 0xF
Jie Yang43250dd2009-02-18 17:24:15 -0800165#define PM_CTRL_LCKDET_TIMER_SHIFT 24
Luis R. Rodriguez496c1852010-02-16 15:16:45 -0800166#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000
167#define PM_CTRL_SA_DLY_EN 0x20000000
Jie Yang43250dd2009-02-18 17:24:15 -0800168#define PM_CTRL_MAC_ASPM_CHK 0x40000000
169#define PM_CTRL_HOTRST 0x80000000
170
Jie Yang8f574b32010-06-01 00:28:12 -0700171#define REG_LTSSM_ID_CTRL 0x12FC
172#define LTSSM_ID_EN_WRO 0x1000
Jie Yang43250dd2009-02-18 17:24:15 -0800173/* Selene Master Control Register */
174#define REG_MASTER_CTRL 0x1400
175#define MASTER_CTRL_SOFT_RST 0x1
176#define MASTER_CTRL_TEST_MODE_MASK 0x3
177#define MASTER_CTRL_TEST_MODE_SHIFT 2
178#define MASTER_CTRL_BERT_START 0x10
Jie Yang8f574b32010-06-01 00:28:12 -0700179#define MASTER_CTRL_OOB_DIS_OFF 0x40
180#define MASTER_CTRL_SA_TIMER_EN 0x80
Jie Yang43250dd2009-02-18 17:24:15 -0800181#define MASTER_CTRL_MTIMER_EN 0x100
182#define MASTER_CTRL_MANUAL_INT 0x200
183#define MASTER_CTRL_TX_ITIMER_EN 0x400
184#define MASTER_CTRL_RX_ITIMER_EN 0x800
185#define MASTER_CTRL_CLK_SEL_DIS 0x1000
186#define MASTER_CTRL_CLK_SWH_MODE 0x2000
187#define MASTER_CTRL_INT_RDCLR 0x4000
188#define MASTER_CTRL_REV_NUM_SHIFT 16
189#define MASTER_CTRL_REV_NUM_MASK 0xff
190#define MASTER_CTRL_DEV_ID_SHIFT 24
191#define MASTER_CTRL_DEV_ID_MASK 0x7f
192#define MASTER_CTRL_OTP_SEL 0x80000000
193
194/* Timer Initial Value Register */
195#define REG_MANUAL_TIMER_INIT 0x1404
196
197/* IRQ ModeratorTimer Initial Value Register */
198#define REG_IRQ_MODRT_TIMER_INIT 0x1408
199#define IRQ_MODRT_TIMER_MASK 0xffff
200#define IRQ_MODRT_TX_TIMER_SHIFT 0
201#define IRQ_MODRT_RX_TIMER_SHIFT 16
202
203#define REG_GPHY_CTRL 0x140C
204#define GPHY_CTRL_EXT_RESET 0x1
205#define GPHY_CTRL_RTL_MODE 0x2
206#define GPHY_CTRL_LED_MODE 0x4
207#define GPHY_CTRL_ANEG_NOW 0x8
208#define GPHY_CTRL_REV_ANEG 0x10
209#define GPHY_CTRL_GATE_25M_EN 0x20
210#define GPHY_CTRL_LPW_EXIT 0x40
211#define GPHY_CTRL_PHY_IDDQ 0x80
212#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
213#define GPHY_CTRL_GIGA_DIS 0x200
214#define GPHY_CTRL_HIB_EN 0x400
215#define GPHY_CTRL_HIB_PULSE 0x800
216#define GPHY_CTRL_SEL_ANA_RST 0x1000
217#define GPHY_CTRL_PHY_PLL_ON 0x2000
218#define GPHY_CTRL_PWDOWN_HW 0x4000
219#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
220
221#define GPHY_CTRL_DEFAULT ( \
222 GPHY_CTRL_SEL_ANA_RST |\
223 GPHY_CTRL_HIB_PULSE |\
224 GPHY_CTRL_HIB_EN)
225
226#define GPHY_CTRL_PW_WOL_DIS ( \
227 GPHY_CTRL_SEL_ANA_RST |\
228 GPHY_CTRL_HIB_PULSE |\
229 GPHY_CTRL_HIB_EN |\
230 GPHY_CTRL_PWDOWN_HW |\
231 GPHY_CTRL_PHY_IDDQ)
232
Jie Yang8f574b32010-06-01 00:28:12 -0700233#define GPHY_CTRL_POWER_SAVING ( \
234 GPHY_CTRL_SEL_ANA_RST |\
235 GPHY_CTRL_HIB_EN |\
236 GPHY_CTRL_HIB_PULSE |\
237 GPHY_CTRL_PWDOWN_HW |\
238 GPHY_CTRL_PHY_IDDQ)
Jie Yang43250dd2009-02-18 17:24:15 -0800239/* Block IDLE Status Register */
240#define REG_IDLE_STATUS 0x1410
241#define IDLE_STATUS_MASK 0x00FF
242#define IDLE_STATUS_RXMAC_NO_IDLE 0x1
243#define IDLE_STATUS_TXMAC_NO_IDLE 0x2
244#define IDLE_STATUS_RXQ_NO_IDLE 0x4
245#define IDLE_STATUS_TXQ_NO_IDLE 0x8
246#define IDLE_STATUS_DMAR_NO_IDLE 0x10
247#define IDLE_STATUS_DMAW_NO_IDLE 0x20
248#define IDLE_STATUS_SMB_NO_IDLE 0x40
249#define IDLE_STATUS_CMB_NO_IDLE 0x80
250
251/* MDIO Control Register */
252#define REG_MDIO_CTRL 0x1414
253#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
254 * control data to write to PHY
255 * MII management register */
256#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
257 * status data that was read
258 * from the PHY MII management register */
259#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
260#define MDIO_REG_ADDR_SHIFT 16
261#define MDIO_RW 0x200000 /* 1: read, 0: write */
262#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
263#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
264 * master. And this bit is self
265 * cleared after one cycle */
266#define MDIO_CLK_SEL_SHIFT 24
267#define MDIO_CLK_25_4 0
268#define MDIO_CLK_25_6 2
269#define MDIO_CLK_25_8 3
270#define MDIO_CLK_25_10 4
271#define MDIO_CLK_25_14 5
272#define MDIO_CLK_25_20 6
273#define MDIO_CLK_25_28 7
274#define MDIO_BUSY 0x8000000
275#define MDIO_AP_EN 0x10000000
276#define MDIO_WAIT_TIMES 10
277
278/* MII PHY Status Register */
279#define REG_PHY_STATUS 0x1418
280#define PHY_GENERAL_STATUS_MASK 0xFFFF
281#define PHY_STATUS_RECV_ENABLE 0x0001
282#define PHY_OE_PWSP_STATUS_MASK 0x07FF
283#define PHY_OE_PWSP_STATUS_SHIFT 16
284#define PHY_STATUS_LPW_STATE 0x80000000
285/* BIST Control and Status Register0 (for the Packet Memory) */
286#define REG_BIST0_CTRL 0x141c
287#define BIST0_NOW 0x1
288#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
289 * un-repairable because
290 * it has address decoder
291 * failure or more than 1 cell
292 * stuck-to-x failure */
293#define BIST0_FUSE_FLAG 0x4
294
295/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
296#define REG_BIST1_CTRL 0x1420
297#define BIST1_NOW 0x1
298#define BIST1_SRAM_FAIL 0x2
299#define BIST1_FUSE_FLAG 0x4
300
301/* SerDes Lock Detect Control and Status Register */
302#define REG_SERDES_LOCK 0x1424
303#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
304 * comes from Analog SerDes */
305#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
Jie Yang8f574b32010-06-01 00:28:12 -0700306#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE
307#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3
308#define SERDES_OVCLK_18_25 0x0
309#define SERDES_OVCLK_12_18 0x1
310#define SERDES_OVCLK_0_4 0x2
311#define SERDES_OVCLK_4_12 0x3
312#define SERDES_MAC_CLK_SLOWDOWN 0x20000
313#define SERDES_PYH_CLK_SLOWDOWN 0x40000
Jie Yang43250dd2009-02-18 17:24:15 -0800314
315/* MAC Control Register */
316#define REG_MAC_CTRL 0x1480
317#define MAC_CTRL_TX_EN 0x1
318#define MAC_CTRL_RX_EN 0x2
319#define MAC_CTRL_TX_FLOW 0x4
320#define MAC_CTRL_RX_FLOW 0x8
321#define MAC_CTRL_LOOPBACK 0x10
322#define MAC_CTRL_DUPLX 0x20
323#define MAC_CTRL_ADD_CRC 0x40
324#define MAC_CTRL_PAD 0x80
325#define MAC_CTRL_LENCHK 0x100
326#define MAC_CTRL_HUGE_EN 0x200
327#define MAC_CTRL_PRMLEN_SHIFT 10
328#define MAC_CTRL_PRMLEN_MASK 0xf
329#define MAC_CTRL_RMV_VLAN 0x4000
330#define MAC_CTRL_PROMIS_EN 0x8000
331#define MAC_CTRL_TX_PAUSE 0x10000
332#define MAC_CTRL_SCNT 0x20000
333#define MAC_CTRL_SRST_TX 0x40000
334#define MAC_CTRL_TX_SIMURST 0x80000
335#define MAC_CTRL_SPEED_SHIFT 20
336#define MAC_CTRL_SPEED_MASK 0x3
337#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
338#define MAC_CTRL_TX_HUGE 0x800000
339#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
340#define MAC_CTRL_MC_ALL_EN 0x2000000
341#define MAC_CTRL_BC_EN 0x4000000
342#define MAC_CTRL_DBG 0x8000000
343#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
Luis R. Rodriguez496c1852010-02-16 15:16:45 -0800344#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
345#define MAC_CTRL_SPEED_MODE_SW 0x40000000
Jie Yang43250dd2009-02-18 17:24:15 -0800346
347/* MAC IPG/IFG Control Register */
348#define REG_MAC_IPG_IFG 0x1484
349#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
350 * inter-packet gap. The
351 * default is 96-bit time */
352#define MAC_IPG_IFG_IPGT_MASK 0x7f
353#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
354 * enforce in between RX frames */
355#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
356#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
357#define MAC_IPG_IFG_IPGR1_MASK 0x7f
358#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
359#define MAC_IPG_IFG_IPGR2_MASK 0x7f
360
361/* MAC STATION ADDRESS */
362#define REG_MAC_STA_ADDR 0x1488
363
364/* Hash table for multicast address */
365#define REG_RX_HASH_TABLE 0x1490
366
367/* MAC Half-Duplex Control Register */
368#define REG_MAC_HALF_DUPLX_CTRL 0x1498
369#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
370#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
371#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
372#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
373#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
374#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
375#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
376 * immediately start the
377 * transmission after back pressure */
378#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
379#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
380#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
381#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
382#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
383
384/* Maximum Frame Length Control Register */
385#define REG_MTU 0x149c
386
387/* Wake-On-Lan control register */
388#define REG_WOL_CTRL 0x14a0
389#define WOL_PATTERN_EN 0x00000001
390#define WOL_PATTERN_PME_EN 0x00000002
391#define WOL_MAGIC_EN 0x00000004
392#define WOL_MAGIC_PME_EN 0x00000008
393#define WOL_LINK_CHG_EN 0x00000010
394#define WOL_LINK_CHG_PME_EN 0x00000020
395#define WOL_PATTERN_ST 0x00000100
396#define WOL_MAGIC_ST 0x00000200
397#define WOL_LINKCHG_ST 0x00000400
398#define WOL_CLK_SWITCH_EN 0x00008000
399#define WOL_PT0_EN 0x00010000
400#define WOL_PT1_EN 0x00020000
401#define WOL_PT2_EN 0x00040000
402#define WOL_PT3_EN 0x00080000
403#define WOL_PT4_EN 0x00100000
404#define WOL_PT5_EN 0x00200000
405#define WOL_PT6_EN 0x00400000
406
407/* WOL Length ( 2 DWORD ) */
408#define REG_WOL_PATTERN_LEN 0x14a4
409#define WOL_PT_LEN_MASK 0x7f
410#define WOL_PT0_LEN_SHIFT 0
411#define WOL_PT1_LEN_SHIFT 8
412#define WOL_PT2_LEN_SHIFT 16
413#define WOL_PT3_LEN_SHIFT 24
414#define WOL_PT4_LEN_SHIFT 0
415#define WOL_PT5_LEN_SHIFT 8
416#define WOL_PT6_LEN_SHIFT 16
417
418/* Internal SRAM Partition Register */
419#define RFDX_HEAD_ADDR_MASK 0x03FF
420#define RFDX_HARD_ADDR_SHIFT 0
421#define RFDX_TAIL_ADDR_MASK 0x03FF
422#define RFDX_TAIL_ADDR_SHIFT 16
423
424#define REG_SRAM_RFD0_INFO 0x1500
425#define REG_SRAM_RFD1_INFO 0x1504
426#define REG_SRAM_RFD2_INFO 0x1508
427#define REG_SRAM_RFD3_INFO 0x150C
428
429#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
430#define RFD_NIC_LEN_MASK 0x03FF
431
432#define REG_SRAM_TRD_ADDR 0x1518
433#define TPD_HEAD_ADDR_MASK 0x03FF
434#define TPD_HEAD_ADDR_SHIFT 0
435#define TPD_TAIL_ADDR_MASK 0x03FF
436#define TPD_TAIL_ADDR_SHIFT 16
437
438#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
439#define TPD_NIC_LEN_MASK 0x03FF
440
441#define REG_SRAM_RXF_ADDR 0x1520
442#define REG_SRAM_RXF_LEN 0x1524
443#define REG_SRAM_TXF_ADDR 0x1528
444#define REG_SRAM_TXF_LEN 0x152C
445#define REG_SRAM_TCPH_ADDR 0x1530
446#define REG_SRAM_PKTH_ADDR 0x1532
447
448/*
449 * Load Ptr Register
450 * Software sets this bit after the initialization of the head and tail */
451#define REG_LOAD_PTR 0x1534
452
453/*
454 * addresses of all descriptors, as well as the following descriptor
455 * control register, which triggers each function block to load the head
456 * pointer to prepare for the operation. This bit is then self-cleared
457 * after one cycle.
458 */
459#define REG_RX_BASE_ADDR_HI 0x1540
460#define REG_TX_BASE_ADDR_HI 0x1544
461#define REG_SMB_BASE_ADDR_HI 0x1548
462#define REG_SMB_BASE_ADDR_LO 0x154C
463#define REG_RFD0_HEAD_ADDR_LO 0x1550
464#define REG_RFD1_HEAD_ADDR_LO 0x1554
465#define REG_RFD2_HEAD_ADDR_LO 0x1558
466#define REG_RFD3_HEAD_ADDR_LO 0x155C
467#define REG_RFD_RING_SIZE 0x1560
468#define RFD_RING_SIZE_MASK 0x0FFF
469#define REG_RX_BUF_SIZE 0x1564
470#define RX_BUF_SIZE_MASK 0xFFFF
471#define REG_RRD0_HEAD_ADDR_LO 0x1568
472#define REG_RRD1_HEAD_ADDR_LO 0x156C
473#define REG_RRD2_HEAD_ADDR_LO 0x1570
474#define REG_RRD3_HEAD_ADDR_LO 0x1574
475#define REG_RRD_RING_SIZE 0x1578
476#define RRD_RING_SIZE_MASK 0x0FFF
477#define REG_HTPD_HEAD_ADDR_LO 0x157C
478#define REG_NTPD_HEAD_ADDR_LO 0x1580
479#define REG_TPD_RING_SIZE 0x1584
480#define TPD_RING_SIZE_MASK 0xFFFF
481#define REG_CMB_BASE_ADDR_LO 0x1588
482
483/* RSS about */
484#define REG_RSS_KEY0 0x14B0
485#define REG_RSS_KEY1 0x14B4
486#define REG_RSS_KEY2 0x14B8
487#define REG_RSS_KEY3 0x14BC
488#define REG_RSS_KEY4 0x14C0
489#define REG_RSS_KEY5 0x14C4
490#define REG_RSS_KEY6 0x14C8
491#define REG_RSS_KEY7 0x14CC
492#define REG_RSS_KEY8 0x14D0
493#define REG_RSS_KEY9 0x14D4
494#define REG_IDT_TABLE0 0x14E0
495#define REG_IDT_TABLE1 0x14E4
496#define REG_IDT_TABLE2 0x14E8
497#define REG_IDT_TABLE3 0x14EC
498#define REG_IDT_TABLE4 0x14F0
499#define REG_IDT_TABLE5 0x14F4
500#define REG_IDT_TABLE6 0x14F8
501#define REG_IDT_TABLE7 0x14FC
502#define REG_IDT_TABLE REG_IDT_TABLE0
503#define REG_RSS_HASH_VALUE 0x15B0
504#define REG_RSS_HASH_FLAG 0x15B4
505#define REG_BASE_CPU_NUMBER 0x15B8
506
507/* TXQ Control Register */
508#define REG_TXQ_CTRL 0x1590
509#define TXQ_NUM_TPD_BURST_MASK 0xF
510#define TXQ_NUM_TPD_BURST_SHIFT 0
511#define TXQ_CTRL_IP_OPTION_EN 0x10
512#define TXQ_CTRL_EN 0x20
513#define TXQ_CTRL_ENH_MODE 0x40
514#define TXQ_CTRL_LS_8023_EN 0x80
515#define TXQ_TXF_BURST_NUM_SHIFT 16
516#define TXQ_TXF_BURST_NUM_MASK 0xFFFF
517
518/* Jumbo packet Threshold for task offload */
519#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
520#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
521
522#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
523#define TXF_WATER_MARK_MASK 0x0FFF
524#define TXF_LOW_WATER_MARK_SHIFT 0
525#define TXF_HIGH_WATER_MARK_SHIFT 16
526#define TXQ_CTRL_BURST_MODE_EN 0x80000000
527
528#define REG_THRUPUT_MON_CTRL 0x159C
529#define THRUPUT_MON_RATE_MASK 0x3
530#define THRUPUT_MON_RATE_SHIFT 0
531#define THRUPUT_MON_EN 0x80
532
533/* RXQ Control Register */
534#define REG_RXQ_CTRL 0x15A0
535#define ASPM_THRUPUT_LIMIT_MASK 0x3
536#define ASPM_THRUPUT_LIMIT_SHIFT 0
537#define ASPM_THRUPUT_LIMIT_NO 0x00
538#define ASPM_THRUPUT_LIMIT_1M 0x01
539#define ASPM_THRUPUT_LIMIT_10M 0x02
540#define ASPM_THRUPUT_LIMIT_100M 0x04
541#define RXQ1_CTRL_EN 0x10
542#define RXQ2_CTRL_EN 0x20
543#define RXQ3_CTRL_EN 0x40
544#define IPV6_CHKSUM_CTRL_EN 0x80
545#define RSS_HASH_BITS_MASK 0x00FF
546#define RSS_HASH_BITS_SHIFT 8
547#define RSS_HASH_IPV4 0x10000
548#define RSS_HASH_IPV4_TCP 0x20000
549#define RSS_HASH_IPV6 0x40000
550#define RSS_HASH_IPV6_TCP 0x80000
551#define RXQ_RFD_BURST_NUM_MASK 0x003F
552#define RXQ_RFD_BURST_NUM_SHIFT 20
553#define RSS_MODE_MASK 0x0003
554#define RSS_MODE_SHIFT 26
555#define RSS_NIP_QUEUE_SEL_MASK 0x1
556#define RSS_NIP_QUEUE_SEL_SHIFT 28
557#define RRS_HASH_CTRL_EN 0x20000000
558#define RX_CUT_THRU_EN 0x40000000
559#define RXQ_CTRL_EN 0x80000000
560
561#define REG_RFD_FREE_THRESH 0x15A4
562#define RFD_FREE_THRESH_MASK 0x003F
563#define RFD_FREE_HI_THRESH_SHIFT 0
564#define RFD_FREE_LO_THRESH_SHIFT 6
565
566/* RXF flow control register */
567#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
568#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
569#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
570#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
571#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
572
573#define REG_RXD_DMA_CTRL 0x15AC
574#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
575#define RXD_DMA_THRESH_SHIFT 0
576#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
577#define RXD_DMA_DOWN_TIMER_SHIFT 16
578
579/* DMA Engine Control Register */
580#define REG_DMA_CTRL 0x15C0
581#define DMA_CTRL_DMAR_IN_ORDER 0x1
582#define DMA_CTRL_DMAR_ENH_ORDER 0x2
583#define DMA_CTRL_DMAR_OUT_ORDER 0x4
584#define DMA_CTRL_RCB_VALUE 0x8
585#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
586#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
587#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
588#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
589#define DMA_CTRL_DMAR_REQ_PRI 0x400
590#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
591#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
592#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
593#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
594#define DMA_CTRL_CMB_EN 0x100000
595#define DMA_CTRL_SMB_EN 0x200000
596#define DMA_CTRL_CMB_NOW 0x400000
597#define MAC_CTRL_SMB_DIS 0x1000000
598#define DMA_CTRL_SMB_NOW 0x80000000
599
600/* CMB/SMB Control Register */
601#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
602#define SMB_STAT_TIMER_MASK 0xFFFFFF
603#define REG_CMB_TPD_THRESH 0x15C8
604#define CMB_TPD_THRESH_MASK 0xFFFF
605#define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
606#define CMB_TX_TIMER_MASK 0xFFFF
607
608/* Mail box */
609#define MB_RFDX_PROD_IDX_MASK 0xFFFF
610#define REG_MB_RFD0_PROD_IDX 0x15E0
611#define REG_MB_RFD1_PROD_IDX 0x15E4
612#define REG_MB_RFD2_PROD_IDX 0x15E8
613#define REG_MB_RFD3_PROD_IDX 0x15EC
614
615#define MB_PRIO_PROD_IDX_MASK 0xFFFF
616#define REG_MB_PRIO_PROD_IDX 0x15F0
617#define MB_HTPD_PROD_IDX_SHIFT 0
618#define MB_NTPD_PROD_IDX_SHIFT 16
619
620#define MB_PRIO_CONS_IDX_MASK 0xFFFF
621#define REG_MB_PRIO_CONS_IDX 0x15F4
622#define MB_HTPD_CONS_IDX_SHIFT 0
623#define MB_NTPD_CONS_IDX_SHIFT 16
624
625#define REG_MB_RFD01_CONS_IDX 0x15F8
626#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
627#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
628#define REG_MB_RFD23_CONS_IDX 0x15FC
629#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
630#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
631
632/* Interrupt Status Register */
633#define REG_ISR 0x1600
634#define ISR_SMB 0x00000001
635#define ISR_TIMER 0x00000002
636/*
637 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
638 * in Table 51 Selene Master Control Register (Offset 0x1400).
639 */
640#define ISR_MANUAL 0x00000004
641#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
642#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
643#define ISR_RFD1_UR 0x00000020
644#define ISR_RFD2_UR 0x00000040
645#define ISR_RFD3_UR 0x00000080
646#define ISR_TXF_UR 0x00000100
647#define ISR_DMAR_TO_RST 0x00000200
648#define ISR_DMAW_TO_RST 0x00000400
649#define ISR_TX_CREDIT 0x00000800
650#define ISR_GPHY 0x00001000
651/* GPHY low power state interrupt */
652#define ISR_GPHY_LPW 0x00002000
653#define ISR_TXQ_TO_RST 0x00004000
654#define ISR_TX_PKT 0x00008000
655#define ISR_RX_PKT_0 0x00010000
656#define ISR_RX_PKT_1 0x00020000
657#define ISR_RX_PKT_2 0x00040000
658#define ISR_RX_PKT_3 0x00080000
659#define ISR_MAC_RX 0x00100000
660#define ISR_MAC_TX 0x00200000
661#define ISR_UR_DETECTED 0x00400000
662#define ISR_FERR_DETECTED 0x00800000
663#define ISR_NFERR_DETECTED 0x01000000
664#define ISR_CERR_DETECTED 0x02000000
665#define ISR_PHY_LINKDOWN 0x04000000
666#define ISR_DIS_INT 0x80000000
667
668/* Interrupt Mask Register */
669#define REG_IMR 0x1604
670
671#define IMR_NORMAL_MASK (\
672 ISR_MANUAL |\
673 ISR_HW_RXF_OV |\
674 ISR_RFD0_UR |\
675 ISR_TXF_UR |\
676 ISR_DMAR_TO_RST |\
677 ISR_TXQ_TO_RST |\
678 ISR_DMAW_TO_RST |\
679 ISR_GPHY |\
680 ISR_TX_PKT |\
681 ISR_RX_PKT_0 |\
682 ISR_GPHY_LPW |\
683 ISR_PHY_LINKDOWN)
684
685#define ISR_RX_PKT (\
686 ISR_RX_PKT_0 |\
687 ISR_RX_PKT_1 |\
688 ISR_RX_PKT_2 |\
689 ISR_RX_PKT_3)
690
691#define ISR_OVER (\
692 ISR_RFD0_UR |\
693 ISR_RFD1_UR |\
694 ISR_RFD2_UR |\
695 ISR_RFD3_UR |\
696 ISR_HW_RXF_OV |\
697 ISR_TXF_UR)
698
699#define ISR_ERROR (\
700 ISR_DMAR_TO_RST |\
701 ISR_TXQ_TO_RST |\
702 ISR_DMAW_TO_RST |\
703 ISR_PHY_LINKDOWN)
704
705#define REG_INT_RETRIG_TIMER 0x1608
706#define INT_RETRIG_TIMER_MASK 0xFFFF
707
708#define REG_HDS_CTRL 0x160C
709#define HDS_CTRL_EN 0x0001
710#define HDS_CTRL_BACKFILLSIZE_SHIFT 8
711#define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
712#define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
713#define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
714
715#define REG_MAC_RX_STATUS_BIN 0x1700
716#define REG_MAC_RX_STATUS_END 0x175c
717#define REG_MAC_TX_STATUS_BIN 0x1760
718#define REG_MAC_TX_STATUS_END 0x17c0
719
Jie Yang8f574b32010-06-01 00:28:12 -0700720#define REG_CLK_GATING_CTRL 0x1814
721#define CLK_GATING_DMAW_EN 0x0001
722#define CLK_GATING_DMAR_EN 0x0002
723#define CLK_GATING_TXQ_EN 0x0004
724#define CLK_GATING_RXQ_EN 0x0008
725#define CLK_GATING_TXMAC_EN 0x0010
726#define CLK_GATING_RXMAC_EN 0x0020
727
728#define CLK_GATING_EN_ALL (CLK_GATING_DMAW_EN |\
729 CLK_GATING_DMAR_EN |\
730 CLK_GATING_TXQ_EN |\
731 CLK_GATING_RXQ_EN |\
732 CLK_GATING_TXMAC_EN|\
733 CLK_GATING_RXMAC_EN)
734
Jie Yang43250dd2009-02-18 17:24:15 -0800735/* DEBUG ADDR */
736#define REG_DEBUG_DATA0 0x1900
737#define REG_DEBUG_DATA1 0x1904
738
Jie Yang8f574b32010-06-01 00:28:12 -0700739#define L1D_MPW_PHYID1 0xD01C /* V7 */
740#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */
741#define L1D_MPW_PHYID3 0xD01E /* V8 */
742
Jie Yang43250dd2009-02-18 17:24:15 -0800743
744/* Autoneg Advertisement Register */
françois romieu34aac662011-01-20 04:59:06 +0000745#define ADVERTISE_DEFAULT_CAP \
746 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)
Jie Yang43250dd2009-02-18 17:24:15 -0800747
748/* 1000BASE-T Control Register */
Jie Yang43250dd2009-02-18 17:24:15 -0800749#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
750
751#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
752#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
753#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
754#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
755#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
756#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
757#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
758#define GIGA_CR_1000T_SPEED_MASK 0x0300
759#define GIGA_CR_1000T_DEFAULT_CAP 0x0300
760
761/* PHY Specific Status Register */
762#define MII_GIGA_PSSR 0x11
763#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
764#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
765#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
766#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
767#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
768#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
769
770/* PHY Interrupt Enable Register */
771#define MII_IER 0x12
772#define IER_LINK_UP 0x0400
773#define IER_LINK_DOWN 0x0800
774
775/* PHY Interrupt Status Register */
776#define MII_ISR 0x13
777#define ISR_LINK_UP 0x0400
778#define ISR_LINK_DOWN 0x0800
779
780/* Cable-Detect-Test Control Register */
781#define MII_CDTC 0x16
782#define CDTC_EN_OFF 0 /* sc */
783#define CDTC_EN_BITS 1
784#define CDTC_PAIR_OFF 8
785#define CDTC_PAIR_BIT 2
786
787/* Cable-Detect-Test Status Register */
788#define MII_CDTS 0x1C
789#define CDTS_STATUS_OFF 8
790#define CDTS_STATUS_BITS 2
791#define CDTS_STATUS_NORMAL 0
792#define CDTS_STATUS_SHORT 1
793#define CDTS_STATUS_OPEN 2
794#define CDTS_STATUS_INVALID 3
795
796#define MII_DBG_ADDR 0x1D
797#define MII_DBG_DATA 0x1E
798
799#define MII_ANA_CTRL_0 0x0
800#define ANA_RESTART_CAL 0x0001
801#define ANA_MANUL_SWICH_ON_SHIFT 0x1
802#define ANA_MANUL_SWICH_ON_MASK 0xF
803#define ANA_MAN_ENABLE 0x0020
804#define ANA_SEL_HSP 0x0040
805#define ANA_EN_HB 0x0080
806#define ANA_EN_HBIAS 0x0100
807#define ANA_OEN_125M 0x0200
808#define ANA_EN_LCKDT 0x0400
809#define ANA_LCKDT_PHY 0x0800
810#define ANA_AFE_MODE 0x1000
811#define ANA_VCO_SLOW 0x2000
812#define ANA_VCO_FAST 0x4000
813#define ANA_SEL_CLK125M_DSP 0x8000
814
815#define MII_ANA_CTRL_4 0x4
816#define ANA_IECHO_ADJ_MASK 0xF
817#define ANA_IECHO_ADJ_3_SHIFT 0
818#define ANA_IECHO_ADJ_2_SHIFT 4
819#define ANA_IECHO_ADJ_1_SHIFT 8
820#define ANA_IECHO_ADJ_0_SHIFT 12
821
822#define MII_ANA_CTRL_5 0x5
823#define ANA_SERDES_CDR_BW_SHIFT 0
824#define ANA_SERDES_CDR_BW_MASK 0x3
825#define ANA_MS_PAD_DBG 0x0004
826#define ANA_SPEEDUP_DBG 0x0008
827#define ANA_SERDES_TH_LOS_SHIFT 4
828#define ANA_SERDES_TH_LOS_MASK 0x3
829#define ANA_SERDES_EN_DEEM 0x0040
830#define ANA_SERDES_TXELECIDLE 0x0080
831#define ANA_SERDES_BEACON 0x0100
832#define ANA_SERDES_HALFTXDR 0x0200
833#define ANA_SERDES_SEL_HSP 0x0400
834#define ANA_SERDES_EN_PLL 0x0800
835#define ANA_SERDES_EN 0x1000
836#define ANA_SERDES_EN_LCKDT 0x2000
837
838#define MII_ANA_CTRL_11 0xB
839#define ANA_PS_HIB_EN 0x8000
840
841#define MII_ANA_CTRL_18 0x12
842#define ANA_TEST_MODE_10BT_01SHIFT 0
843#define ANA_TEST_MODE_10BT_01MASK 0x3
844#define ANA_LOOP_SEL_10BT 0x0004
845#define ANA_RGMII_MODE_SW 0x0008
846#define ANA_EN_LONGECABLE 0x0010
847#define ANA_TEST_MODE_10BT_2 0x0020
848#define ANA_EN_10BT_IDLE 0x0400
849#define ANA_EN_MASK_TB 0x0800
850#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
851#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
852#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
853#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
854
855#define MII_ANA_CTRL_41 0x29
856#define ANA_TOP_PS_EN 0x8000
857
858#define MII_ANA_CTRL_54 0x36
859#define ANA_LONG_CABLE_TH_100_SHIFT 0
860#define ANA_LONG_CABLE_TH_100_MASK 0x3F
861#define ANA_DESERVED 0x0040
862#define ANA_EN_LIT_CH 0x0080
863#define ANA_SHORT_CABLE_TH_100_SHIFT 8
864#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
865#define ANA_BP_BAD_LINK_ACCUM 0x4000
866#define ANA_BP_SMALL_BW 0x8000
867
868#endif /*_ATL1C_HW_H_*/