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Duy Truong790f06d2013-02-13 16:38:12 -08001/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
Jordan Crouse914de9b2012-07-09 13:49:46 -06002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _ARCH_ARM_MACH_KGSL_H
14#define _ARCH_ARM_MACH_KGSL_H
15
16/* Clock flags to show which clocks should be controled by a given platform */
17#define KGSL_CLK_SRC 0x00000001
18#define KGSL_CLK_CORE 0x00000002
19#define KGSL_CLK_IFACE 0x00000004
20#define KGSL_CLK_MEM 0x00000008
21#define KGSL_CLK_MEM_IFACE 0x00000010
22#define KGSL_CLK_AXI 0x00000020
23
24#define KGSL_MAX_PWRLEVELS 5
25
26#define KGSL_CONVERT_TO_MBPS(val) \
27 (val*1000*1000U)
28
29#define KGSL_3D0_REG_MEMORY "kgsl_3d0_reg_memory"
Harsh Vardhan Dwivedi623b9a22012-10-28 20:54:17 -060030#define KGSL_3D0_SHADER_MEMORY "kgsl_3d0_shader_memory"
Jordan Crouse914de9b2012-07-09 13:49:46 -060031#define KGSL_3D0_IRQ "kgsl_3d0_irq"
32#define KGSL_2D0_REG_MEMORY "kgsl_2d0_reg_memory"
33#define KGSL_2D0_IRQ "kgsl_2d0_irq"
34#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory"
35#define KGSL_2D1_IRQ "kgsl_2d1_irq"
36
Jordan Crouse4815e9f2012-07-09 15:36:37 -060037#define ADRENO_CHIPID(_co, _ma, _mi, _pa) \
38 ((((_co) & 0xFF) << 24) | \
39 (((_ma) & 0xFF) << 16) | \
40 (((_mi) & 0xFF) << 8) | \
41 ((_pa) & 0xFF))
42
Jordan Crouse914de9b2012-07-09 13:49:46 -060043enum kgsl_iommu_context_id {
44 KGSL_IOMMU_CONTEXT_USER = 0,
45 KGSL_IOMMU_CONTEXT_PRIV = 1,
46};
47
48struct kgsl_iommu_ctx {
49 const char *iommu_ctx_name;
50 enum kgsl_iommu_context_id ctx_id;
51};
52
53struct kgsl_device_iommu_data {
54 const struct kgsl_iommu_ctx *iommu_ctxs;
55 int iommu_ctx_count;
56 unsigned int physstart;
57 unsigned int physend;
58};
59
60struct kgsl_pwrlevel {
61 unsigned int gpu_freq;
62 unsigned int bus_freq;
63 unsigned int io_fraction;
64};
65
66struct kgsl_device_platform_data {
67 struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
68 int init_level;
69 int num_levels;
70 int (*set_grp_async)(void);
71 unsigned int idle_timeout;
72 bool strtstp_sleepwake;
73 unsigned int nap_allowed;
74 unsigned int clk_map;
75 unsigned int idle_needed;
76 struct msm_bus_scale_pdata *bus_scale_table;
77 struct kgsl_device_iommu_data *iommu_data;
78 int iommu_count;
79 struct msm_dcvs_core_info *core_info;
Jordan Crouse4815e9f2012-07-09 15:36:37 -060080 unsigned int chipid;
Jordan Crouse914de9b2012-07-09 13:49:46 -060081};
82
83#endif