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Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -07001/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
Jiri Pirkof1b553f2011-07-20 04:54:22 +000037#include <linux/bitops.h>
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070038#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/netdevice.h>
Jiri Pirkof1b553f2011-07-20 04:54:22 +000042#include <linux/if_vlan.h>
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070043
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/qp.h>
46#include <linux/mlx4/cq.h>
47#include <linux/mlx4/srq.h>
48#include <linux/mlx4/doorbell.h>
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +000049#include <linux/mlx4/cmd.h>
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070050
51#include "en_port.h"
52
53#define DRV_NAME "mlx4_en"
Yevgeny Petrilin6edf91d2011-12-13 04:19:34 +000054#define DRV_VERSION "2.0"
55#define DRV_RELDATE "Dec 2011"
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070056
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070057#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
58
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070059/*
60 * Device constants
61 */
62
63
64#define MLX4_EN_PAGE_SHIFT 12
65#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070066#define MAX_RX_RINGS 16
Yevgeny Petrilin1fb98762011-03-22 22:37:52 +000067#define MIN_RX_RINGS 4
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070068#define TXBB_SIZE 64
69#define HEADROOM (2048 / TXBB_SIZE + 1)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070070#define STAMP_STRIDE 64
71#define STAMP_DWORDS (STAMP_STRIDE / 4)
72#define STAMP_SHIFT 31
73#define STAMP_VAL 0x7fffffff
74#define STATS_DELAY (HZ / 4)
75
76/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
77#define MAX_DESC_SIZE 512
78#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
79
80/*
81 * OS related constants and tunables
82 */
83
84#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
85
86#define MLX4_EN_ALLOC_ORDER 2
87#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
88
89#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
90
91/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
92 * and 4K allocations) */
93enum {
94 FRAG_SZ0 = 512 - NET_IP_ALIGN,
95 FRAG_SZ1 = 1024,
96 FRAG_SZ2 = 4096,
97 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
98};
99#define MLX4_EN_MAX_RX_FRAGS 4
100
Yevgeny Petrilinbd531e32009-01-08 10:57:37 -0800101/* Maximum ring sizes */
102#define MLX4_EN_MAX_TX_SIZE 8192
103#define MLX4_EN_MAX_RX_SIZE 8192
104
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700105/* Minimum ring size for our page-allocation sceme to work */
106#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
107#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
108
Yevgeny Petrilinf813cad2009-06-01 23:24:07 +0000109#define MLX4_EN_SMALL_PKT_SIZE 64
110#define MLX4_EN_NUM_TX_RINGS 8
111#define MLX4_EN_NUM_PPP_RINGS 8
Yevgeny Petrilina0b4e6e2010-08-24 03:45:54 +0000112#define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
Yevgeny Petrilinf813cad2009-06-01 23:24:07 +0000113#define MLX4_EN_DEF_TX_RING_SIZE 512
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700114#define MLX4_EN_DEF_RX_RING_SIZE 1024
115
Yevgeny Petrilin3db36fb2009-06-01 23:23:13 +0000116/* Target number of packets to coalesce with interrupt moderation */
117#define MLX4_EN_RX_COAL_TARGET 44
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700118#define MLX4_EN_RX_COAL_TIME 0x10
119
120#define MLX4_EN_TX_COAL_PKTS 5
121#define MLX4_EN_TX_COAL_TIME 0x80
122
123#define MLX4_EN_RX_RATE_LOW 400000
124#define MLX4_EN_RX_COAL_TIME_LOW 0
125#define MLX4_EN_RX_RATE_HIGH 450000
126#define MLX4_EN_RX_COAL_TIME_HIGH 128
127#define MLX4_EN_RX_SIZE_THRESH 1024
128#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
129#define MLX4_EN_SAMPLE_INTERVAL 0
Yevgeny Petrilin46afd0f2011-03-22 22:37:36 +0000130#define MLX4_EN_AVG_PKT_SMALL 256
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700131
132#define MLX4_EN_AUTO_CONF 0xffff
133
134#define MLX4_EN_DEF_RX_PAUSE 1
135#define MLX4_EN_DEF_TX_PAUSE 1
136
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200137/* Interval between successive polls in the Tx routine when polling is used
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700138 instead of interrupts (in per-core Tx rings) - should be power of 2 */
139#define MLX4_EN_TX_POLL_MODER 16
140#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
141
142#define ETH_LLC_SNAP_SIZE 8
143
144#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
145#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000146#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700147
148#define MLX4_EN_MIN_MTU 46
149#define ETH_BCAST 0xffffffffffffULL
150
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000151#define MLX4_EN_LOOPBACK_RETRIES 5
152#define MLX4_EN_LOOPBACK_TIMEOUT 100
153
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700154#ifdef MLX4_EN_PERF_STAT
155/* Number of samples to 'average' */
156#define AVG_SIZE 128
157#define AVG_FACTOR 1024
158#define NUM_PERF_STATS NUM_PERF_COUNTERS
159
160#define INC_PERF_COUNTER(cnt) (++(cnt))
161#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
162#define AVG_PERF_COUNTER(cnt, sample) \
163 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
164#define GET_PERF_COUNTER(cnt) (cnt)
165#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
166
167#else
168
169#define NUM_PERF_STATS 0
170#define INC_PERF_COUNTER(cnt) do {} while (0)
171#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
172#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
173#define GET_PERF_COUNTER(cnt) (0)
174#define GET_AVG_PERF_COUNTER(cnt) (0)
175#endif /* MLX4_EN_PERF_STAT */
176
177/*
178 * Configurables
179 */
180
181enum cq_type {
182 RX = 0,
183 TX = 1,
184};
185
186
187/*
188 * Useful macros
189 */
190#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
191#define XNOR(x, y) (!(x) == !(y))
192#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
193
194
195struct mlx4_en_tx_info {
196 struct sk_buff *skb;
197 u32 nr_txbb;
198 u8 linear;
199 u8 data_offset;
Yevgeny Petrilin41efea52009-01-08 10:57:15 -0800200 u8 inl;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700201};
202
203
204#define MLX4_EN_BIT_DESC_OWN 0x80000000
205#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
206#define MLX4_EN_MEMTYPE_PAD 0x100
207#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
208
209
210struct mlx4_en_tx_desc {
211 struct mlx4_wqe_ctrl_seg ctrl;
212 union {
213 struct mlx4_wqe_data_seg data; /* at least one data segment */
214 struct mlx4_wqe_lso_seg lso;
215 struct mlx4_wqe_inline_seg inl;
216 };
217};
218
219#define MLX4_EN_USE_SRQ 0x01000000
220
Yevgeny Petrilin725c8992011-03-22 22:38:07 +0000221#define MLX4_EN_CX3_LOW_ID 0x1000
222#define MLX4_EN_CX3_HIGH_ID 0x1005
223
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700224struct mlx4_en_rx_alloc {
225 struct page *page;
226 u16 offset;
227};
228
229struct mlx4_en_tx_ring {
230 struct mlx4_hwq_resources wqres;
231 u32 size ; /* number of TXBBs */
232 u32 size_mask;
233 u16 stride;
234 u16 cqn; /* index of port CQ associated with this ring */
235 u32 prod;
236 u32 cons;
237 u32 buf_size;
238 u32 doorbell_qpn;
239 void *buf;
240 u16 poll_cnt;
241 int blocked;
242 struct mlx4_en_tx_info *tx_info;
243 u8 *bounce_buf;
244 u32 last_nr_txbb;
245 struct mlx4_qp qp;
246 struct mlx4_qp_context context;
247 int qpn;
248 enum mlx4_qp_state qp_state;
249 struct mlx4_srq dummy;
250 unsigned long bytes;
251 unsigned long packets;
Yevgeny Petrilinad043782011-10-18 01:50:56 +0000252 unsigned long tx_csum;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700253 spinlock_t comp_lock;
Yevgeny Petrilin87a5c382011-03-22 22:38:52 +0000254 struct mlx4_bf bf;
255 bool bf_enabled;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700256};
257
258struct mlx4_en_rx_desc {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700259 /* actual number of entries depends on rx ring stride */
260 struct mlx4_wqe_data_seg data[0];
261};
262
263struct mlx4_en_rx_ring {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700264 struct mlx4_hwq_resources wqres;
265 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700266 u32 size ; /* number of Rx descs*/
267 u32 actual_size;
268 u32 size_mask;
269 u16 stride;
270 u16 log_stride;
271 u16 cqn; /* index of port CQ associated with this ring */
272 u32 prod;
273 u32 cons;
274 u32 buf_size;
Yevgeny Petrilin4a5f4dd2011-11-14 14:25:36 -0500275 u8 fcs_del;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700276 void *buf;
277 void *rx_info;
278 unsigned long bytes;
279 unsigned long packets;
Yevgeny Petrilinad043782011-10-18 01:50:56 +0000280 unsigned long csum_ok;
281 unsigned long csum_none;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700282};
283
284
285static inline int mlx4_en_can_lro(__be16 status)
286{
287 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
288 MLX4_CQE_STATUS_IPV4F |
289 MLX4_CQE_STATUS_IPV6 |
290 MLX4_CQE_STATUS_IPV4OPT |
291 MLX4_CQE_STATUS_TCP |
292 MLX4_CQE_STATUS_UDP |
293 MLX4_CQE_STATUS_IPOK)) ==
294 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
295 MLX4_CQE_STATUS_IPOK |
296 MLX4_CQE_STATUS_TCP);
297}
298
299struct mlx4_en_cq {
300 struct mlx4_cq mcq;
301 struct mlx4_hwq_resources wqres;
302 int ring;
303 spinlock_t lock;
304 struct net_device *dev;
305 struct napi_struct napi;
306 /* Per-core Tx cq processing support */
307 struct timer_list timer;
308 int size;
309 int buf_size;
310 unsigned vector;
311 enum cq_type is_tx;
312 u16 moder_time;
313 u16 moder_cnt;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700314 struct mlx4_cqe *buf;
315#define MLX4_EN_OPCODE_ERROR 0x1e
316};
317
318struct mlx4_en_port_profile {
319 u32 flags;
320 u32 tx_ring_num;
321 u32 rx_ring_num;
322 u32 tx_ring_size;
323 u32 rx_ring_size;
Yevgeny Petrilind53b93f2008-11-05 04:48:36 +0000324 u8 rx_pause;
325 u8 rx_ppp;
326 u8 tx_pause;
327 u8 tx_ppp;
Yevgeny Petrilin93d3e362012-01-17 22:54:55 +0000328 int rss_rings;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700329};
330
331struct mlx4_en_profile {
332 int rss_xor;
Yevgeny Petrilin05339432010-08-24 03:46:42 +0000333 int udp_rss;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700334 u8 rss_mask;
335 u32 active_ports;
336 u32 small_pkt_int;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700337 u8 no_reset;
338 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
339};
340
341struct mlx4_en_dev {
342 struct mlx4_dev *dev;
343 struct pci_dev *pdev;
344 struct mutex state_lock;
345 struct net_device *pndev[MLX4_MAX_PORTS + 1];
346 u32 port_cnt;
347 bool device_up;
348 struct mlx4_en_profile profile;
349 u32 LSO_support;
350 struct workqueue_struct *workqueue;
351 struct device *dma_device;
352 void __iomem *uar_map;
353 struct mlx4_uar priv_uar;
354 struct mlx4_mr mr;
355 u32 priv_pdn;
356 spinlock_t uar_lock;
Yevgeny Petrilind7e1a482010-08-24 03:46:38 +0000357 u8 mac_removed[MLX4_MAX_PORTS + 1];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700358};
359
360
361struct mlx4_en_rss_map {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700362 int base_qpn;
Yevgeny Petrilinb6b912e2009-08-06 19:27:51 -0700363 struct mlx4_qp qps[MAX_RX_RINGS];
364 enum mlx4_qp_state state[MAX_RX_RINGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700365 struct mlx4_qp indir_qp;
366 enum mlx4_qp_state indir_state;
367};
368
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000369struct mlx4_en_port_state {
370 int link_state;
371 int link_speed;
372 int transciver;
373};
374
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700375struct mlx4_en_pkt_stats {
376 unsigned long broadcast;
377 unsigned long rx_prio[8];
378 unsigned long tx_prio[8];
379#define NUM_PKT_STATS 17
380};
381
382struct mlx4_en_port_stats {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700383 unsigned long tso_packets;
384 unsigned long queue_stopped;
385 unsigned long wake_queue;
386 unsigned long tx_timeout;
387 unsigned long rx_alloc_failed;
388 unsigned long rx_chksum_good;
389 unsigned long rx_chksum_none;
390 unsigned long tx_chksum_offload;
Yevgeny Petrilind61702f2010-09-05 22:20:24 +0000391#define NUM_PORT_STATS 8
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700392};
393
394struct mlx4_en_perf_stats {
395 u32 tx_poll;
396 u64 tx_pktsz_avg;
397 u32 inflight_avg;
398 u16 tx_coal_avg;
399 u16 rx_coal_avg;
400 u32 napi_quota;
401#define NUM_PERF_COUNTERS 6
402};
403
404struct mlx4_en_frag_info {
405 u16 frag_size;
406 u16 frag_prefix_size;
407 u16 frag_stride;
408 u16 frag_align;
409 u16 last_offset;
410
411};
412
413struct mlx4_en_priv {
414 struct mlx4_en_dev *mdev;
415 struct mlx4_en_port_profile *prof;
416 struct net_device *dev;
Jiri Pirkof1b553f2011-07-20 04:54:22 +0000417 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700418 struct net_device_stats stats;
419 struct net_device_stats ret_stats;
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000420 struct mlx4_en_port_state port_state;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700421 spinlock_t stats_lock;
422
Alexander Guller6b4d8d92011-10-09 05:38:23 +0000423 unsigned long last_moder_packets[MAX_RX_RINGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700424 unsigned long last_moder_tx_packets;
Alexander Guller6b4d8d92011-10-09 05:38:23 +0000425 unsigned long last_moder_bytes[MAX_RX_RINGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700426 unsigned long last_moder_jiffies;
Alexander Guller6b4d8d92011-10-09 05:38:23 +0000427 int last_moder_time[MAX_RX_RINGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700428 u16 rx_usecs;
429 u16 rx_frames;
430 u16 tx_usecs;
431 u16 tx_frames;
432 u32 pkt_rate_low;
433 u16 rx_usecs_low;
434 u32 pkt_rate_high;
435 u16 rx_usecs_high;
436 u16 sample_interval;
437 u16 adaptive_rx_coal;
438 u32 msg_enable;
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000439 u32 loopback_ok;
440 u32 validate_loopback;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700441
442 struct mlx4_hwq_resources res;
443 int link_state;
444 int last_link_state;
445 bool port_up;
446 int port;
447 int registered;
448 int allocated;
449 int stride;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700450 u64 mac;
451 int mac_index;
452 unsigned max_mtu;
453 int base_qpn;
454
455 struct mlx4_en_rss_map rss_map;
Or Gerlitz4ef2a432012-03-06 04:03:41 +0000456 __be32 ctrl_flags;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700457 u32 flags;
458#define MLX4_EN_FLAG_PROMISC 0x1
Yevgeny Petrilin16792002011-03-22 22:38:31 +0000459#define MLX4_EN_FLAG_MC_PROMISC 0x2
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700460 u32 tx_ring_num;
461 u32 rx_ring_num;
462 u32 rx_skb_size;
463 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
464 u16 num_frags;
465 u16 log_rx_info;
466
467 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
468 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
469 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
470 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
471 struct work_struct mcast_task;
472 struct work_struct mac_task;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700473 struct work_struct watchdog_task;
474 struct work_struct linkstate_task;
475 struct delayed_work stats_task;
476 struct mlx4_en_perf_stats pstats;
477 struct mlx4_en_pkt_stats pkstats;
478 struct mlx4_en_port_stats port_stats;
Eugenia Emantayev93ece0c2012-01-19 09:45:05 +0000479 u64 stats_bitmap;
Jiri Pirkoff6e2162010-03-01 05:09:14 +0000480 char *mc_addrs;
481 int mc_addrs_cnt;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700482 struct mlx4_en_stat_out_mbox hw_stats;
Eli Cohen4c3eb3c2010-08-26 17:19:22 +0300483 int vids[128];
Yevgeny Petrilin14c07b12011-03-22 22:37:59 +0000484 bool wol;
Yevgeny Petrilinebf8c9a2012-03-06 04:03:34 +0000485 struct device *ddev;
Yevgeny Petrilin14c07b12011-03-22 22:37:59 +0000486};
487
488enum mlx4_en_wol {
489 MLX4_EN_WOL_MAGIC = (1ULL << 61),
490 MLX4_EN_WOL_ENABLED = (1ULL << 62),
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700491};
492
Or Gerlitz0d9fdaa2011-11-26 19:55:06 +0000493#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700494
495void mlx4_en_destroy_netdev(struct net_device *dev);
496int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
497 struct mlx4_en_port_profile *prof);
498
Yevgeny Petrilin18cc42a2008-12-29 18:39:20 -0800499int mlx4_en_start_port(struct net_device *dev);
500void mlx4_en_stop_port(struct net_device *dev);
501
Alexander Gullerfe0af032011-10-09 05:26:46 +0000502void mlx4_en_free_resources(struct mlx4_en_priv *priv);
Yevgeny Petrilin18cc42a2008-12-29 18:39:20 -0800503int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
504
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700505int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
506 int entries, int ring, enum cq_type mode);
Alexander Gullerfe0af032011-10-09 05:26:46 +0000507void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
Alexander Guller76532d02011-10-09 05:26:31 +0000508int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
509 int cq_idx);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700510void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
511int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
512int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
513
514void mlx4_en_poll_tx_cq(unsigned long data);
515void mlx4_en_tx_irq(struct mlx4_cq *mcq);
Yevgeny Petrilinf813cad2009-06-01 23:24:07 +0000516u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
Stephen Hemminger613573252009-08-31 19:50:58 +0000517netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700518
519int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
Yevgeny Petrilin87a5c382011-03-22 22:38:52 +0000520 int qpn, u32 size, u16 stride);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700521void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
522int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
523 struct mlx4_en_tx_ring *ring,
Yevgeny Petrilin9f519f62009-08-06 19:28:18 -0700524 int cq);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700525void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
526 struct mlx4_en_tx_ring *ring);
527
528int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
529 struct mlx4_en_rx_ring *ring,
530 u32 size, u16 stride);
531void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
Thadeu Lima de Souza Cascardo68355f72012-02-06 08:39:49 +0000532 struct mlx4_en_rx_ring *ring,
533 u32 size, u16 stride);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700534int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
535void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
536 struct mlx4_en_rx_ring *ring);
537int mlx4_en_process_rx_cq(struct net_device *dev,
538 struct mlx4_en_cq *cq,
539 int budget);
540int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
541void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
Yevgeny Petrilin9f519f62009-08-06 19:28:18 -0700542 int is_tx, int rss, int qpn, int cqn,
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700543 struct mlx4_qp_context *context);
Yevgeny Petrilin966508f2009-04-20 04:30:03 +0000544void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700545int mlx4_en_map_buffer(struct mlx4_buf *buf);
546void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
547
548void mlx4_en_calc_rx_buf(struct net_device *dev);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700549int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
550void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
551int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700552void mlx4_en_rx_irq(struct mlx4_cq *mcq);
553
554int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
Jiri Pirkof1b553f2011-07-20 04:54:22 +0000555int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700556
557int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000558int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
559
560#define MLX4_EN_NUM_SELF_TEST 5
561void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
562u64 mlx4_en_mac_to_u64(u8 *addr);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700563
564/*
565 * Globals
566 */
567extern const struct ethtool_ops mlx4_en_ethtool_ops;
Joe Perches0a645e82010-07-10 07:22:46 +0000568
569
570
571/*
572 * printk / logging functions
573 */
574
Joe Perchesb9075fa2011-10-31 17:11:33 -0700575__printf(3, 4)
Joe Perches0a645e82010-07-10 07:22:46 +0000576int en_print(const char *level, const struct mlx4_en_priv *priv,
Joe Perchesb9075fa2011-10-31 17:11:33 -0700577 const char *format, ...);
Joe Perches0a645e82010-07-10 07:22:46 +0000578
579#define en_dbg(mlevel, priv, format, arg...) \
580do { \
581 if (NETIF_MSG_##mlevel & priv->msg_enable) \
582 en_print(KERN_DEBUG, priv, format, ##arg); \
583} while (0)
584#define en_warn(priv, format, arg...) \
585 en_print(KERN_WARNING, priv, format, ##arg)
586#define en_err(priv, format, arg...) \
587 en_print(KERN_ERR, priv, format, ##arg)
Yevgeny Petriline5cc44b2010-08-24 03:46:01 +0000588#define en_info(priv, format, arg...) \
589 en_print(KERN_INFO, priv, format, ## arg)
Joe Perches0a645e82010-07-10 07:22:46 +0000590
591#define mlx4_err(mdev, format, arg...) \
592 pr_err("%s %s: " format, DRV_NAME, \
593 dev_name(&mdev->pdev->dev), ##arg)
594#define mlx4_info(mdev, format, arg...) \
595 pr_info("%s %s: " format, DRV_NAME, \
596 dev_name(&mdev->pdev->dev), ##arg)
597#define mlx4_warn(mdev, format, arg...) \
598 pr_warning("%s %s: " format, DRV_NAME, \
599 dev_name(&mdev->pdev->dev), ##arg)
600
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700601#endif