blob: 9a09a1b11ca5575a9415317977a64f609cacc0da [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov80b89872007-08-10 21:02:15 +040011 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 *
14 * TODO
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 * Work out best PLL policy
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt3x2n"
Sergei Shtylyov5600c702009-11-27 22:29:02 +040028#define DRV_VERSION "0.3.7"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30enum {
31 HPT_PCI_FAST = (1 << 31),
32 PCI66 = (1 << 1),
33 USE_DPLL = (1 << 0)
34};
35
36struct hpt_clock {
37 u8 xfer_speed;
38 u32 timing;
39};
40
41struct hpt_chip {
42 const char *name;
43 struct hpt_clock *clocks[3];
44};
45
46/* key for bus clock timings
47 * bit
48 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
49 * DMA. cycles = value + 1
50 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
51 * DMA. cycles = value + 1
52 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
53 * register access.
54 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
55 * register access.
56 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
57 * during task file register access.
58 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
59 * xfer.
60 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
61 * register access.
62 * 28 UDMA enable
63 * 29 DMA enable
64 * 30 PIO_MST enable. if set, the chip is in bus master mode during
65 * PIO.
66 * 31 FIFO enable.
67 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040068
Jeff Garzik669a5db2006-08-29 18:12:40 -040069/* 66MHz DPLL clocks */
70
71static struct hpt_clock hpt3x2n_clocks[] = {
72 { XFER_UDMA_7, 0x1c869c62 },
73 { XFER_UDMA_6, 0x1c869c62 },
74 { XFER_UDMA_5, 0x1c8a9c62 },
75 { XFER_UDMA_4, 0x1c8a9c62 },
76 { XFER_UDMA_3, 0x1c8e9c62 },
77 { XFER_UDMA_2, 0x1c929c62 },
78 { XFER_UDMA_1, 0x1c9a9c62 },
79 { XFER_UDMA_0, 0x1c829c62 },
80
81 { XFER_MW_DMA_2, 0x2c829c62 },
82 { XFER_MW_DMA_1, 0x2c829c66 },
Bartlomiej Zolnierkiewiczd413ff32009-12-03 20:32:09 +010083 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -040084
85 { XFER_PIO_4, 0x0c829c62 },
86 { XFER_PIO_3, 0x0c829c84 },
87 { XFER_PIO_2, 0x0c829ca6 },
88 { XFER_PIO_1, 0x0d029d26 },
89 { XFER_PIO_0, 0x0d029d5e },
Jeff Garzik669a5db2006-08-29 18:12:40 -040090};
91
92/**
93 * hpt3x2n_find_mode - reset the hpt3x2n bus
94 * @ap: ATA port
95 * @speed: transfer mode
96 *
97 * Return the 32bit register programming information for this channel
98 * that matches the speed provided. For the moment the clocks table
99 * is hard coded but easy to change. This will be needed if we use
100 * different DPLLs
101 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400102
Jeff Garzik669a5db2006-08-29 18:12:40 -0400103static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
104{
105 struct hpt_clock *clocks = hpt3x2n_clocks;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400106
Jeff Garzik669a5db2006-08-29 18:12:40 -0400107 while(clocks->xfer_speed) {
108 if (clocks->xfer_speed == speed)
109 return clocks->timing;
110 clocks++;
111 }
112 BUG();
113 return 0xffffffffU; /* silence compiler warning */
114}
115
116/**
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500117 * hpt3x2n_cable_detect - Detect the cable type
118 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400119 *
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500120 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400121 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400122
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500123static int hpt3x2n_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400124{
125 u8 scr2, ata66;
126 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400127
Jeff Garzik669a5db2006-08-29 18:12:40 -0400128 pci_read_config_byte(pdev, 0x5B, &scr2);
129 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
Bartlomiej Zolnierkiewicz10a9c962009-11-19 20:31:31 +0100130
131 udelay(10); /* debounce */
132
Jeff Garzik669a5db2006-08-29 18:12:40 -0400133 /* Cable register now active */
134 pci_read_config_byte(pdev, 0x5A, &ata66);
135 /* Restore state */
136 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400137
Bartlomiej Zolnierkiewiczf3b1cf42009-11-19 18:38:11 +0100138 if (ata66 & (2 >> ap->port_no))
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500139 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140 else
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500141 return ATA_CBL_PATA80;
142}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400143
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500144/**
145 * hpt3x2n_pre_reset - reset the hpt3x2n bus
Tejun Heocc0680a2007-08-06 18:36:23 +0900146 * @link: ATA link to reset
Alan Cox28e21c82007-04-26 00:19:25 -0700147 * @deadline: deadline jiffies for the operation
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500148 *
149 * Perform the initial reset handling for the 3x2n series controllers.
150 * Reset the hardware and state machine,
151 */
152
Tejun Heoa1efdab2008-03-25 12:22:50 +0900153static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500154{
Tejun Heocc0680a2007-08-06 18:36:23 +0900155 struct ata_port *ap = link->ap;
Jeff Garzika0fcdc02007-03-09 07:24:15 -0500156 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400157 /* Reset the state machine */
Alan Cox28e21c82007-04-26 00:19:25 -0700158 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400159 udelay(100);
Tejun Heod4b2bab2007-02-02 16:50:52 +0900160
Tejun Heo9363c382008-04-07 22:47:16 +0900161 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400163
Jeff Garzik669a5db2006-08-29 18:12:40 -0400164/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 * hpt3x2n_set_piomode - PIO setup
166 * @ap: ATA interface
167 * @adev: device on the interface
168 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400169 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400170 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400171
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
173{
174 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
175 u32 addr1, addr2;
176 u32 reg;
177 u32 mode;
178 u8 fast;
179
180 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
181 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400182
Jeff Garzik669a5db2006-08-29 18:12:40 -0400183 /* Fast interrupt prediction disable, hold off interrupt disable */
184 pci_read_config_byte(pdev, addr2, &fast);
185 fast &= ~0x07;
186 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400187
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188 pci_read_config_dword(pdev, addr1, &reg);
189 mode = hpt3x2n_find_mode(ap, adev->pio_mode);
Sergei Shtylyov5600c702009-11-27 22:29:02 +0400190 mode &= 0xCFC3FFFF; /* Leave DMA bits alone */
191 reg &= ~0xCFC3FFFF; /* Strip timing bits */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400192 pci_write_config_dword(pdev, addr1, reg | mode);
193}
194
195/**
196 * hpt3x2n_set_dmamode - DMA timing setup
197 * @ap: ATA interface
198 * @adev: Device being configured
199 *
200 * Set up the channel for MWDMA or UDMA modes. Much the same as with
201 * PIO, load the mode number and then set MWDMA or UDMA flag.
202 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400203
Jeff Garzik669a5db2006-08-29 18:12:40 -0400204static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
205{
206 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
207 u32 addr1, addr2;
Sergei Shtylyov5600c702009-11-27 22:29:02 +0400208 u32 reg, mode, mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400209 u8 fast;
210
211 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
212 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214 /* Fast interrupt prediction disable, hold off interrupt disable */
215 pci_read_config_byte(pdev, addr2, &fast);
216 fast &= ~0x07;
217 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400218
Sergei Shtylyov5600c702009-11-27 22:29:02 +0400219 mask = adev->dma_mode < XFER_UDMA_0 ? 0x31C001FF : 0x303C0000;
220
Jeff Garzik669a5db2006-08-29 18:12:40 -0400221 pci_read_config_dword(pdev, addr1, &reg);
222 mode = hpt3x2n_find_mode(ap, adev->dma_mode);
Sergei Shtylyov5600c702009-11-27 22:29:02 +0400223 mode &= mask;
224 reg &= ~mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400225 pci_write_config_dword(pdev, addr1, reg | mode);
226}
227
228/**
229 * hpt3x2n_bmdma_end - DMA engine stop
230 * @qc: ATA command
231 *
232 * Clean up after the HPT3x2n and later DMA engine
233 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400234
Jeff Garzik669a5db2006-08-29 18:12:40 -0400235static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
236{
237 struct ata_port *ap = qc->ap;
238 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
239 int mscreg = 0x50 + 2 * ap->port_no;
240 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400241
Jeff Garzik669a5db2006-08-29 18:12:40 -0400242 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
243 pci_read_config_byte(pdev, mscreg, &msc_stat);
244 if (bwsr_stat & (1 << ap->port_no))
245 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
246 ata_bmdma_stop(qc);
247}
248
249/**
250 * hpt3x2n_set_clock - clock control
251 * @ap: ATA port
252 * @source: 0x21 or 0x23 for PLL or PCI sourced clock
253 *
254 * Switch the ATA bus clock between the PLL and PCI clock sources
255 * while correctly isolating the bus and resetting internal logic
256 *
257 * We must use the DPLL for
258 * - writing
259 * - second channel UDMA7 (SATA ports) or higher
260 * - 66MHz PCI
Jeff Garzik85cd7252006-08-31 00:03:49 -0400261 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400262 * or we will underclock the device and get reduced performance.
263 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400264
Jeff Garzik669a5db2006-08-29 18:12:40 -0400265static void hpt3x2n_set_clock(struct ata_port *ap, int source)
266{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900267 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400268
Jeff Garzik669a5db2006-08-29 18:12:40 -0400269 /* Tristate the bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900270 iowrite8(0x80, bmdma+0x73);
271 iowrite8(0x80, bmdma+0x77);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400272
Jeff Garzik669a5db2006-08-29 18:12:40 -0400273 /* Switch clock and reset channels */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900274 iowrite8(source, bmdma+0x7B);
275 iowrite8(0xC0, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400276
Jeff Garzik669a5db2006-08-29 18:12:40 -0400277 /* Reset state machines */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900278 iowrite8(0x37, bmdma+0x70);
279 iowrite8(0x37, bmdma+0x74);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400280
Jeff Garzik669a5db2006-08-29 18:12:40 -0400281 /* Complete reset */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900282 iowrite8(0x00, bmdma+0x79);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400283
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 /* Reconnect channels to bus */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900285 iowrite8(0x00, bmdma+0x73);
286 iowrite8(0x00, bmdma+0x77);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287}
288
289/* Check if our partner interface is busy */
290
291static int hpt3x2n_pair_idle(struct ata_port *ap)
292{
293 struct ata_host *host = ap->host;
294 struct ata_port *pair = host->ports[ap->port_no ^ 1];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400295
Jeff Garzik669a5db2006-08-29 18:12:40 -0400296 if (pair->hsm_task_state == HSM_ST_IDLE)
297 return 1;
298 return 0;
299}
300
Alana52865c2007-01-24 11:51:38 +0000301static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400302{
303 long flags = (long)ap->host->private_data;
304 /* See if we should use the DPLL */
Alana52865c2007-01-24 11:51:38 +0000305 if (writing)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400306 return USE_DPLL; /* Needed for write */
307 if (flags & PCI66)
308 return USE_DPLL; /* Needed at 66Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400309 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310}
311
Tejun Heo9363c382008-04-07 22:47:16 +0900312static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400313{
314 struct ata_taskfile *tf = &qc->tf;
315 struct ata_port *ap = qc->ap;
316 int flags = (long)ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400317
Jeff Garzik669a5db2006-08-29 18:12:40 -0400318 if (hpt3x2n_pair_idle(ap)) {
319 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
320 if ((flags & USE_DPLL) != dpll) {
321 if (dpll == 1)
322 hpt3x2n_set_clock(ap, 0x21);
323 else
324 hpt3x2n_set_clock(ap, 0x23);
325 }
326 }
Tejun Heo9363c382008-04-07 22:47:16 +0900327 return ata_sff_qc_issue(qc);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400328}
329
330static struct scsi_host_template hpt3x2n_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900331 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400332};
333
334/*
335 * Configuration for HPT3x2n.
336 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400337
Jeff Garzik669a5db2006-08-29 18:12:40 -0400338static struct ata_port_operations hpt3x2n_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900339 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400340
Jeff Garzik669a5db2006-08-29 18:12:40 -0400341 .bmdma_stop = hpt3x2n_bmdma_stop,
Tejun Heo9363c382008-04-07 22:47:16 +0900342 .qc_issue = hpt3x2n_qc_issue,
Jeff Garzikbda30282006-09-27 05:41:13 -0400343
Tejun Heo029cfd62008-03-25 12:22:49 +0900344 .cable_detect = hpt3x2n_cable_detect,
345 .set_piomode = hpt3x2n_set_piomode,
346 .set_dmamode = hpt3x2n_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900347 .prereset = hpt3x2n_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400348};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400349
350/**
351 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400352 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400353 *
354 * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
355 * succeeds
356 */
357
358static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
359{
360 u8 reg5b;
361 u32 reg5c;
362 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400363
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364 for(tries = 0; tries < 0x5000; tries++) {
365 udelay(50);
366 pci_read_config_byte(dev, 0x5b, &reg5b);
367 if (reg5b & 0x80) {
368 /* See if it stays set */
369 for(tries = 0; tries < 0x1000; tries ++) {
370 pci_read_config_byte(dev, 0x5b, &reg5b);
371 /* Failed ? */
372 if ((reg5b & 0x80) == 0)
373 return 0;
374 }
375 /* Turn off tuning, we have the DPLL set */
376 pci_read_config_dword(dev, 0x5c, &reg5c);
377 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
378 return 1;
379 }
380 }
381 /* Never went stable */
382 return 0;
383}
384
385static int hpt3x2n_pci_clock(struct pci_dev *pdev)
386{
387 unsigned long freq;
388 u32 fcnt;
Alan Cox28e21c82007-04-26 00:19:25 -0700389 unsigned long iobase = pci_resource_start(pdev, 4);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400390
Alan Cox28e21c82007-04-26 00:19:25 -0700391 fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400392 if ((fcnt >> 12) != 0xABCDE) {
393 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
394 return 33; /* Not BIOS set */
395 }
396 fcnt &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400397
Jeff Garzik669a5db2006-08-29 18:12:40 -0400398 freq = (fcnt * 77) / 192;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400399
Jeff Garzik669a5db2006-08-29 18:12:40 -0400400 /* Clamp to bands */
401 if (freq < 40)
402 return 33;
403 if (freq < 45)
404 return 40;
405 if (freq < 55)
406 return 50;
407 return 66;
408}
409
410/**
411 * hpt3x2n_init_one - Initialise an HPT37X/302
412 * @dev: PCI device
413 * @id: Entry in match table
414 *
415 * Initialise an HPT3x2n device. There are some interesting complications
416 * here. Firstly the chip may report 366 and be one of several variants.
417 * Secondly all the timings depend on the clock for the chip which we must
418 * detect and look up
419 *
420 * This is the known chip mappings. It may be missing a couple of later
421 * releases.
422 *
423 * Chip version PCI Rev Notes
424 * HPT372 4 (HPT366) 5 Other driver
425 * HPT372N 4 (HPT366) 6 UDMA133
426 * HPT372 5 (HPT372) 1 Other driver
427 * HPT372N 5 (HPT372) 2 UDMA133
428 * HPT302 6 (HPT302) * Other driver
429 * HPT302N 6 (HPT302) > 1 UDMA133
430 * HPT371 7 (HPT371) * Other driver
431 * HPT371N 7 (HPT371) > 1 UDMA133
432 * HPT374 8 (HPT374) * Other driver
433 * HPT372N 9 (HPT372N) * UDMA133
434 *
435 * (1) UDMA133 support depends on the bus clock
436 *
437 * To pin down HPT371N
438 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400439
Jeff Garzik669a5db2006-08-29 18:12:40 -0400440static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
441{
442 /* HPT372N and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200443 static const struct ata_port_info info = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400444 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100445 .pio_mask = ATA_PIO4,
446 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400447 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400448 .port_ops = &hpt3x2n_port_ops
449 };
Tejun Heo887125e2008-03-25 12:22:49 +0900450 const struct ata_port_info *ppi[] = { &info, NULL };
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400451 u8 rev = dev->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400452 u8 irqmask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400453 unsigned int pci_mhz;
454 unsigned int f_low, f_high;
455 int adjust;
Alan Cox28e21c82007-04-26 00:19:25 -0700456 unsigned long iobase = pci_resource_start(dev, 4);
Tejun Heo887125e2008-03-25 12:22:49 +0900457 void *hpriv = NULL;
Tejun Heof08048e2008-03-25 12:22:47 +0900458 int rc;
459
460 rc = pcim_enable_device(dev);
461 if (rc)
462 return rc;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400463
Jeff Garzik669a5db2006-08-29 18:12:40 -0400464 switch(dev->device) {
465 case PCI_DEVICE_ID_TTI_HPT366:
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400466 if (rev < 6)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400467 return -ENODEV;
468 break;
Alan Cox28e21c82007-04-26 00:19:25 -0700469 case PCI_DEVICE_ID_TTI_HPT371:
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400470 if (rev < 2)
Alan Cox28e21c82007-04-26 00:19:25 -0700471 return -ENODEV;
472 /* 371N if rev > 1 */
473 break;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400474 case PCI_DEVICE_ID_TTI_HPT372:
Alan Cox824cf332007-05-21 14:57:01 +0100475 /* 372N if rev >= 2*/
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400476 if (rev < 2)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400477 return -ENODEV;
478 break;
479 case PCI_DEVICE_ID_TTI_HPT302:
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400480 if (rev < 2)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400481 return -ENODEV;
482 break;
483 case PCI_DEVICE_ID_TTI_HPT372N:
484 break;
485 default:
486 printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
487 return -ENODEV;
488 }
489
490 /* Ok so this is a chip we support */
491
492 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
493 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
494 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
495 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
496
497 pci_read_config_byte(dev, 0x5A, &irqmask);
498 irqmask &= ~0x10;
499 pci_write_config_byte(dev, 0x5a, irqmask);
500
Alan Cox28e21c82007-04-26 00:19:25 -0700501 /*
502 * HPT371 chips physically have only one channel, the secondary one,
503 * but the primary channel registers do exist! Go figure...
504 * So, we manually disable the non-existing channel here
505 * (if the BIOS hasn't done this already).
506 */
507 if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
508 u8 mcr1;
509 pci_read_config_byte(dev, 0x50, &mcr1);
510 mcr1 &= ~0x04;
511 pci_write_config_byte(dev, 0x50, mcr1);
512 }
513
Jeff Garzik669a5db2006-08-29 18:12:40 -0400514 /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
515 50 for UDMA100. Right now we always use 66 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400516
Jeff Garzik669a5db2006-08-29 18:12:40 -0400517 pci_mhz = hpt3x2n_pci_clock(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400518
Jeff Garzik669a5db2006-08-29 18:12:40 -0400519 f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
520 f_high = f_low + 2; /* Tolerance */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400521
Jeff Garzik669a5db2006-08-29 18:12:40 -0400522 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
523 /* PLL clock */
524 pci_write_config_byte(dev, 0x5B, 0x21);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400525
Jeff Garzik669a5db2006-08-29 18:12:40 -0400526 /* Unlike the 37x we don't try jiggling the frequency */
527 for(adjust = 0; adjust < 8; adjust++) {
528 if (hpt3xn_calibrate_dpll(dev))
529 break;
530 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
531 }
Alan Cox28e21c82007-04-26 00:19:25 -0700532 if (adjust == 8) {
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400533 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
Alan Cox28e21c82007-04-26 00:19:25 -0700534 return -ENODEV;
535 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400536
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400537 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
538 pci_mhz);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400539 /* Set our private data up. We only need a few flags so we use
540 it directly */
Alan Cox28e21c82007-04-26 00:19:25 -0700541 if (pci_mhz > 60) {
Tejun Heo887125e2008-03-25 12:22:49 +0900542 hpriv = (void *)PCI66;
Alan Cox28e21c82007-04-26 00:19:25 -0700543 /*
544 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
545 * the MISC. register to stretch the UltraDMA Tss timing.
546 * NOTE: This register is only writeable via I/O space.
547 */
548 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
549 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
550 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400551
Jeff Garzik669a5db2006-08-29 18:12:40 -0400552 /* Now kick off ATA set up */
Tejun Heo9363c382008-04-07 22:47:16 +0900553 return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400554}
555
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400556static const struct pci_device_id hpt3x2n[] = {
557 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
Alan Cox28e21c82007-04-26 00:19:25 -0700558 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400559 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
560 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
561 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
562
563 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400564};
565
566static struct pci_driver hpt3x2n_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400567 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400568 .id_table = hpt3x2n,
569 .probe = hpt3x2n_init_one,
570 .remove = ata_pci_remove_one
571};
572
573static int __init hpt3x2n_init(void)
574{
575 return pci_register_driver(&hpt3x2n_pci_driver);
576}
577
Jeff Garzik669a5db2006-08-29 18:12:40 -0400578static void __exit hpt3x2n_exit(void)
579{
580 pci_unregister_driver(&hpt3x2n_pci_driver);
581}
582
Jeff Garzik669a5db2006-08-29 18:12:40 -0400583MODULE_AUTHOR("Alan Cox");
584MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
585MODULE_LICENSE("GPL");
586MODULE_DEVICE_TABLE(pci, hpt3x2n);
587MODULE_VERSION(DRV_VERSION);
588
589module_init(hpt3x2n_init);
590module_exit(hpt3x2n_exit);