blob: cd8de29e38cc289c94101c480d9f410d6f614e4c [file] [log] [blame]
Scott Wood76b10462008-02-06 15:36:21 -06001/* Freescale Enhanced Local Bus Controller NAND driver
2 *
Roy Zang3ab8f2a2010-10-18 15:22:31 +08003 * Copyright © 2006-2007, 2010 Freescale Semiconductor
Scott Wood76b10462008-02-06 15:36:21 -06004 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
Roy Zang3ab8f2a2010-10-18 15:22:31 +08007 * Jack Lan <jack.lan@freescale.com>
8 * Roy Zang <tie-fei.zang@freescale.com>
Scott Wood76b10462008-02-06 15:36:21 -06009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include <linux/module.h>
26#include <linux/types.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/string.h>
30#include <linux/ioport.h>
31#include <linux/of_platform.h>
Roy Zang3ab8f2a2010-10-18 15:22:31 +080032#include <linux/platform_device.h>
Scott Wood76b10462008-02-06 15:36:21 -060033#include <linux/slab.h>
34#include <linux/interrupt.h>
35
36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/nand_ecc.h>
39#include <linux/mtd/partitions.h>
40
41#include <asm/io.h>
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +030042#include <asm/fsl_lbc.h>
Scott Wood76b10462008-02-06 15:36:21 -060043
44#define MAX_BANKS 8
45#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
46#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
47
Scott Wood76b10462008-02-06 15:36:21 -060048/* mtd information per set */
49
50struct fsl_elbc_mtd {
51 struct mtd_info mtd;
52 struct nand_chip chip;
Roy Zang3ab8f2a2010-10-18 15:22:31 +080053 struct fsl_lbc_ctrl *ctrl;
Scott Wood76b10462008-02-06 15:36:21 -060054
55 struct device *dev;
56 int bank; /* Chip select bank number */
57 u8 __iomem *vbase; /* Chip select base virtual address */
58 int page_size; /* NAND page size (0=512, 1=2048) */
59 unsigned int fmr; /* FCM Flash Mode Register value */
60};
61
Roy Zang3ab8f2a2010-10-18 15:22:31 +080062/* Freescale eLBC FCM controller infomation */
Scott Wood76b10462008-02-06 15:36:21 -060063
Roy Zang3ab8f2a2010-10-18 15:22:31 +080064struct fsl_elbc_fcm_ctrl {
Scott Wood76b10462008-02-06 15:36:21 -060065 struct nand_hw_control controller;
66 struct fsl_elbc_mtd *chips[MAX_BANKS];
67
Scott Wood76b10462008-02-06 15:36:21 -060068 u8 __iomem *addr; /* Address of assigned FCM buffer */
69 unsigned int page; /* Last page written to / read from */
70 unsigned int read_bytes; /* Number of bytes read during command */
71 unsigned int column; /* Saved column from SEQIN */
72 unsigned int index; /* Pointer to next byte to 'read' */
73 unsigned int status; /* status read from LTESR after last op */
74 unsigned int mdr; /* UPM/FCM Data Register value */
75 unsigned int use_mdr; /* Non zero if the MDR is to be set */
76 unsigned int oob; /* Non zero if operating on OOB data */
Roy Zang3ab8f2a2010-10-18 15:22:31 +080077 unsigned int counter; /* counter for the initializations */
Scott Wood76b10462008-02-06 15:36:21 -060078 char *oob_poi; /* Place to write ECC after read back */
79};
80
81/* These map to the positions used by the FCM hardware ECC generator */
82
83/* Small Page FLASH with FMR[ECCM] = 0 */
84static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
85 .eccbytes = 3,
86 .eccpos = {6, 7, 8},
87 .oobfree = { {0, 5}, {9, 7} },
Scott Wood76b10462008-02-06 15:36:21 -060088};
89
90/* Small Page FLASH with FMR[ECCM] = 1 */
91static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
92 .eccbytes = 3,
93 .eccpos = {8, 9, 10},
94 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
Scott Wood76b10462008-02-06 15:36:21 -060095};
96
97/* Large Page FLASH with FMR[ECCM] = 0 */
98static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
99 .eccbytes = 12,
100 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
101 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
Scott Wood76b10462008-02-06 15:36:21 -0600102};
103
104/* Large Page FLASH with FMR[ECCM] = 1 */
105static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
106 .eccbytes = 12,
107 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
108 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
Scott Wood76b10462008-02-06 15:36:21 -0600109};
110
Anton Vorontsov452db272008-06-27 23:04:04 +0400111/*
112 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
113 * 1, so we have to adjust bad block pattern. This pattern should be used for
114 * x8 chips only. So far hardware does not support x16 chips anyway.
115 */
116static u8 scan_ff_pattern[] = { 0xff, };
117
118static struct nand_bbt_descr largepage_memorybased = {
119 .options = 0,
120 .offs = 0,
121 .len = 1,
122 .pattern = scan_ff_pattern,
123};
124
Anton Vorontsovec6e0ea2008-06-27 23:04:13 +0400125/*
126 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
127 * interfere with ECC positions, that's why we implement our own descriptors.
128 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
129 */
130static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
131static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
132
133static struct nand_bbt_descr bbt_main_descr = {
134 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
135 NAND_BBT_2BIT | NAND_BBT_VERSION,
136 .offs = 11,
137 .len = 4,
138 .veroffs = 15,
139 .maxblocks = 4,
140 .pattern = bbt_pattern,
141};
142
143static struct nand_bbt_descr bbt_mirror_descr = {
144 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
145 NAND_BBT_2BIT | NAND_BBT_VERSION,
146 .offs = 11,
147 .len = 4,
148 .veroffs = 15,
149 .maxblocks = 4,
150 .pattern = mirror_pattern,
151};
152
Scott Wood76b10462008-02-06 15:36:21 -0600153/*=================================*/
154
155/*
156 * Set up the FCM hardware block and page address fields, and the fcm
157 * structure addr field to point to the correct FCM buffer in memory
158 */
159static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
160{
161 struct nand_chip *chip = mtd->priv;
162 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800163 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +0300164 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800165 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600166 int buf_num;
167
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800168 elbc_fcm_ctrl->page = page_addr;
Scott Wood76b10462008-02-06 15:36:21 -0600169
170 out_be32(&lbc->fbar,
171 page_addr >> (chip->phys_erase_shift - chip->page_shift));
172
173 if (priv->page_size) {
174 out_be32(&lbc->fpar,
175 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
176 (oob ? FPAR_LP_MS : 0) | column);
177 buf_num = (page_addr & 1) << 2;
178 } else {
179 out_be32(&lbc->fpar,
180 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
181 (oob ? FPAR_SP_MS : 0) | column);
182 buf_num = page_addr & 7;
183 }
184
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800185 elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
186 elbc_fcm_ctrl->index = column;
Scott Wood76b10462008-02-06 15:36:21 -0600187
188 /* for OOB data point to the second half of the buffer */
189 if (oob)
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800190 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
Scott Wood76b10462008-02-06 15:36:21 -0600191
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800192 dev_vdbg(priv->dev, "set_addr: bank=%d, "
193 "elbc_fcm_ctrl->addr=0x%p (0x%p), "
Scott Wood76b10462008-02-06 15:36:21 -0600194 "index %x, pes %d ps %d\n",
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800195 buf_num, elbc_fcm_ctrl->addr, priv->vbase,
196 elbc_fcm_ctrl->index,
Scott Wood76b10462008-02-06 15:36:21 -0600197 chip->phys_erase_shift, chip->page_shift);
198}
199
200/*
201 * execute FCM command and wait for it to complete
202 */
203static int fsl_elbc_run_command(struct mtd_info *mtd)
204{
205 struct nand_chip *chip = mtd->priv;
206 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800207 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
208 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +0300209 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Scott Wood76b10462008-02-06 15:36:21 -0600210
211 /* Setup the FMR[OP] to execute without write protection */
212 out_be32(&lbc->fmr, priv->fmr | 3);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800213 if (elbc_fcm_ctrl->use_mdr)
214 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
Scott Wood76b10462008-02-06 15:36:21 -0600215
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800216 dev_vdbg(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600217 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
218 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800219 dev_vdbg(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600220 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
221 "fbcr=%08x bank=%d\n",
222 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
223 in_be32(&lbc->fbcr), priv->bank);
224
Mike Hench1938de42008-03-19 12:40:15 -0500225 ctrl->irq_status = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600226 /* execute special operation */
227 out_be32(&lbc->lsor, priv->bank);
228
229 /* wait for FCM complete flag or timeout */
Scott Wood76b10462008-02-06 15:36:21 -0600230 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
231 FCM_TIMEOUT_MSECS * HZ/1000);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800232 elbc_fcm_ctrl->status = ctrl->irq_status;
Scott Wood76b10462008-02-06 15:36:21 -0600233 /* store mdr value in case it was needed */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800234 if (elbc_fcm_ctrl->use_mdr)
235 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
Scott Wood76b10462008-02-06 15:36:21 -0600236
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800237 elbc_fcm_ctrl->use_mdr = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600238
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800239 if (elbc_fcm_ctrl->status != LTESR_CC) {
240 dev_info(priv->dev,
Scott Woodc1317f72009-11-13 14:14:15 -0600241 "command failed: fir %x fcr %x status %x mdr %x\n",
242 in_be32(&lbc->fir), in_be32(&lbc->fcr),
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800243 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
Scott Woodc1317f72009-11-13 14:14:15 -0600244 return -EIO;
245 }
Scott Wood76b10462008-02-06 15:36:21 -0600246
Scott Woodc1317f72009-11-13 14:14:15 -0600247 return 0;
Scott Wood76b10462008-02-06 15:36:21 -0600248}
249
250static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
251{
252 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800253 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +0300254 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Scott Wood76b10462008-02-06 15:36:21 -0600255
256 if (priv->page_size) {
257 out_be32(&lbc->fir,
Scott Wood476459a2009-11-13 14:13:01 -0600258 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600259 (FIR_OP_CA << FIR_OP1_SHIFT) |
260 (FIR_OP_PA << FIR_OP2_SHIFT) |
Scott Wood476459a2009-11-13 14:13:01 -0600261 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600262 (FIR_OP_RBW << FIR_OP4_SHIFT));
263
264 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
265 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
266 } else {
267 out_be32(&lbc->fir,
Scott Wood476459a2009-11-13 14:13:01 -0600268 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600269 (FIR_OP_CA << FIR_OP1_SHIFT) |
270 (FIR_OP_PA << FIR_OP2_SHIFT) |
271 (FIR_OP_RBW << FIR_OP3_SHIFT));
272
273 if (oob)
274 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
275 else
276 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
277 }
278}
279
280/* cmdfunc send commands to the FCM */
281static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
282 int column, int page_addr)
283{
284 struct nand_chip *chip = mtd->priv;
285 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800286 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
287 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +0300288 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Scott Wood76b10462008-02-06 15:36:21 -0600289
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800290 elbc_fcm_ctrl->use_mdr = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600291
292 /* clear the read buffer */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800293 elbc_fcm_ctrl->read_bytes = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600294 if (command != NAND_CMD_PAGEPROG)
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800295 elbc_fcm_ctrl->index = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600296
297 switch (command) {
298 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
299 case NAND_CMD_READ1:
300 column += 256;
301
302 /* fall-through */
303 case NAND_CMD_READ0:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800304 dev_dbg(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600305 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
306 " 0x%x, column: 0x%x.\n", page_addr, column);
307
308
309 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
310 set_addr(mtd, 0, page_addr, 0);
311
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800312 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
313 elbc_fcm_ctrl->index += column;
Scott Wood76b10462008-02-06 15:36:21 -0600314
315 fsl_elbc_do_read(chip, 0);
316 fsl_elbc_run_command(mtd);
317 return;
318
319 /* READOOB reads only the OOB because no ECC is performed. */
320 case NAND_CMD_READOOB:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800321 dev_vdbg(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600322 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
323 " 0x%x, column: 0x%x.\n", page_addr, column);
324
325 out_be32(&lbc->fbcr, mtd->oobsize - column);
326 set_addr(mtd, column, page_addr, 1);
327
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800328 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
Scott Wood76b10462008-02-06 15:36:21 -0600329
330 fsl_elbc_do_read(chip, 1);
331 fsl_elbc_run_command(mtd);
332 return;
333
334 /* READID must read all 5 possible bytes while CEB is active */
335 case NAND_CMD_READID:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800336 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
Scott Wood76b10462008-02-06 15:36:21 -0600337
Scott Wood476459a2009-11-13 14:13:01 -0600338 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600339 (FIR_OP_UA << FIR_OP1_SHIFT) |
340 (FIR_OP_RBW << FIR_OP2_SHIFT));
341 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
342 /* 5 bytes for manuf, device and exts */
343 out_be32(&lbc->fbcr, 5);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800344 elbc_fcm_ctrl->read_bytes = 5;
345 elbc_fcm_ctrl->use_mdr = 1;
346 elbc_fcm_ctrl->mdr = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600347
348 set_addr(mtd, 0, 0, 0);
349 fsl_elbc_run_command(mtd);
350 return;
351
352 /* ERASE1 stores the block and page address */
353 case NAND_CMD_ERASE1:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800354 dev_vdbg(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600355 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
356 "page_addr: 0x%x.\n", page_addr);
357 set_addr(mtd, 0, page_addr, 0);
358 return;
359
360 /* ERASE2 uses the block and page address from ERASE1 */
361 case NAND_CMD_ERASE2:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800362 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
Scott Wood76b10462008-02-06 15:36:21 -0600363
364 out_be32(&lbc->fir,
Scott Wood476459a2009-11-13 14:13:01 -0600365 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600366 (FIR_OP_PA << FIR_OP1_SHIFT) |
Scott Wood476459a2009-11-13 14:13:01 -0600367 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
368 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
369 (FIR_OP_RS << FIR_OP4_SHIFT));
Scott Wood76b10462008-02-06 15:36:21 -0600370
371 out_be32(&lbc->fcr,
372 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
Scott Wood476459a2009-11-13 14:13:01 -0600373 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
374 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
Scott Wood76b10462008-02-06 15:36:21 -0600375
376 out_be32(&lbc->fbcr, 0);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800377 elbc_fcm_ctrl->read_bytes = 0;
378 elbc_fcm_ctrl->use_mdr = 1;
Scott Wood76b10462008-02-06 15:36:21 -0600379
380 fsl_elbc_run_command(mtd);
381 return;
382
383 /* SEQIN sets up the addr buffer and all registers except the length */
384 case NAND_CMD_SEQIN: {
385 __be32 fcr;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800386 dev_vdbg(priv->dev,
387 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
Scott Wood76b10462008-02-06 15:36:21 -0600388 "page_addr: 0x%x, column: 0x%x.\n",
389 page_addr, column);
390
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800391 elbc_fcm_ctrl->use_mdr = 1;
Scott Wood476459a2009-11-13 14:13:01 -0600392
393 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
394 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
395 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
Scott Wood76b10462008-02-06 15:36:21 -0600396
Scott Wood76b10462008-02-06 15:36:21 -0600397 if (priv->page_size) {
398 out_be32(&lbc->fir,
Scott Wood476459a2009-11-13 14:13:01 -0600399 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600400 (FIR_OP_CA << FIR_OP1_SHIFT) |
401 (FIR_OP_PA << FIR_OP2_SHIFT) |
402 (FIR_OP_WB << FIR_OP3_SHIFT) |
Scott Wood476459a2009-11-13 14:13:01 -0600403 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
404 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
405 (FIR_OP_RS << FIR_OP6_SHIFT));
Scott Wood76b10462008-02-06 15:36:21 -0600406 } else {
407 out_be32(&lbc->fir,
Scott Wood476459a2009-11-13 14:13:01 -0600408 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
Scott Wood76b10462008-02-06 15:36:21 -0600409 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
410 (FIR_OP_CA << FIR_OP2_SHIFT) |
411 (FIR_OP_PA << FIR_OP3_SHIFT) |
412 (FIR_OP_WB << FIR_OP4_SHIFT) |
Scott Wood476459a2009-11-13 14:13:01 -0600413 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
414 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
415 (FIR_OP_RS << FIR_OP7_SHIFT));
Scott Wood76b10462008-02-06 15:36:21 -0600416
417 if (column >= mtd->writesize) {
418 /* OOB area --> READOOB */
419 column -= mtd->writesize;
420 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800421 elbc_fcm_ctrl->oob = 1;
Scott Wood476459a2009-11-13 14:13:01 -0600422 } else {
423 WARN_ON(column != 0);
Scott Wood76b10462008-02-06 15:36:21 -0600424 /* First 256 bytes --> READ0 */
425 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
Scott Wood76b10462008-02-06 15:36:21 -0600426 }
427 }
428
429 out_be32(&lbc->fcr, fcr);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800430 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
Scott Wood76b10462008-02-06 15:36:21 -0600431 return;
432 }
433
434 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
435 case NAND_CMD_PAGEPROG: {
436 int full_page;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800437 dev_vdbg(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600438 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800439 "writing %d bytes.\n", elbc_fcm_ctrl->index);
Scott Wood76b10462008-02-06 15:36:21 -0600440
441 /* if the write did not start at 0 or is not a full page
442 * then set the exact length, otherwise use a full page
443 * write so the HW generates the ECC.
444 */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800445 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
446 elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) {
447 out_be32(&lbc->fbcr, elbc_fcm_ctrl->index);
Scott Wood76b10462008-02-06 15:36:21 -0600448 full_page = 0;
449 } else {
450 out_be32(&lbc->fbcr, 0);
451 full_page = 1;
452 }
453
454 fsl_elbc_run_command(mtd);
455
456 /* Read back the page in order to fill in the ECC for the
457 * caller. Is this really needed?
458 */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800459 if (full_page && elbc_fcm_ctrl->oob_poi) {
Scott Wood76b10462008-02-06 15:36:21 -0600460 out_be32(&lbc->fbcr, 3);
461 set_addr(mtd, 6, page_addr, 1);
462
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800463 elbc_fcm_ctrl->read_bytes = mtd->writesize + 9;
Scott Wood76b10462008-02-06 15:36:21 -0600464
465 fsl_elbc_do_read(chip, 1);
466 fsl_elbc_run_command(mtd);
467
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800468 memcpy_fromio(elbc_fcm_ctrl->oob_poi + 6,
469 &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], 3);
470 elbc_fcm_ctrl->index += 3;
Scott Wood76b10462008-02-06 15:36:21 -0600471 }
472
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800473 elbc_fcm_ctrl->oob_poi = NULL;
Scott Wood76b10462008-02-06 15:36:21 -0600474 return;
475 }
476
477 /* CMD_STATUS must read the status byte while CEB is active */
478 /* Note - it does not wait for the ready line */
479 case NAND_CMD_STATUS:
480 out_be32(&lbc->fir,
481 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
482 (FIR_OP_RBW << FIR_OP1_SHIFT));
483 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
484 out_be32(&lbc->fbcr, 1);
485 set_addr(mtd, 0, 0, 0);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800486 elbc_fcm_ctrl->read_bytes = 1;
Scott Wood76b10462008-02-06 15:36:21 -0600487
488 fsl_elbc_run_command(mtd);
489
490 /* The chip always seems to report that it is
491 * write-protected, even when it is not.
492 */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800493 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
Scott Wood76b10462008-02-06 15:36:21 -0600494 return;
495
496 /* RESET without waiting for the ready line */
497 case NAND_CMD_RESET:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800498 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
Scott Wood76b10462008-02-06 15:36:21 -0600499 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
500 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
501 fsl_elbc_run_command(mtd);
502 return;
503
504 default:
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800505 dev_err(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600506 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
507 command);
508 }
509}
510
511static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
512{
513 /* The hardware does not seem to support multiple
514 * chips per bank.
515 */
516}
517
518/*
519 * Write buf to the FCM Controller Data Buffer
520 */
521static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
522{
523 struct nand_chip *chip = mtd->priv;
524 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800525 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600526 unsigned int bufsize = mtd->writesize + mtd->oobsize;
527
Anton Vorontsov0ff66312008-03-28 22:10:54 +0300528 if (len <= 0) {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800529 dev_err(priv->dev, "write_buf of %d bytes", len);
530 elbc_fcm_ctrl->status = 0;
Scott Wood76b10462008-02-06 15:36:21 -0600531 return;
532 }
533
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800534 if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
535 dev_err(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600536 "write_buf beyond end of buffer "
537 "(%d requested, %u available)\n",
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800538 len, bufsize - elbc_fcm_ctrl->index);
539 len = bufsize - elbc_fcm_ctrl->index;
Scott Wood76b10462008-02-06 15:36:21 -0600540 }
541
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800542 memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
Anton Vorontsov0ff66312008-03-28 22:10:54 +0300543 /*
544 * This is workaround for the weird elbc hangs during nand write,
545 * Scott Wood says: "...perhaps difference in how long it takes a
546 * write to make it through the localbus compared to a write to IMMR
547 * is causing problems, and sync isn't helping for some reason."
548 * Reading back the last byte helps though.
549 */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800550 in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
Anton Vorontsov0ff66312008-03-28 22:10:54 +0300551
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800552 elbc_fcm_ctrl->index += len;
Scott Wood76b10462008-02-06 15:36:21 -0600553}
554
555/*
556 * read a byte from either the FCM hardware buffer if it has any data left
557 * otherwise issue a command to read a single byte.
558 */
559static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
560{
561 struct nand_chip *chip = mtd->priv;
562 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800563 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600564
565 /* If there are still bytes in the FCM, then use the next byte. */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800566 if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
567 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
Scott Wood76b10462008-02-06 15:36:21 -0600568
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800569 dev_err(priv->dev, "read_byte beyond end of buffer\n");
Scott Wood76b10462008-02-06 15:36:21 -0600570 return ERR_BYTE;
571}
572
573/*
574 * Read from the FCM Controller Data Buffer
575 */
576static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
577{
578 struct nand_chip *chip = mtd->priv;
579 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800580 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600581 int avail;
582
583 if (len < 0)
584 return;
585
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800586 avail = min((unsigned int)len,
587 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
588 memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
589 elbc_fcm_ctrl->index += avail;
Scott Wood76b10462008-02-06 15:36:21 -0600590
591 if (len > avail)
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800592 dev_err(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600593 "read_buf beyond end of buffer "
594 "(%d requested, %d available)\n",
595 len, avail);
596}
597
598/*
599 * Verify buffer against the FCM Controller Data Buffer
600 */
601static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
602{
603 struct nand_chip *chip = mtd->priv;
604 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800605 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600606 int i;
607
608 if (len < 0) {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800609 dev_err(priv->dev, "write_buf of %d bytes", len);
Scott Wood76b10462008-02-06 15:36:21 -0600610 return -EINVAL;
611 }
612
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800613 if ((unsigned int)len >
614 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
615 dev_err(priv->dev,
616 "verify_buf beyond end of buffer "
617 "(%d requested, %u available)\n",
618 len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
Scott Wood76b10462008-02-06 15:36:21 -0600619
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800620 elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
Scott Wood76b10462008-02-06 15:36:21 -0600621 return -EINVAL;
622 }
623
624 for (i = 0; i < len; i++)
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800625 if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
626 != buf[i])
Scott Wood76b10462008-02-06 15:36:21 -0600627 break;
628
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800629 elbc_fcm_ctrl->index += len;
630 return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
Scott Wood76b10462008-02-06 15:36:21 -0600631}
632
633/* This function is called after Program and Erase Operations to
634 * check for success or failure.
635 */
636static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
637{
638 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800639 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600640
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800641 if (elbc_fcm_ctrl->status != LTESR_CC)
Scott Wood76b10462008-02-06 15:36:21 -0600642 return NAND_STATUS_FAIL;
643
644 /* The chip always seems to report that it is
645 * write-protected, even when it is not.
646 */
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800647 return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
Scott Wood76b10462008-02-06 15:36:21 -0600648}
649
650static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
651{
652 struct nand_chip *chip = mtd->priv;
653 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800654 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +0300655 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Scott Wood76b10462008-02-06 15:36:21 -0600656 unsigned int al;
657
658 /* calculate FMR Address Length field */
659 al = 0;
660 if (chip->pagemask & 0xffff0000)
661 al++;
662 if (chip->pagemask & 0xff000000)
663 al++;
664
665 /* add to ECCM mode set in fsl_elbc_init */
666 priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
667 (al << FMR_AL_SHIFT);
668
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800669 dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600670 chip->numchips);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800671 dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
Scott Wood76b10462008-02-06 15:36:21 -0600672 chip->chipsize);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800673 dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
Scott Wood76b10462008-02-06 15:36:21 -0600674 chip->pagemask);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800675 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600676 chip->chip_delay);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800677 dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600678 chip->badblockpos);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800679 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600680 chip->chip_shift);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800681 dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600682 chip->page_shift);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800683 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600684 chip->phys_erase_shift);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800685 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
Scott Wood76b10462008-02-06 15:36:21 -0600686 chip->ecclayout);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800687 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600688 chip->ecc.mode);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800689 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600690 chip->ecc.steps);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800691 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600692 chip->ecc.bytes);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800693 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600694 chip->ecc.total);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800695 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
Scott Wood76b10462008-02-06 15:36:21 -0600696 chip->ecc.layout);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800697 dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
698 dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
699 dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600700 mtd->erasesize);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800701 dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600702 mtd->writesize);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800703 dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
Scott Wood76b10462008-02-06 15:36:21 -0600704 mtd->oobsize);
705
706 /* adjust Option Register and ECC to match Flash page size */
707 if (mtd->writesize == 512) {
708 priv->page_size = 0;
Mike Hench1938de42008-03-19 12:40:15 -0500709 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
Scott Wood76b10462008-02-06 15:36:21 -0600710 } else if (mtd->writesize == 2048) {
711 priv->page_size = 1;
712 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
713 /* adjust ecc setup if needed */
714 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
715 BR_DECC_CHK_GEN) {
716 chip->ecc.size = 512;
717 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
718 &fsl_elbc_oob_lp_eccm1 :
719 &fsl_elbc_oob_lp_eccm0;
Anton Vorontsov452db272008-06-27 23:04:04 +0400720 chip->badblock_pattern = &largepage_memorybased;
Scott Wood76b10462008-02-06 15:36:21 -0600721 }
722 } else {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800723 dev_err(priv->dev,
Scott Wood76b10462008-02-06 15:36:21 -0600724 "fsl_elbc_init: page size %d is not supported\n",
725 mtd->writesize);
726 return -1;
727 }
728
Scott Wood76b10462008-02-06 15:36:21 -0600729 return 0;
730}
731
732static int fsl_elbc_read_page(struct mtd_info *mtd,
733 struct nand_chip *chip,
Sneha Narnakaje46a8cf22009-09-18 12:51:46 -0700734 uint8_t *buf,
735 int page)
Scott Wood76b10462008-02-06 15:36:21 -0600736{
737 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
738 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
739
740 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
741 mtd->ecc_stats.failed++;
742
743 return 0;
744}
745
746/* ECC will be calculated automatically, and errors will be detected in
747 * waitfunc.
748 */
749static void fsl_elbc_write_page(struct mtd_info *mtd,
750 struct nand_chip *chip,
751 const uint8_t *buf)
752{
753 struct fsl_elbc_mtd *priv = chip->priv;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800754 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600755
756 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
757 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
758
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800759 elbc_fcm_ctrl->oob_poi = chip->oob_poi;
Scott Wood76b10462008-02-06 15:36:21 -0600760}
761
762static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
763{
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800764 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
Anton Vorontsovd4a32fe2008-03-11 20:23:28 +0300765 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800766 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600767 struct nand_chip *chip = &priv->chip;
768
769 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
770
771 /* Fill in fsl_elbc_mtd structure */
772 priv->mtd.priv = chip;
773 priv->mtd.owner = THIS_MODULE;
Jason Jin03ed1072008-12-09 14:32:31 +0800774
775 /* Set the ECCM according to the settings in bootloader.*/
776 priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
Scott Wood76b10462008-02-06 15:36:21 -0600777
778 /* fill in nand_chip structure */
779 /* set up function call table */
780 chip->read_byte = fsl_elbc_read_byte;
781 chip->write_buf = fsl_elbc_write_buf;
782 chip->read_buf = fsl_elbc_read_buf;
783 chip->verify_buf = fsl_elbc_verify_buf;
784 chip->select_chip = fsl_elbc_select_chip;
785 chip->cmdfunc = fsl_elbc_cmdfunc;
786 chip->waitfunc = fsl_elbc_wait;
787
Anton Vorontsovec6e0ea2008-06-27 23:04:13 +0400788 chip->bbt_td = &bbt_main_descr;
789 chip->bbt_md = &bbt_mirror_descr;
790
Scott Wood76b10462008-02-06 15:36:21 -0600791 /* set up nand options */
Anton Vorontsovec6e0ea2008-06-27 23:04:13 +0400792 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
793 NAND_USE_FLASH_BBT;
Scott Wood76b10462008-02-06 15:36:21 -0600794
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800795 chip->controller = &elbc_fcm_ctrl->controller;
Scott Wood76b10462008-02-06 15:36:21 -0600796 chip->priv = priv;
797
798 chip->ecc.read_page = fsl_elbc_read_page;
799 chip->ecc.write_page = fsl_elbc_write_page;
800
801 /* If CS Base Register selects full hardware ECC then use it */
802 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
803 BR_DECC_CHK_GEN) {
804 chip->ecc.mode = NAND_ECC_HW;
805 /* put in small page settings and adjust later if needed */
806 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
807 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
808 chip->ecc.size = 512;
809 chip->ecc.bytes = 3;
810 } else {
811 /* otherwise fall back to default software ECC */
812 chip->ecc.mode = NAND_ECC_SOFT;
813 }
814
815 return 0;
816}
817
818static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
819{
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800820 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600821 nand_release(&priv->mtd);
822
Anton Vorontsov9ebed3e2008-03-18 19:34:03 +0300823 kfree(priv->mtd.name);
824
Scott Wood76b10462008-02-06 15:36:21 -0600825 if (priv->vbase)
826 iounmap(priv->vbase);
827
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800828 elbc_fcm_ctrl->chips[priv->bank] = NULL;
Scott Wood76b10462008-02-06 15:36:21 -0600829 kfree(priv);
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800830 kfree(elbc_fcm_ctrl);
Scott Wood76b10462008-02-06 15:36:21 -0600831 return 0;
832}
833
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800834static DEFINE_MUTEX(fsl_elbc_nand_mutex);
835
836static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
Scott Wood76b10462008-02-06 15:36:21 -0600837{
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800838 struct fsl_lbc_regs __iomem *lbc;
Scott Wood76b10462008-02-06 15:36:21 -0600839 struct fsl_elbc_mtd *priv;
840 struct resource res;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800841 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
842
Scott Wood76b10462008-02-06 15:36:21 -0600843#ifdef CONFIG_MTD_PARTITIONS
844 static const char *part_probe_types[]
845 = { "cmdlinepart", "RedBoot", NULL };
846 struct mtd_partition *parts;
847#endif
848 int ret;
849 int bank;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800850 struct device *dev;
851 struct device_node *node = pdev->dev.of_node;
852
853 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
854 return -ENODEV;
855 lbc = fsl_lbc_ctrl_dev->regs;
856 dev = fsl_lbc_ctrl_dev->dev;
Scott Wood76b10462008-02-06 15:36:21 -0600857
858 /* get, allocate and map the memory resource */
859 ret = of_address_to_resource(node, 0, &res);
860 if (ret) {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800861 dev_err(dev, "failed to get resource\n");
Scott Wood76b10462008-02-06 15:36:21 -0600862 return ret;
863 }
864
865 /* find which chip select it is connected to */
866 for (bank = 0; bank < MAX_BANKS; bank++)
867 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
868 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
869 (in_be32(&lbc->bank[bank].br) &
870 in_be32(&lbc->bank[bank].or) & BR_BA)
871 == res.start)
872 break;
873
874 if (bank >= MAX_BANKS) {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800875 dev_err(dev, "address did not match any chip selects\n");
Scott Wood76b10462008-02-06 15:36:21 -0600876 return -ENODEV;
877 }
878
879 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
880 if (!priv)
881 return -ENOMEM;
882
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800883 mutex_lock(&fsl_elbc_nand_mutex);
884 if (!fsl_lbc_ctrl_dev->nand) {
885 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
886 if (!elbc_fcm_ctrl) {
887 dev_err(dev, "failed to allocate memory\n");
888 mutex_unlock(&fsl_elbc_nand_mutex);
889 ret = -ENOMEM;
890 goto err;
891 }
892 elbc_fcm_ctrl->counter++;
893
894 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
895 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
896 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
897 } else {
898 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
899 }
900 mutex_unlock(&fsl_elbc_nand_mutex);
901
902 elbc_fcm_ctrl->chips[bank] = priv;
Scott Wood76b10462008-02-06 15:36:21 -0600903 priv->bank = bank;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800904 priv->ctrl = fsl_lbc_ctrl_dev;
905 priv->dev = dev;
Scott Wood76b10462008-02-06 15:36:21 -0600906
H Hartley Sweeten8a19b552009-12-14 16:19:44 -0500907 priv->vbase = ioremap(res.start, resource_size(&res));
Scott Wood76b10462008-02-06 15:36:21 -0600908 if (!priv->vbase) {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800909 dev_err(dev, "failed to map chip region\n");
Scott Wood76b10462008-02-06 15:36:21 -0600910 ret = -ENOMEM;
911 goto err;
912 }
913
akpm@linux-foundation.org650da9d2008-07-29 21:27:14 -0700914 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
Anton Vorontsov9ebed3e2008-03-18 19:34:03 +0300915 if (!priv->mtd.name) {
916 ret = -ENOMEM;
917 goto err;
918 }
919
Scott Wood76b10462008-02-06 15:36:21 -0600920 ret = fsl_elbc_chip_init(priv);
921 if (ret)
922 goto err;
923
David Woodhouse5e81e882010-02-26 18:32:56 +0000924 ret = nand_scan_ident(&priv->mtd, 1, NULL);
Scott Wood76b10462008-02-06 15:36:21 -0600925 if (ret)
926 goto err;
927
928 ret = fsl_elbc_chip_init_tail(&priv->mtd);
929 if (ret)
930 goto err;
931
932 ret = nand_scan_tail(&priv->mtd);
933 if (ret)
934 goto err;
935
936#ifdef CONFIG_MTD_PARTITIONS
937 /* First look for RedBoot table or partitions on the command
938 * line, these take precedence over device tree information */
939 ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
940 if (ret < 0)
941 goto err;
942
943#ifdef CONFIG_MTD_OF_PARTS
944 if (ret == 0) {
Sebastian Andrzej Siewior69fd3a82008-10-12 16:18:36 +0200945 ret = of_mtd_parse_partitions(priv->dev, node, &parts);
Scott Wood76b10462008-02-06 15:36:21 -0600946 if (ret < 0)
947 goto err;
948 }
949#endif
950
951 if (ret > 0)
952 add_mtd_partitions(&priv->mtd, parts, ret);
953 else
954#endif
955 add_mtd_device(&priv->mtd);
956
Stephen Rothwell4712fff2009-01-21 13:16:28 +0000957 printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
958 (unsigned long long)res.start, priv->bank);
Scott Wood76b10462008-02-06 15:36:21 -0600959 return 0;
960
961err:
962 fsl_elbc_chip_remove(priv);
963 return ret;
964}
965
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800966static int fsl_elbc_nand_remove(struct platform_device *pdev)
Scott Wood76b10462008-02-06 15:36:21 -0600967{
Scott Wood76b10462008-02-06 15:36:21 -0600968 int i;
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800969 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
Scott Wood76b10462008-02-06 15:36:21 -0600970 for (i = 0; i < MAX_BANKS; i++)
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800971 if (elbc_fcm_ctrl->chips[i])
972 fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]);
Scott Wood76b10462008-02-06 15:36:21 -0600973
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800974 mutex_lock(&fsl_elbc_nand_mutex);
975 elbc_fcm_ctrl->counter--;
976 if (!elbc_fcm_ctrl->counter) {
977 fsl_lbc_ctrl_dev->nand = NULL;
978 kfree(elbc_fcm_ctrl);
Scott Wood76b10462008-02-06 15:36:21 -0600979 }
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800980 mutex_unlock(&fsl_elbc_nand_mutex);
Scott Wood76b10462008-02-06 15:36:21 -0600981
982 return 0;
983
Scott Wood76b10462008-02-06 15:36:21 -0600984}
985
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800986static const struct of_device_id fsl_elbc_nand_match[] = {
987 { .compatible = "fsl,elbc-fcm-nand", },
Scott Wood76b10462008-02-06 15:36:21 -0600988 {}
989};
990
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800991static struct platform_driver fsl_elbc_nand_driver = {
Scott Wood76b10462008-02-06 15:36:21 -0600992 .driver = {
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800993 .name = "fsl,elbc-fcm-nand",
Grant Likely40182942010-04-13 16:13:02 -0700994 .owner = THIS_MODULE,
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800995 .of_match_table = fsl_elbc_nand_match,
Scott Wood76b10462008-02-06 15:36:21 -0600996 },
Roy Zang3ab8f2a2010-10-18 15:22:31 +0800997 .probe = fsl_elbc_nand_probe,
998 .remove = fsl_elbc_nand_remove,
Scott Wood76b10462008-02-06 15:36:21 -0600999};
1000
Roy Zang3ab8f2a2010-10-18 15:22:31 +08001001static int __init fsl_elbc_nand_init(void)
Scott Wood76b10462008-02-06 15:36:21 -06001002{
Roy Zang3ab8f2a2010-10-18 15:22:31 +08001003 return platform_driver_register(&fsl_elbc_nand_driver);
Scott Wood76b10462008-02-06 15:36:21 -06001004}
1005
Roy Zang3ab8f2a2010-10-18 15:22:31 +08001006static void __exit fsl_elbc_nand_exit(void)
Scott Wood76b10462008-02-06 15:36:21 -06001007{
Roy Zang3ab8f2a2010-10-18 15:22:31 +08001008 platform_driver_unregister(&fsl_elbc_nand_driver);
Scott Wood76b10462008-02-06 15:36:21 -06001009}
1010
Roy Zang3ab8f2a2010-10-18 15:22:31 +08001011module_init(fsl_elbc_nand_init);
1012module_exit(fsl_elbc_nand_exit);
Scott Wood76b10462008-02-06 15:36:21 -06001013
1014MODULE_LICENSE("GPL");
1015MODULE_AUTHOR("Freescale");
1016MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");