Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/clk.h> |
| 22 | |
| 23 | #include <asm/clkdev.h> |
| 24 | #include <asm/mach-types.h> |
| 25 | |
| 26 | #include <mach/msm_iomap.h> |
| 27 | #include <mach/clk.h> |
| 28 | #include <mach/rpm-regulator.h> |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 29 | #include <mach/socinfo.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 30 | |
| 31 | #include "clock-local.h" |
| 32 | #include "clock-rpm.h" |
| 33 | #include "clock-voter.h" |
| 34 | #include "clock-dss-8960.h" |
| 35 | #include "devices.h" |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 36 | #include "clock-pll.h" |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 37 | |
| 38 | #define REG(off) (MSM_CLK_CTL_BASE + (off)) |
| 39 | #define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off)) |
| 40 | #define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off)) |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 41 | #define REG_GCC(off) (MSM_APCS_GCC_BASE + (off)) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 42 | |
| 43 | /* Peripheral clock registers. */ |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 44 | #define ADM0_PBUS_CLK_CTL_REG REG(0x2208) |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 45 | #define SFAB_SATA_S_HCLK_CTL_REG REG(0x2480) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 46 | #define CE1_HCLK_CTL_REG REG(0x2720) |
| 47 | #define CE1_CORE_CLK_CTL_REG REG(0x2724) |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 48 | #define PRNG_CLK_NS_REG REG(0x2E80) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 49 | #define CE3_HCLK_CTL_REG REG(0x36C4) |
| 50 | #define CE3_CORE_CLK_CTL_REG REG(0x36CC) |
| 51 | #define CE3_CLK_SRC_NS_REG REG(0x36C0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 52 | #define DMA_BAM_HCLK_CTL REG(0x25C0) |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 53 | #define CLK_HALT_AFAB_SFAB_STATEA_REG REG(0x2FC0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 54 | #define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 55 | #define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC) |
| 56 | #define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0) |
| 57 | #define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4) |
| 58 | #define CLK_HALT_DFAB_STATE_REG REG(0x2FC8) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 59 | /* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 60 | #define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC) |
| 61 | #define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8) |
Stephen Boyd | 973e4ba | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 62 | #define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 63 | #define CLK_TEST_REG REG(0x2FA0) |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 64 | #define GPn_MD_REG(n) REG(0x2D00+(0x20*(n))) |
| 65 | #define GPn_NS_REG(n) REG(0x2D24+(0x20*(n))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 66 | #define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) |
| 67 | #define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1))) |
| 68 | #define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1))) |
| 69 | #define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1))) |
| 70 | #define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) |
| 71 | #define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 72 | #define PDM_CLK_NS_REG REG(0x2CC0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 73 | /* 8064 name BB_PLL_ENA_APCS_REG */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 74 | #define BB_PLL_ENA_SC0_REG REG(0x34C0) |
Tianyi Gou | 59608a7 | 2012-01-31 22:19:30 -0800 | [diff] [blame] | 75 | #define BB_PLL_ENA_RPM_REG REG(0x34A0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 76 | #define BB_PLL0_STATUS_REG REG(0x30D8) |
| 77 | #define BB_PLL5_STATUS_REG REG(0x30F8) |
| 78 | #define BB_PLL6_STATUS_REG REG(0x3118) |
| 79 | #define BB_PLL7_STATUS_REG REG(0x3138) |
| 80 | #define BB_PLL8_L_VAL_REG REG(0x3144) |
| 81 | #define BB_PLL8_M_VAL_REG REG(0x3148) |
| 82 | #define BB_PLL8_MODE_REG REG(0x3140) |
| 83 | #define BB_PLL8_N_VAL_REG REG(0x314C) |
| 84 | #define BB_PLL8_STATUS_REG REG(0x3158) |
| 85 | #define BB_PLL8_CONFIG_REG REG(0x3154) |
| 86 | #define BB_PLL8_TEST_CTL_REG REG(0x3150) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 87 | #define BB_MMCC_PLL2_MODE_REG REG(0x3160) |
| 88 | #define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 89 | #define BB_PLL14_MODE_REG REG(0x31C0) |
| 90 | #define BB_PLL14_L_VAL_REG REG(0x31C4) |
| 91 | #define BB_PLL14_M_VAL_REG REG(0x31C8) |
| 92 | #define BB_PLL14_N_VAL_REG REG(0x31CC) |
| 93 | #define BB_PLL14_TEST_CTL_REG REG(0x31D0) |
| 94 | #define BB_PLL14_CONFIG_REG REG(0x31D4) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 95 | #define BB_PLL14_STATUS_REG REG(0x31D8) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 96 | #define PLLTEST_PAD_CFG_REG REG(0x2FA4) |
| 97 | #define PMEM_ACLK_CTL_REG REG(0x25A0) |
| 98 | #define RINGOSC_NS_REG REG(0x2DC0) |
| 99 | #define RINGOSC_STATUS_REG REG(0x2DCC) |
| 100 | #define RINGOSC_TCXO_CTL_REG REG(0x2DC4) |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 101 | #define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 102 | #define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080) |
| 103 | #define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1))) |
| 104 | #define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1))) |
| 105 | #define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1))) |
| 106 | #define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1))) |
| 107 | #define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628) |
| 108 | #define TSIF_HCLK_CTL_REG REG(0x2700) |
| 109 | #define TSIF_REF_CLK_MD_REG REG(0x270C) |
| 110 | #define TSIF_REF_CLK_NS_REG REG(0x2710) |
| 111 | #define TSSC_CLK_CTL_REG REG(0x2CA0) |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 112 | #define SATA_HCLK_CTL_REG REG(0x2C00) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 113 | #define SATA_CLK_SRC_NS_REG REG(0x2C08) |
| 114 | #define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C) |
| 115 | #define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10) |
| 116 | #define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14) |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 117 | #define SATA_ACLK_CTL_REG REG(0x2C20) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 118 | #define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 119 | #define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1))) |
| 120 | #define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1))) |
| 121 | #define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1))) |
| 122 | #define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1))) |
| 123 | #define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1))) |
| 124 | #define USB_HS1_HCLK_CTL_REG REG(0x2900) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 125 | #define USB_HS1_HCLK_FS_REG REG(0x2904) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 126 | #define USB_HS1_RESET_REG REG(0x2910) |
| 127 | #define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908) |
| 128 | #define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 129 | #define USB_HS3_HCLK_CTL_REG REG(0x3700) |
| 130 | #define USB_HS3_HCLK_FS_REG REG(0x3704) |
| 131 | #define USB_HS3_RESET_REG REG(0x3710) |
| 132 | #define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708) |
| 133 | #define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C) |
| 134 | #define USB_HS4_HCLK_CTL_REG REG(0x3720) |
| 135 | #define USB_HS4_HCLK_FS_REG REG(0x3724) |
| 136 | #define USB_HS4_RESET_REG REG(0x3730) |
| 137 | #define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728) |
| 138 | #define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 139 | #define USB_HSIC_HCLK_CTL_REG REG(0x2920) |
| 140 | #define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44) |
| 141 | #define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40) |
| 142 | #define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48) |
| 143 | #define USB_HSIC_RESET_REG REG(0x2934) |
| 144 | #define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C) |
| 145 | #define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924) |
| 146 | #define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 147 | #define USB_PHY0_RESET_REG REG(0x2E20) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 148 | #define PCIE_ALT_REF_CLK_NS_REG REG(0x3860) |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 149 | #define PCIE_ACLK_CTL_REG REG(0x22C0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 150 | #define PCIE_HCLK_CTL_REG REG(0x22CC) |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 151 | #define PCIE_PCLK_CTL_REG REG(0x22D0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 152 | #define GPLL1_MODE_REG REG(0x3160) |
| 153 | #define GPLL1_L_VAL_REG REG(0x3164) |
| 154 | #define GPLL1_M_VAL_REG REG(0x3168) |
| 155 | #define GPLL1_N_VAL_REG REG(0x316C) |
| 156 | #define GPLL1_CONFIG_REG REG(0x3174) |
| 157 | #define GPLL1_STATUS_REG REG(0x3178) |
| 158 | #define PXO_SRC_CLK_CTL_REG REG(0x2EA0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 159 | |
| 160 | /* Multimedia clock registers. */ |
| 161 | #define AHB_EN_REG REG_MM(0x0008) |
| 162 | #define AHB_EN2_REG REG_MM(0x0038) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 163 | #define AHB_EN3_REG REG_MM(0x0248) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 164 | #define AHB_NS_REG REG_MM(0x0004) |
| 165 | #define AXI_NS_REG REG_MM(0x0014) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 166 | #define CAMCLK0_NS_REG REG_MM(0x0148) |
| 167 | #define CAMCLK0_CC_REG REG_MM(0x0140) |
| 168 | #define CAMCLK0_MD_REG REG_MM(0x0144) |
| 169 | #define CAMCLK1_NS_REG REG_MM(0x015C) |
| 170 | #define CAMCLK1_CC_REG REG_MM(0x0154) |
| 171 | #define CAMCLK1_MD_REG REG_MM(0x0158) |
| 172 | #define CAMCLK2_NS_REG REG_MM(0x0228) |
| 173 | #define CAMCLK2_CC_REG REG_MM(0x0220) |
| 174 | #define CAMCLK2_MD_REG REG_MM(0x0224) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 175 | #define CSI0_NS_REG REG_MM(0x0048) |
| 176 | #define CSI0_CC_REG REG_MM(0x0040) |
| 177 | #define CSI0_MD_REG REG_MM(0x0044) |
| 178 | #define CSI1_NS_REG REG_MM(0x0010) |
| 179 | #define CSI1_CC_REG REG_MM(0x0024) |
| 180 | #define CSI1_MD_REG REG_MM(0x0028) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 181 | #define CSI2_NS_REG REG_MM(0x0234) |
| 182 | #define CSI2_CC_REG REG_MM(0x022C) |
| 183 | #define CSI2_MD_REG REG_MM(0x0230) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 184 | #define CSIPHYTIMER_CC_REG REG_MM(0x0160) |
| 185 | #define CSIPHYTIMER_MD_REG REG_MM(0x0164) |
| 186 | #define CSIPHYTIMER_NS_REG REG_MM(0x0168) |
| 187 | #define DSI1_BYTE_NS_REG REG_MM(0x00B0) |
| 188 | #define DSI1_BYTE_CC_REG REG_MM(0x0090) |
| 189 | #define DSI2_BYTE_NS_REG REG_MM(0x00BC) |
| 190 | #define DSI2_BYTE_CC_REG REG_MM(0x00B4) |
| 191 | #define DSI1_ESC_NS_REG REG_MM(0x011C) |
| 192 | #define DSI1_ESC_CC_REG REG_MM(0x00CC) |
| 193 | #define DSI2_ESC_NS_REG REG_MM(0x0150) |
| 194 | #define DSI2_ESC_CC_REG REG_MM(0x013C) |
| 195 | #define DSI_PIXEL_CC_REG REG_MM(0x0130) |
| 196 | #define DSI2_PIXEL_CC_REG REG_MM(0x0094) |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 197 | #define DSI2_PIXEL_CC2_REG REG_MM(0x0264) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 198 | #define DBG_BUS_VEC_A_REG REG_MM(0x01C8) |
| 199 | #define DBG_BUS_VEC_B_REG REG_MM(0x01CC) |
| 200 | #define DBG_BUS_VEC_C_REG REG_MM(0x01D0) |
| 201 | #define DBG_BUS_VEC_D_REG REG_MM(0x01D4) |
| 202 | #define DBG_BUS_VEC_E_REG REG_MM(0x01D8) |
| 203 | #define DBG_BUS_VEC_F_REG REG_MM(0x01DC) |
| 204 | #define DBG_BUS_VEC_G_REG REG_MM(0x01E0) |
| 205 | #define DBG_BUS_VEC_H_REG REG_MM(0x01E4) |
| 206 | #define DBG_BUS_VEC_I_REG REG_MM(0x01E8) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 207 | #define DBG_BUS_VEC_J_REG REG_MM(0x0240) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 208 | #define DBG_CFG_REG_HS_REG REG_MM(0x01B4) |
| 209 | #define DBG_CFG_REG_LS_REG REG_MM(0x01B8) |
| 210 | #define GFX2D0_CC_REG REG_MM(0x0060) |
| 211 | #define GFX2D0_MD0_REG REG_MM(0x0064) |
| 212 | #define GFX2D0_MD1_REG REG_MM(0x0068) |
| 213 | #define GFX2D0_NS_REG REG_MM(0x0070) |
| 214 | #define GFX2D1_CC_REG REG_MM(0x0074) |
| 215 | #define GFX2D1_MD0_REG REG_MM(0x0078) |
| 216 | #define GFX2D1_MD1_REG REG_MM(0x006C) |
| 217 | #define GFX2D1_NS_REG REG_MM(0x007C) |
| 218 | #define GFX3D_CC_REG REG_MM(0x0080) |
| 219 | #define GFX3D_MD0_REG REG_MM(0x0084) |
| 220 | #define GFX3D_MD1_REG REG_MM(0x0088) |
| 221 | #define GFX3D_NS_REG REG_MM(0x008C) |
| 222 | #define IJPEG_CC_REG REG_MM(0x0098) |
| 223 | #define IJPEG_MD_REG REG_MM(0x009C) |
| 224 | #define IJPEG_NS_REG REG_MM(0x00A0) |
| 225 | #define JPEGD_CC_REG REG_MM(0x00A4) |
| 226 | #define JPEGD_NS_REG REG_MM(0x00AC) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 227 | #define VCAP_CC_REG REG_MM(0x0178) |
| 228 | #define VCAP_NS_REG REG_MM(0x021C) |
| 229 | #define VCAP_MD0_REG REG_MM(0x01EC) |
| 230 | #define VCAP_MD1_REG REG_MM(0x0218) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 231 | #define MAXI_EN_REG REG_MM(0x0018) |
| 232 | #define MAXI_EN2_REG REG_MM(0x0020) |
| 233 | #define MAXI_EN3_REG REG_MM(0x002C) |
| 234 | #define MAXI_EN4_REG REG_MM(0x0114) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 235 | #define MAXI_EN5_REG REG_MM(0x0244) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 236 | #define MDP_CC_REG REG_MM(0x00C0) |
| 237 | #define MDP_LUT_CC_REG REG_MM(0x016C) |
| 238 | #define MDP_MD0_REG REG_MM(0x00C4) |
| 239 | #define MDP_MD1_REG REG_MM(0x00C8) |
| 240 | #define MDP_NS_REG REG_MM(0x00D0) |
| 241 | #define MISC_CC_REG REG_MM(0x0058) |
| 242 | #define MISC_CC2_REG REG_MM(0x005C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 243 | #define MISC_CC3_REG REG_MM(0x0238) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 244 | #define MM_PLL1_MODE_REG REG_MM(0x031C) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 245 | #define MM_PLL1_L_VAL_REG REG_MM(0x0320) |
| 246 | #define MM_PLL1_M_VAL_REG REG_MM(0x0324) |
| 247 | #define MM_PLL1_N_VAL_REG REG_MM(0x0328) |
| 248 | #define MM_PLL1_CONFIG_REG REG_MM(0x032C) |
| 249 | #define MM_PLL1_TEST_CTL_REG REG_MM(0x0330) |
| 250 | #define MM_PLL1_STATUS_REG REG_MM(0x0334) |
| 251 | #define MM_PLL3_MODE_REG REG_MM(0x0338) |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 252 | #define MM_PLL3_L_VAL_REG REG_MM(0x033C) |
| 253 | #define MM_PLL3_M_VAL_REG REG_MM(0x0340) |
| 254 | #define MM_PLL3_N_VAL_REG REG_MM(0x0344) |
| 255 | #define MM_PLL3_CONFIG_REG REG_MM(0x0348) |
| 256 | #define MM_PLL3_TEST_CTL_REG REG_MM(0x034C) |
| 257 | #define MM_PLL3_STATUS_REG REG_MM(0x0350) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 258 | #define ROT_CC_REG REG_MM(0x00E0) |
| 259 | #define ROT_NS_REG REG_MM(0x00E8) |
| 260 | #define SAXI_EN_REG REG_MM(0x0030) |
| 261 | #define SW_RESET_AHB_REG REG_MM(0x020C) |
| 262 | #define SW_RESET_AHB2_REG REG_MM(0x0200) |
| 263 | #define SW_RESET_ALL_REG REG_MM(0x0204) |
| 264 | #define SW_RESET_AXI_REG REG_MM(0x0208) |
| 265 | #define SW_RESET_CORE_REG REG_MM(0x0210) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 266 | #define SW_RESET_CORE2_REG REG_MM(0x0214) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 267 | #define TV_CC_REG REG_MM(0x00EC) |
| 268 | #define TV_CC2_REG REG_MM(0x0124) |
| 269 | #define TV_MD_REG REG_MM(0x00F0) |
| 270 | #define TV_NS_REG REG_MM(0x00F4) |
| 271 | #define VCODEC_CC_REG REG_MM(0x00F8) |
| 272 | #define VCODEC_MD0_REG REG_MM(0x00FC) |
| 273 | #define VCODEC_MD1_REG REG_MM(0x0128) |
| 274 | #define VCODEC_NS_REG REG_MM(0x0100) |
| 275 | #define VFE_CC_REG REG_MM(0x0104) |
| 276 | #define VFE_MD_REG REG_MM(0x0108) |
| 277 | #define VFE_NS_REG REG_MM(0x010C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 278 | #define VFE_CC2_REG REG_MM(0x023C) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 279 | #define VPE_CC_REG REG_MM(0x0110) |
| 280 | #define VPE_NS_REG REG_MM(0x0118) |
| 281 | |
| 282 | /* Low-power Audio clock registers. */ |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 283 | #define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 284 | #define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8) |
| 285 | #define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064) |
| 286 | #define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060) |
| 287 | #define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068) |
| 288 | #define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070) |
| 289 | #define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C) |
| 290 | #define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074) |
| 291 | #define LCC_MI2S_MD_REG REG_LPA(0x004C) |
| 292 | #define LCC_MI2S_NS_REG REG_LPA(0x0048) |
| 293 | #define LCC_MI2S_STATUS_REG REG_LPA(0x0050) |
| 294 | #define LCC_PCM_MD_REG REG_LPA(0x0058) |
| 295 | #define LCC_PCM_NS_REG REG_LPA(0x0054) |
| 296 | #define LCC_PCM_STATUS_REG REG_LPA(0x005C) |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 297 | #define LCC_PLL0_MODE_REG REG_LPA(0x0000) |
| 298 | #define LCC_PLL0_L_VAL_REG REG_LPA(0x0004) |
| 299 | #define LCC_PLL0_M_VAL_REG REG_LPA(0x0008) |
| 300 | #define LCC_PLL0_N_VAL_REG REG_LPA(0x000C) |
| 301 | #define LCC_PLL0_CONFIG_REG REG_LPA(0x0014) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 302 | #define LCC_PLL0_STATUS_REG REG_LPA(0x0018) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 303 | #define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C) |
| 304 | #define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078) |
| 305 | #define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080) |
| 306 | #define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088) |
| 307 | #define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084) |
| 308 | #define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C) |
| 309 | #define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC) |
| 310 | #define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0) |
| 311 | #define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4) |
| 312 | #define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4) |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 313 | #define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 314 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 315 | #define GCC_APCS_CLK_DIAG REG_GCC(0x001C) |
| 316 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 317 | /* MUX source input identifiers. */ |
| 318 | #define pxo_to_bb_mux 0 |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 319 | #define cxo_to_bb_mux 5 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 320 | #define pll0_to_bb_mux 2 |
| 321 | #define pll8_to_bb_mux 3 |
| 322 | #define pll6_to_bb_mux 4 |
| 323 | #define gnd_to_bb_mux 5 |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 324 | #define pll3_to_bb_mux 6 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 325 | #define pxo_to_mm_mux 0 |
| 326 | #define pll1_to_mm_mux 1 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 327 | #define pll2_to_mm_mux 1 /* or MMCC_PLL1 */ |
| 328 | #define pll8_to_mm_mux 2 /* or GCC_PERF */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 329 | #define pll0_to_mm_mux 3 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 330 | #define pll15_to_mm_mux 3 /* or MM_PLL3 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 331 | #define gnd_to_mm_mux 4 |
Stephen Boyd | 7a776cd | 2011-10-20 12:46:04 -0700 | [diff] [blame] | 332 | #define pll3_to_mm_mux 3 /* or MMCC_PLL2 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 333 | #define hdmi_pll_to_mm_mux 3 |
| 334 | #define cxo_to_xo_mux 0 |
| 335 | #define pxo_to_xo_mux 1 |
| 336 | #define gnd_to_xo_mux 3 |
| 337 | #define pxo_to_lpa_mux 0 |
| 338 | #define cxo_to_lpa_mux 1 |
| 339 | #define pll4_to_lpa_mux 2 |
| 340 | #define gnd_to_lpa_mux 6 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 341 | #define pxo_to_pcie_mux 0 |
| 342 | #define pll3_to_pcie_mux 1 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 343 | |
| 344 | /* Test Vector Macros */ |
| 345 | #define TEST_TYPE_PER_LS 1 |
| 346 | #define TEST_TYPE_PER_HS 2 |
| 347 | #define TEST_TYPE_MM_LS 3 |
| 348 | #define TEST_TYPE_MM_HS 4 |
| 349 | #define TEST_TYPE_LPA 5 |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 350 | #define TEST_TYPE_CPUL2 6 |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 351 | #define TEST_TYPE_LPA_HS 7 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 352 | #define TEST_TYPE_SHIFT 24 |
| 353 | #define TEST_CLK_SEL_MASK BM(23, 0) |
| 354 | #define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s))) |
| 355 | #define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS) |
| 356 | #define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS) |
| 357 | #define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS) |
| 358 | #define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS) |
| 359 | #define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA) |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 360 | #define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS) |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 361 | #define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 362 | |
| 363 | #define MN_MODE_DUAL_EDGE 0x2 |
| 364 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 365 | struct pll_rate { |
| 366 | const uint32_t l_val; |
| 367 | const uint32_t m_val; |
| 368 | const uint32_t n_val; |
| 369 | const uint32_t vco; |
| 370 | const uint32_t post_div; |
| 371 | const uint32_t i_bits; |
| 372 | }; |
| 373 | #define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i } |
| 374 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 375 | enum vdd_dig_levels { |
| 376 | VDD_DIG_NONE, |
| 377 | VDD_DIG_LOW, |
| 378 | VDD_DIG_NOMINAL, |
| 379 | VDD_DIG_HIGH |
| 380 | }; |
| 381 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 382 | static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level) |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 383 | { |
| 384 | static const int vdd_uv[] = { |
| 385 | [VDD_DIG_NONE] = 0, |
| 386 | [VDD_DIG_LOW] = 945000, |
| 387 | [VDD_DIG_NOMINAL] = 1050000, |
| 388 | [VDD_DIG_HIGH] = 1150000 |
| 389 | }; |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 390 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 391 | vdd_uv[level], 1150000, 1); |
| 392 | } |
| 393 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 394 | static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960); |
| 395 | |
| 396 | static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level) |
| 397 | { |
Saravana Kannan | ebaa3ac | 2012-02-08 19:55:44 -0800 | [diff] [blame] | 398 | static const int vdd_corner[] = { |
| 399 | [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE, |
| 400 | [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW, |
| 401 | [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL, |
| 402 | [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH, |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 403 | }; |
Saravana Kannan | ebaa3ac | 2012-02-08 19:55:44 -0800 | [diff] [blame] | 404 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_VDD_DIG_CORNER, |
| 405 | RPM_VREG_VOTER3, |
| 406 | vdd_corner[level], |
| 407 | RPM_VREG_CORNER_HIGH, 1); |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 408 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 409 | |
| 410 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
| 411 | .vdd_class = &vdd_dig, \ |
| 412 | .fmax[VDD_DIG_##l1] = (f1) |
| 413 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
| 414 | .vdd_class = &vdd_dig, \ |
| 415 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 416 | .fmax[VDD_DIG_##l2] = (f2) |
| 417 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
| 418 | .vdd_class = &vdd_dig, \ |
| 419 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 420 | .fmax[VDD_DIG_##l2] = (f2), \ |
| 421 | .fmax[VDD_DIG_##l3] = (f3) |
| 422 | |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 423 | enum vdd_sr2_hdmi_pll_levels { |
| 424 | VDD_SR2_HDMI_PLL_OFF, |
| 425 | VDD_SR2_HDMI_PLL_ON |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 426 | }; |
| 427 | |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 428 | static int set_vdd_sr2_hdmi_pll_8960(struct clk_vdd_class *vdd_class, int level) |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 429 | { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 430 | int rc = 0; |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 431 | |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 432 | if (level == VDD_SR2_HDMI_PLL_OFF) { |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 433 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 434 | RPM_VREG_VOTER3, 0, 0, 1); |
| 435 | if (rc) |
| 436 | return rc; |
| 437 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
| 438 | RPM_VREG_VOTER3, 0, 0, 1); |
| 439 | if (rc) |
| 440 | rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 441 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 442 | } else { |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 443 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
David Collins | 9a81d6c | 2012-03-29 15:11:33 -0700 | [diff] [blame] | 444 | RPM_VREG_VOTER3, 2050000, 2100000, 1); |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 445 | if (rc) |
| 446 | return rc; |
| 447 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 448 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
| 449 | if (rc) |
| 450 | rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 451 | RPM_VREG_VOTER3, 0, 0, 1); |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 452 | } |
| 453 | |
| 454 | return rc; |
| 455 | } |
| 456 | |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 457 | static DEFINE_VDD_CLASS(vdd_sr2_hdmi_pll, set_vdd_sr2_hdmi_pll_8960); |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 458 | |
| 459 | static int sr2_lreg_uv[] = { |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 460 | [VDD_SR2_HDMI_PLL_OFF] = 0, |
| 461 | [VDD_SR2_HDMI_PLL_ON] = 1800000, |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 462 | }; |
| 463 | |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 464 | static int set_vdd_sr2_hdmi_pll_8064(struct clk_vdd_class *vdd_class, int level) |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 465 | { |
| 466 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3, |
| 467 | sr2_lreg_uv[level], sr2_lreg_uv[level], 1); |
| 468 | } |
| 469 | |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 470 | static int set_vdd_sr2_hdmi_pll_8930(struct clk_vdd_class *vdd_class, int level) |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 471 | { |
| 472 | return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3, |
| 473 | sr2_lreg_uv[level], sr2_lreg_uv[level], 1); |
| 474 | } |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 475 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 476 | /* |
| 477 | * Clock Descriptions |
| 478 | */ |
| 479 | |
Stephen Boyd | 72a8035 | 2012-01-26 15:57:38 -0800 | [diff] [blame] | 480 | DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000); |
| 481 | DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 482 | |
| 483 | static struct pll_clk pll2_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 484 | .mode_reg = MM_PLL1_MODE_REG, |
| 485 | .parent = &pxo_clk.c, |
| 486 | .c = { |
| 487 | .dbg_name = "pll2_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 488 | .rate = 800000000, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 489 | .ops = &clk_ops_local_pll, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 490 | CLK_INIT(pll2_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 491 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 492 | }, |
| 493 | }; |
| 494 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 495 | static struct pll_clk pll3_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 496 | .mode_reg = BB_MMCC_PLL2_MODE_REG, |
| 497 | .parent = &pxo_clk.c, |
| 498 | .c = { |
| 499 | .dbg_name = "pll3_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 500 | .rate = 1200000000, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 501 | .ops = &clk_ops_local_pll, |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 502 | .vdd_class = &vdd_sr2_hdmi_pll, |
| 503 | .fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 504 | CLK_INIT(pll3_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 505 | .warned = true, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 506 | }, |
| 507 | }; |
| 508 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 509 | static struct pll_vote_clk pll4_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 510 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 511 | .en_mask = BIT(4), |
| 512 | .status_reg = LCC_PLL0_STATUS_REG, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 513 | .status_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 514 | .parent = &pxo_clk.c, |
| 515 | .c = { |
| 516 | .dbg_name = "pll4_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 517 | .rate = 393216000, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 518 | .ops = &clk_ops_pll_vote, |
| 519 | CLK_INIT(pll4_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 520 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 521 | }, |
| 522 | }; |
| 523 | |
| 524 | static struct pll_vote_clk pll8_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 525 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 526 | .en_mask = BIT(8), |
| 527 | .status_reg = BB_PLL8_STATUS_REG, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 528 | .status_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 529 | .parent = &pxo_clk.c, |
| 530 | .c = { |
| 531 | .dbg_name = "pll8_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 532 | .rate = 384000000, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 533 | .ops = &clk_ops_pll_vote, |
| 534 | CLK_INIT(pll8_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 535 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 536 | }, |
| 537 | }; |
| 538 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 539 | static struct pll_vote_clk pll14_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 540 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 541 | .en_mask = BIT(14), |
| 542 | .status_reg = BB_PLL14_STATUS_REG, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 543 | .status_mask = BIT(16), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 544 | .parent = &pxo_clk.c, |
| 545 | .c = { |
| 546 | .dbg_name = "pll14_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 547 | .rate = 480000000, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 548 | .ops = &clk_ops_pll_vote, |
| 549 | CLK_INIT(pll14_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 550 | .warned = true, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 551 | }, |
| 552 | }; |
| 553 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 554 | static struct pll_clk pll15_clk = { |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 555 | .mode_reg = MM_PLL3_MODE_REG, |
| 556 | .parent = &pxo_clk.c, |
| 557 | .c = { |
| 558 | .dbg_name = "pll15_clk", |
Tianyi Gou | 7949ecb | 2012-02-14 14:25:32 -0800 | [diff] [blame] | 559 | .rate = 975000000, |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 560 | .ops = &clk_ops_local_pll, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 561 | CLK_INIT(pll15_clk.c), |
Stephen Boyd | 3bbf346 | 2012-01-12 00:19:23 -0800 | [diff] [blame] | 562 | .warned = true, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 563 | }, |
| 564 | }; |
| 565 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 566 | /* AXI Interfaces */ |
| 567 | static struct branch_clk gmem_axi_clk = { |
| 568 | .b = { |
| 569 | .ctl_reg = MAXI_EN_REG, |
| 570 | .en_mask = BIT(24), |
| 571 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 572 | .halt_bit = 6, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 573 | .retain_reg = MAXI_EN2_REG, |
| 574 | .retain_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 575 | }, |
| 576 | .c = { |
| 577 | .dbg_name = "gmem_axi_clk", |
| 578 | .ops = &clk_ops_branch, |
| 579 | CLK_INIT(gmem_axi_clk.c), |
| 580 | }, |
| 581 | }; |
| 582 | |
| 583 | static struct branch_clk ijpeg_axi_clk = { |
| 584 | .b = { |
| 585 | .ctl_reg = MAXI_EN_REG, |
| 586 | .en_mask = BIT(21), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 587 | .hwcg_reg = MAXI_EN_REG, |
| 588 | .hwcg_mask = BIT(11), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 589 | .reset_reg = SW_RESET_AXI_REG, |
| 590 | .reset_mask = BIT(14), |
| 591 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 592 | .halt_bit = 4, |
| 593 | }, |
| 594 | .c = { |
| 595 | .dbg_name = "ijpeg_axi_clk", |
| 596 | .ops = &clk_ops_branch, |
| 597 | CLK_INIT(ijpeg_axi_clk.c), |
| 598 | }, |
| 599 | }; |
| 600 | |
| 601 | static struct branch_clk imem_axi_clk = { |
| 602 | .b = { |
| 603 | .ctl_reg = MAXI_EN_REG, |
| 604 | .en_mask = BIT(22), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 605 | .hwcg_reg = MAXI_EN_REG, |
| 606 | .hwcg_mask = BIT(15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 607 | .reset_reg = SW_RESET_CORE_REG, |
| 608 | .reset_mask = BIT(10), |
| 609 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 610 | .halt_bit = 7, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 611 | .retain_reg = MAXI_EN2_REG, |
| 612 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 613 | }, |
| 614 | .c = { |
| 615 | .dbg_name = "imem_axi_clk", |
| 616 | .ops = &clk_ops_branch, |
| 617 | CLK_INIT(imem_axi_clk.c), |
| 618 | }, |
| 619 | }; |
| 620 | |
| 621 | static struct branch_clk jpegd_axi_clk = { |
| 622 | .b = { |
| 623 | .ctl_reg = MAXI_EN_REG, |
| 624 | .en_mask = BIT(25), |
| 625 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 626 | .halt_bit = 5, |
| 627 | }, |
| 628 | .c = { |
| 629 | .dbg_name = "jpegd_axi_clk", |
| 630 | .ops = &clk_ops_branch, |
| 631 | CLK_INIT(jpegd_axi_clk.c), |
| 632 | }, |
| 633 | }; |
| 634 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 635 | static struct branch_clk vcodec_axi_b_clk = { |
| 636 | .b = { |
| 637 | .ctl_reg = MAXI_EN4_REG, |
| 638 | .en_mask = BIT(23), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 639 | .hwcg_reg = MAXI_EN4_REG, |
| 640 | .hwcg_mask = BIT(22), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 641 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 642 | .halt_bit = 25, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 643 | .retain_reg = MAXI_EN4_REG, |
| 644 | .retain_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 645 | }, |
| 646 | .c = { |
| 647 | .dbg_name = "vcodec_axi_b_clk", |
| 648 | .ops = &clk_ops_branch, |
| 649 | CLK_INIT(vcodec_axi_b_clk.c), |
| 650 | }, |
| 651 | }; |
| 652 | |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 653 | static struct branch_clk vcodec_axi_a_clk = { |
| 654 | .b = { |
| 655 | .ctl_reg = MAXI_EN4_REG, |
| 656 | .en_mask = BIT(25), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 657 | .hwcg_reg = MAXI_EN4_REG, |
| 658 | .hwcg_mask = BIT(24), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 659 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 660 | .halt_bit = 26, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 661 | .retain_reg = MAXI_EN4_REG, |
| 662 | .retain_mask = BIT(10), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 663 | }, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 664 | .c = { |
| 665 | .dbg_name = "vcodec_axi_a_clk", |
| 666 | .ops = &clk_ops_branch, |
| 667 | CLK_INIT(vcodec_axi_a_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 668 | .depends = &vcodec_axi_b_clk.c, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 669 | }, |
| 670 | }; |
| 671 | |
| 672 | static struct branch_clk vcodec_axi_clk = { |
| 673 | .b = { |
| 674 | .ctl_reg = MAXI_EN_REG, |
| 675 | .en_mask = BIT(19), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 676 | .hwcg_reg = MAXI_EN_REG, |
| 677 | .hwcg_mask = BIT(13), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 678 | .reset_reg = SW_RESET_AXI_REG, |
Gopikrishnaiah Anandan | 83b6e85 | 2012-01-05 17:47:02 -0800 | [diff] [blame] | 679 | .reset_mask = BIT(4)|BIT(5)|BIT(7), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 680 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 681 | .halt_bit = 3, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 682 | .retain_reg = MAXI_EN2_REG, |
| 683 | .retain_mask = BIT(28), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 684 | }, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 685 | .c = { |
| 686 | .dbg_name = "vcodec_axi_clk", |
| 687 | .ops = &clk_ops_branch, |
| 688 | CLK_INIT(vcodec_axi_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 689 | .depends = &vcodec_axi_a_clk.c, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 690 | }, |
| 691 | }; |
| 692 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 693 | static struct branch_clk vfe_axi_clk = { |
| 694 | .b = { |
| 695 | .ctl_reg = MAXI_EN_REG, |
| 696 | .en_mask = BIT(18), |
| 697 | .reset_reg = SW_RESET_AXI_REG, |
| 698 | .reset_mask = BIT(9), |
| 699 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 700 | .halt_bit = 0, |
| 701 | }, |
| 702 | .c = { |
| 703 | .dbg_name = "vfe_axi_clk", |
| 704 | .ops = &clk_ops_branch, |
| 705 | CLK_INIT(vfe_axi_clk.c), |
| 706 | }, |
| 707 | }; |
| 708 | |
| 709 | static struct branch_clk mdp_axi_clk = { |
| 710 | .b = { |
| 711 | .ctl_reg = MAXI_EN_REG, |
| 712 | .en_mask = BIT(23), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 713 | .hwcg_reg = MAXI_EN_REG, |
| 714 | .hwcg_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 715 | .reset_reg = SW_RESET_AXI_REG, |
| 716 | .reset_mask = BIT(13), |
| 717 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 718 | .halt_bit = 8, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 719 | .retain_reg = MAXI_EN_REG, |
| 720 | .retain_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 721 | }, |
| 722 | .c = { |
| 723 | .dbg_name = "mdp_axi_clk", |
| 724 | .ops = &clk_ops_branch, |
| 725 | CLK_INIT(mdp_axi_clk.c), |
| 726 | }, |
| 727 | }; |
| 728 | |
| 729 | static struct branch_clk rot_axi_clk = { |
| 730 | .b = { |
| 731 | .ctl_reg = MAXI_EN2_REG, |
| 732 | .en_mask = BIT(24), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 733 | .hwcg_reg = MAXI_EN2_REG, |
| 734 | .hwcg_mask = BIT(25), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 735 | .reset_reg = SW_RESET_AXI_REG, |
| 736 | .reset_mask = BIT(6), |
| 737 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 738 | .halt_bit = 2, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 739 | .retain_reg = MAXI_EN3_REG, |
| 740 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 741 | }, |
| 742 | .c = { |
| 743 | .dbg_name = "rot_axi_clk", |
| 744 | .ops = &clk_ops_branch, |
| 745 | CLK_INIT(rot_axi_clk.c), |
| 746 | }, |
| 747 | }; |
| 748 | |
| 749 | static struct branch_clk vpe_axi_clk = { |
| 750 | .b = { |
| 751 | .ctl_reg = MAXI_EN2_REG, |
| 752 | .en_mask = BIT(26), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 753 | .hwcg_reg = MAXI_EN2_REG, |
| 754 | .hwcg_mask = BIT(27), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 755 | .reset_reg = SW_RESET_AXI_REG, |
| 756 | .reset_mask = BIT(15), |
| 757 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 758 | .halt_bit = 1, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 759 | .retain_reg = MAXI_EN3_REG, |
| 760 | .retain_mask = BIT(21), |
| 761 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 762 | }, |
| 763 | .c = { |
| 764 | .dbg_name = "vpe_axi_clk", |
| 765 | .ops = &clk_ops_branch, |
| 766 | CLK_INIT(vpe_axi_clk.c), |
| 767 | }, |
| 768 | }; |
| 769 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 770 | static struct branch_clk vcap_axi_clk = { |
| 771 | .b = { |
| 772 | .ctl_reg = MAXI_EN5_REG, |
| 773 | .en_mask = BIT(12), |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 774 | .hwcg_reg = MAXI_EN5_REG, |
| 775 | .hwcg_mask = BIT(11), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 776 | .reset_reg = SW_RESET_AXI_REG, |
| 777 | .reset_mask = BIT(16), |
| 778 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 779 | .halt_bit = 20, |
| 780 | }, |
| 781 | .c = { |
| 782 | .dbg_name = "vcap_axi_clk", |
| 783 | .ops = &clk_ops_branch, |
| 784 | CLK_INIT(vcap_axi_clk.c), |
| 785 | }, |
| 786 | }; |
| 787 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 788 | /* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */ |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 789 | static struct branch_clk gfx3d_axi_clk = { |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 790 | .b = { |
| 791 | .ctl_reg = MAXI_EN5_REG, |
| 792 | .en_mask = BIT(25), |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 793 | .hwcg_reg = MAXI_EN5_REG, |
| 794 | .hwcg_mask = BIT(24), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 795 | .reset_reg = SW_RESET_AXI_REG, |
| 796 | .reset_mask = BIT(17), |
| 797 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 798 | .halt_bit = 30, |
| 799 | }, |
| 800 | .c = { |
| 801 | .dbg_name = "gfx3d_axi_clk", |
| 802 | .ops = &clk_ops_branch, |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 803 | CLK_INIT(gfx3d_axi_clk.c), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 804 | }, |
| 805 | }; |
| 806 | |
| 807 | static struct branch_clk gfx3d_axi_clk_8930 = { |
| 808 | .b = { |
| 809 | .ctl_reg = MAXI_EN5_REG, |
| 810 | .en_mask = BIT(12), |
| 811 | .reset_reg = SW_RESET_AXI_REG, |
| 812 | .reset_mask = BIT(16), |
| 813 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 814 | .halt_bit = 12, |
| 815 | }, |
| 816 | .c = { |
| 817 | .dbg_name = "gfx3d_axi_clk", |
| 818 | .ops = &clk_ops_branch, |
| 819 | CLK_INIT(gfx3d_axi_clk_8930.c), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 820 | }, |
| 821 | }; |
| 822 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 823 | /* AHB Interfaces */ |
| 824 | static struct branch_clk amp_p_clk = { |
| 825 | .b = { |
| 826 | .ctl_reg = AHB_EN_REG, |
| 827 | .en_mask = BIT(24), |
Matt Wagantall | d40857a | 2012-04-10 19:15:43 -0700 | [diff] [blame] | 828 | .reset_reg = SW_RESET_CORE_REG, |
| 829 | .reset_mask = BIT(20), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 830 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 831 | .halt_bit = 18, |
| 832 | }, |
| 833 | .c = { |
| 834 | .dbg_name = "amp_p_clk", |
| 835 | .ops = &clk_ops_branch, |
| 836 | CLK_INIT(amp_p_clk.c), |
| 837 | }, |
| 838 | }; |
| 839 | |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 840 | static struct branch_clk csi_p_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 841 | .b = { |
| 842 | .ctl_reg = AHB_EN_REG, |
| 843 | .en_mask = BIT(7), |
| 844 | .reset_reg = SW_RESET_AHB_REG, |
| 845 | .reset_mask = BIT(17), |
| 846 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 847 | .halt_bit = 16, |
| 848 | }, |
| 849 | .c = { |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 850 | .dbg_name = "csi_p_clk", |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 851 | .ops = &clk_ops_branch, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 852 | CLK_INIT(csi_p_clk.c), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 853 | }, |
| 854 | }; |
| 855 | |
| 856 | static struct branch_clk dsi1_m_p_clk = { |
| 857 | .b = { |
| 858 | .ctl_reg = AHB_EN_REG, |
| 859 | .en_mask = BIT(9), |
| 860 | .reset_reg = SW_RESET_AHB_REG, |
| 861 | .reset_mask = BIT(6), |
| 862 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 863 | .halt_bit = 19, |
| 864 | }, |
| 865 | .c = { |
| 866 | .dbg_name = "dsi1_m_p_clk", |
| 867 | .ops = &clk_ops_branch, |
| 868 | CLK_INIT(dsi1_m_p_clk.c), |
| 869 | }, |
| 870 | }; |
| 871 | |
| 872 | static struct branch_clk dsi1_s_p_clk = { |
| 873 | .b = { |
| 874 | .ctl_reg = AHB_EN_REG, |
| 875 | .en_mask = BIT(18), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 876 | .hwcg_reg = AHB_EN2_REG, |
| 877 | .hwcg_mask = BIT(20), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 878 | .reset_reg = SW_RESET_AHB_REG, |
| 879 | .reset_mask = BIT(5), |
| 880 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 881 | .halt_bit = 21, |
| 882 | }, |
| 883 | .c = { |
| 884 | .dbg_name = "dsi1_s_p_clk", |
| 885 | .ops = &clk_ops_branch, |
| 886 | CLK_INIT(dsi1_s_p_clk.c), |
| 887 | }, |
| 888 | }; |
| 889 | |
| 890 | static struct branch_clk dsi2_m_p_clk = { |
| 891 | .b = { |
| 892 | .ctl_reg = AHB_EN_REG, |
| 893 | .en_mask = BIT(17), |
| 894 | .reset_reg = SW_RESET_AHB2_REG, |
| 895 | .reset_mask = BIT(1), |
| 896 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 897 | .halt_bit = 18, |
| 898 | }, |
| 899 | .c = { |
| 900 | .dbg_name = "dsi2_m_p_clk", |
| 901 | .ops = &clk_ops_branch, |
| 902 | CLK_INIT(dsi2_m_p_clk.c), |
| 903 | }, |
| 904 | }; |
| 905 | |
| 906 | static struct branch_clk dsi2_s_p_clk = { |
| 907 | .b = { |
| 908 | .ctl_reg = AHB_EN_REG, |
| 909 | .en_mask = BIT(22), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 910 | .hwcg_reg = AHB_EN2_REG, |
| 911 | .hwcg_mask = BIT(15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 912 | .reset_reg = SW_RESET_AHB2_REG, |
| 913 | .reset_mask = BIT(0), |
| 914 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 915 | .halt_bit = 20, |
| 916 | }, |
| 917 | .c = { |
| 918 | .dbg_name = "dsi2_s_p_clk", |
| 919 | .ops = &clk_ops_branch, |
| 920 | CLK_INIT(dsi2_s_p_clk.c), |
| 921 | }, |
| 922 | }; |
| 923 | |
| 924 | static struct branch_clk gfx2d0_p_clk = { |
| 925 | .b = { |
| 926 | .ctl_reg = AHB_EN_REG, |
| 927 | .en_mask = BIT(19), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 928 | .hwcg_reg = AHB_EN2_REG, |
| 929 | .hwcg_mask = BIT(28), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 930 | .reset_reg = SW_RESET_AHB_REG, |
| 931 | .reset_mask = BIT(12), |
| 932 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 933 | .halt_bit = 2, |
| 934 | }, |
| 935 | .c = { |
| 936 | .dbg_name = "gfx2d0_p_clk", |
| 937 | .ops = &clk_ops_branch, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 938 | .flags = CLKFLAG_SKIP_HANDOFF, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 939 | CLK_INIT(gfx2d0_p_clk.c), |
| 940 | }, |
| 941 | }; |
| 942 | |
| 943 | static struct branch_clk gfx2d1_p_clk = { |
| 944 | .b = { |
| 945 | .ctl_reg = AHB_EN_REG, |
| 946 | .en_mask = BIT(2), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 947 | .hwcg_reg = AHB_EN2_REG, |
| 948 | .hwcg_mask = BIT(29), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 949 | .reset_reg = SW_RESET_AHB_REG, |
| 950 | .reset_mask = BIT(11), |
| 951 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 952 | .halt_bit = 3, |
| 953 | }, |
| 954 | .c = { |
| 955 | .dbg_name = "gfx2d1_p_clk", |
| 956 | .ops = &clk_ops_branch, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 957 | .flags = CLKFLAG_SKIP_HANDOFF, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 958 | CLK_INIT(gfx2d1_p_clk.c), |
| 959 | }, |
| 960 | }; |
| 961 | |
| 962 | static struct branch_clk gfx3d_p_clk = { |
| 963 | .b = { |
| 964 | .ctl_reg = AHB_EN_REG, |
| 965 | .en_mask = BIT(3), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 966 | .hwcg_reg = AHB_EN2_REG, |
| 967 | .hwcg_mask = BIT(27), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 968 | .reset_reg = SW_RESET_AHB_REG, |
| 969 | .reset_mask = BIT(10), |
| 970 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 971 | .halt_bit = 4, |
| 972 | }, |
| 973 | .c = { |
| 974 | .dbg_name = "gfx3d_p_clk", |
| 975 | .ops = &clk_ops_branch, |
| 976 | CLK_INIT(gfx3d_p_clk.c), |
| 977 | }, |
| 978 | }; |
| 979 | |
| 980 | static struct branch_clk hdmi_m_p_clk = { |
| 981 | .b = { |
| 982 | .ctl_reg = AHB_EN_REG, |
| 983 | .en_mask = BIT(14), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 984 | .hwcg_reg = AHB_EN2_REG, |
| 985 | .hwcg_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 986 | .reset_reg = SW_RESET_AHB_REG, |
| 987 | .reset_mask = BIT(9), |
| 988 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 989 | .halt_bit = 5, |
| 990 | }, |
| 991 | .c = { |
| 992 | .dbg_name = "hdmi_m_p_clk", |
| 993 | .ops = &clk_ops_branch, |
| 994 | CLK_INIT(hdmi_m_p_clk.c), |
| 995 | }, |
| 996 | }; |
| 997 | |
| 998 | static struct branch_clk hdmi_s_p_clk = { |
| 999 | .b = { |
| 1000 | .ctl_reg = AHB_EN_REG, |
| 1001 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1002 | .hwcg_reg = AHB_EN2_REG, |
| 1003 | .hwcg_mask = BIT(22), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1004 | .reset_reg = SW_RESET_AHB_REG, |
| 1005 | .reset_mask = BIT(9), |
| 1006 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1007 | .halt_bit = 6, |
| 1008 | }, |
| 1009 | .c = { |
| 1010 | .dbg_name = "hdmi_s_p_clk", |
| 1011 | .ops = &clk_ops_branch, |
| 1012 | CLK_INIT(hdmi_s_p_clk.c), |
| 1013 | }, |
| 1014 | }; |
| 1015 | |
| 1016 | static struct branch_clk ijpeg_p_clk = { |
| 1017 | .b = { |
| 1018 | .ctl_reg = AHB_EN_REG, |
| 1019 | .en_mask = BIT(5), |
| 1020 | .reset_reg = SW_RESET_AHB_REG, |
| 1021 | .reset_mask = BIT(7), |
| 1022 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1023 | .halt_bit = 9, |
| 1024 | }, |
| 1025 | .c = { |
| 1026 | .dbg_name = "ijpeg_p_clk", |
| 1027 | .ops = &clk_ops_branch, |
| 1028 | CLK_INIT(ijpeg_p_clk.c), |
| 1029 | }, |
| 1030 | }; |
| 1031 | |
| 1032 | static struct branch_clk imem_p_clk = { |
| 1033 | .b = { |
| 1034 | .ctl_reg = AHB_EN_REG, |
| 1035 | .en_mask = BIT(6), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1036 | .hwcg_reg = AHB_EN2_REG, |
| 1037 | .hwcg_mask = BIT(12), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1038 | .reset_reg = SW_RESET_AHB_REG, |
| 1039 | .reset_mask = BIT(8), |
| 1040 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1041 | .halt_bit = 10, |
| 1042 | }, |
| 1043 | .c = { |
| 1044 | .dbg_name = "imem_p_clk", |
| 1045 | .ops = &clk_ops_branch, |
| 1046 | CLK_INIT(imem_p_clk.c), |
| 1047 | }, |
| 1048 | }; |
| 1049 | |
| 1050 | static struct branch_clk jpegd_p_clk = { |
| 1051 | .b = { |
| 1052 | .ctl_reg = AHB_EN_REG, |
| 1053 | .en_mask = BIT(21), |
| 1054 | .reset_reg = SW_RESET_AHB_REG, |
| 1055 | .reset_mask = BIT(4), |
| 1056 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1057 | .halt_bit = 7, |
| 1058 | }, |
| 1059 | .c = { |
| 1060 | .dbg_name = "jpegd_p_clk", |
| 1061 | .ops = &clk_ops_branch, |
| 1062 | CLK_INIT(jpegd_p_clk.c), |
| 1063 | }, |
| 1064 | }; |
| 1065 | |
| 1066 | static struct branch_clk mdp_p_clk = { |
| 1067 | .b = { |
| 1068 | .ctl_reg = AHB_EN_REG, |
| 1069 | .en_mask = BIT(10), |
| 1070 | .reset_reg = SW_RESET_AHB_REG, |
| 1071 | .reset_mask = BIT(3), |
| 1072 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1073 | .halt_bit = 11, |
| 1074 | }, |
| 1075 | .c = { |
| 1076 | .dbg_name = "mdp_p_clk", |
| 1077 | .ops = &clk_ops_branch, |
| 1078 | CLK_INIT(mdp_p_clk.c), |
| 1079 | }, |
| 1080 | }; |
| 1081 | |
| 1082 | static struct branch_clk rot_p_clk = { |
| 1083 | .b = { |
| 1084 | .ctl_reg = AHB_EN_REG, |
| 1085 | .en_mask = BIT(12), |
| 1086 | .reset_reg = SW_RESET_AHB_REG, |
| 1087 | .reset_mask = BIT(2), |
| 1088 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1089 | .halt_bit = 13, |
| 1090 | }, |
| 1091 | .c = { |
| 1092 | .dbg_name = "rot_p_clk", |
| 1093 | .ops = &clk_ops_branch, |
| 1094 | CLK_INIT(rot_p_clk.c), |
| 1095 | }, |
| 1096 | }; |
| 1097 | |
| 1098 | static struct branch_clk smmu_p_clk = { |
| 1099 | .b = { |
| 1100 | .ctl_reg = AHB_EN_REG, |
| 1101 | .en_mask = BIT(15), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1102 | .hwcg_reg = AHB_EN_REG, |
| 1103 | .hwcg_mask = BIT(26), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1104 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1105 | .halt_bit = 22, |
| 1106 | }, |
| 1107 | .c = { |
| 1108 | .dbg_name = "smmu_p_clk", |
| 1109 | .ops = &clk_ops_branch, |
| 1110 | CLK_INIT(smmu_p_clk.c), |
| 1111 | }, |
| 1112 | }; |
| 1113 | |
| 1114 | static struct branch_clk tv_enc_p_clk = { |
| 1115 | .b = { |
| 1116 | .ctl_reg = AHB_EN_REG, |
| 1117 | .en_mask = BIT(25), |
| 1118 | .reset_reg = SW_RESET_AHB_REG, |
| 1119 | .reset_mask = BIT(15), |
| 1120 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1121 | .halt_bit = 23, |
| 1122 | }, |
| 1123 | .c = { |
| 1124 | .dbg_name = "tv_enc_p_clk", |
| 1125 | .ops = &clk_ops_branch, |
| 1126 | CLK_INIT(tv_enc_p_clk.c), |
| 1127 | }, |
| 1128 | }; |
| 1129 | |
| 1130 | static struct branch_clk vcodec_p_clk = { |
| 1131 | .b = { |
| 1132 | .ctl_reg = AHB_EN_REG, |
| 1133 | .en_mask = BIT(11), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1134 | .hwcg_reg = AHB_EN2_REG, |
| 1135 | .hwcg_mask = BIT(26), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1136 | .reset_reg = SW_RESET_AHB_REG, |
| 1137 | .reset_mask = BIT(1), |
| 1138 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1139 | .halt_bit = 12, |
| 1140 | }, |
| 1141 | .c = { |
| 1142 | .dbg_name = "vcodec_p_clk", |
| 1143 | .ops = &clk_ops_branch, |
| 1144 | CLK_INIT(vcodec_p_clk.c), |
| 1145 | }, |
| 1146 | }; |
| 1147 | |
| 1148 | static struct branch_clk vfe_p_clk = { |
| 1149 | .b = { |
| 1150 | .ctl_reg = AHB_EN_REG, |
| 1151 | .en_mask = BIT(13), |
| 1152 | .reset_reg = SW_RESET_AHB_REG, |
| 1153 | .reset_mask = BIT(0), |
| 1154 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1155 | .halt_bit = 14, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 1156 | .retain_reg = AHB_EN2_REG, |
| 1157 | .retain_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1158 | }, |
| 1159 | .c = { |
| 1160 | .dbg_name = "vfe_p_clk", |
| 1161 | .ops = &clk_ops_branch, |
| 1162 | CLK_INIT(vfe_p_clk.c), |
| 1163 | }, |
| 1164 | }; |
| 1165 | |
| 1166 | static struct branch_clk vpe_p_clk = { |
| 1167 | .b = { |
| 1168 | .ctl_reg = AHB_EN_REG, |
| 1169 | .en_mask = BIT(16), |
| 1170 | .reset_reg = SW_RESET_AHB_REG, |
| 1171 | .reset_mask = BIT(14), |
| 1172 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1173 | .halt_bit = 15, |
| 1174 | }, |
| 1175 | .c = { |
| 1176 | .dbg_name = "vpe_p_clk", |
| 1177 | .ops = &clk_ops_branch, |
| 1178 | CLK_INIT(vpe_p_clk.c), |
| 1179 | }, |
| 1180 | }; |
| 1181 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1182 | static struct branch_clk vcap_p_clk = { |
| 1183 | .b = { |
| 1184 | .ctl_reg = AHB_EN3_REG, |
| 1185 | .en_mask = BIT(1), |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 1186 | .hwcg_reg = AHB_EN3_REG, |
| 1187 | .hwcg_mask = BIT(0), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1188 | .reset_reg = SW_RESET_AHB2_REG, |
| 1189 | .reset_mask = BIT(2), |
| 1190 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 1191 | .halt_bit = 23, |
| 1192 | }, |
| 1193 | .c = { |
| 1194 | .dbg_name = "vcap_p_clk", |
| 1195 | .ops = &clk_ops_branch, |
| 1196 | CLK_INIT(vcap_p_clk.c), |
| 1197 | }, |
| 1198 | }; |
| 1199 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1200 | /* |
| 1201 | * Peripheral Clocks |
| 1202 | */ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1203 | #define CLK_GP(i, n, h_r, h_b) \ |
| 1204 | struct rcg_clk i##_clk = { \ |
| 1205 | .b = { \ |
| 1206 | .ctl_reg = GPn_NS_REG(n), \ |
| 1207 | .en_mask = BIT(9), \ |
| 1208 | .halt_reg = h_r, \ |
| 1209 | .halt_bit = h_b, \ |
| 1210 | }, \ |
| 1211 | .ns_reg = GPn_NS_REG(n), \ |
| 1212 | .md_reg = GPn_MD_REG(n), \ |
| 1213 | .root_en_mask = BIT(11), \ |
| 1214 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1215 | .mnd_en_mask = BIT(8), \ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1216 | .set_rate = set_rate_mnd, \ |
| 1217 | .freq_tbl = clk_tbl_gp, \ |
| 1218 | .current_freq = &rcg_dummy_freq, \ |
| 1219 | .c = { \ |
| 1220 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1221 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1222 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \ |
| 1223 | CLK_INIT(i##_clk.c), \ |
| 1224 | }, \ |
| 1225 | } |
| 1226 | #define F_GP(f, s, d, m, n) \ |
| 1227 | { \ |
| 1228 | .freq_hz = f, \ |
| 1229 | .src_clk = &s##_clk.c, \ |
| 1230 | .md_val = MD8(16, m, 0, n), \ |
| 1231 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1232 | } |
| 1233 | static struct clk_freq_tbl clk_tbl_gp[] = { |
| 1234 | F_GP( 0, gnd, 1, 0, 0), |
| 1235 | F_GP( 9600000, cxo, 2, 0, 0), |
| 1236 | F_GP( 13500000, pxo, 2, 0, 0), |
| 1237 | F_GP( 19200000, cxo, 1, 0, 0), |
| 1238 | F_GP( 27000000, pxo, 1, 0, 0), |
| 1239 | F_GP( 64000000, pll8, 2, 1, 3), |
| 1240 | F_GP( 76800000, pll8, 1, 1, 5), |
| 1241 | F_GP( 96000000, pll8, 4, 0, 0), |
| 1242 | F_GP(128000000, pll8, 3, 0, 0), |
| 1243 | F_GP(192000000, pll8, 2, 0, 0), |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1244 | F_END |
| 1245 | }; |
| 1246 | |
| 1247 | static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7); |
| 1248 | static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6); |
| 1249 | static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5); |
| 1250 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1251 | #define CLK_GSBI_UART(i, n, h_r, h_b) \ |
| 1252 | struct rcg_clk i##_clk = { \ |
| 1253 | .b = { \ |
| 1254 | .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \ |
| 1255 | .en_mask = BIT(9), \ |
| 1256 | .reset_reg = GSBIn_RESET_REG(n), \ |
| 1257 | .reset_mask = BIT(0), \ |
| 1258 | .halt_reg = h_r, \ |
| 1259 | .halt_bit = h_b, \ |
| 1260 | }, \ |
| 1261 | .ns_reg = GSBIn_UART_APPS_NS_REG(n), \ |
| 1262 | .md_reg = GSBIn_UART_APPS_MD_REG(n), \ |
| 1263 | .root_en_mask = BIT(11), \ |
| 1264 | .ns_mask = (BM(31, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1265 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1266 | .set_rate = set_rate_mnd, \ |
| 1267 | .freq_tbl = clk_tbl_gsbi_uart, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1268 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1269 | .c = { \ |
| 1270 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1271 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1272 | VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1273 | CLK_INIT(i##_clk.c), \ |
| 1274 | }, \ |
| 1275 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1276 | #define F_GSBI_UART(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1277 | { \ |
| 1278 | .freq_hz = f, \ |
| 1279 | .src_clk = &s##_clk.c, \ |
| 1280 | .md_val = MD16(m, n), \ |
| 1281 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1282 | } |
| 1283 | static struct clk_freq_tbl clk_tbl_gsbi_uart[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1284 | F_GSBI_UART( 0, gnd, 1, 0, 0), |
Matt Wagantall | 9a561f7 | 2012-01-19 16:13:12 -0800 | [diff] [blame] | 1285 | F_GSBI_UART( 1843200, pll8, 2, 6, 625), |
| 1286 | F_GSBI_UART( 3686400, pll8, 2, 12, 625), |
| 1287 | F_GSBI_UART( 7372800, pll8, 2, 24, 625), |
| 1288 | F_GSBI_UART(14745600, pll8, 2, 48, 625), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1289 | F_GSBI_UART(16000000, pll8, 4, 1, 6), |
| 1290 | F_GSBI_UART(24000000, pll8, 4, 1, 4), |
| 1291 | F_GSBI_UART(32000000, pll8, 4, 1, 3), |
| 1292 | F_GSBI_UART(40000000, pll8, 1, 5, 48), |
| 1293 | F_GSBI_UART(46400000, pll8, 1, 29, 240), |
| 1294 | F_GSBI_UART(48000000, pll8, 4, 1, 2), |
| 1295 | F_GSBI_UART(51200000, pll8, 1, 2, 15), |
| 1296 | F_GSBI_UART(56000000, pll8, 1, 7, 48), |
| 1297 | F_GSBI_UART(58982400, pll8, 1, 96, 625), |
| 1298 | F_GSBI_UART(64000000, pll8, 2, 1, 3), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1299 | F_END |
| 1300 | }; |
| 1301 | |
| 1302 | static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10); |
| 1303 | static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6); |
| 1304 | static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2); |
| 1305 | static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26); |
| 1306 | static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22); |
| 1307 | static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18); |
| 1308 | static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14); |
| 1309 | static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10); |
| 1310 | static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6); |
| 1311 | static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2); |
| 1312 | static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17); |
| 1313 | static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13); |
| 1314 | |
| 1315 | #define CLK_GSBI_QUP(i, n, h_r, h_b) \ |
| 1316 | struct rcg_clk i##_clk = { \ |
| 1317 | .b = { \ |
| 1318 | .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \ |
| 1319 | .en_mask = BIT(9), \ |
| 1320 | .reset_reg = GSBIn_RESET_REG(n), \ |
| 1321 | .reset_mask = BIT(0), \ |
| 1322 | .halt_reg = h_r, \ |
| 1323 | .halt_bit = h_b, \ |
| 1324 | }, \ |
| 1325 | .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \ |
| 1326 | .md_reg = GSBIn_QUP_APPS_MD_REG(n), \ |
| 1327 | .root_en_mask = BIT(11), \ |
| 1328 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1329 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1330 | .set_rate = set_rate_mnd, \ |
| 1331 | .freq_tbl = clk_tbl_gsbi_qup, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1332 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1333 | .c = { \ |
| 1334 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1335 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1336 | VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1337 | CLK_INIT(i##_clk.c), \ |
| 1338 | }, \ |
| 1339 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1340 | #define F_GSBI_QUP(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1341 | { \ |
| 1342 | .freq_hz = f, \ |
| 1343 | .src_clk = &s##_clk.c, \ |
| 1344 | .md_val = MD8(16, m, 0, n), \ |
| 1345 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1346 | } |
| 1347 | static struct clk_freq_tbl clk_tbl_gsbi_qup[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1348 | F_GSBI_QUP( 0, gnd, 1, 0, 0), |
| 1349 | F_GSBI_QUP( 1100000, pxo, 1, 2, 49), |
| 1350 | F_GSBI_QUP( 5400000, pxo, 1, 1, 5), |
| 1351 | F_GSBI_QUP(10800000, pxo, 1, 2, 5), |
| 1352 | F_GSBI_QUP(15060000, pll8, 1, 2, 51), |
| 1353 | F_GSBI_QUP(24000000, pll8, 4, 1, 4), |
| 1354 | F_GSBI_QUP(25600000, pll8, 1, 1, 15), |
| 1355 | F_GSBI_QUP(27000000, pxo, 1, 0, 0), |
| 1356 | F_GSBI_QUP(48000000, pll8, 4, 1, 2), |
| 1357 | F_GSBI_QUP(51200000, pll8, 1, 2, 15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1358 | F_END |
| 1359 | }; |
| 1360 | |
| 1361 | static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9); |
| 1362 | static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4); |
| 1363 | static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0); |
| 1364 | static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24); |
| 1365 | static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20); |
| 1366 | static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16); |
| 1367 | static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12); |
| 1368 | static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8); |
| 1369 | static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4); |
| 1370 | static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0); |
| 1371 | static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15); |
| 1372 | static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11); |
| 1373 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1374 | #define F_PDM(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1375 | { \ |
| 1376 | .freq_hz = f, \ |
| 1377 | .src_clk = &s##_clk.c, \ |
| 1378 | .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1379 | } |
| 1380 | static struct clk_freq_tbl clk_tbl_pdm[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1381 | F_PDM( 0, gnd, 1), |
| 1382 | F_PDM(27000000, pxo, 1), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1383 | F_END |
| 1384 | }; |
| 1385 | |
| 1386 | static struct rcg_clk pdm_clk = { |
| 1387 | .b = { |
| 1388 | .ctl_reg = PDM_CLK_NS_REG, |
| 1389 | .en_mask = BIT(9), |
| 1390 | .reset_reg = PDM_CLK_NS_REG, |
| 1391 | .reset_mask = BIT(12), |
| 1392 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1393 | .halt_bit = 3, |
| 1394 | }, |
| 1395 | .ns_reg = PDM_CLK_NS_REG, |
| 1396 | .root_en_mask = BIT(11), |
| 1397 | .ns_mask = BM(1, 0), |
| 1398 | .set_rate = set_rate_nop, |
| 1399 | .freq_tbl = clk_tbl_pdm, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1400 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1401 | .c = { |
| 1402 | .dbg_name = "pdm_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1403 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1404 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1405 | CLK_INIT(pdm_clk.c), |
| 1406 | }, |
| 1407 | }; |
| 1408 | |
| 1409 | static struct branch_clk pmem_clk = { |
| 1410 | .b = { |
| 1411 | .ctl_reg = PMEM_ACLK_CTL_REG, |
| 1412 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1413 | .hwcg_reg = PMEM_ACLK_CTL_REG, |
| 1414 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1415 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 1416 | .halt_bit = 20, |
| 1417 | }, |
| 1418 | .c = { |
| 1419 | .dbg_name = "pmem_clk", |
| 1420 | .ops = &clk_ops_branch, |
| 1421 | CLK_INIT(pmem_clk.c), |
| 1422 | }, |
| 1423 | }; |
| 1424 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1425 | #define F_PRNG(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1426 | { \ |
| 1427 | .freq_hz = f, \ |
| 1428 | .src_clk = &s##_clk.c, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1429 | } |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 1430 | static struct clk_freq_tbl clk_tbl_prng_32[] = { |
| 1431 | F_PRNG(32000000, pll8), |
| 1432 | F_END |
| 1433 | }; |
| 1434 | |
| 1435 | static struct clk_freq_tbl clk_tbl_prng_64[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1436 | F_PRNG(64000000, pll8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1437 | F_END |
| 1438 | }; |
| 1439 | |
| 1440 | static struct rcg_clk prng_clk = { |
| 1441 | .b = { |
| 1442 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 1443 | .en_mask = BIT(10), |
| 1444 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 1445 | .halt_check = HALT_VOTED, |
| 1446 | .halt_bit = 10, |
| 1447 | }, |
| 1448 | .set_rate = set_rate_nop, |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 1449 | .freq_tbl = clk_tbl_prng_32, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1450 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1451 | .c = { |
| 1452 | .dbg_name = "prng_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1453 | .ops = &clk_ops_rcg, |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 1454 | VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1455 | CLK_INIT(prng_clk.c), |
| 1456 | }, |
| 1457 | }; |
| 1458 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1459 | #define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1460 | struct rcg_clk name = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1461 | .b = { \ |
| 1462 | .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \ |
| 1463 | .en_mask = BIT(9), \ |
| 1464 | .reset_reg = SDCn_RESET_REG(n), \ |
| 1465 | .reset_mask = BIT(0), \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1466 | .halt_reg = CLK_HALT_DFAB_STATE_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1467 | .halt_bit = h_b, \ |
| 1468 | }, \ |
| 1469 | .ns_reg = SDCn_APPS_CLK_NS_REG(n), \ |
| 1470 | .md_reg = SDCn_APPS_CLK_MD_REG(n), \ |
| 1471 | .root_en_mask = BIT(11), \ |
| 1472 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1473 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1474 | .set_rate = set_rate_mnd, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1475 | .freq_tbl = clk_tbl_sdc, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1476 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1477 | .c = { \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1478 | .dbg_name = #name, \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1479 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1480 | VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1481 | CLK_INIT(name.c), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1482 | }, \ |
| 1483 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1484 | #define F_SDC(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1485 | { \ |
| 1486 | .freq_hz = f, \ |
| 1487 | .src_clk = &s##_clk.c, \ |
| 1488 | .md_val = MD8(16, m, 0, n), \ |
| 1489 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1490 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1491 | static struct clk_freq_tbl clk_tbl_sdc[] = { |
| 1492 | F_SDC( 0, gnd, 1, 0, 0), |
| 1493 | F_SDC( 144000, pxo, 3, 2, 125), |
| 1494 | F_SDC( 400000, pll8, 4, 1, 240), |
| 1495 | F_SDC( 16000000, pll8, 4, 1, 6), |
| 1496 | F_SDC( 17070000, pll8, 1, 2, 45), |
| 1497 | F_SDC( 20210000, pll8, 1, 1, 19), |
| 1498 | F_SDC( 24000000, pll8, 4, 1, 4), |
| 1499 | F_SDC( 48000000, pll8, 4, 1, 2), |
| 1500 | F_SDC( 64000000, pll8, 3, 1, 2), |
| 1501 | F_SDC( 96000000, pll8, 4, 0, 0), |
Subhash Jadavani | bd238ba | 2011-11-24 15:12:39 +0530 | [diff] [blame] | 1502 | F_SDC(192000000, pll8, 2, 0, 0), |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1503 | F_END |
| 1504 | }; |
| 1505 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1506 | static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000); |
| 1507 | static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000); |
| 1508 | static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000); |
| 1509 | static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000); |
| 1510 | static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000); |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1511 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1512 | #define F_TSIF_REF(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1513 | { \ |
| 1514 | .freq_hz = f, \ |
| 1515 | .src_clk = &s##_clk.c, \ |
| 1516 | .md_val = MD16(m, n), \ |
| 1517 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1518 | } |
| 1519 | static struct clk_freq_tbl clk_tbl_tsif_ref[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1520 | F_TSIF_REF( 0, gnd, 1, 0, 0), |
| 1521 | F_TSIF_REF(105000, pxo, 1, 1, 256), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1522 | F_END |
| 1523 | }; |
| 1524 | |
| 1525 | static struct rcg_clk tsif_ref_clk = { |
| 1526 | .b = { |
| 1527 | .ctl_reg = TSIF_REF_CLK_NS_REG, |
| 1528 | .en_mask = BIT(9), |
| 1529 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1530 | .halt_bit = 5, |
| 1531 | }, |
| 1532 | .ns_reg = TSIF_REF_CLK_NS_REG, |
| 1533 | .md_reg = TSIF_REF_CLK_MD_REG, |
| 1534 | .root_en_mask = BIT(11), |
| 1535 | .ns_mask = (BM(31, 16) | BM(6, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1536 | .mnd_en_mask = BIT(8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1537 | .set_rate = set_rate_mnd, |
| 1538 | .freq_tbl = clk_tbl_tsif_ref, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1539 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1540 | .c = { |
| 1541 | .dbg_name = "tsif_ref_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1542 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1543 | VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1544 | CLK_INIT(tsif_ref_clk.c), |
| 1545 | }, |
| 1546 | }; |
| 1547 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1548 | #define F_TSSC(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1549 | { \ |
| 1550 | .freq_hz = f, \ |
| 1551 | .src_clk = &s##_clk.c, \ |
| 1552 | .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1553 | } |
| 1554 | static struct clk_freq_tbl clk_tbl_tssc[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1555 | F_TSSC( 0, gnd), |
| 1556 | F_TSSC(27000000, pxo), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1557 | F_END |
| 1558 | }; |
| 1559 | |
| 1560 | static struct rcg_clk tssc_clk = { |
| 1561 | .b = { |
| 1562 | .ctl_reg = TSSC_CLK_CTL_REG, |
| 1563 | .en_mask = BIT(4), |
| 1564 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1565 | .halt_bit = 4, |
| 1566 | }, |
| 1567 | .ns_reg = TSSC_CLK_CTL_REG, |
| 1568 | .ns_mask = BM(1, 0), |
| 1569 | .set_rate = set_rate_nop, |
| 1570 | .freq_tbl = clk_tbl_tssc, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1571 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1572 | .c = { |
| 1573 | .dbg_name = "tssc_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1574 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1575 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1576 | CLK_INIT(tssc_clk.c), |
| 1577 | }, |
| 1578 | }; |
| 1579 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1580 | #define CLK_USB_HS(name, n, h_b) \ |
| 1581 | static struct rcg_clk name = { \ |
| 1582 | .b = { \ |
| 1583 | .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \ |
| 1584 | .en_mask = BIT(9), \ |
| 1585 | .reset_reg = USB_HS##n##_RESET_REG, \ |
| 1586 | .reset_mask = BIT(0), \ |
| 1587 | .halt_reg = CLK_HALT_DFAB_STATE_REG, \ |
| 1588 | .halt_bit = h_b, \ |
| 1589 | }, \ |
| 1590 | .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \ |
| 1591 | .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \ |
| 1592 | .root_en_mask = BIT(11), \ |
| 1593 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1594 | .mnd_en_mask = BIT(8), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1595 | .set_rate = set_rate_mnd, \ |
| 1596 | .freq_tbl = clk_tbl_usb, \ |
| 1597 | .current_freq = &rcg_dummy_freq, \ |
| 1598 | .c = { \ |
| 1599 | .dbg_name = #name, \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1600 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1601 | VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1602 | CLK_INIT(name.c), \ |
| 1603 | }, \ |
| 1604 | } |
| 1605 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1606 | #define F_USB(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1607 | { \ |
| 1608 | .freq_hz = f, \ |
| 1609 | .src_clk = &s##_clk.c, \ |
| 1610 | .md_val = MD8(16, m, 0, n), \ |
| 1611 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1612 | } |
| 1613 | static struct clk_freq_tbl clk_tbl_usb[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1614 | F_USB( 0, gnd, 1, 0, 0), |
| 1615 | F_USB(60000000, pll8, 1, 5, 32), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1616 | F_END |
| 1617 | }; |
| 1618 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1619 | CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0); |
| 1620 | CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30); |
| 1621 | CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1622 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1623 | static struct clk_freq_tbl clk_tbl_usb_hsic[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1624 | F_USB( 0, gnd, 1, 0, 0), |
| 1625 | F_USB(60000000, pll8, 1, 5, 32), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1626 | F_END |
| 1627 | }; |
| 1628 | |
| 1629 | static struct rcg_clk usb_hsic_xcvr_fs_clk = { |
| 1630 | .b = { |
| 1631 | .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG, |
| 1632 | .en_mask = BIT(9), |
| 1633 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1634 | .halt_bit = 26, |
| 1635 | }, |
| 1636 | .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG, |
| 1637 | .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG, |
| 1638 | .root_en_mask = BIT(11), |
| 1639 | .ns_mask = (BM(23, 16) | BM(6, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1640 | .mnd_en_mask = BIT(8), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1641 | .set_rate = set_rate_mnd, |
| 1642 | .freq_tbl = clk_tbl_usb_hsic, |
| 1643 | .current_freq = &rcg_dummy_freq, |
| 1644 | .c = { |
| 1645 | .dbg_name = "usb_hsic_xcvr_fs_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1646 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1647 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1648 | CLK_INIT(usb_hsic_xcvr_fs_clk.c), |
| 1649 | }, |
| 1650 | }; |
| 1651 | |
| 1652 | static struct branch_clk usb_hsic_system_clk = { |
| 1653 | .b = { |
| 1654 | .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG, |
| 1655 | .en_mask = BIT(4), |
| 1656 | .reset_reg = USB_HSIC_RESET_REG, |
| 1657 | .reset_mask = BIT(0), |
| 1658 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1659 | .halt_bit = 24, |
| 1660 | }, |
| 1661 | .parent = &usb_hsic_xcvr_fs_clk.c, |
| 1662 | .c = { |
| 1663 | .dbg_name = "usb_hsic_system_clk", |
| 1664 | .ops = &clk_ops_branch, |
| 1665 | CLK_INIT(usb_hsic_system_clk.c), |
| 1666 | }, |
| 1667 | }; |
| 1668 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1669 | #define F_USB_HSIC(f, s) \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1670 | { \ |
| 1671 | .freq_hz = f, \ |
| 1672 | .src_clk = &s##_clk.c, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1673 | } |
| 1674 | static struct clk_freq_tbl clk_tbl_usb2_hsic[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1675 | F_USB_HSIC(480000000, pll14), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1676 | F_END |
| 1677 | }; |
| 1678 | |
| 1679 | static struct rcg_clk usb_hsic_hsic_src_clk = { |
| 1680 | .b = { |
| 1681 | .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG, |
| 1682 | .halt_check = NOCHECK, |
| 1683 | }, |
| 1684 | .root_en_mask = BIT(0), |
| 1685 | .set_rate = set_rate_nop, |
| 1686 | .freq_tbl = clk_tbl_usb2_hsic, |
| 1687 | .current_freq = &rcg_dummy_freq, |
| 1688 | .c = { |
| 1689 | .dbg_name = "usb_hsic_hsic_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1690 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1691 | VDD_DIG_FMAX_MAP1(LOW, 480000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1692 | CLK_INIT(usb_hsic_hsic_src_clk.c), |
| 1693 | }, |
| 1694 | }; |
| 1695 | |
| 1696 | static struct branch_clk usb_hsic_hsic_clk = { |
| 1697 | .b = { |
| 1698 | .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG, |
| 1699 | .en_mask = BIT(0), |
| 1700 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1701 | .halt_bit = 19, |
| 1702 | }, |
| 1703 | .parent = &usb_hsic_hsic_src_clk.c, |
| 1704 | .c = { |
| 1705 | .dbg_name = "usb_hsic_hsic_clk", |
| 1706 | .ops = &clk_ops_branch, |
| 1707 | CLK_INIT(usb_hsic_hsic_clk.c), |
| 1708 | }, |
| 1709 | }; |
| 1710 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1711 | #define F_USB_HSIO_CAL(f, s) \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1712 | { \ |
| 1713 | .freq_hz = f, \ |
| 1714 | .src_clk = &s##_clk.c, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1715 | } |
| 1716 | static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1717 | F_USB_HSIO_CAL(9000000, pxo), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1718 | F_END |
| 1719 | }; |
| 1720 | |
| 1721 | static struct rcg_clk usb_hsic_hsio_cal_clk = { |
| 1722 | .b = { |
| 1723 | .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG, |
| 1724 | .en_mask = BIT(0), |
| 1725 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1726 | .halt_bit = 23, |
| 1727 | }, |
| 1728 | .set_rate = set_rate_nop, |
| 1729 | .freq_tbl = clk_tbl_usb_hsio_cal, |
| 1730 | .current_freq = &rcg_dummy_freq, |
| 1731 | .c = { |
| 1732 | .dbg_name = "usb_hsic_hsio_cal_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1733 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1734 | VDD_DIG_FMAX_MAP1(LOW, 10000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1735 | CLK_INIT(usb_hsic_hsio_cal_clk.c), |
| 1736 | }, |
| 1737 | }; |
| 1738 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1739 | static struct branch_clk usb_phy0_clk = { |
| 1740 | .b = { |
| 1741 | .reset_reg = USB_PHY0_RESET_REG, |
| 1742 | .reset_mask = BIT(0), |
| 1743 | }, |
| 1744 | .c = { |
| 1745 | .dbg_name = "usb_phy0_clk", |
| 1746 | .ops = &clk_ops_reset, |
| 1747 | CLK_INIT(usb_phy0_clk.c), |
| 1748 | }, |
| 1749 | }; |
| 1750 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1751 | #define CLK_USB_FS(i, n, fmax_nom) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1752 | struct rcg_clk i##_clk = { \ |
| 1753 | .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \ |
| 1754 | .b = { \ |
| 1755 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \ |
| 1756 | .halt_check = NOCHECK, \ |
| 1757 | }, \ |
| 1758 | .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \ |
| 1759 | .root_en_mask = BIT(11), \ |
| 1760 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 1761 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1762 | .set_rate = set_rate_mnd, \ |
| 1763 | .freq_tbl = clk_tbl_usb, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1764 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1765 | .c = { \ |
| 1766 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1767 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1768 | VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1769 | CLK_INIT(i##_clk.c), \ |
| 1770 | }, \ |
| 1771 | } |
| 1772 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1773 | static CLK_USB_FS(usb_fs1_src, 1, 64000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1774 | static struct branch_clk usb_fs1_xcvr_clk = { |
| 1775 | .b = { |
| 1776 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1), |
| 1777 | .en_mask = BIT(9), |
| 1778 | .reset_reg = USB_FSn_RESET_REG(1), |
| 1779 | .reset_mask = BIT(1), |
| 1780 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1781 | .halt_bit = 15, |
| 1782 | }, |
| 1783 | .parent = &usb_fs1_src_clk.c, |
| 1784 | .c = { |
| 1785 | .dbg_name = "usb_fs1_xcvr_clk", |
| 1786 | .ops = &clk_ops_branch, |
| 1787 | CLK_INIT(usb_fs1_xcvr_clk.c), |
| 1788 | }, |
| 1789 | }; |
| 1790 | |
| 1791 | static struct branch_clk usb_fs1_sys_clk = { |
| 1792 | .b = { |
| 1793 | .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1), |
| 1794 | .en_mask = BIT(4), |
| 1795 | .reset_reg = USB_FSn_RESET_REG(1), |
| 1796 | .reset_mask = BIT(0), |
| 1797 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1798 | .halt_bit = 16, |
| 1799 | }, |
| 1800 | .parent = &usb_fs1_src_clk.c, |
| 1801 | .c = { |
| 1802 | .dbg_name = "usb_fs1_sys_clk", |
| 1803 | .ops = &clk_ops_branch, |
| 1804 | CLK_INIT(usb_fs1_sys_clk.c), |
| 1805 | }, |
| 1806 | }; |
| 1807 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1808 | static CLK_USB_FS(usb_fs2_src, 2, 60000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1809 | static struct branch_clk usb_fs2_xcvr_clk = { |
| 1810 | .b = { |
| 1811 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2), |
| 1812 | .en_mask = BIT(9), |
| 1813 | .reset_reg = USB_FSn_RESET_REG(2), |
| 1814 | .reset_mask = BIT(1), |
| 1815 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1816 | .halt_bit = 12, |
| 1817 | }, |
| 1818 | .parent = &usb_fs2_src_clk.c, |
| 1819 | .c = { |
| 1820 | .dbg_name = "usb_fs2_xcvr_clk", |
| 1821 | .ops = &clk_ops_branch, |
| 1822 | CLK_INIT(usb_fs2_xcvr_clk.c), |
| 1823 | }, |
| 1824 | }; |
| 1825 | |
| 1826 | static struct branch_clk usb_fs2_sys_clk = { |
| 1827 | .b = { |
| 1828 | .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2), |
| 1829 | .en_mask = BIT(4), |
| 1830 | .reset_reg = USB_FSn_RESET_REG(2), |
| 1831 | .reset_mask = BIT(0), |
| 1832 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1833 | .halt_bit = 13, |
| 1834 | }, |
| 1835 | .parent = &usb_fs2_src_clk.c, |
| 1836 | .c = { |
| 1837 | .dbg_name = "usb_fs2_sys_clk", |
| 1838 | .ops = &clk_ops_branch, |
| 1839 | CLK_INIT(usb_fs2_sys_clk.c), |
| 1840 | }, |
| 1841 | }; |
| 1842 | |
| 1843 | /* Fast Peripheral Bus Clocks */ |
| 1844 | static struct branch_clk ce1_core_clk = { |
| 1845 | .b = { |
| 1846 | .ctl_reg = CE1_CORE_CLK_CTL_REG, |
| 1847 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1848 | .hwcg_reg = CE1_CORE_CLK_CTL_REG, |
| 1849 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1850 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1851 | .halt_bit = 27, |
| 1852 | }, |
| 1853 | .c = { |
| 1854 | .dbg_name = "ce1_core_clk", |
| 1855 | .ops = &clk_ops_branch, |
| 1856 | CLK_INIT(ce1_core_clk.c), |
| 1857 | }, |
| 1858 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1859 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1860 | static struct branch_clk ce1_p_clk = { |
| 1861 | .b = { |
| 1862 | .ctl_reg = CE1_HCLK_CTL_REG, |
| 1863 | .en_mask = BIT(4), |
| 1864 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1865 | .halt_bit = 1, |
| 1866 | }, |
| 1867 | .c = { |
| 1868 | .dbg_name = "ce1_p_clk", |
| 1869 | .ops = &clk_ops_branch, |
| 1870 | CLK_INIT(ce1_p_clk.c), |
| 1871 | }, |
| 1872 | }; |
| 1873 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1874 | #define F_CE3(f, s, d) \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1875 | { \ |
| 1876 | .freq_hz = f, \ |
| 1877 | .src_clk = &s##_clk.c, \ |
| 1878 | .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1879 | } |
| 1880 | |
| 1881 | static struct clk_freq_tbl clk_tbl_ce3[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1882 | F_CE3( 0, gnd, 1), |
| 1883 | F_CE3( 48000000, pll8, 8), |
| 1884 | F_CE3(100000000, pll3, 12), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1885 | F_END |
| 1886 | }; |
| 1887 | |
| 1888 | static struct rcg_clk ce3_src_clk = { |
| 1889 | .b = { |
| 1890 | .ctl_reg = CE3_CLK_SRC_NS_REG, |
| 1891 | .halt_check = NOCHECK, |
| 1892 | }, |
| 1893 | .ns_reg = CE3_CLK_SRC_NS_REG, |
| 1894 | .root_en_mask = BIT(7), |
| 1895 | .ns_mask = BM(6, 0), |
| 1896 | .set_rate = set_rate_nop, |
| 1897 | .freq_tbl = clk_tbl_ce3, |
| 1898 | .current_freq = &rcg_dummy_freq, |
| 1899 | .c = { |
| 1900 | .dbg_name = "ce3_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 1901 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1902 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1903 | CLK_INIT(ce3_src_clk.c), |
| 1904 | }, |
| 1905 | }; |
| 1906 | |
| 1907 | static struct branch_clk ce3_core_clk = { |
| 1908 | .b = { |
| 1909 | .ctl_reg = CE3_CORE_CLK_CTL_REG, |
| 1910 | .en_mask = BIT(4), |
| 1911 | .reset_reg = CE3_CORE_CLK_CTL_REG, |
| 1912 | .reset_mask = BIT(7), |
| 1913 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1914 | .halt_bit = 5, |
| 1915 | }, |
| 1916 | .parent = &ce3_src_clk.c, |
| 1917 | .c = { |
| 1918 | .dbg_name = "ce3_core_clk", |
| 1919 | .ops = &clk_ops_branch, |
| 1920 | CLK_INIT(ce3_core_clk.c), |
| 1921 | } |
| 1922 | }; |
| 1923 | |
| 1924 | static struct branch_clk ce3_p_clk = { |
| 1925 | .b = { |
| 1926 | .ctl_reg = CE3_HCLK_CTL_REG, |
| 1927 | .en_mask = BIT(4), |
| 1928 | .reset_reg = CE3_HCLK_CTL_REG, |
| 1929 | .reset_mask = BIT(7), |
| 1930 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG, |
| 1931 | .halt_bit = 16, |
| 1932 | }, |
| 1933 | .parent = &ce3_src_clk.c, |
| 1934 | .c = { |
| 1935 | .dbg_name = "ce3_p_clk", |
| 1936 | .ops = &clk_ops_branch, |
| 1937 | CLK_INIT(ce3_p_clk.c), |
| 1938 | } |
| 1939 | }; |
| 1940 | |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 1941 | #define F_SATA(f, s, d) \ |
| 1942 | { \ |
| 1943 | .freq_hz = f, \ |
| 1944 | .src_clk = &s##_clk.c, \ |
| 1945 | .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1946 | } |
| 1947 | |
| 1948 | static struct clk_freq_tbl clk_tbl_sata[] = { |
| 1949 | F_SATA( 0, gnd, 1), |
| 1950 | F_SATA( 48000000, pll8, 8), |
| 1951 | F_SATA(100000000, pll3, 12), |
| 1952 | F_END |
| 1953 | }; |
| 1954 | |
| 1955 | static struct rcg_clk sata_src_clk = { |
| 1956 | .b = { |
| 1957 | .ctl_reg = SATA_CLK_SRC_NS_REG, |
| 1958 | .halt_check = NOCHECK, |
| 1959 | }, |
| 1960 | .ns_reg = SATA_CLK_SRC_NS_REG, |
| 1961 | .root_en_mask = BIT(7), |
| 1962 | .ns_mask = BM(6, 0), |
| 1963 | .set_rate = set_rate_nop, |
| 1964 | .freq_tbl = clk_tbl_sata, |
| 1965 | .current_freq = &rcg_dummy_freq, |
| 1966 | .c = { |
| 1967 | .dbg_name = "sata_src_clk", |
| 1968 | .ops = &clk_ops_rcg, |
| 1969 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 1970 | CLK_INIT(sata_src_clk.c), |
| 1971 | }, |
| 1972 | }; |
| 1973 | |
| 1974 | static struct branch_clk sata_rxoob_clk = { |
| 1975 | .b = { |
| 1976 | .ctl_reg = SATA_RXOOB_CLK_CTL_REG, |
| 1977 | .en_mask = BIT(4), |
| 1978 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1979 | .halt_bit = 26, |
| 1980 | }, |
| 1981 | .parent = &sata_src_clk.c, |
| 1982 | .c = { |
| 1983 | .dbg_name = "sata_rxoob_clk", |
| 1984 | .ops = &clk_ops_branch, |
| 1985 | CLK_INIT(sata_rxoob_clk.c), |
| 1986 | }, |
| 1987 | }; |
| 1988 | |
| 1989 | static struct branch_clk sata_pmalive_clk = { |
| 1990 | .b = { |
| 1991 | .ctl_reg = SATA_PMALIVE_CLK_CTL_REG, |
| 1992 | .en_mask = BIT(4), |
| 1993 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1994 | .halt_bit = 25, |
| 1995 | }, |
| 1996 | .parent = &sata_src_clk.c, |
| 1997 | .c = { |
| 1998 | .dbg_name = "sata_pmalive_clk", |
| 1999 | .ops = &clk_ops_branch, |
| 2000 | CLK_INIT(sata_pmalive_clk.c), |
| 2001 | }, |
| 2002 | }; |
| 2003 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2004 | static struct branch_clk sata_phy_ref_clk = { |
| 2005 | .b = { |
| 2006 | .ctl_reg = SATA_PHY_REF_CLK_CTL_REG, |
| 2007 | .en_mask = BIT(4), |
| 2008 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2009 | .halt_bit = 24, |
| 2010 | }, |
| 2011 | .parent = &pxo_clk.c, |
| 2012 | .c = { |
| 2013 | .dbg_name = "sata_phy_ref_clk", |
| 2014 | .ops = &clk_ops_branch, |
| 2015 | CLK_INIT(sata_phy_ref_clk.c), |
| 2016 | }, |
| 2017 | }; |
| 2018 | |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 2019 | static struct branch_clk sata_a_clk = { |
| 2020 | .b = { |
| 2021 | .ctl_reg = SATA_ACLK_CTL_REG, |
| 2022 | .en_mask = BIT(4), |
| 2023 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG, |
| 2024 | .halt_bit = 12, |
| 2025 | }, |
| 2026 | .c = { |
| 2027 | .dbg_name = "sata_a_clk", |
| 2028 | .ops = &clk_ops_branch, |
| 2029 | CLK_INIT(sata_a_clk.c), |
| 2030 | }, |
| 2031 | }; |
| 2032 | |
| 2033 | static struct branch_clk sata_p_clk = { |
| 2034 | .b = { |
| 2035 | .ctl_reg = SATA_HCLK_CTL_REG, |
| 2036 | .en_mask = BIT(4), |
| 2037 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2038 | .halt_bit = 27, |
| 2039 | }, |
| 2040 | .c = { |
| 2041 | .dbg_name = "sata_p_clk", |
| 2042 | .ops = &clk_ops_branch, |
| 2043 | CLK_INIT(sata_p_clk.c), |
| 2044 | }, |
| 2045 | }; |
| 2046 | |
| 2047 | static struct branch_clk sfab_sata_s_p_clk = { |
| 2048 | .b = { |
| 2049 | .ctl_reg = SFAB_SATA_S_HCLK_CTL_REG, |
| 2050 | .en_mask = BIT(4), |
| 2051 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG, |
| 2052 | .halt_bit = 14, |
| 2053 | }, |
| 2054 | .c = { |
| 2055 | .dbg_name = "sfab_sata_s_p_clk", |
| 2056 | .ops = &clk_ops_branch, |
| 2057 | CLK_INIT(sfab_sata_s_p_clk.c), |
| 2058 | }, |
| 2059 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2060 | static struct branch_clk pcie_p_clk = { |
| 2061 | .b = { |
| 2062 | .ctl_reg = PCIE_HCLK_CTL_REG, |
| 2063 | .en_mask = BIT(4), |
| 2064 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2065 | .halt_bit = 8, |
| 2066 | }, |
| 2067 | .c = { |
| 2068 | .dbg_name = "pcie_p_clk", |
| 2069 | .ops = &clk_ops_branch, |
| 2070 | CLK_INIT(pcie_p_clk.c), |
| 2071 | }, |
| 2072 | }; |
| 2073 | |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 2074 | static struct branch_clk pcie_phy_ref_clk = { |
| 2075 | .b = { |
| 2076 | .ctl_reg = PCIE_PCLK_CTL_REG, |
| 2077 | .en_mask = BIT(4), |
| 2078 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2079 | .halt_bit = 29, |
| 2080 | }, |
| 2081 | .c = { |
| 2082 | .dbg_name = "pcie_phy_ref_clk", |
| 2083 | .ops = &clk_ops_branch, |
| 2084 | CLK_INIT(pcie_phy_ref_clk.c), |
| 2085 | }, |
| 2086 | }; |
| 2087 | |
| 2088 | static struct branch_clk pcie_a_clk = { |
| 2089 | .b = { |
| 2090 | .ctl_reg = PCIE_ACLK_CTL_REG, |
| 2091 | .en_mask = BIT(4), |
| 2092 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG, |
| 2093 | .halt_bit = 13, |
| 2094 | }, |
| 2095 | .c = { |
| 2096 | .dbg_name = "pcie_a_clk", |
| 2097 | .ops = &clk_ops_branch, |
| 2098 | CLK_INIT(pcie_a_clk.c), |
| 2099 | }, |
| 2100 | }; |
| 2101 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2102 | static struct branch_clk dma_bam_p_clk = { |
| 2103 | .b = { |
| 2104 | .ctl_reg = DMA_BAM_HCLK_CTL, |
| 2105 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2106 | .hwcg_reg = DMA_BAM_HCLK_CTL, |
| 2107 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2108 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2109 | .halt_bit = 12, |
| 2110 | }, |
| 2111 | .c = { |
| 2112 | .dbg_name = "dma_bam_p_clk", |
| 2113 | .ops = &clk_ops_branch, |
| 2114 | CLK_INIT(dma_bam_p_clk.c), |
| 2115 | }, |
| 2116 | }; |
| 2117 | |
| 2118 | static struct branch_clk gsbi1_p_clk = { |
| 2119 | .b = { |
| 2120 | .ctl_reg = GSBIn_HCLK_CTL_REG(1), |
| 2121 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2122 | .hwcg_reg = GSBIn_HCLK_CTL_REG(1), |
| 2123 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2124 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2125 | .halt_bit = 11, |
| 2126 | }, |
| 2127 | .c = { |
| 2128 | .dbg_name = "gsbi1_p_clk", |
| 2129 | .ops = &clk_ops_branch, |
| 2130 | CLK_INIT(gsbi1_p_clk.c), |
| 2131 | }, |
| 2132 | }; |
| 2133 | |
| 2134 | static struct branch_clk gsbi2_p_clk = { |
| 2135 | .b = { |
| 2136 | .ctl_reg = GSBIn_HCLK_CTL_REG(2), |
| 2137 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2138 | .hwcg_reg = GSBIn_HCLK_CTL_REG(2), |
| 2139 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2140 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2141 | .halt_bit = 7, |
| 2142 | }, |
| 2143 | .c = { |
| 2144 | .dbg_name = "gsbi2_p_clk", |
| 2145 | .ops = &clk_ops_branch, |
| 2146 | CLK_INIT(gsbi2_p_clk.c), |
| 2147 | }, |
| 2148 | }; |
| 2149 | |
| 2150 | static struct branch_clk gsbi3_p_clk = { |
| 2151 | .b = { |
| 2152 | .ctl_reg = GSBIn_HCLK_CTL_REG(3), |
| 2153 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2154 | .hwcg_reg = GSBIn_HCLK_CTL_REG(3), |
| 2155 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2156 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2157 | .halt_bit = 3, |
| 2158 | }, |
| 2159 | .c = { |
| 2160 | .dbg_name = "gsbi3_p_clk", |
| 2161 | .ops = &clk_ops_branch, |
| 2162 | CLK_INIT(gsbi3_p_clk.c), |
| 2163 | }, |
| 2164 | }; |
| 2165 | |
| 2166 | static struct branch_clk gsbi4_p_clk = { |
| 2167 | .b = { |
| 2168 | .ctl_reg = GSBIn_HCLK_CTL_REG(4), |
| 2169 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2170 | .hwcg_reg = GSBIn_HCLK_CTL_REG(4), |
| 2171 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2172 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2173 | .halt_bit = 27, |
| 2174 | }, |
| 2175 | .c = { |
| 2176 | .dbg_name = "gsbi4_p_clk", |
| 2177 | .ops = &clk_ops_branch, |
| 2178 | CLK_INIT(gsbi4_p_clk.c), |
| 2179 | }, |
| 2180 | }; |
| 2181 | |
| 2182 | static struct branch_clk gsbi5_p_clk = { |
| 2183 | .b = { |
| 2184 | .ctl_reg = GSBIn_HCLK_CTL_REG(5), |
| 2185 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2186 | .hwcg_reg = GSBIn_HCLK_CTL_REG(5), |
| 2187 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2188 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2189 | .halt_bit = 23, |
| 2190 | }, |
| 2191 | .c = { |
| 2192 | .dbg_name = "gsbi5_p_clk", |
| 2193 | .ops = &clk_ops_branch, |
| 2194 | CLK_INIT(gsbi5_p_clk.c), |
| 2195 | }, |
| 2196 | }; |
| 2197 | |
| 2198 | static struct branch_clk gsbi6_p_clk = { |
| 2199 | .b = { |
| 2200 | .ctl_reg = GSBIn_HCLK_CTL_REG(6), |
| 2201 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2202 | .hwcg_reg = GSBIn_HCLK_CTL_REG(6), |
| 2203 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2204 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2205 | .halt_bit = 19, |
| 2206 | }, |
| 2207 | .c = { |
| 2208 | .dbg_name = "gsbi6_p_clk", |
| 2209 | .ops = &clk_ops_branch, |
| 2210 | CLK_INIT(gsbi6_p_clk.c), |
| 2211 | }, |
| 2212 | }; |
| 2213 | |
| 2214 | static struct branch_clk gsbi7_p_clk = { |
| 2215 | .b = { |
| 2216 | .ctl_reg = GSBIn_HCLK_CTL_REG(7), |
| 2217 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2218 | .hwcg_reg = GSBIn_HCLK_CTL_REG(7), |
| 2219 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2220 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2221 | .halt_bit = 15, |
| 2222 | }, |
| 2223 | .c = { |
| 2224 | .dbg_name = "gsbi7_p_clk", |
| 2225 | .ops = &clk_ops_branch, |
| 2226 | CLK_INIT(gsbi7_p_clk.c), |
| 2227 | }, |
| 2228 | }; |
| 2229 | |
| 2230 | static struct branch_clk gsbi8_p_clk = { |
| 2231 | .b = { |
| 2232 | .ctl_reg = GSBIn_HCLK_CTL_REG(8), |
| 2233 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2234 | .hwcg_reg = GSBIn_HCLK_CTL_REG(8), |
| 2235 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2236 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2237 | .halt_bit = 11, |
| 2238 | }, |
| 2239 | .c = { |
| 2240 | .dbg_name = "gsbi8_p_clk", |
| 2241 | .ops = &clk_ops_branch, |
| 2242 | CLK_INIT(gsbi8_p_clk.c), |
| 2243 | }, |
| 2244 | }; |
| 2245 | |
| 2246 | static struct branch_clk gsbi9_p_clk = { |
| 2247 | .b = { |
| 2248 | .ctl_reg = GSBIn_HCLK_CTL_REG(9), |
| 2249 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2250 | .hwcg_reg = GSBIn_HCLK_CTL_REG(9), |
| 2251 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2252 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2253 | .halt_bit = 7, |
| 2254 | }, |
| 2255 | .c = { |
| 2256 | .dbg_name = "gsbi9_p_clk", |
| 2257 | .ops = &clk_ops_branch, |
| 2258 | CLK_INIT(gsbi9_p_clk.c), |
| 2259 | }, |
| 2260 | }; |
| 2261 | |
| 2262 | static struct branch_clk gsbi10_p_clk = { |
| 2263 | .b = { |
| 2264 | .ctl_reg = GSBIn_HCLK_CTL_REG(10), |
| 2265 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2266 | .hwcg_reg = GSBIn_HCLK_CTL_REG(10), |
| 2267 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2268 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2269 | .halt_bit = 3, |
| 2270 | }, |
| 2271 | .c = { |
| 2272 | .dbg_name = "gsbi10_p_clk", |
| 2273 | .ops = &clk_ops_branch, |
| 2274 | CLK_INIT(gsbi10_p_clk.c), |
| 2275 | }, |
| 2276 | }; |
| 2277 | |
| 2278 | static struct branch_clk gsbi11_p_clk = { |
| 2279 | .b = { |
| 2280 | .ctl_reg = GSBIn_HCLK_CTL_REG(11), |
| 2281 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2282 | .hwcg_reg = GSBIn_HCLK_CTL_REG(11), |
| 2283 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2284 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2285 | .halt_bit = 18, |
| 2286 | }, |
| 2287 | .c = { |
| 2288 | .dbg_name = "gsbi11_p_clk", |
| 2289 | .ops = &clk_ops_branch, |
| 2290 | CLK_INIT(gsbi11_p_clk.c), |
| 2291 | }, |
| 2292 | }; |
| 2293 | |
| 2294 | static struct branch_clk gsbi12_p_clk = { |
| 2295 | .b = { |
| 2296 | .ctl_reg = GSBIn_HCLK_CTL_REG(12), |
| 2297 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2298 | .hwcg_reg = GSBIn_HCLK_CTL_REG(12), |
| 2299 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2300 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2301 | .halt_bit = 14, |
| 2302 | }, |
| 2303 | .c = { |
| 2304 | .dbg_name = "gsbi12_p_clk", |
| 2305 | .ops = &clk_ops_branch, |
| 2306 | CLK_INIT(gsbi12_p_clk.c), |
| 2307 | }, |
| 2308 | }; |
| 2309 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2310 | static struct branch_clk sata_phy_cfg_clk = { |
| 2311 | .b = { |
| 2312 | .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG, |
| 2313 | .en_mask = BIT(4), |
| 2314 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2315 | .halt_bit = 12, |
| 2316 | }, |
| 2317 | .c = { |
| 2318 | .dbg_name = "sata_phy_cfg_clk", |
| 2319 | .ops = &clk_ops_branch, |
| 2320 | CLK_INIT(sata_phy_cfg_clk.c), |
Stephen Boyd | 973e4ba | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2321 | }, |
| 2322 | }; |
| 2323 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2324 | static struct branch_clk tsif_p_clk = { |
| 2325 | .b = { |
| 2326 | .ctl_reg = TSIF_HCLK_CTL_REG, |
| 2327 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2328 | .hwcg_reg = TSIF_HCLK_CTL_REG, |
| 2329 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2330 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2331 | .halt_bit = 7, |
| 2332 | }, |
| 2333 | .c = { |
| 2334 | .dbg_name = "tsif_p_clk", |
| 2335 | .ops = &clk_ops_branch, |
| 2336 | CLK_INIT(tsif_p_clk.c), |
| 2337 | }, |
| 2338 | }; |
| 2339 | |
| 2340 | static struct branch_clk usb_fs1_p_clk = { |
| 2341 | .b = { |
| 2342 | .ctl_reg = USB_FSn_HCLK_CTL_REG(1), |
| 2343 | .en_mask = BIT(4), |
| 2344 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2345 | .halt_bit = 17, |
| 2346 | }, |
| 2347 | .c = { |
| 2348 | .dbg_name = "usb_fs1_p_clk", |
| 2349 | .ops = &clk_ops_branch, |
| 2350 | CLK_INIT(usb_fs1_p_clk.c), |
| 2351 | }, |
| 2352 | }; |
| 2353 | |
| 2354 | static struct branch_clk usb_fs2_p_clk = { |
| 2355 | .b = { |
| 2356 | .ctl_reg = USB_FSn_HCLK_CTL_REG(2), |
| 2357 | .en_mask = BIT(4), |
| 2358 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2359 | .halt_bit = 14, |
| 2360 | }, |
| 2361 | .c = { |
| 2362 | .dbg_name = "usb_fs2_p_clk", |
| 2363 | .ops = &clk_ops_branch, |
| 2364 | CLK_INIT(usb_fs2_p_clk.c), |
| 2365 | }, |
| 2366 | }; |
| 2367 | |
| 2368 | static struct branch_clk usb_hs1_p_clk = { |
| 2369 | .b = { |
| 2370 | .ctl_reg = USB_HS1_HCLK_CTL_REG, |
| 2371 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2372 | .hwcg_reg = USB_HS1_HCLK_CTL_REG, |
| 2373 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2374 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2375 | .halt_bit = 1, |
| 2376 | }, |
| 2377 | .c = { |
| 2378 | .dbg_name = "usb_hs1_p_clk", |
| 2379 | .ops = &clk_ops_branch, |
| 2380 | CLK_INIT(usb_hs1_p_clk.c), |
| 2381 | }, |
| 2382 | }; |
| 2383 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2384 | static struct branch_clk usb_hs3_p_clk = { |
| 2385 | .b = { |
| 2386 | .ctl_reg = USB_HS3_HCLK_CTL_REG, |
| 2387 | .en_mask = BIT(4), |
| 2388 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2389 | .halt_bit = 31, |
| 2390 | }, |
| 2391 | .c = { |
| 2392 | .dbg_name = "usb_hs3_p_clk", |
| 2393 | .ops = &clk_ops_branch, |
| 2394 | CLK_INIT(usb_hs3_p_clk.c), |
| 2395 | }, |
| 2396 | }; |
| 2397 | |
| 2398 | static struct branch_clk usb_hs4_p_clk = { |
| 2399 | .b = { |
| 2400 | .ctl_reg = USB_HS4_HCLK_CTL_REG, |
| 2401 | .en_mask = BIT(4), |
| 2402 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2403 | .halt_bit = 7, |
| 2404 | }, |
| 2405 | .c = { |
| 2406 | .dbg_name = "usb_hs4_p_clk", |
| 2407 | .ops = &clk_ops_branch, |
| 2408 | CLK_INIT(usb_hs4_p_clk.c), |
| 2409 | }, |
| 2410 | }; |
| 2411 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2412 | static struct branch_clk usb_hsic_p_clk = { |
| 2413 | .b = { |
| 2414 | .ctl_reg = USB_HSIC_HCLK_CTL_REG, |
| 2415 | .en_mask = BIT(4), |
| 2416 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2417 | .halt_bit = 28, |
| 2418 | }, |
| 2419 | .c = { |
| 2420 | .dbg_name = "usb_hsic_p_clk", |
| 2421 | .ops = &clk_ops_branch, |
| 2422 | CLK_INIT(usb_hsic_p_clk.c), |
| 2423 | }, |
| 2424 | }; |
| 2425 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2426 | static struct branch_clk sdc1_p_clk = { |
| 2427 | .b = { |
| 2428 | .ctl_reg = SDCn_HCLK_CTL_REG(1), |
| 2429 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2430 | .hwcg_reg = SDCn_HCLK_CTL_REG(1), |
| 2431 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2432 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2433 | .halt_bit = 11, |
| 2434 | }, |
| 2435 | .c = { |
| 2436 | .dbg_name = "sdc1_p_clk", |
| 2437 | .ops = &clk_ops_branch, |
| 2438 | CLK_INIT(sdc1_p_clk.c), |
| 2439 | }, |
| 2440 | }; |
| 2441 | |
| 2442 | static struct branch_clk sdc2_p_clk = { |
| 2443 | .b = { |
| 2444 | .ctl_reg = SDCn_HCLK_CTL_REG(2), |
| 2445 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2446 | .hwcg_reg = SDCn_HCLK_CTL_REG(2), |
| 2447 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2448 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2449 | .halt_bit = 10, |
| 2450 | }, |
| 2451 | .c = { |
| 2452 | .dbg_name = "sdc2_p_clk", |
| 2453 | .ops = &clk_ops_branch, |
| 2454 | CLK_INIT(sdc2_p_clk.c), |
| 2455 | }, |
| 2456 | }; |
| 2457 | |
| 2458 | static struct branch_clk sdc3_p_clk = { |
| 2459 | .b = { |
| 2460 | .ctl_reg = SDCn_HCLK_CTL_REG(3), |
| 2461 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2462 | .hwcg_reg = SDCn_HCLK_CTL_REG(3), |
| 2463 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2464 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2465 | .halt_bit = 9, |
| 2466 | }, |
| 2467 | .c = { |
| 2468 | .dbg_name = "sdc3_p_clk", |
| 2469 | .ops = &clk_ops_branch, |
| 2470 | CLK_INIT(sdc3_p_clk.c), |
| 2471 | }, |
| 2472 | }; |
| 2473 | |
| 2474 | static struct branch_clk sdc4_p_clk = { |
| 2475 | .b = { |
| 2476 | .ctl_reg = SDCn_HCLK_CTL_REG(4), |
| 2477 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2478 | .hwcg_reg = SDCn_HCLK_CTL_REG(4), |
| 2479 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2480 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2481 | .halt_bit = 8, |
| 2482 | }, |
| 2483 | .c = { |
| 2484 | .dbg_name = "sdc4_p_clk", |
| 2485 | .ops = &clk_ops_branch, |
| 2486 | CLK_INIT(sdc4_p_clk.c), |
| 2487 | }, |
| 2488 | }; |
| 2489 | |
| 2490 | static struct branch_clk sdc5_p_clk = { |
| 2491 | .b = { |
| 2492 | .ctl_reg = SDCn_HCLK_CTL_REG(5), |
| 2493 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2494 | .hwcg_reg = SDCn_HCLK_CTL_REG(5), |
| 2495 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2496 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2497 | .halt_bit = 7, |
| 2498 | }, |
| 2499 | .c = { |
| 2500 | .dbg_name = "sdc5_p_clk", |
| 2501 | .ops = &clk_ops_branch, |
| 2502 | CLK_INIT(sdc5_p_clk.c), |
| 2503 | }, |
| 2504 | }; |
| 2505 | |
| 2506 | /* HW-Voteable Clocks */ |
| 2507 | static struct branch_clk adm0_clk = { |
| 2508 | .b = { |
| 2509 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2510 | .en_mask = BIT(2), |
| 2511 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2512 | .halt_check = HALT_VOTED, |
| 2513 | .halt_bit = 14, |
| 2514 | }, |
| 2515 | .c = { |
| 2516 | .dbg_name = "adm0_clk", |
| 2517 | .ops = &clk_ops_branch, |
| 2518 | CLK_INIT(adm0_clk.c), |
| 2519 | }, |
| 2520 | }; |
| 2521 | |
| 2522 | static struct branch_clk adm0_p_clk = { |
| 2523 | .b = { |
| 2524 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2525 | .en_mask = BIT(3), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2526 | .hwcg_reg = ADM0_PBUS_CLK_CTL_REG, |
| 2527 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2528 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2529 | .halt_check = HALT_VOTED, |
| 2530 | .halt_bit = 13, |
| 2531 | }, |
| 2532 | .c = { |
| 2533 | .dbg_name = "adm0_p_clk", |
| 2534 | .ops = &clk_ops_branch, |
| 2535 | CLK_INIT(adm0_p_clk.c), |
| 2536 | }, |
| 2537 | }; |
| 2538 | |
| 2539 | static struct branch_clk pmic_arb0_p_clk = { |
| 2540 | .b = { |
| 2541 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2542 | .en_mask = BIT(8), |
| 2543 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2544 | .halt_check = HALT_VOTED, |
| 2545 | .halt_bit = 22, |
| 2546 | }, |
| 2547 | .c = { |
| 2548 | .dbg_name = "pmic_arb0_p_clk", |
| 2549 | .ops = &clk_ops_branch, |
| 2550 | CLK_INIT(pmic_arb0_p_clk.c), |
| 2551 | }, |
| 2552 | }; |
| 2553 | |
| 2554 | static struct branch_clk pmic_arb1_p_clk = { |
| 2555 | .b = { |
| 2556 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2557 | .en_mask = BIT(9), |
| 2558 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2559 | .halt_check = HALT_VOTED, |
| 2560 | .halt_bit = 21, |
| 2561 | }, |
| 2562 | .c = { |
| 2563 | .dbg_name = "pmic_arb1_p_clk", |
| 2564 | .ops = &clk_ops_branch, |
| 2565 | CLK_INIT(pmic_arb1_p_clk.c), |
| 2566 | }, |
| 2567 | }; |
| 2568 | |
| 2569 | static struct branch_clk pmic_ssbi2_clk = { |
| 2570 | .b = { |
| 2571 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2572 | .en_mask = BIT(7), |
| 2573 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2574 | .halt_check = HALT_VOTED, |
| 2575 | .halt_bit = 23, |
| 2576 | }, |
| 2577 | .c = { |
| 2578 | .dbg_name = "pmic_ssbi2_clk", |
| 2579 | .ops = &clk_ops_branch, |
| 2580 | CLK_INIT(pmic_ssbi2_clk.c), |
| 2581 | }, |
| 2582 | }; |
| 2583 | |
| 2584 | static struct branch_clk rpm_msg_ram_p_clk = { |
| 2585 | .b = { |
| 2586 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2587 | .en_mask = BIT(6), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2588 | .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG, |
| 2589 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2590 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2591 | .halt_check = HALT_VOTED, |
| 2592 | .halt_bit = 12, |
| 2593 | }, |
| 2594 | .c = { |
| 2595 | .dbg_name = "rpm_msg_ram_p_clk", |
| 2596 | .ops = &clk_ops_branch, |
| 2597 | CLK_INIT(rpm_msg_ram_p_clk.c), |
| 2598 | }, |
| 2599 | }; |
| 2600 | |
| 2601 | /* |
| 2602 | * Multimedia Clocks |
| 2603 | */ |
| 2604 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2605 | #define CLK_CAM(name, n, hb) \ |
| 2606 | struct rcg_clk name = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2607 | .b = { \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2608 | .ctl_reg = CAMCLK##n##_CC_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2609 | .en_mask = BIT(0), \ |
| 2610 | .halt_reg = DBG_BUS_VEC_I_REG, \ |
| 2611 | .halt_bit = hb, \ |
| 2612 | }, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2613 | .ns_reg = CAMCLK##n##_NS_REG, \ |
| 2614 | .md_reg = CAMCLK##n##_MD_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2615 | .root_en_mask = BIT(2), \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2616 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2617 | .mnd_en_mask = BIT(5), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2618 | .ctl_mask = BM(7, 6), \ |
| 2619 | .set_rate = set_rate_mnd_8, \ |
| 2620 | .freq_tbl = clk_tbl_cam, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2621 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2622 | .c = { \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2623 | .dbg_name = #name, \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2624 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2625 | VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2626 | CLK_INIT(name.c), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2627 | }, \ |
| 2628 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2629 | #define F_CAM(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2630 | { \ |
| 2631 | .freq_hz = f, \ |
| 2632 | .src_clk = &s##_clk.c, \ |
| 2633 | .md_val = MD8(8, m, 0, n), \ |
| 2634 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 2635 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2636 | } |
| 2637 | static struct clk_freq_tbl clk_tbl_cam[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2638 | F_CAM( 0, gnd, 1, 0, 0), |
| 2639 | F_CAM( 6000000, pll8, 4, 1, 16), |
| 2640 | F_CAM( 8000000, pll8, 4, 1, 12), |
| 2641 | F_CAM( 12000000, pll8, 4, 1, 8), |
| 2642 | F_CAM( 16000000, pll8, 4, 1, 6), |
| 2643 | F_CAM( 19200000, pll8, 4, 1, 5), |
| 2644 | F_CAM( 24000000, pll8, 4, 1, 4), |
| 2645 | F_CAM( 32000000, pll8, 4, 1, 3), |
| 2646 | F_CAM( 48000000, pll8, 4, 1, 2), |
| 2647 | F_CAM( 64000000, pll8, 3, 1, 2), |
| 2648 | F_CAM( 96000000, pll8, 4, 0, 0), |
| 2649 | F_CAM(128000000, pll8, 3, 0, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2650 | F_END |
| 2651 | }; |
| 2652 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2653 | static CLK_CAM(cam0_clk, 0, 15); |
| 2654 | static CLK_CAM(cam1_clk, 1, 16); |
| 2655 | static CLK_CAM(cam2_clk, 2, 31); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2656 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2657 | #define F_CSI(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2658 | { \ |
| 2659 | .freq_hz = f, \ |
| 2660 | .src_clk = &s##_clk.c, \ |
| 2661 | .md_val = MD8(8, m, 0, n), \ |
| 2662 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 2663 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2664 | } |
| 2665 | static struct clk_freq_tbl clk_tbl_csi[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2666 | F_CSI( 0, gnd, 1, 0, 0), |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2667 | F_CSI( 27000000, pxo, 1, 0, 0), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2668 | F_CSI( 85330000, pll8, 1, 2, 9), |
| 2669 | F_CSI(177780000, pll2, 1, 2, 9), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2670 | F_END |
| 2671 | }; |
| 2672 | |
| 2673 | static struct rcg_clk csi0_src_clk = { |
| 2674 | .ns_reg = CSI0_NS_REG, |
| 2675 | .b = { |
| 2676 | .ctl_reg = CSI0_CC_REG, |
| 2677 | .halt_check = NOCHECK, |
| 2678 | }, |
| 2679 | .md_reg = CSI0_MD_REG, |
| 2680 | .root_en_mask = BIT(2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2681 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2682 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2683 | .ctl_mask = BM(7, 6), |
| 2684 | .set_rate = set_rate_mnd, |
| 2685 | .freq_tbl = clk_tbl_csi, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2686 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2687 | .c = { |
| 2688 | .dbg_name = "csi0_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2689 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2690 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2691 | CLK_INIT(csi0_src_clk.c), |
Matt Wagantall | 67b8a923 | 2012-07-20 17:16:03 -0700 | [diff] [blame] | 2692 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2693 | }, |
| 2694 | }; |
| 2695 | |
| 2696 | static struct branch_clk csi0_clk = { |
| 2697 | .b = { |
| 2698 | .ctl_reg = CSI0_CC_REG, |
| 2699 | .en_mask = BIT(0), |
| 2700 | .reset_reg = SW_RESET_CORE_REG, |
| 2701 | .reset_mask = BIT(8), |
| 2702 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2703 | .halt_bit = 13, |
| 2704 | }, |
| 2705 | .parent = &csi0_src_clk.c, |
| 2706 | .c = { |
| 2707 | .dbg_name = "csi0_clk", |
| 2708 | .ops = &clk_ops_branch, |
| 2709 | CLK_INIT(csi0_clk.c), |
Matt Wagantall | 67b8a923 | 2012-07-20 17:16:03 -0700 | [diff] [blame] | 2710 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2711 | }, |
| 2712 | }; |
| 2713 | |
| 2714 | static struct branch_clk csi0_phy_clk = { |
| 2715 | .b = { |
| 2716 | .ctl_reg = CSI0_CC_REG, |
| 2717 | .en_mask = BIT(8), |
| 2718 | .reset_reg = SW_RESET_CORE_REG, |
| 2719 | .reset_mask = BIT(29), |
| 2720 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2721 | .halt_bit = 9, |
| 2722 | }, |
| 2723 | .parent = &csi0_src_clk.c, |
| 2724 | .c = { |
| 2725 | .dbg_name = "csi0_phy_clk", |
| 2726 | .ops = &clk_ops_branch, |
| 2727 | CLK_INIT(csi0_phy_clk.c), |
| 2728 | }, |
| 2729 | }; |
| 2730 | |
| 2731 | static struct rcg_clk csi1_src_clk = { |
| 2732 | .ns_reg = CSI1_NS_REG, |
| 2733 | .b = { |
| 2734 | .ctl_reg = CSI1_CC_REG, |
| 2735 | .halt_check = NOCHECK, |
| 2736 | }, |
| 2737 | .md_reg = CSI1_MD_REG, |
| 2738 | .root_en_mask = BIT(2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2739 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2740 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2741 | .ctl_mask = BM(7, 6), |
| 2742 | .set_rate = set_rate_mnd, |
| 2743 | .freq_tbl = clk_tbl_csi, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2744 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2745 | .c = { |
| 2746 | .dbg_name = "csi1_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2747 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2748 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2749 | CLK_INIT(csi1_src_clk.c), |
Matt Wagantall | 67b8a923 | 2012-07-20 17:16:03 -0700 | [diff] [blame] | 2750 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2751 | }, |
| 2752 | }; |
| 2753 | |
| 2754 | static struct branch_clk csi1_clk = { |
| 2755 | .b = { |
| 2756 | .ctl_reg = CSI1_CC_REG, |
| 2757 | .en_mask = BIT(0), |
| 2758 | .reset_reg = SW_RESET_CORE_REG, |
| 2759 | .reset_mask = BIT(18), |
| 2760 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2761 | .halt_bit = 14, |
| 2762 | }, |
| 2763 | .parent = &csi1_src_clk.c, |
| 2764 | .c = { |
| 2765 | .dbg_name = "csi1_clk", |
| 2766 | .ops = &clk_ops_branch, |
| 2767 | CLK_INIT(csi1_clk.c), |
Matt Wagantall | 67b8a923 | 2012-07-20 17:16:03 -0700 | [diff] [blame] | 2768 | .warned = true, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2769 | }, |
| 2770 | }; |
| 2771 | |
| 2772 | static struct branch_clk csi1_phy_clk = { |
| 2773 | .b = { |
| 2774 | .ctl_reg = CSI1_CC_REG, |
| 2775 | .en_mask = BIT(8), |
| 2776 | .reset_reg = SW_RESET_CORE_REG, |
| 2777 | .reset_mask = BIT(28), |
| 2778 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2779 | .halt_bit = 10, |
| 2780 | }, |
| 2781 | .parent = &csi1_src_clk.c, |
| 2782 | .c = { |
| 2783 | .dbg_name = "csi1_phy_clk", |
| 2784 | .ops = &clk_ops_branch, |
| 2785 | CLK_INIT(csi1_phy_clk.c), |
| 2786 | }, |
| 2787 | }; |
| 2788 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2789 | static struct rcg_clk csi2_src_clk = { |
| 2790 | .ns_reg = CSI2_NS_REG, |
| 2791 | .b = { |
| 2792 | .ctl_reg = CSI2_CC_REG, |
| 2793 | .halt_check = NOCHECK, |
| 2794 | }, |
| 2795 | .md_reg = CSI2_MD_REG, |
| 2796 | .root_en_mask = BIT(2), |
| 2797 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 2798 | .mnd_en_mask = BIT(5), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2799 | .ctl_mask = BM(7, 6), |
| 2800 | .set_rate = set_rate_mnd, |
| 2801 | .freq_tbl = clk_tbl_csi, |
| 2802 | .current_freq = &rcg_dummy_freq, |
| 2803 | .c = { |
| 2804 | .dbg_name = "csi2_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 2805 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2806 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2807 | CLK_INIT(csi2_src_clk.c), |
Matt Wagantall | 67b8a923 | 2012-07-20 17:16:03 -0700 | [diff] [blame] | 2808 | .warned = true, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2809 | }, |
| 2810 | }; |
| 2811 | |
| 2812 | static struct branch_clk csi2_clk = { |
| 2813 | .b = { |
| 2814 | .ctl_reg = CSI2_CC_REG, |
| 2815 | .en_mask = BIT(0), |
| 2816 | .reset_reg = SW_RESET_CORE2_REG, |
| 2817 | .reset_mask = BIT(2), |
| 2818 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2819 | .halt_bit = 29, |
| 2820 | }, |
| 2821 | .parent = &csi2_src_clk.c, |
| 2822 | .c = { |
| 2823 | .dbg_name = "csi2_clk", |
| 2824 | .ops = &clk_ops_branch, |
| 2825 | CLK_INIT(csi2_clk.c), |
Matt Wagantall | 67b8a923 | 2012-07-20 17:16:03 -0700 | [diff] [blame] | 2826 | .warned = true, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2827 | }, |
| 2828 | }; |
| 2829 | |
| 2830 | static struct branch_clk csi2_phy_clk = { |
| 2831 | .b = { |
| 2832 | .ctl_reg = CSI2_CC_REG, |
| 2833 | .en_mask = BIT(8), |
| 2834 | .reset_reg = SW_RESET_CORE_REG, |
| 2835 | .reset_mask = BIT(31), |
| 2836 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2837 | .halt_bit = 29, |
| 2838 | }, |
| 2839 | .parent = &csi2_src_clk.c, |
| 2840 | .c = { |
| 2841 | .dbg_name = "csi2_phy_clk", |
| 2842 | .ops = &clk_ops_branch, |
| 2843 | CLK_INIT(csi2_phy_clk.c), |
| 2844 | }, |
| 2845 | }; |
| 2846 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2847 | static struct clk *pix_rdi_mux_map[] = { |
| 2848 | [0] = &csi0_clk.c, |
| 2849 | [1] = &csi1_clk.c, |
| 2850 | [2] = &csi2_clk.c, |
| 2851 | NULL, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2852 | }; |
| 2853 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2854 | struct pix_rdi_clk { |
| 2855 | bool enabled; |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2856 | unsigned long cur_rate; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2857 | |
| 2858 | void __iomem *const s_reg; |
| 2859 | u32 s_mask; |
| 2860 | |
| 2861 | void __iomem *const s2_reg; |
| 2862 | u32 s2_mask; |
| 2863 | |
| 2864 | struct branch b; |
| 2865 | struct clk c; |
| 2866 | }; |
| 2867 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2868 | static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2869 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2870 | return container_of(c, struct pix_rdi_clk, c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2871 | } |
| 2872 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2873 | static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2874 | { |
| 2875 | int ret, i; |
| 2876 | u32 reg; |
| 2877 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2878 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2879 | struct clk **mux_map = pix_rdi_mux_map; |
| 2880 | |
| 2881 | /* |
| 2882 | * These clocks select three inputs via two muxes. One mux selects |
| 2883 | * between csi0 and csi1 and the second mux selects between that mux's |
| 2884 | * output and csi2. The source and destination selections for each |
| 2885 | * mux must be clocking for the switch to succeed so just turn on |
| 2886 | * all three sources because it's easier than figuring out what source |
| 2887 | * needs to be on at what time. |
| 2888 | */ |
| 2889 | for (i = 0; mux_map[i]; i++) { |
| 2890 | ret = clk_enable(mux_map[i]); |
| 2891 | if (ret) |
| 2892 | goto err; |
| 2893 | } |
| 2894 | if (rate >= i) { |
| 2895 | ret = -EINVAL; |
| 2896 | goto err; |
| 2897 | } |
| 2898 | /* Keep the new source on when switching inputs of an enabled clock */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2899 | if (rdi->enabled) { |
| 2900 | clk_disable(mux_map[rdi->cur_rate]); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2901 | clk_enable(mux_map[rate]); |
| 2902 | } |
| 2903 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2904 | reg = readl_relaxed(rdi->s2_reg); |
| 2905 | reg &= ~rdi->s2_mask; |
| 2906 | reg |= rate == 2 ? rdi->s2_mask : 0; |
| 2907 | writel_relaxed(reg, rdi->s2_reg); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2908 | /* |
| 2909 | * Wait at least 6 cycles of slowest clock |
| 2910 | * for the glitch-free MUX to fully switch sources. |
| 2911 | */ |
| 2912 | mb(); |
| 2913 | udelay(1); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2914 | reg = readl_relaxed(rdi->s_reg); |
| 2915 | reg &= ~rdi->s_mask; |
| 2916 | reg |= rate == 1 ? rdi->s_mask : 0; |
| 2917 | writel_relaxed(reg, rdi->s_reg); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2918 | /* |
| 2919 | * Wait at least 6 cycles of slowest clock |
| 2920 | * for the glitch-free MUX to fully switch sources. |
| 2921 | */ |
| 2922 | mb(); |
| 2923 | udelay(1); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2924 | rdi->cur_rate = rate; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2925 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2926 | err: |
| 2927 | for (i--; i >= 0; i--) |
| 2928 | clk_disable(mux_map[i]); |
| 2929 | |
| 2930 | return 0; |
| 2931 | } |
| 2932 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2933 | static unsigned long pix_rdi_clk_get_rate(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2934 | { |
| 2935 | return to_pix_rdi_clk(c)->cur_rate; |
| 2936 | } |
| 2937 | |
| 2938 | static int pix_rdi_clk_enable(struct clk *c) |
| 2939 | { |
| 2940 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2941 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2942 | |
| 2943 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
Matt Wagantall | 0de1b3f | 2012-06-05 19:52:43 -0700 | [diff] [blame] | 2944 | __branch_enable_reg(&rdi->b, rdi->c.dbg_name); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2945 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2946 | rdi->enabled = true; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2947 | |
| 2948 | return 0; |
| 2949 | } |
| 2950 | |
| 2951 | static void pix_rdi_clk_disable(struct clk *c) |
| 2952 | { |
| 2953 | unsigned long flags; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2954 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2955 | |
| 2956 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
Matt Wagantall | 0de1b3f | 2012-06-05 19:52:43 -0700 | [diff] [blame] | 2957 | __branch_disable_reg(&rdi->b, rdi->c.dbg_name); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2958 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2959 | rdi->enabled = false; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2960 | } |
| 2961 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2962 | static int pix_rdi_clk_reset(struct clk *c, enum clk_reset_action action) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2963 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2964 | return branch_reset(&to_pix_rdi_clk(c)->b, action); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2965 | } |
| 2966 | |
| 2967 | static struct clk *pix_rdi_clk_get_parent(struct clk *c) |
| 2968 | { |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2969 | return pix_rdi_mux_map[to_pix_rdi_clk(c)->cur_rate]; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2970 | } |
| 2971 | |
| 2972 | static int pix_rdi_clk_list_rate(struct clk *c, unsigned n) |
| 2973 | { |
| 2974 | if (pix_rdi_mux_map[n]) |
| 2975 | return n; |
| 2976 | return -ENXIO; |
| 2977 | } |
| 2978 | |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2979 | static enum handoff pix_rdi_clk_handoff(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2980 | { |
| 2981 | u32 reg; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2982 | struct pix_rdi_clk *rdi = to_pix_rdi_clk(c); |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2983 | enum handoff ret; |
| 2984 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2985 | ret = branch_handoff(&rdi->b, &rdi->c); |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2986 | if (ret == HANDOFF_DISABLED_CLK) |
| 2987 | return ret; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2988 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 2989 | reg = readl_relaxed(rdi->s_reg); |
| 2990 | rdi->cur_rate = reg & rdi->s_mask ? 1 : 0; |
| 2991 | reg = readl_relaxed(rdi->s2_reg); |
| 2992 | rdi->cur_rate = reg & rdi->s2_mask ? 2 : rdi->cur_rate; |
Matt Wagantall | a15833b | 2012-04-03 11:00:56 -0700 | [diff] [blame] | 2993 | |
| 2994 | return HANDOFF_ENABLED_CLK; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2995 | } |
| 2996 | |
| 2997 | static struct clk_ops clk_ops_pix_rdi_8960 = { |
| 2998 | .enable = pix_rdi_clk_enable, |
| 2999 | .disable = pix_rdi_clk_disable, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3000 | .handoff = pix_rdi_clk_handoff, |
| 3001 | .set_rate = pix_rdi_clk_set_rate, |
| 3002 | .get_rate = pix_rdi_clk_get_rate, |
| 3003 | .list_rate = pix_rdi_clk_list_rate, |
| 3004 | .reset = pix_rdi_clk_reset, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3005 | .get_parent = pix_rdi_clk_get_parent, |
| 3006 | }; |
| 3007 | |
| 3008 | static struct pix_rdi_clk csi_pix_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3009 | .b = { |
| 3010 | .ctl_reg = MISC_CC_REG, |
| 3011 | .en_mask = BIT(26), |
| 3012 | .halt_check = DELAY, |
| 3013 | .reset_reg = SW_RESET_CORE_REG, |
| 3014 | .reset_mask = BIT(26), |
| 3015 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3016 | .s_reg = MISC_CC_REG, |
| 3017 | .s_mask = BIT(25), |
| 3018 | .s2_reg = MISC_CC3_REG, |
| 3019 | .s2_mask = BIT(13), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3020 | .c = { |
| 3021 | .dbg_name = "csi_pix_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3022 | .ops = &clk_ops_pix_rdi_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3023 | CLK_INIT(csi_pix_clk.c), |
| 3024 | }, |
| 3025 | }; |
| 3026 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3027 | static struct pix_rdi_clk csi_pix1_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3028 | .b = { |
| 3029 | .ctl_reg = MISC_CC3_REG, |
| 3030 | .en_mask = BIT(10), |
| 3031 | .halt_check = DELAY, |
| 3032 | .reset_reg = SW_RESET_CORE_REG, |
| 3033 | .reset_mask = BIT(30), |
| 3034 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3035 | .s_reg = MISC_CC3_REG, |
| 3036 | .s_mask = BIT(8), |
| 3037 | .s2_reg = MISC_CC3_REG, |
| 3038 | .s2_mask = BIT(9), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3039 | .c = { |
| 3040 | .dbg_name = "csi_pix1_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3041 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3042 | CLK_INIT(csi_pix1_clk.c), |
| 3043 | }, |
| 3044 | }; |
| 3045 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3046 | static struct pix_rdi_clk csi_rdi_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3047 | .b = { |
| 3048 | .ctl_reg = MISC_CC_REG, |
| 3049 | .en_mask = BIT(13), |
| 3050 | .halt_check = DELAY, |
| 3051 | .reset_reg = SW_RESET_CORE_REG, |
| 3052 | .reset_mask = BIT(27), |
| 3053 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3054 | .s_reg = MISC_CC_REG, |
| 3055 | .s_mask = BIT(12), |
| 3056 | .s2_reg = MISC_CC3_REG, |
| 3057 | .s2_mask = BIT(12), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3058 | .c = { |
| 3059 | .dbg_name = "csi_rdi_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3060 | .ops = &clk_ops_pix_rdi_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3061 | CLK_INIT(csi_rdi_clk.c), |
| 3062 | }, |
| 3063 | }; |
| 3064 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3065 | static struct pix_rdi_clk csi_rdi1_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3066 | .b = { |
| 3067 | .ctl_reg = MISC_CC3_REG, |
| 3068 | .en_mask = BIT(2), |
| 3069 | .halt_check = DELAY, |
| 3070 | .reset_reg = SW_RESET_CORE2_REG, |
| 3071 | .reset_mask = BIT(1), |
| 3072 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3073 | .s_reg = MISC_CC3_REG, |
| 3074 | .s_mask = BIT(0), |
| 3075 | .s2_reg = MISC_CC3_REG, |
| 3076 | .s2_mask = BIT(1), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3077 | .c = { |
| 3078 | .dbg_name = "csi_rdi1_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3079 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3080 | CLK_INIT(csi_rdi1_clk.c), |
| 3081 | }, |
| 3082 | }; |
| 3083 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3084 | static struct pix_rdi_clk csi_rdi2_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3085 | .b = { |
| 3086 | .ctl_reg = MISC_CC3_REG, |
| 3087 | .en_mask = BIT(6), |
| 3088 | .halt_check = DELAY, |
| 3089 | .reset_reg = SW_RESET_CORE2_REG, |
| 3090 | .reset_mask = BIT(0), |
| 3091 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3092 | .s_reg = MISC_CC3_REG, |
| 3093 | .s_mask = BIT(4), |
| 3094 | .s2_reg = MISC_CC3_REG, |
| 3095 | .s2_mask = BIT(5), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3096 | .c = { |
| 3097 | .dbg_name = "csi_rdi2_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 3098 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3099 | CLK_INIT(csi_rdi2_clk.c), |
| 3100 | }, |
| 3101 | }; |
| 3102 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3103 | #define F_CSI_PHYTIMER(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3104 | { \ |
| 3105 | .freq_hz = f, \ |
| 3106 | .src_clk = &s##_clk.c, \ |
| 3107 | .md_val = MD8(8, m, 0, n), \ |
| 3108 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3109 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3110 | } |
| 3111 | static struct clk_freq_tbl clk_tbl_csi_phytimer[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3112 | F_CSI_PHYTIMER( 0, gnd, 1, 0, 0), |
| 3113 | F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9), |
| 3114 | F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3115 | F_END |
| 3116 | }; |
| 3117 | |
| 3118 | static struct rcg_clk csiphy_timer_src_clk = { |
| 3119 | .ns_reg = CSIPHYTIMER_NS_REG, |
| 3120 | .b = { |
| 3121 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3122 | .halt_check = NOCHECK, |
| 3123 | }, |
| 3124 | .md_reg = CSIPHYTIMER_MD_REG, |
| 3125 | .root_en_mask = BIT(2), |
| 3126 | .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 3127 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3128 | .ctl_mask = BM(7, 6), |
| 3129 | .set_rate = set_rate_mnd_8, |
| 3130 | .freq_tbl = clk_tbl_csi_phytimer, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3131 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3132 | .c = { |
| 3133 | .dbg_name = "csiphy_timer_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3134 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3135 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3136 | CLK_INIT(csiphy_timer_src_clk.c), |
| 3137 | }, |
| 3138 | }; |
| 3139 | |
| 3140 | static struct branch_clk csi0phy_timer_clk = { |
| 3141 | .b = { |
| 3142 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3143 | .en_mask = BIT(0), |
| 3144 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3145 | .halt_bit = 17, |
| 3146 | }, |
| 3147 | .parent = &csiphy_timer_src_clk.c, |
| 3148 | .c = { |
| 3149 | .dbg_name = "csi0phy_timer_clk", |
| 3150 | .ops = &clk_ops_branch, |
| 3151 | CLK_INIT(csi0phy_timer_clk.c), |
| 3152 | }, |
| 3153 | }; |
| 3154 | |
| 3155 | static struct branch_clk csi1phy_timer_clk = { |
| 3156 | .b = { |
| 3157 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3158 | .en_mask = BIT(9), |
| 3159 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3160 | .halt_bit = 18, |
| 3161 | }, |
| 3162 | .parent = &csiphy_timer_src_clk.c, |
| 3163 | .c = { |
| 3164 | .dbg_name = "csi1phy_timer_clk", |
| 3165 | .ops = &clk_ops_branch, |
| 3166 | CLK_INIT(csi1phy_timer_clk.c), |
| 3167 | }, |
| 3168 | }; |
| 3169 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3170 | static struct branch_clk csi2phy_timer_clk = { |
| 3171 | .b = { |
| 3172 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3173 | .en_mask = BIT(11), |
| 3174 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3175 | .halt_bit = 30, |
| 3176 | }, |
| 3177 | .parent = &csiphy_timer_src_clk.c, |
| 3178 | .c = { |
| 3179 | .dbg_name = "csi2phy_timer_clk", |
| 3180 | .ops = &clk_ops_branch, |
| 3181 | CLK_INIT(csi2phy_timer_clk.c), |
| 3182 | }, |
| 3183 | }; |
| 3184 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3185 | #define F_DSI(d) \ |
| 3186 | { \ |
| 3187 | .freq_hz = d, \ |
| 3188 | .ns_val = BVAL(15, 12, (d-1)), \ |
| 3189 | } |
| 3190 | /* |
| 3191 | * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate |
| 3192 | * without this clock driver knowing. So, overload the clk_set_rate() to set |
| 3193 | * the divider (1 to 16) of the clock with respect to the PLL rate. |
| 3194 | */ |
| 3195 | static struct clk_freq_tbl clk_tbl_dsi_byte[] = { |
| 3196 | F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4), |
| 3197 | F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8), |
| 3198 | F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12), |
| 3199 | F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16), |
| 3200 | F_END |
| 3201 | }; |
| 3202 | |
Matt Wagantall | 735e41b | 2012-07-23 17:18:58 -0700 | [diff] [blame] | 3203 | static struct branch_clk dsi1_reset_clk = { |
| 3204 | .b = { |
| 3205 | .reset_reg = SW_RESET_CORE_REG, |
| 3206 | .reset_mask = BIT(7), |
| 3207 | .halt_check = NOCHECK, |
| 3208 | }, |
| 3209 | .c = { |
| 3210 | .dbg_name = "dsi1_reset_clk", |
| 3211 | .ops = &clk_ops_branch, |
| 3212 | CLK_INIT(dsi1_reset_clk.c), |
| 3213 | }, |
| 3214 | }; |
| 3215 | |
| 3216 | static struct branch_clk dsi2_reset_clk = { |
| 3217 | .b = { |
| 3218 | .reset_reg = SW_RESET_CORE_REG, |
| 3219 | .reset_mask = BIT(25), |
| 3220 | .halt_check = NOCHECK, |
| 3221 | }, |
| 3222 | .c = { |
| 3223 | .dbg_name = "dsi2_reset_clk", |
| 3224 | .ops = &clk_ops_branch, |
| 3225 | CLK_INIT(dsi2_reset_clk.c), |
| 3226 | }, |
| 3227 | }; |
| 3228 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3229 | static struct rcg_clk dsi1_byte_clk = { |
| 3230 | .b = { |
| 3231 | .ctl_reg = DSI1_BYTE_CC_REG, |
| 3232 | .en_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3233 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3234 | .halt_bit = 21, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3235 | .retain_reg = DSI1_BYTE_CC_REG, |
| 3236 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3237 | }, |
| 3238 | .ns_reg = DSI1_BYTE_NS_REG, |
| 3239 | .root_en_mask = BIT(2), |
| 3240 | .ns_mask = BM(15, 12), |
| 3241 | .set_rate = set_rate_nop, |
| 3242 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3243 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3244 | .c = { |
| 3245 | .dbg_name = "dsi1_byte_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3246 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3247 | CLK_INIT(dsi1_byte_clk.c), |
| 3248 | }, |
| 3249 | }; |
| 3250 | |
| 3251 | static struct rcg_clk dsi2_byte_clk = { |
| 3252 | .b = { |
| 3253 | .ctl_reg = DSI2_BYTE_CC_REG, |
| 3254 | .en_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3255 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3256 | .halt_bit = 20, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3257 | .retain_reg = DSI2_BYTE_CC_REG, |
| 3258 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3259 | }, |
| 3260 | .ns_reg = DSI2_BYTE_NS_REG, |
| 3261 | .root_en_mask = BIT(2), |
| 3262 | .ns_mask = BM(15, 12), |
| 3263 | .set_rate = set_rate_nop, |
| 3264 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3265 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3266 | .c = { |
| 3267 | .dbg_name = "dsi2_byte_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3268 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3269 | CLK_INIT(dsi2_byte_clk.c), |
| 3270 | }, |
| 3271 | }; |
| 3272 | |
| 3273 | static struct rcg_clk dsi1_esc_clk = { |
| 3274 | .b = { |
| 3275 | .ctl_reg = DSI1_ESC_CC_REG, |
| 3276 | .en_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3277 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3278 | .halt_bit = 1, |
| 3279 | }, |
| 3280 | .ns_reg = DSI1_ESC_NS_REG, |
| 3281 | .root_en_mask = BIT(2), |
| 3282 | .ns_mask = BM(15, 12), |
| 3283 | .set_rate = set_rate_nop, |
| 3284 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3285 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3286 | .c = { |
| 3287 | .dbg_name = "dsi1_esc_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3288 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3289 | CLK_INIT(dsi1_esc_clk.c), |
| 3290 | }, |
| 3291 | }; |
| 3292 | |
| 3293 | static struct rcg_clk dsi2_esc_clk = { |
| 3294 | .b = { |
| 3295 | .ctl_reg = DSI2_ESC_CC_REG, |
| 3296 | .en_mask = BIT(0), |
| 3297 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3298 | .halt_bit = 3, |
| 3299 | }, |
| 3300 | .ns_reg = DSI2_ESC_NS_REG, |
| 3301 | .root_en_mask = BIT(2), |
| 3302 | .ns_mask = BM(15, 12), |
| 3303 | .set_rate = set_rate_nop, |
| 3304 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3305 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3306 | .c = { |
| 3307 | .dbg_name = "dsi2_esc_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3308 | .ops = &clk_ops_rcg, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3309 | CLK_INIT(dsi2_esc_clk.c), |
| 3310 | }, |
| 3311 | }; |
| 3312 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3313 | #define F_GFX2D(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3314 | { \ |
| 3315 | .freq_hz = f, \ |
| 3316 | .src_clk = &s##_clk.c, \ |
| 3317 | .md_val = MD4(4, m, 0, n), \ |
| 3318 | .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \ |
| 3319 | .ctl_val = CC_BANKED(9, 6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3320 | } |
| 3321 | static struct clk_freq_tbl clk_tbl_gfx2d[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3322 | F_GFX2D( 0, gnd, 0, 0), |
| 3323 | F_GFX2D( 27000000, pxo, 0, 0), |
| 3324 | F_GFX2D( 48000000, pll8, 1, 8), |
| 3325 | F_GFX2D( 54857000, pll8, 1, 7), |
| 3326 | F_GFX2D( 64000000, pll8, 1, 6), |
| 3327 | F_GFX2D( 76800000, pll8, 1, 5), |
| 3328 | F_GFX2D( 96000000, pll8, 1, 4), |
| 3329 | F_GFX2D(128000000, pll8, 1, 3), |
| 3330 | F_GFX2D(145455000, pll2, 2, 11), |
| 3331 | F_GFX2D(160000000, pll2, 1, 5), |
| 3332 | F_GFX2D(177778000, pll2, 2, 9), |
| 3333 | F_GFX2D(200000000, pll2, 1, 4), |
| 3334 | F_GFX2D(228571000, pll2, 2, 7), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3335 | F_END |
| 3336 | }; |
| 3337 | |
| 3338 | static struct bank_masks bmnd_info_gfx2d0 = { |
| 3339 | .bank_sel_mask = BIT(11), |
| 3340 | .bank0_mask = { |
| 3341 | .md_reg = GFX2D0_MD0_REG, |
| 3342 | .ns_mask = BM(23, 20) | BM(5, 3), |
| 3343 | .rst_mask = BIT(25), |
| 3344 | .mnd_en_mask = BIT(8), |
| 3345 | .mode_mask = BM(10, 9), |
| 3346 | }, |
| 3347 | .bank1_mask = { |
| 3348 | .md_reg = GFX2D0_MD1_REG, |
| 3349 | .ns_mask = BM(19, 16) | BM(2, 0), |
| 3350 | .rst_mask = BIT(24), |
| 3351 | .mnd_en_mask = BIT(5), |
| 3352 | .mode_mask = BM(7, 6), |
| 3353 | }, |
| 3354 | }; |
| 3355 | |
| 3356 | static struct rcg_clk gfx2d0_clk = { |
| 3357 | .b = { |
| 3358 | .ctl_reg = GFX2D0_CC_REG, |
| 3359 | .en_mask = BIT(0), |
| 3360 | .reset_reg = SW_RESET_CORE_REG, |
| 3361 | .reset_mask = BIT(14), |
| 3362 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3363 | .halt_bit = 9, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3364 | .retain_reg = GFX2D0_CC_REG, |
| 3365 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3366 | }, |
| 3367 | .ns_reg = GFX2D0_NS_REG, |
| 3368 | .root_en_mask = BIT(2), |
| 3369 | .set_rate = set_rate_mnd_banked, |
| 3370 | .freq_tbl = clk_tbl_gfx2d, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3371 | .bank_info = &bmnd_info_gfx2d0, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3372 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3373 | .c = { |
| 3374 | .dbg_name = "gfx2d0_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3375 | .ops = &clk_ops_rcg, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 3376 | .flags = CLKFLAG_SKIP_HANDOFF, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3377 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 3378 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3379 | CLK_INIT(gfx2d0_clk.c), |
| 3380 | }, |
| 3381 | }; |
| 3382 | |
| 3383 | static struct bank_masks bmnd_info_gfx2d1 = { |
| 3384 | .bank_sel_mask = BIT(11), |
| 3385 | .bank0_mask = { |
| 3386 | .md_reg = GFX2D1_MD0_REG, |
| 3387 | .ns_mask = BM(23, 20) | BM(5, 3), |
| 3388 | .rst_mask = BIT(25), |
| 3389 | .mnd_en_mask = BIT(8), |
| 3390 | .mode_mask = BM(10, 9), |
| 3391 | }, |
| 3392 | .bank1_mask = { |
| 3393 | .md_reg = GFX2D1_MD1_REG, |
| 3394 | .ns_mask = BM(19, 16) | BM(2, 0), |
| 3395 | .rst_mask = BIT(24), |
| 3396 | .mnd_en_mask = BIT(5), |
| 3397 | .mode_mask = BM(7, 6), |
| 3398 | }, |
| 3399 | }; |
| 3400 | |
| 3401 | static struct rcg_clk gfx2d1_clk = { |
| 3402 | .b = { |
| 3403 | .ctl_reg = GFX2D1_CC_REG, |
| 3404 | .en_mask = BIT(0), |
| 3405 | .reset_reg = SW_RESET_CORE_REG, |
| 3406 | .reset_mask = BIT(13), |
| 3407 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3408 | .halt_bit = 14, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3409 | .retain_reg = GFX2D1_CC_REG, |
| 3410 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3411 | }, |
| 3412 | .ns_reg = GFX2D1_NS_REG, |
| 3413 | .root_en_mask = BIT(2), |
| 3414 | .set_rate = set_rate_mnd_banked, |
| 3415 | .freq_tbl = clk_tbl_gfx2d, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3416 | .bank_info = &bmnd_info_gfx2d1, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3417 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3418 | .c = { |
| 3419 | .dbg_name = "gfx2d1_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3420 | .ops = &clk_ops_rcg, |
Matt Wagantall | 158f73b | 2012-05-16 11:29:35 -0700 | [diff] [blame] | 3421 | .flags = CLKFLAG_SKIP_HANDOFF, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3422 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 3423 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3424 | CLK_INIT(gfx2d1_clk.c), |
| 3425 | }, |
| 3426 | }; |
| 3427 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3428 | #define F_GFX3D(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3429 | { \ |
| 3430 | .freq_hz = f, \ |
| 3431 | .src_clk = &s##_clk.c, \ |
| 3432 | .md_val = MD4(4, m, 0, n), \ |
| 3433 | .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3434 | .ctl_val = CC_BANKED(9, 6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3435 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3436 | |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 3437 | static struct clk_freq_tbl clk_tbl_gfx3d_8960ab[] = { |
| 3438 | F_GFX3D( 0, gnd, 0, 0), |
| 3439 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3440 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3441 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3442 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3443 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3444 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3445 | F_GFX3D(128000000, pll8, 1, 3), |
| 3446 | F_GFX3D(145455000, pll2, 2, 11), |
| 3447 | F_GFX3D(160000000, pll2, 1, 5), |
| 3448 | F_GFX3D(177778000, pll2, 2, 9), |
| 3449 | F_GFX3D(200000000, pll2, 1, 4), |
| 3450 | F_GFX3D(228571000, pll2, 2, 7), |
| 3451 | F_GFX3D(266667000, pll2, 1, 3), |
| 3452 | F_GFX3D(320000000, pll2, 2, 5), |
| 3453 | F_GFX3D(325000000, pll3, 1, 2), |
| 3454 | F_GFX3D(400000000, pll2, 1, 2), |
| 3455 | F_END |
| 3456 | }; |
| 3457 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3458 | static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3459 | F_GFX3D( 0, gnd, 0, 0), |
| 3460 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3461 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3462 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3463 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3464 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3465 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3466 | F_GFX3D(128000000, pll8, 1, 3), |
| 3467 | F_GFX3D(145455000, pll2, 2, 11), |
| 3468 | F_GFX3D(160000000, pll2, 1, 5), |
| 3469 | F_GFX3D(177778000, pll2, 2, 9), |
| 3470 | F_GFX3D(200000000, pll2, 1, 4), |
| 3471 | F_GFX3D(228571000, pll2, 2, 7), |
| 3472 | F_GFX3D(266667000, pll2, 1, 3), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3473 | F_GFX3D(300000000, pll3, 1, 4), |
| 3474 | F_GFX3D(320000000, pll2, 2, 5), |
| 3475 | F_GFX3D(400000000, pll2, 1, 2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3476 | F_END |
| 3477 | }; |
| 3478 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3479 | static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3480 | F_GFX3D( 0, gnd, 0, 0), |
| 3481 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3482 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3483 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3484 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3485 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3486 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3487 | F_GFX3D(128000000, pll8, 1, 3), |
| 3488 | F_GFX3D(145455000, pll2, 2, 11), |
| 3489 | F_GFX3D(160000000, pll2, 1, 5), |
| 3490 | F_GFX3D(177778000, pll2, 2, 9), |
| 3491 | F_GFX3D(200000000, pll2, 1, 4), |
| 3492 | F_GFX3D(228571000, pll2, 2, 7), |
| 3493 | F_GFX3D(266667000, pll2, 1, 3), |
Tianyi Gou | 0c50fe3 | 2011-10-19 15:50:35 -0700 | [diff] [blame] | 3494 | F_GFX3D(325000000, pll15, 1, 3), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3495 | F_GFX3D(400000000, pll2, 1, 2), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3496 | F_END |
| 3497 | }; |
| 3498 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3499 | static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = { |
| 3500 | F_GFX3D( 0, gnd, 0, 0), |
| 3501 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3502 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3503 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3504 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3505 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3506 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3507 | F_GFX3D(128000000, pll8, 1, 3), |
| 3508 | F_GFX3D(145455000, pll2, 2, 11), |
| 3509 | F_GFX3D(160000000, pll2, 1, 5), |
| 3510 | F_GFX3D(177778000, pll2, 2, 9), |
Tianyi Gou | 4d33c9c | 2012-03-30 11:10:15 -0700 | [diff] [blame] | 3511 | F_GFX3D(192000000, pll8, 1, 2), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3512 | F_GFX3D(200000000, pll2, 1, 4), |
| 3513 | F_GFX3D(228571000, pll2, 2, 7), |
| 3514 | F_GFX3D(266667000, pll2, 1, 3), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3515 | F_GFX3D(320000000, pll2, 2, 5), |
| 3516 | F_GFX3D(400000000, pll2, 1, 2), |
| 3517 | F_GFX3D(450000000, pll15, 1, 2), |
| 3518 | F_END |
| 3519 | }; |
| 3520 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3521 | static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = { |
| 3522 | [VDD_DIG_LOW] = 128000000, |
| 3523 | [VDD_DIG_NOMINAL] = 325000000, |
| 3524 | [VDD_DIG_HIGH] = 400000000 |
| 3525 | }; |
| 3526 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3527 | static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = { |
Tianyi Gou | 4d33c9c | 2012-03-30 11:10:15 -0700 | [diff] [blame] | 3528 | [VDD_DIG_LOW] = 192000000, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 3529 | [VDD_DIG_NOMINAL] = 320000000, |
| 3530 | [VDD_DIG_HIGH] = 450000000 |
| 3531 | }; |
| 3532 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3533 | static struct bank_masks bmnd_info_gfx3d = { |
| 3534 | .bank_sel_mask = BIT(11), |
| 3535 | .bank0_mask = { |
| 3536 | .md_reg = GFX3D_MD0_REG, |
| 3537 | .ns_mask = BM(21, 18) | BM(5, 3), |
| 3538 | .rst_mask = BIT(23), |
| 3539 | .mnd_en_mask = BIT(8), |
| 3540 | .mode_mask = BM(10, 9), |
| 3541 | }, |
| 3542 | .bank1_mask = { |
| 3543 | .md_reg = GFX3D_MD1_REG, |
| 3544 | .ns_mask = BM(17, 14) | BM(2, 0), |
| 3545 | .rst_mask = BIT(22), |
| 3546 | .mnd_en_mask = BIT(5), |
| 3547 | .mode_mask = BM(7, 6), |
| 3548 | }, |
| 3549 | }; |
| 3550 | |
| 3551 | static struct rcg_clk gfx3d_clk = { |
| 3552 | .b = { |
| 3553 | .ctl_reg = GFX3D_CC_REG, |
| 3554 | .en_mask = BIT(0), |
| 3555 | .reset_reg = SW_RESET_CORE_REG, |
| 3556 | .reset_mask = BIT(12), |
| 3557 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3558 | .halt_bit = 4, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3559 | .retain_reg = GFX3D_CC_REG, |
| 3560 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3561 | }, |
| 3562 | .ns_reg = GFX3D_NS_REG, |
| 3563 | .root_en_mask = BIT(2), |
| 3564 | .set_rate = set_rate_mnd_banked, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3565 | .freq_tbl = clk_tbl_gfx3d_8960, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3566 | .bank_info = &bmnd_info_gfx3d, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3567 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3568 | .c = { |
| 3569 | .dbg_name = "gfx3d_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3570 | .ops = &clk_ops_rcg, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 3571 | VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000, |
| 3572 | HIGH, 400000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3573 | CLK_INIT(gfx3d_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3574 | .depends = &gmem_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3575 | }, |
| 3576 | }; |
| 3577 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3578 | #define F_VCAP(f, s, m, n) \ |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3579 | { \ |
| 3580 | .freq_hz = f, \ |
| 3581 | .src_clk = &s##_clk.c, \ |
| 3582 | .md_val = MD4(4, m, 0, n), \ |
| 3583 | .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3584 | .ctl_val = CC_BANKED(9, 6, n), \ |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3585 | } |
| 3586 | |
| 3587 | static struct clk_freq_tbl clk_tbl_vcap[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3588 | F_VCAP( 0, gnd, 0, 0), |
| 3589 | F_VCAP( 27000000, pxo, 0, 0), |
| 3590 | F_VCAP( 54860000, pll8, 1, 7), |
| 3591 | F_VCAP( 64000000, pll8, 1, 6), |
| 3592 | F_VCAP( 76800000, pll8, 1, 5), |
| 3593 | F_VCAP(128000000, pll8, 1, 3), |
| 3594 | F_VCAP(160000000, pll2, 1, 5), |
| 3595 | F_VCAP(200000000, pll2, 1, 4), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3596 | F_END |
| 3597 | }; |
| 3598 | |
| 3599 | static struct bank_masks bmnd_info_vcap = { |
| 3600 | .bank_sel_mask = BIT(11), |
| 3601 | .bank0_mask = { |
| 3602 | .md_reg = VCAP_MD0_REG, |
| 3603 | .ns_mask = BM(21, 18) | BM(5, 3), |
| 3604 | .rst_mask = BIT(23), |
| 3605 | .mnd_en_mask = BIT(8), |
| 3606 | .mode_mask = BM(10, 9), |
| 3607 | }, |
| 3608 | .bank1_mask = { |
| 3609 | .md_reg = VCAP_MD1_REG, |
| 3610 | .ns_mask = BM(17, 14) | BM(2, 0), |
| 3611 | .rst_mask = BIT(22), |
| 3612 | .mnd_en_mask = BIT(5), |
| 3613 | .mode_mask = BM(7, 6), |
| 3614 | }, |
| 3615 | }; |
| 3616 | |
| 3617 | static struct rcg_clk vcap_clk = { |
| 3618 | .b = { |
| 3619 | .ctl_reg = VCAP_CC_REG, |
| 3620 | .en_mask = BIT(0), |
| 3621 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 3622 | .halt_bit = 15, |
| 3623 | }, |
| 3624 | .ns_reg = VCAP_NS_REG, |
| 3625 | .root_en_mask = BIT(2), |
| 3626 | .set_rate = set_rate_mnd_banked, |
| 3627 | .freq_tbl = clk_tbl_vcap, |
| 3628 | .bank_info = &bmnd_info_vcap, |
| 3629 | .current_freq = &rcg_dummy_freq, |
| 3630 | .c = { |
| 3631 | .dbg_name = "vcap_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3632 | .ops = &clk_ops_rcg, |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3633 | .depends = &vcap_axi_clk.c, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3634 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3635 | CLK_INIT(vcap_clk.c), |
| 3636 | }, |
| 3637 | }; |
| 3638 | |
| 3639 | static struct branch_clk vcap_npl_clk = { |
| 3640 | .b = { |
| 3641 | .ctl_reg = VCAP_CC_REG, |
| 3642 | .en_mask = BIT(13), |
| 3643 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 3644 | .halt_bit = 25, |
| 3645 | }, |
| 3646 | .parent = &vcap_clk.c, |
| 3647 | .c = { |
| 3648 | .dbg_name = "vcap_npl_clk", |
| 3649 | .ops = &clk_ops_branch, |
| 3650 | CLK_INIT(vcap_npl_clk.c), |
| 3651 | }, |
| 3652 | }; |
| 3653 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3654 | #define F_IJPEG(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3655 | { \ |
| 3656 | .freq_hz = f, \ |
| 3657 | .src_clk = &s##_clk.c, \ |
| 3658 | .md_val = MD8(8, m, 0, n), \ |
| 3659 | .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \ |
| 3660 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3661 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3662 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3663 | static struct clk_freq_tbl clk_tbl_ijpeg[] = { |
| 3664 | F_IJPEG( 0, gnd, 1, 0, 0), |
| 3665 | F_IJPEG( 27000000, pxo, 1, 0, 0), |
| 3666 | F_IJPEG( 36570000, pll8, 1, 2, 21), |
| 3667 | F_IJPEG( 54860000, pll8, 7, 0, 0), |
| 3668 | F_IJPEG( 96000000, pll8, 4, 0, 0), |
| 3669 | F_IJPEG(109710000, pll8, 1, 2, 7), |
| 3670 | F_IJPEG(128000000, pll8, 3, 0, 0), |
| 3671 | F_IJPEG(153600000, pll8, 1, 2, 5), |
| 3672 | F_IJPEG(200000000, pll2, 4, 0, 0), |
| 3673 | F_IJPEG(228571000, pll2, 1, 2, 7), |
| 3674 | F_IJPEG(266667000, pll2, 1, 1, 3), |
| 3675 | F_IJPEG(320000000, pll2, 1, 2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3676 | F_END |
| 3677 | }; |
| 3678 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3679 | static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = { |
| 3680 | [VDD_DIG_LOW] = 128000000, |
| 3681 | [VDD_DIG_NOMINAL] = 266667000, |
| 3682 | [VDD_DIG_HIGH] = 320000000 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3683 | }; |
| 3684 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3685 | static struct rcg_clk ijpeg_clk = { |
| 3686 | .b = { |
| 3687 | .ctl_reg = IJPEG_CC_REG, |
| 3688 | .en_mask = BIT(0), |
| 3689 | .reset_reg = SW_RESET_CORE_REG, |
| 3690 | .reset_mask = BIT(9), |
| 3691 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3692 | .halt_bit = 24, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3693 | .retain_reg = IJPEG_CC_REG, |
| 3694 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3695 | }, |
| 3696 | .ns_reg = IJPEG_NS_REG, |
| 3697 | .md_reg = IJPEG_MD_REG, |
| 3698 | .root_en_mask = BIT(2), |
| 3699 | .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 3700 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3701 | .ctl_mask = BM(7, 6), |
| 3702 | .set_rate = set_rate_mnd, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3703 | .freq_tbl = clk_tbl_ijpeg, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3704 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3705 | .c = { |
| 3706 | .dbg_name = "ijpeg_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3707 | .ops = &clk_ops_rcg, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 3708 | VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000, |
| 3709 | HIGH, 320000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3710 | CLK_INIT(ijpeg_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3711 | .depends = &ijpeg_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3712 | }, |
| 3713 | }; |
| 3714 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3715 | #define F_JPEGD(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3716 | { \ |
| 3717 | .freq_hz = f, \ |
| 3718 | .src_clk = &s##_clk.c, \ |
| 3719 | .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3720 | } |
| 3721 | static struct clk_freq_tbl clk_tbl_jpegd[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3722 | F_JPEGD( 0, gnd, 1), |
| 3723 | F_JPEGD( 64000000, pll8, 6), |
| 3724 | F_JPEGD( 76800000, pll8, 5), |
| 3725 | F_JPEGD( 96000000, pll8, 4), |
| 3726 | F_JPEGD(160000000, pll2, 5), |
| 3727 | F_JPEGD(200000000, pll2, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3728 | F_END |
| 3729 | }; |
| 3730 | |
| 3731 | static struct rcg_clk jpegd_clk = { |
| 3732 | .b = { |
| 3733 | .ctl_reg = JPEGD_CC_REG, |
| 3734 | .en_mask = BIT(0), |
| 3735 | .reset_reg = SW_RESET_CORE_REG, |
| 3736 | .reset_mask = BIT(19), |
| 3737 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3738 | .halt_bit = 19, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3739 | .retain_reg = JPEGD_CC_REG, |
| 3740 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3741 | }, |
| 3742 | .ns_reg = JPEGD_NS_REG, |
| 3743 | .root_en_mask = BIT(2), |
| 3744 | .ns_mask = (BM(15, 12) | BM(2, 0)), |
| 3745 | .set_rate = set_rate_nop, |
| 3746 | .freq_tbl = clk_tbl_jpegd, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3747 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3748 | .c = { |
| 3749 | .dbg_name = "jpegd_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3750 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3751 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3752 | CLK_INIT(jpegd_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3753 | .depends = &jpegd_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3754 | }, |
| 3755 | }; |
| 3756 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3757 | #define F_MDP(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3758 | { \ |
| 3759 | .freq_hz = f, \ |
| 3760 | .src_clk = &s##_clk.c, \ |
| 3761 | .md_val = MD8(8, m, 0, n), \ |
| 3762 | .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3763 | .ctl_val = CC_BANKED(9, 6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3764 | } |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 3765 | static struct clk_freq_tbl clk_tbl_mdp_8960ab[] = { |
| 3766 | F_MDP( 0, gnd, 0, 0), |
| 3767 | F_MDP( 9600000, pll8, 1, 40), |
| 3768 | F_MDP( 13710000, pll8, 1, 28), |
| 3769 | F_MDP( 27000000, pxo, 0, 0), |
| 3770 | F_MDP( 29540000, pll8, 1, 13), |
| 3771 | F_MDP( 34910000, pll8, 1, 11), |
| 3772 | F_MDP( 38400000, pll8, 1, 10), |
| 3773 | F_MDP( 59080000, pll8, 2, 13), |
| 3774 | F_MDP( 76800000, pll8, 1, 5), |
| 3775 | F_MDP( 85330000, pll8, 2, 9), |
| 3776 | F_MDP( 96000000, pll8, 1, 4), |
| 3777 | F_MDP(128000000, pll8, 1, 3), |
| 3778 | F_MDP(160000000, pll2, 1, 5), |
| 3779 | F_MDP(177780000, pll2, 2, 9), |
| 3780 | F_MDP(200000000, pll2, 1, 4), |
| 3781 | F_MDP(228571000, pll2, 2, 7), |
| 3782 | F_MDP(266667000, pll2, 1, 3), |
| 3783 | F_END |
| 3784 | }; |
| 3785 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3786 | static struct clk_freq_tbl clk_tbl_mdp[] = { |
| 3787 | F_MDP( 0, gnd, 0, 0), |
| 3788 | F_MDP( 9600000, pll8, 1, 40), |
| 3789 | F_MDP( 13710000, pll8, 1, 28), |
| 3790 | F_MDP( 27000000, pxo, 0, 0), |
| 3791 | F_MDP( 29540000, pll8, 1, 13), |
| 3792 | F_MDP( 34910000, pll8, 1, 11), |
| 3793 | F_MDP( 38400000, pll8, 1, 10), |
| 3794 | F_MDP( 59080000, pll8, 2, 13), |
| 3795 | F_MDP( 76800000, pll8, 1, 5), |
| 3796 | F_MDP( 85330000, pll8, 2, 9), |
| 3797 | F_MDP( 96000000, pll8, 1, 4), |
| 3798 | F_MDP(128000000, pll8, 1, 3), |
| 3799 | F_MDP(160000000, pll2, 1, 5), |
| 3800 | F_MDP(177780000, pll2, 2, 9), |
| 3801 | F_MDP(200000000, pll2, 1, 4), |
| 3802 | F_MDP(266667000, pll2, 1, 3), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3803 | F_END |
| 3804 | }; |
| 3805 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3806 | static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = { |
| 3807 | [VDD_DIG_LOW] = 128000000, |
| 3808 | [VDD_DIG_NOMINAL] = 266667000 |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3809 | }; |
| 3810 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3811 | static struct bank_masks bmnd_info_mdp = { |
| 3812 | .bank_sel_mask = BIT(11), |
| 3813 | .bank0_mask = { |
| 3814 | .md_reg = MDP_MD0_REG, |
| 3815 | .ns_mask = BM(29, 22) | BM(5, 3), |
| 3816 | .rst_mask = BIT(31), |
| 3817 | .mnd_en_mask = BIT(8), |
| 3818 | .mode_mask = BM(10, 9), |
| 3819 | }, |
| 3820 | .bank1_mask = { |
| 3821 | .md_reg = MDP_MD1_REG, |
| 3822 | .ns_mask = BM(21, 14) | BM(2, 0), |
| 3823 | .rst_mask = BIT(30), |
| 3824 | .mnd_en_mask = BIT(5), |
| 3825 | .mode_mask = BM(7, 6), |
| 3826 | }, |
| 3827 | }; |
| 3828 | |
| 3829 | static struct rcg_clk mdp_clk = { |
| 3830 | .b = { |
| 3831 | .ctl_reg = MDP_CC_REG, |
| 3832 | .en_mask = BIT(0), |
| 3833 | .reset_reg = SW_RESET_CORE_REG, |
| 3834 | .reset_mask = BIT(21), |
| 3835 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 3836 | .halt_bit = 10, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3837 | .retain_reg = MDP_CC_REG, |
| 3838 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3839 | }, |
| 3840 | .ns_reg = MDP_NS_REG, |
| 3841 | .root_en_mask = BIT(2), |
| 3842 | .set_rate = set_rate_mnd_banked, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3843 | .freq_tbl = clk_tbl_mdp, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3844 | .bank_info = &bmnd_info_mdp, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3845 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3846 | .c = { |
| 3847 | .dbg_name = "mdp_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3848 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3849 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3850 | CLK_INIT(mdp_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3851 | .depends = &mdp_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3852 | }, |
| 3853 | }; |
| 3854 | |
| 3855 | static struct branch_clk lut_mdp_clk = { |
| 3856 | .b = { |
| 3857 | .ctl_reg = MDP_LUT_CC_REG, |
| 3858 | .en_mask = BIT(0), |
| 3859 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3860 | .halt_bit = 13, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3861 | .retain_reg = MDP_LUT_CC_REG, |
| 3862 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3863 | }, |
| 3864 | .parent = &mdp_clk.c, |
| 3865 | .c = { |
| 3866 | .dbg_name = "lut_mdp_clk", |
| 3867 | .ops = &clk_ops_branch, |
| 3868 | CLK_INIT(lut_mdp_clk.c), |
| 3869 | }, |
| 3870 | }; |
| 3871 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3872 | #define F_MDP_VSYNC(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3873 | { \ |
| 3874 | .freq_hz = f, \ |
| 3875 | .src_clk = &s##_clk.c, \ |
| 3876 | .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3877 | } |
| 3878 | static struct clk_freq_tbl clk_tbl_mdp_vsync[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3879 | F_MDP_VSYNC(27000000, pxo), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3880 | F_END |
| 3881 | }; |
| 3882 | |
| 3883 | static struct rcg_clk mdp_vsync_clk = { |
| 3884 | .b = { |
| 3885 | .ctl_reg = MISC_CC_REG, |
| 3886 | .en_mask = BIT(6), |
| 3887 | .reset_reg = SW_RESET_CORE_REG, |
| 3888 | .reset_mask = BIT(3), |
| 3889 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3890 | .halt_bit = 22, |
| 3891 | }, |
| 3892 | .ns_reg = MISC_CC2_REG, |
| 3893 | .ns_mask = BIT(13), |
| 3894 | .set_rate = set_rate_nop, |
| 3895 | .freq_tbl = clk_tbl_mdp_vsync, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3896 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3897 | .c = { |
| 3898 | .dbg_name = "mdp_vsync_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3899 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3900 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3901 | CLK_INIT(mdp_vsync_clk.c), |
| 3902 | }, |
| 3903 | }; |
| 3904 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3905 | #define F_ROT(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3906 | { \ |
| 3907 | .freq_hz = f, \ |
| 3908 | .src_clk = &s##_clk.c, \ |
| 3909 | .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \ |
| 3910 | 21, 19, 18, 16, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3911 | } |
| 3912 | static struct clk_freq_tbl clk_tbl_rot[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3913 | F_ROT( 0, gnd, 1), |
| 3914 | F_ROT( 27000000, pxo, 1), |
| 3915 | F_ROT( 29540000, pll8, 13), |
| 3916 | F_ROT( 32000000, pll8, 12), |
| 3917 | F_ROT( 38400000, pll8, 10), |
| 3918 | F_ROT( 48000000, pll8, 8), |
| 3919 | F_ROT( 54860000, pll8, 7), |
| 3920 | F_ROT( 64000000, pll8, 6), |
| 3921 | F_ROT( 76800000, pll8, 5), |
| 3922 | F_ROT( 96000000, pll8, 4), |
| 3923 | F_ROT(100000000, pll2, 8), |
| 3924 | F_ROT(114290000, pll2, 7), |
| 3925 | F_ROT(133330000, pll2, 6), |
| 3926 | F_ROT(160000000, pll2, 5), |
| 3927 | F_ROT(200000000, pll2, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3928 | F_END |
| 3929 | }; |
| 3930 | |
| 3931 | static struct bank_masks bdiv_info_rot = { |
| 3932 | .bank_sel_mask = BIT(30), |
| 3933 | .bank0_mask = { |
| 3934 | .ns_mask = BM(25, 22) | BM(18, 16), |
| 3935 | }, |
| 3936 | .bank1_mask = { |
| 3937 | .ns_mask = BM(29, 26) | BM(21, 19), |
| 3938 | }, |
| 3939 | }; |
| 3940 | |
| 3941 | static struct rcg_clk rot_clk = { |
| 3942 | .b = { |
| 3943 | .ctl_reg = ROT_CC_REG, |
| 3944 | .en_mask = BIT(0), |
| 3945 | .reset_reg = SW_RESET_CORE_REG, |
| 3946 | .reset_mask = BIT(2), |
| 3947 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 3948 | .halt_bit = 15, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3949 | .retain_reg = ROT_CC_REG, |
| 3950 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3951 | }, |
| 3952 | .ns_reg = ROT_NS_REG, |
| 3953 | .root_en_mask = BIT(2), |
| 3954 | .set_rate = set_rate_div_banked, |
| 3955 | .freq_tbl = clk_tbl_rot, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3956 | .bank_info = &bdiv_info_rot, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3957 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3958 | .c = { |
| 3959 | .dbg_name = "rot_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 3960 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3961 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3962 | CLK_INIT(rot_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3963 | .depends = &rot_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3964 | }, |
| 3965 | }; |
| 3966 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3967 | static int hdmi_pll_clk_enable(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3968 | { |
| 3969 | int ret; |
| 3970 | unsigned long flags; |
| 3971 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3972 | ret = hdmi_pll_enable(); |
| 3973 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3974 | return ret; |
| 3975 | } |
| 3976 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3977 | static void hdmi_pll_clk_disable(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3978 | { |
| 3979 | unsigned long flags; |
| 3980 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3981 | hdmi_pll_disable(); |
| 3982 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3983 | } |
| 3984 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 3985 | static struct clk *hdmi_pll_clk_get_parent(struct clk *c) |
Stephen Boyd | 5b35dee | 2011-09-21 12:17:38 -0700 | [diff] [blame] | 3986 | { |
| 3987 | return &pxo_clk.c; |
| 3988 | } |
| 3989 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3990 | static struct clk_ops clk_ops_hdmi_pll = { |
| 3991 | .enable = hdmi_pll_clk_enable, |
| 3992 | .disable = hdmi_pll_clk_disable, |
Stephen Boyd | 5b35dee | 2011-09-21 12:17:38 -0700 | [diff] [blame] | 3993 | .get_parent = hdmi_pll_clk_get_parent, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3994 | }; |
| 3995 | |
| 3996 | static struct clk hdmi_pll_clk = { |
| 3997 | .dbg_name = "hdmi_pll_clk", |
| 3998 | .ops = &clk_ops_hdmi_pll, |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 3999 | .vdd_class = &vdd_sr2_hdmi_pll, |
| 4000 | .fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4001 | CLK_INIT(hdmi_pll_clk), |
| 4002 | }; |
| 4003 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4004 | #define F_TV_GND(f, s, p_r, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4005 | { \ |
| 4006 | .freq_hz = f, \ |
| 4007 | .src_clk = &s##_clk.c, \ |
| 4008 | .md_val = MD8(8, m, 0, n), \ |
| 4009 | .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 4010 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4011 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4012 | #define F_TV(f, s, p_r, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4013 | { \ |
| 4014 | .freq_hz = f, \ |
| 4015 | .src_clk = &s##_clk, \ |
| 4016 | .md_val = MD8(8, m, 0, n), \ |
| 4017 | .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 4018 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4019 | .extra_freq_data = (void *)p_r, \ |
| 4020 | } |
| 4021 | /* Switching TV freqs requires PLL reconfiguration. */ |
| 4022 | static struct clk_freq_tbl clk_tbl_tv[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4023 | F_TV_GND( 0, gnd, 0, 1, 0, 0), |
| 4024 | F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0), |
| 4025 | F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0), |
| 4026 | F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0), |
| 4027 | F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0), |
| 4028 | F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4029 | F_END |
| 4030 | }; |
| 4031 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4032 | static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = { |
| 4033 | [VDD_DIG_LOW] = 74250000, |
| 4034 | [VDD_DIG_NOMINAL] = 149000000 |
| 4035 | }; |
| 4036 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4037 | /* |
| 4038 | * Unlike other clocks, the TV rate is adjusted through PLL |
| 4039 | * re-programming. It is also routed through an MND divider. |
| 4040 | */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4041 | void set_rate_tv(struct rcg_clk *rcg, struct clk_freq_tbl *nf) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4042 | { |
| 4043 | unsigned long pll_rate = (unsigned long)nf->extra_freq_data; |
Matt Wagantall | f6c39a1 | 2012-07-09 19:24:42 -0700 | [diff] [blame] | 4044 | if (pll_rate) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4045 | hdmi_pll_set_rate(pll_rate); |
Matt Wagantall | f6c39a1 | 2012-07-09 19:24:42 -0700 | [diff] [blame] | 4046 | hdmi_pll_clk.rate = pll_rate; |
| 4047 | } |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4048 | set_rate_mnd(rcg, nf); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4049 | } |
| 4050 | |
| 4051 | static struct rcg_clk tv_src_clk = { |
| 4052 | .ns_reg = TV_NS_REG, |
| 4053 | .b = { |
| 4054 | .ctl_reg = TV_CC_REG, |
| 4055 | .halt_check = NOCHECK, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4056 | .retain_reg = TV_CC_REG, |
| 4057 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4058 | }, |
| 4059 | .md_reg = TV_MD_REG, |
| 4060 | .root_en_mask = BIT(2), |
| 4061 | .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4062 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4063 | .ctl_mask = BM(7, 6), |
| 4064 | .set_rate = set_rate_tv, |
| 4065 | .freq_tbl = clk_tbl_tv, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4066 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4067 | .c = { |
| 4068 | .dbg_name = "tv_src_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4069 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4070 | VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4071 | CLK_INIT(tv_src_clk.c), |
| 4072 | }, |
| 4073 | }; |
| 4074 | |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4075 | static struct cdiv_clk tv_src_div_clk = { |
| 4076 | .b = { |
| 4077 | .ctl_reg = TV_NS_REG, |
| 4078 | .halt_check = NOCHECK, |
| 4079 | }, |
| 4080 | .ns_reg = TV_NS_REG, |
| 4081 | .div_offset = 6, |
| 4082 | .max_div = 2, |
| 4083 | .c = { |
| 4084 | .dbg_name = "tv_src_div_clk", |
| 4085 | .ops = &clk_ops_cdiv, |
| 4086 | CLK_INIT(tv_src_div_clk.c), |
Stephen Boyd | d51d5e8 | 2012-06-18 18:09:50 -0700 | [diff] [blame] | 4087 | .rate = ULONG_MAX, |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4088 | }, |
| 4089 | }; |
| 4090 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4091 | static struct branch_clk tv_enc_clk = { |
| 4092 | .b = { |
| 4093 | .ctl_reg = TV_CC_REG, |
| 4094 | .en_mask = BIT(8), |
| 4095 | .reset_reg = SW_RESET_CORE_REG, |
| 4096 | .reset_mask = BIT(0), |
| 4097 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4098 | .halt_bit = 9, |
| 4099 | }, |
| 4100 | .parent = &tv_src_clk.c, |
| 4101 | .c = { |
| 4102 | .dbg_name = "tv_enc_clk", |
| 4103 | .ops = &clk_ops_branch, |
| 4104 | CLK_INIT(tv_enc_clk.c), |
| 4105 | }, |
| 4106 | }; |
| 4107 | |
| 4108 | static struct branch_clk tv_dac_clk = { |
| 4109 | .b = { |
| 4110 | .ctl_reg = TV_CC_REG, |
| 4111 | .en_mask = BIT(10), |
| 4112 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4113 | .halt_bit = 10, |
| 4114 | }, |
| 4115 | .parent = &tv_src_clk.c, |
| 4116 | .c = { |
| 4117 | .dbg_name = "tv_dac_clk", |
| 4118 | .ops = &clk_ops_branch, |
| 4119 | CLK_INIT(tv_dac_clk.c), |
| 4120 | }, |
| 4121 | }; |
| 4122 | |
| 4123 | static struct branch_clk mdp_tv_clk = { |
| 4124 | .b = { |
| 4125 | .ctl_reg = TV_CC_REG, |
| 4126 | .en_mask = BIT(0), |
| 4127 | .reset_reg = SW_RESET_CORE_REG, |
| 4128 | .reset_mask = BIT(4), |
| 4129 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4130 | .halt_bit = 12, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4131 | .retain_reg = TV_CC2_REG, |
| 4132 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4133 | }, |
| 4134 | .parent = &tv_src_clk.c, |
| 4135 | .c = { |
| 4136 | .dbg_name = "mdp_tv_clk", |
| 4137 | .ops = &clk_ops_branch, |
| 4138 | CLK_INIT(mdp_tv_clk.c), |
| 4139 | }, |
| 4140 | }; |
| 4141 | |
| 4142 | static struct branch_clk hdmi_tv_clk = { |
| 4143 | .b = { |
| 4144 | .ctl_reg = TV_CC_REG, |
| 4145 | .en_mask = BIT(12), |
| 4146 | .reset_reg = SW_RESET_CORE_REG, |
| 4147 | .reset_mask = BIT(1), |
| 4148 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 4149 | .halt_bit = 11, |
| 4150 | }, |
| 4151 | .parent = &tv_src_clk.c, |
| 4152 | .c = { |
| 4153 | .dbg_name = "hdmi_tv_clk", |
| 4154 | .ops = &clk_ops_branch, |
| 4155 | CLK_INIT(hdmi_tv_clk.c), |
| 4156 | }, |
| 4157 | }; |
| 4158 | |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4159 | static struct branch_clk rgb_tv_clk = { |
| 4160 | .b = { |
| 4161 | .ctl_reg = TV_CC2_REG, |
| 4162 | .en_mask = BIT(14), |
| 4163 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 4164 | .halt_bit = 27, |
| 4165 | }, |
| 4166 | .parent = &tv_src_clk.c, |
| 4167 | .c = { |
| 4168 | .dbg_name = "rgb_tv_clk", |
| 4169 | .ops = &clk_ops_branch, |
| 4170 | CLK_INIT(rgb_tv_clk.c), |
| 4171 | }, |
| 4172 | }; |
| 4173 | |
| 4174 | static struct branch_clk npl_tv_clk = { |
| 4175 | .b = { |
| 4176 | .ctl_reg = TV_CC2_REG, |
| 4177 | .en_mask = BIT(16), |
| 4178 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 4179 | .halt_bit = 26, |
| 4180 | }, |
| 4181 | .parent = &tv_src_clk.c, |
| 4182 | .c = { |
| 4183 | .dbg_name = "npl_tv_clk", |
| 4184 | .ops = &clk_ops_branch, |
| 4185 | CLK_INIT(npl_tv_clk.c), |
| 4186 | }, |
| 4187 | }; |
| 4188 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4189 | static struct branch_clk hdmi_app_clk = { |
| 4190 | .b = { |
| 4191 | .ctl_reg = MISC_CC2_REG, |
| 4192 | .en_mask = BIT(11), |
| 4193 | .reset_reg = SW_RESET_CORE_REG, |
| 4194 | .reset_mask = BIT(11), |
| 4195 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4196 | .halt_bit = 25, |
| 4197 | }, |
| 4198 | .c = { |
| 4199 | .dbg_name = "hdmi_app_clk", |
| 4200 | .ops = &clk_ops_branch, |
| 4201 | CLK_INIT(hdmi_app_clk.c), |
| 4202 | }, |
| 4203 | }; |
| 4204 | |
| 4205 | static struct bank_masks bmnd_info_vcodec = { |
| 4206 | .bank_sel_mask = BIT(13), |
| 4207 | .bank0_mask = { |
| 4208 | .md_reg = VCODEC_MD0_REG, |
| 4209 | .ns_mask = BM(18, 11) | BM(2, 0), |
| 4210 | .rst_mask = BIT(31), |
| 4211 | .mnd_en_mask = BIT(5), |
| 4212 | .mode_mask = BM(7, 6), |
| 4213 | }, |
| 4214 | .bank1_mask = { |
| 4215 | .md_reg = VCODEC_MD1_REG, |
| 4216 | .ns_mask = BM(26, 19) | BM(29, 27), |
| 4217 | .rst_mask = BIT(30), |
| 4218 | .mnd_en_mask = BIT(10), |
| 4219 | .mode_mask = BM(12, 11), |
| 4220 | }, |
| 4221 | }; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4222 | #define F_VCODEC(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4223 | { \ |
| 4224 | .freq_hz = f, \ |
| 4225 | .src_clk = &s##_clk.c, \ |
| 4226 | .md_val = MD8(8, m, 0, n), \ |
| 4227 | .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \ |
| 4228 | .ctl_val = CC_BANKED(6, 11, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4229 | } |
| 4230 | static struct clk_freq_tbl clk_tbl_vcodec[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4231 | F_VCODEC( 0, gnd, 0, 0), |
| 4232 | F_VCODEC( 27000000, pxo, 0, 0), |
| 4233 | F_VCODEC( 32000000, pll8, 1, 12), |
| 4234 | F_VCODEC( 48000000, pll8, 1, 8), |
| 4235 | F_VCODEC( 54860000, pll8, 1, 7), |
| 4236 | F_VCODEC( 96000000, pll8, 1, 4), |
| 4237 | F_VCODEC(133330000, pll2, 1, 6), |
| 4238 | F_VCODEC(200000000, pll2, 1, 4), |
| 4239 | F_VCODEC(228570000, pll2, 2, 7), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4240 | F_END |
| 4241 | }; |
| 4242 | |
| 4243 | static struct rcg_clk vcodec_clk = { |
| 4244 | .b = { |
| 4245 | .ctl_reg = VCODEC_CC_REG, |
| 4246 | .en_mask = BIT(0), |
| 4247 | .reset_reg = SW_RESET_CORE_REG, |
| 4248 | .reset_mask = BIT(6), |
| 4249 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 4250 | .halt_bit = 29, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4251 | .retain_reg = VCODEC_CC_REG, |
| 4252 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4253 | }, |
| 4254 | .ns_reg = VCODEC_NS_REG, |
| 4255 | .root_en_mask = BIT(2), |
| 4256 | .set_rate = set_rate_mnd_banked, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 4257 | .bank_info = &bmnd_info_vcodec, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4258 | .freq_tbl = clk_tbl_vcodec, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4259 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4260 | .c = { |
| 4261 | .dbg_name = "vcodec_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4262 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4263 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 4264 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4265 | CLK_INIT(vcodec_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4266 | .depends = &vcodec_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4267 | }, |
| 4268 | }; |
| 4269 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4270 | #define F_VPE(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4271 | { \ |
| 4272 | .freq_hz = f, \ |
| 4273 | .src_clk = &s##_clk.c, \ |
| 4274 | .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4275 | } |
| 4276 | static struct clk_freq_tbl clk_tbl_vpe[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4277 | F_VPE( 0, gnd, 1), |
| 4278 | F_VPE( 27000000, pxo, 1), |
| 4279 | F_VPE( 34909000, pll8, 11), |
| 4280 | F_VPE( 38400000, pll8, 10), |
| 4281 | F_VPE( 64000000, pll8, 6), |
| 4282 | F_VPE( 76800000, pll8, 5), |
| 4283 | F_VPE( 96000000, pll8, 4), |
| 4284 | F_VPE(100000000, pll2, 8), |
| 4285 | F_VPE(160000000, pll2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4286 | F_END |
| 4287 | }; |
| 4288 | |
| 4289 | static struct rcg_clk vpe_clk = { |
| 4290 | .b = { |
| 4291 | .ctl_reg = VPE_CC_REG, |
| 4292 | .en_mask = BIT(0), |
| 4293 | .reset_reg = SW_RESET_CORE_REG, |
| 4294 | .reset_mask = BIT(17), |
| 4295 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 4296 | .halt_bit = 28, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4297 | .retain_reg = VPE_CC_REG, |
| 4298 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4299 | }, |
| 4300 | .ns_reg = VPE_NS_REG, |
| 4301 | .root_en_mask = BIT(2), |
| 4302 | .ns_mask = (BM(15, 12) | BM(2, 0)), |
| 4303 | .set_rate = set_rate_nop, |
| 4304 | .freq_tbl = clk_tbl_vpe, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4305 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4306 | .c = { |
| 4307 | .dbg_name = "vpe_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4308 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4309 | VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4310 | CLK_INIT(vpe_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4311 | .depends = &vpe_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4312 | }, |
| 4313 | }; |
| 4314 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4315 | #define F_VFE(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4316 | { \ |
| 4317 | .freq_hz = f, \ |
| 4318 | .src_clk = &s##_clk.c, \ |
| 4319 | .md_val = MD8(8, m, 0, n), \ |
| 4320 | .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \ |
| 4321 | .ctl_val = CC(6, n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4322 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4323 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4324 | static struct clk_freq_tbl clk_tbl_vfe[] = { |
| 4325 | F_VFE( 0, gnd, 1, 0, 0), |
| 4326 | F_VFE( 13960000, pll8, 1, 2, 55), |
| 4327 | F_VFE( 27000000, pxo, 1, 0, 0), |
| 4328 | F_VFE( 36570000, pll8, 1, 2, 21), |
| 4329 | F_VFE( 38400000, pll8, 2, 1, 5), |
| 4330 | F_VFE( 45180000, pll8, 1, 2, 17), |
| 4331 | F_VFE( 48000000, pll8, 2, 1, 4), |
| 4332 | F_VFE( 54860000, pll8, 1, 1, 7), |
| 4333 | F_VFE( 64000000, pll8, 2, 1, 3), |
| 4334 | F_VFE( 76800000, pll8, 1, 1, 5), |
| 4335 | F_VFE( 96000000, pll8, 2, 1, 2), |
| 4336 | F_VFE(109710000, pll8, 1, 2, 7), |
| 4337 | F_VFE(128000000, pll8, 1, 1, 3), |
| 4338 | F_VFE(153600000, pll8, 1, 2, 5), |
| 4339 | F_VFE(200000000, pll2, 2, 1, 2), |
| 4340 | F_VFE(228570000, pll2, 1, 2, 7), |
| 4341 | F_VFE(266667000, pll2, 1, 1, 3), |
| 4342 | F_VFE(320000000, pll2, 1, 2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4343 | F_END |
| 4344 | }; |
| 4345 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4346 | static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = { |
| 4347 | [VDD_DIG_LOW] = 128000000, |
| 4348 | [VDD_DIG_NOMINAL] = 266667000, |
| 4349 | [VDD_DIG_HIGH] = 320000000 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4350 | }; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4351 | |
| 4352 | static struct rcg_clk vfe_clk = { |
| 4353 | .b = { |
| 4354 | .ctl_reg = VFE_CC_REG, |
| 4355 | .reset_reg = SW_RESET_CORE_REG, |
| 4356 | .reset_mask = BIT(15), |
| 4357 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4358 | .halt_bit = 6, |
| 4359 | .en_mask = BIT(0), |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4360 | .retain_reg = VFE_CC2_REG, |
| 4361 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4362 | }, |
| 4363 | .ns_reg = VFE_NS_REG, |
| 4364 | .md_reg = VFE_MD_REG, |
| 4365 | .root_en_mask = BIT(2), |
| 4366 | .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4367 | .mnd_en_mask = BIT(5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4368 | .ctl_mask = BM(7, 6), |
| 4369 | .set_rate = set_rate_mnd, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4370 | .freq_tbl = clk_tbl_vfe, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4371 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4372 | .c = { |
| 4373 | .dbg_name = "vfe_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4374 | .ops = &clk_ops_rcg, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 4375 | VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000, |
| 4376 | HIGH, 320000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4377 | CLK_INIT(vfe_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4378 | .depends = &vfe_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4379 | }, |
| 4380 | }; |
| 4381 | |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4382 | static struct branch_clk csi_vfe_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4383 | .b = { |
| 4384 | .ctl_reg = VFE_CC_REG, |
| 4385 | .en_mask = BIT(12), |
| 4386 | .reset_reg = SW_RESET_CORE_REG, |
| 4387 | .reset_mask = BIT(24), |
| 4388 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4389 | .halt_bit = 8, |
| 4390 | }, |
| 4391 | .parent = &vfe_clk.c, |
| 4392 | .c = { |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4393 | .dbg_name = "csi_vfe_clk", |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4394 | .ops = &clk_ops_branch, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4395 | CLK_INIT(csi_vfe_clk.c), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4396 | }, |
| 4397 | }; |
| 4398 | |
| 4399 | /* |
| 4400 | * Low Power Audio Clocks |
| 4401 | */ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4402 | #define F_AIF_OSR(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4403 | { \ |
| 4404 | .freq_hz = f, \ |
| 4405 | .src_clk = &s##_clk.c, \ |
| 4406 | .md_val = MD8(8, m, 0, n), \ |
| 4407 | .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4408 | } |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4409 | static struct clk_freq_tbl clk_tbl_aif_osr_492[] = { |
| 4410 | F_AIF_OSR( 0, gnd, 1, 0, 0), |
| 4411 | F_AIF_OSR( 512000, pll4, 4, 1, 240), |
| 4412 | F_AIF_OSR( 768000, pll4, 4, 1, 160), |
| 4413 | F_AIF_OSR( 1024000, pll4, 4, 1, 120), |
| 4414 | F_AIF_OSR( 1536000, pll4, 4, 1, 80), |
| 4415 | F_AIF_OSR( 2048000, pll4, 4, 1, 60), |
| 4416 | F_AIF_OSR( 3072000, pll4, 4, 1, 40), |
| 4417 | F_AIF_OSR( 4096000, pll4, 4, 1, 30), |
| 4418 | F_AIF_OSR( 6144000, pll4, 4, 1, 20), |
| 4419 | F_AIF_OSR( 8192000, pll4, 4, 1, 15), |
| 4420 | F_AIF_OSR(12288000, pll4, 4, 1, 10), |
| 4421 | F_AIF_OSR(24576000, pll4, 4, 1, 5), |
| 4422 | F_END |
| 4423 | }; |
| 4424 | |
| 4425 | static struct clk_freq_tbl clk_tbl_aif_osr_393[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4426 | F_AIF_OSR( 0, gnd, 1, 0, 0), |
| 4427 | F_AIF_OSR( 512000, pll4, 4, 1, 192), |
| 4428 | F_AIF_OSR( 768000, pll4, 4, 1, 128), |
| 4429 | F_AIF_OSR( 1024000, pll4, 4, 1, 96), |
| 4430 | F_AIF_OSR( 1536000, pll4, 4, 1, 64), |
| 4431 | F_AIF_OSR( 2048000, pll4, 4, 1, 48), |
| 4432 | F_AIF_OSR( 3072000, pll4, 4, 1, 32), |
| 4433 | F_AIF_OSR( 4096000, pll4, 4, 1, 24), |
| 4434 | F_AIF_OSR( 6144000, pll4, 4, 1, 16), |
| 4435 | F_AIF_OSR( 8192000, pll4, 4, 1, 12), |
| 4436 | F_AIF_OSR(12288000, pll4, 4, 1, 8), |
| 4437 | F_AIF_OSR(24576000, pll4, 4, 1, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4438 | F_END |
| 4439 | }; |
| 4440 | |
| 4441 | #define CLK_AIF_OSR(i, ns, md, h_r) \ |
| 4442 | struct rcg_clk i##_clk = { \ |
| 4443 | .b = { \ |
| 4444 | .ctl_reg = ns, \ |
| 4445 | .en_mask = BIT(17), \ |
| 4446 | .reset_reg = ns, \ |
| 4447 | .reset_mask = BIT(19), \ |
| 4448 | .halt_reg = h_r, \ |
| 4449 | .halt_check = ENABLE, \ |
| 4450 | .halt_bit = 1, \ |
| 4451 | }, \ |
| 4452 | .ns_reg = ns, \ |
| 4453 | .md_reg = md, \ |
| 4454 | .root_en_mask = BIT(9), \ |
| 4455 | .ns_mask = (BM(31, 24) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4456 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4457 | .set_rate = set_rate_mnd, \ |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4458 | .freq_tbl = clk_tbl_aif_osr_393, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4459 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4460 | .c = { \ |
| 4461 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4462 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4463 | VDD_DIG_FMAX_MAP1(LOW, 24576000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4464 | CLK_INIT(i##_clk.c), \ |
| 4465 | }, \ |
| 4466 | } |
| 4467 | #define CLK_AIF_OSR_DIV(i, ns, md, h_r) \ |
| 4468 | struct rcg_clk i##_clk = { \ |
| 4469 | .b = { \ |
| 4470 | .ctl_reg = ns, \ |
| 4471 | .en_mask = BIT(21), \ |
| 4472 | .reset_reg = ns, \ |
| 4473 | .reset_mask = BIT(23), \ |
| 4474 | .halt_reg = h_r, \ |
| 4475 | .halt_check = ENABLE, \ |
| 4476 | .halt_bit = 1, \ |
| 4477 | }, \ |
| 4478 | .ns_reg = ns, \ |
| 4479 | .md_reg = md, \ |
| 4480 | .root_en_mask = BIT(9), \ |
| 4481 | .ns_mask = (BM(31, 24) | BM(6, 0)), \ |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4482 | .mnd_en_mask = BIT(8), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4483 | .set_rate = set_rate_mnd, \ |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4484 | .freq_tbl = clk_tbl_aif_osr_393, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4485 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4486 | .c = { \ |
| 4487 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4488 | .ops = &clk_ops_rcg, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4489 | VDD_DIG_FMAX_MAP1(LOW, 24576000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4490 | CLK_INIT(i##_clk.c), \ |
| 4491 | }, \ |
| 4492 | } |
| 4493 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4494 | #define CLK_AIF_BIT(i, ns, h_r) \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4495 | struct cdiv_clk i##_clk = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4496 | .b = { \ |
| 4497 | .ctl_reg = ns, \ |
| 4498 | .en_mask = BIT(15), \ |
| 4499 | .halt_reg = h_r, \ |
| 4500 | .halt_check = DELAY, \ |
| 4501 | }, \ |
| 4502 | .ns_reg = ns, \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4503 | .ext_mask = BIT(14), \ |
| 4504 | .div_offset = 10, \ |
| 4505 | .max_div = 16, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4506 | .c = { \ |
| 4507 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4508 | .ops = &clk_ops_cdiv, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4509 | CLK_INIT(i##_clk.c), \ |
Stephen Boyd | d51d5e8 | 2012-06-18 18:09:50 -0700 | [diff] [blame] | 4510 | .rate = ULONG_MAX, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4511 | }, \ |
| 4512 | } |
| 4513 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4514 | #define CLK_AIF_BIT_DIV(i, ns, h_r) \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4515 | struct cdiv_clk i##_clk = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4516 | .b = { \ |
| 4517 | .ctl_reg = ns, \ |
| 4518 | .en_mask = BIT(19), \ |
| 4519 | .halt_reg = h_r, \ |
Stephen Boyd | 7bb9cf8 | 2012-01-25 18:09:01 -0800 | [diff] [blame] | 4520 | .halt_check = DELAY, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4521 | }, \ |
| 4522 | .ns_reg = ns, \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4523 | .ext_mask = BIT(18), \ |
| 4524 | .div_offset = 10, \ |
| 4525 | .max_div = 256, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4526 | .c = { \ |
| 4527 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4528 | .ops = &clk_ops_cdiv, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4529 | CLK_INIT(i##_clk.c), \ |
Stephen Boyd | d51d5e8 | 2012-06-18 18:09:50 -0700 | [diff] [blame] | 4530 | .rate = ULONG_MAX, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4531 | }, \ |
| 4532 | } |
| 4533 | |
| 4534 | static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG, |
| 4535 | LCC_MI2S_STATUS_REG); |
| 4536 | static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG); |
| 4537 | |
| 4538 | static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG, |
| 4539 | LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG); |
| 4540 | static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG, |
| 4541 | LCC_CODEC_I2S_MIC_STATUS_REG); |
| 4542 | |
| 4543 | static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG, |
| 4544 | LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG); |
| 4545 | static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG, |
| 4546 | LCC_SPARE_I2S_MIC_STATUS_REG); |
| 4547 | |
| 4548 | static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG, |
| 4549 | LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG); |
| 4550 | static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG, |
| 4551 | LCC_CODEC_I2S_SPKR_STATUS_REG); |
| 4552 | |
| 4553 | static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG, |
| 4554 | LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG); |
| 4555 | static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG, |
| 4556 | LCC_SPARE_I2S_SPKR_STATUS_REG); |
| 4557 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4558 | #define F_PCM(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4559 | { \ |
| 4560 | .freq_hz = f, \ |
| 4561 | .src_clk = &s##_clk.c, \ |
| 4562 | .md_val = MD16(m, n), \ |
| 4563 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4564 | } |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4565 | static struct clk_freq_tbl clk_tbl_pcm_492[] = { |
| 4566 | { .ns_val = BIT(10) /* external input */ }, |
Stephen Boyd | e9ed94d | 2012-08-02 10:57:11 -0700 | [diff] [blame] | 4567 | F_PCM( 256000, pll4, 4, 1, 480), |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4568 | F_PCM( 512000, pll4, 4, 1, 240), |
| 4569 | F_PCM( 768000, pll4, 4, 1, 160), |
| 4570 | F_PCM( 1024000, pll4, 4, 1, 120), |
| 4571 | F_PCM( 1536000, pll4, 4, 1, 80), |
| 4572 | F_PCM( 2048000, pll4, 4, 1, 60), |
| 4573 | F_PCM( 3072000, pll4, 4, 1, 40), |
| 4574 | F_PCM( 4096000, pll4, 4, 1, 30), |
| 4575 | F_PCM( 6144000, pll4, 4, 1, 20), |
| 4576 | F_PCM( 8192000, pll4, 4, 1, 15), |
| 4577 | F_PCM(12288000, pll4, 4, 1, 10), |
| 4578 | F_PCM(24576000, pll4, 4, 1, 5), |
| 4579 | F_END |
| 4580 | }; |
| 4581 | |
| 4582 | static struct clk_freq_tbl clk_tbl_pcm_393[] = { |
Stephen Boyd | 630f325 | 2012-01-31 00:10:08 -0800 | [diff] [blame] | 4583 | { .ns_val = BIT(10) /* external input */ }, |
Stephen Boyd | e9ed94d | 2012-08-02 10:57:11 -0700 | [diff] [blame] | 4584 | F_PCM( 256000, pll4, 4, 1, 384), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4585 | F_PCM( 512000, pll4, 4, 1, 192), |
| 4586 | F_PCM( 768000, pll4, 4, 1, 128), |
| 4587 | F_PCM( 1024000, pll4, 4, 1, 96), |
| 4588 | F_PCM( 1536000, pll4, 4, 1, 64), |
| 4589 | F_PCM( 2048000, pll4, 4, 1, 48), |
| 4590 | F_PCM( 3072000, pll4, 4, 1, 32), |
| 4591 | F_PCM( 4096000, pll4, 4, 1, 24), |
| 4592 | F_PCM( 6144000, pll4, 4, 1, 16), |
| 4593 | F_PCM( 8192000, pll4, 4, 1, 12), |
| 4594 | F_PCM(12288000, pll4, 4, 1, 8), |
| 4595 | F_PCM(24576000, pll4, 4, 1, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4596 | F_END |
| 4597 | }; |
| 4598 | |
| 4599 | static struct rcg_clk pcm_clk = { |
| 4600 | .b = { |
| 4601 | .ctl_reg = LCC_PCM_NS_REG, |
| 4602 | .en_mask = BIT(11), |
| 4603 | .reset_reg = LCC_PCM_NS_REG, |
| 4604 | .reset_mask = BIT(13), |
| 4605 | .halt_reg = LCC_PCM_STATUS_REG, |
| 4606 | .halt_check = ENABLE, |
| 4607 | .halt_bit = 0, |
| 4608 | }, |
| 4609 | .ns_reg = LCC_PCM_NS_REG, |
| 4610 | .md_reg = LCC_PCM_MD_REG, |
| 4611 | .root_en_mask = BIT(9), |
Stephen Boyd | 630f325 | 2012-01-31 00:10:08 -0800 | [diff] [blame] | 4612 | .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4613 | .mnd_en_mask = BIT(8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4614 | .set_rate = set_rate_mnd, |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4615 | .freq_tbl = clk_tbl_pcm_393, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4616 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4617 | .c = { |
| 4618 | .dbg_name = "pcm_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4619 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4620 | VDD_DIG_FMAX_MAP1(LOW, 24576000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4621 | CLK_INIT(pcm_clk.c), |
Stephen Boyd | c5492fc | 2012-06-18 18:47:03 -0700 | [diff] [blame] | 4622 | .rate = ULONG_MAX, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4623 | }, |
| 4624 | }; |
| 4625 | |
| 4626 | static struct rcg_clk audio_slimbus_clk = { |
| 4627 | .b = { |
| 4628 | .ctl_reg = LCC_SLIMBUS_NS_REG, |
| 4629 | .en_mask = BIT(10), |
| 4630 | .reset_reg = LCC_AHBEX_BRANCH_CTL_REG, |
| 4631 | .reset_mask = BIT(5), |
| 4632 | .halt_reg = LCC_SLIMBUS_STATUS_REG, |
| 4633 | .halt_check = ENABLE, |
| 4634 | .halt_bit = 0, |
| 4635 | }, |
| 4636 | .ns_reg = LCC_SLIMBUS_NS_REG, |
| 4637 | .md_reg = LCC_SLIMBUS_MD_REG, |
| 4638 | .root_en_mask = BIT(9), |
| 4639 | .ns_mask = (BM(31, 24) | BM(6, 0)), |
Matt Wagantall | 07c4547 | 2012-02-10 23:27:24 -0800 | [diff] [blame] | 4640 | .mnd_en_mask = BIT(8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4641 | .set_rate = set_rate_mnd, |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 4642 | .freq_tbl = clk_tbl_aif_osr_393, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4643 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4644 | .c = { |
| 4645 | .dbg_name = "audio_slimbus_clk", |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 4646 | .ops = &clk_ops_rcg, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4647 | VDD_DIG_FMAX_MAP1(LOW, 24576000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4648 | CLK_INIT(audio_slimbus_clk.c), |
| 4649 | }, |
| 4650 | }; |
| 4651 | |
| 4652 | static struct branch_clk sps_slimbus_clk = { |
| 4653 | .b = { |
| 4654 | .ctl_reg = LCC_SLIMBUS_NS_REG, |
| 4655 | .en_mask = BIT(12), |
| 4656 | .halt_reg = LCC_SLIMBUS_STATUS_REG, |
| 4657 | .halt_check = ENABLE, |
| 4658 | .halt_bit = 1, |
| 4659 | }, |
| 4660 | .parent = &audio_slimbus_clk.c, |
| 4661 | .c = { |
| 4662 | .dbg_name = "sps_slimbus_clk", |
| 4663 | .ops = &clk_ops_branch, |
| 4664 | CLK_INIT(sps_slimbus_clk.c), |
| 4665 | }, |
| 4666 | }; |
| 4667 | |
| 4668 | static struct branch_clk slimbus_xo_src_clk = { |
| 4669 | .b = { |
| 4670 | .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG, |
| 4671 | .en_mask = BIT(2), |
| 4672 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4673 | .halt_bit = 28, |
| 4674 | }, |
| 4675 | .parent = &sps_slimbus_clk.c, |
| 4676 | .c = { |
| 4677 | .dbg_name = "slimbus_xo_src_clk", |
| 4678 | .ops = &clk_ops_branch, |
| 4679 | CLK_INIT(slimbus_xo_src_clk.c), |
| 4680 | }, |
| 4681 | }; |
| 4682 | |
Matt Wagantall | 735f01a | 2011-08-12 12:40:28 -0700 | [diff] [blame] | 4683 | DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL); |
| 4684 | DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL); |
| 4685 | DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL); |
| 4686 | DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL); |
| 4687 | DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL); |
| 4688 | DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL); |
| 4689 | DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL); |
| 4690 | DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL); |
Stephen Boyd | c7fc3b1 | 2012-05-17 14:42:46 -0700 | [diff] [blame] | 4691 | DEFINE_CLK_RPM_QDSS(qdss_clk, qdss_a_clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4692 | |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4693 | static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c, 0); |
| 4694 | static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c, 0); |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 4695 | |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4696 | static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c, 0); |
| 4697 | static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c, 0); |
| 4698 | static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c, 0); |
| 4699 | static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c, 0); |
| 4700 | static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c, 0); |
| 4701 | static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c, 0); |
| 4702 | static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c, 0); |
| 4703 | static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c, 0); |
| 4704 | static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c, 0); |
| 4705 | static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c, 0); |
| 4706 | static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c, 0); |
| 4707 | static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c, 0); |
| 4708 | static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c, 0); |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4709 | static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c, 0); |
| 4710 | static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c, 0); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4711 | |
Matt Wagantall | 42cd12a | 2012-03-30 18:02:40 -0700 | [diff] [blame] | 4712 | static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c, LONG_MAX); |
Matt Wagantall | 35e78fc | 2012-04-05 14:18:44 -0700 | [diff] [blame] | 4713 | static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c, 0); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4714 | |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 4715 | static DEFINE_CLK_VOTER(ebi1_acpu_a_clk, &ebi1_a_clk.c, LONG_MAX); |
| 4716 | static DEFINE_CLK_VOTER(ebi1_msmbus_a_clk, &ebi1_a_clk.c, LONG_MAX); |
| 4717 | static DEFINE_CLK_VOTER(afab_acpu_a_clk, &afab_a_clk.c, LONG_MAX); |
| 4718 | static DEFINE_CLK_VOTER(afab_msmbus_a_clk, &afab_a_clk.c, LONG_MAX); |
| 4719 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4720 | #ifdef CONFIG_DEBUG_FS |
| 4721 | struct measure_sel { |
| 4722 | u32 test_vector; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4723 | struct clk *c; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4724 | }; |
| 4725 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4726 | static DEFINE_CLK_MEASURE(l2_m_clk); |
| 4727 | static DEFINE_CLK_MEASURE(krait0_m_clk); |
| 4728 | static DEFINE_CLK_MEASURE(krait1_m_clk); |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 4729 | static DEFINE_CLK_MEASURE(krait2_m_clk); |
| 4730 | static DEFINE_CLK_MEASURE(krait3_m_clk); |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4731 | static DEFINE_CLK_MEASURE(q6sw_clk); |
| 4732 | static DEFINE_CLK_MEASURE(q6fw_clk); |
| 4733 | static DEFINE_CLK_MEASURE(q6_func_clk); |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4734 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4735 | static struct measure_sel measure_mux[] = { |
| 4736 | { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c }, |
| 4737 | { TEST_PER_LS(0x12), &sdc1_p_clk.c }, |
| 4738 | { TEST_PER_LS(0x13), &sdc1_clk.c }, |
| 4739 | { TEST_PER_LS(0x14), &sdc2_p_clk.c }, |
| 4740 | { TEST_PER_LS(0x15), &sdc2_clk.c }, |
| 4741 | { TEST_PER_LS(0x16), &sdc3_p_clk.c }, |
| 4742 | { TEST_PER_LS(0x17), &sdc3_clk.c }, |
| 4743 | { TEST_PER_LS(0x18), &sdc4_p_clk.c }, |
| 4744 | { TEST_PER_LS(0x19), &sdc4_clk.c }, |
| 4745 | { TEST_PER_LS(0x1A), &sdc5_p_clk.c }, |
| 4746 | { TEST_PER_LS(0x1B), &sdc5_clk.c }, |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 4747 | { TEST_PER_LS(0x1F), &gp0_clk.c }, |
| 4748 | { TEST_PER_LS(0x20), &gp1_clk.c }, |
| 4749 | { TEST_PER_LS(0x21), &gp2_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4750 | { TEST_PER_LS(0x25), &dfab_clk.c }, |
| 4751 | { TEST_PER_LS(0x25), &dfab_a_clk.c }, |
| 4752 | { TEST_PER_LS(0x26), &pmem_clk.c }, |
| 4753 | { TEST_PER_LS(0x32), &dma_bam_p_clk.c }, |
| 4754 | { TEST_PER_LS(0x33), &cfpb_clk.c }, |
| 4755 | { TEST_PER_LS(0x33), &cfpb_a_clk.c }, |
| 4756 | { TEST_PER_LS(0x3D), &gsbi1_p_clk.c }, |
| 4757 | { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c }, |
| 4758 | { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c }, |
| 4759 | { TEST_PER_LS(0x41), &gsbi2_p_clk.c }, |
| 4760 | { TEST_PER_LS(0x42), &gsbi2_uart_clk.c }, |
| 4761 | { TEST_PER_LS(0x44), &gsbi2_qup_clk.c }, |
| 4762 | { TEST_PER_LS(0x45), &gsbi3_p_clk.c }, |
| 4763 | { TEST_PER_LS(0x46), &gsbi3_uart_clk.c }, |
| 4764 | { TEST_PER_LS(0x48), &gsbi3_qup_clk.c }, |
| 4765 | { TEST_PER_LS(0x49), &gsbi4_p_clk.c }, |
| 4766 | { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c }, |
| 4767 | { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c }, |
| 4768 | { TEST_PER_LS(0x4D), &gsbi5_p_clk.c }, |
| 4769 | { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c }, |
| 4770 | { TEST_PER_LS(0x50), &gsbi5_qup_clk.c }, |
| 4771 | { TEST_PER_LS(0x51), &gsbi6_p_clk.c }, |
| 4772 | { TEST_PER_LS(0x52), &gsbi6_uart_clk.c }, |
| 4773 | { TEST_PER_LS(0x54), &gsbi6_qup_clk.c }, |
| 4774 | { TEST_PER_LS(0x55), &gsbi7_p_clk.c }, |
| 4775 | { TEST_PER_LS(0x56), &gsbi7_uart_clk.c }, |
| 4776 | { TEST_PER_LS(0x58), &gsbi7_qup_clk.c }, |
| 4777 | { TEST_PER_LS(0x59), &gsbi8_p_clk.c }, |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 4778 | { TEST_PER_LS(0x59), &sfab_sata_s_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4779 | { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c }, |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 4780 | { TEST_PER_LS(0x5A), &sata_p_clk.c }, |
| 4781 | { TEST_PER_LS(0x5B), &sata_rxoob_clk.c }, |
| 4782 | { TEST_PER_LS(0x5C), &sata_pmalive_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4783 | { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c }, |
| 4784 | { TEST_PER_LS(0x5D), &gsbi9_p_clk.c }, |
| 4785 | { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c }, |
| 4786 | { TEST_PER_LS(0x60), &gsbi9_qup_clk.c }, |
| 4787 | { TEST_PER_LS(0x61), &gsbi10_p_clk.c }, |
| 4788 | { TEST_PER_LS(0x62), &gsbi10_uart_clk.c }, |
| 4789 | { TEST_PER_LS(0x64), &gsbi10_qup_clk.c }, |
| 4790 | { TEST_PER_LS(0x65), &gsbi11_p_clk.c }, |
| 4791 | { TEST_PER_LS(0x66), &gsbi11_uart_clk.c }, |
| 4792 | { TEST_PER_LS(0x68), &gsbi11_qup_clk.c }, |
| 4793 | { TEST_PER_LS(0x69), &gsbi12_p_clk.c }, |
| 4794 | { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c }, |
| 4795 | { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c }, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4796 | { TEST_PER_LS(0x5E), &pcie_p_clk.c }, |
| 4797 | { TEST_PER_LS(0x5F), &ce3_p_clk.c }, |
| 4798 | { TEST_PER_LS(0x60), &ce3_core_clk.c }, |
| 4799 | { TEST_PER_LS(0x63), &usb_hs3_p_clk.c }, |
| 4800 | { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c }, |
| 4801 | { TEST_PER_LS(0x65), &usb_hs4_p_clk.c }, |
| 4802 | { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c }, |
| 4803 | { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c }, |
| 4804 | { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4805 | { TEST_PER_LS(0x78), &sfpb_clk.c }, |
| 4806 | { TEST_PER_LS(0x78), &sfpb_a_clk.c }, |
| 4807 | { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c }, |
| 4808 | { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c }, |
| 4809 | { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c }, |
| 4810 | { TEST_PER_LS(0x7D), &prng_clk.c }, |
| 4811 | { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c }, |
| 4812 | { TEST_PER_LS(0x80), &adm0_p_clk.c }, |
| 4813 | { TEST_PER_LS(0x84), &usb_hs1_p_clk.c }, |
| 4814 | { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4815 | { TEST_PER_LS(0x86), &usb_hsic_p_clk.c }, |
| 4816 | { TEST_PER_LS(0x87), &usb_hsic_system_clk.c }, |
| 4817 | { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4818 | { TEST_PER_LS(0x89), &usb_fs1_p_clk.c }, |
| 4819 | { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c }, |
| 4820 | { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c }, |
| 4821 | { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c }, |
| 4822 | { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c }, |
| 4823 | { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c }, |
| 4824 | { TEST_PER_LS(0x8F), &tsif_p_clk.c }, |
| 4825 | { TEST_PER_LS(0x91), &tsif_ref_clk.c }, |
| 4826 | { TEST_PER_LS(0x92), &ce1_p_clk.c }, |
| 4827 | { TEST_PER_LS(0x94), &tssc_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4828 | { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4829 | { TEST_PER_LS(0xA4), &ce1_core_clk.c }, |
| 4830 | |
| 4831 | { TEST_PER_HS(0x07), &afab_clk.c }, |
| 4832 | { TEST_PER_HS(0x07), &afab_a_clk.c }, |
| 4833 | { TEST_PER_HS(0x18), &sfab_clk.c }, |
| 4834 | { TEST_PER_HS(0x18), &sfab_a_clk.c }, |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4835 | { TEST_PER_HS(0x26), &q6sw_clk }, |
| 4836 | { TEST_PER_HS(0x27), &q6fw_clk }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4837 | { TEST_PER_HS(0x2A), &adm0_clk.c }, |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 4838 | { TEST_PER_HS(0x31), &sata_a_clk.c }, |
Tianyi Gou | 6613de5 | 2012-01-27 17:57:53 -0800 | [diff] [blame] | 4839 | { TEST_PER_HS(0x2D), &pcie_phy_ref_clk.c }, |
| 4840 | { TEST_PER_HS(0x32), &pcie_a_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4841 | { TEST_PER_HS(0x34), &ebi1_clk.c }, |
| 4842 | { TEST_PER_HS(0x34), &ebi1_a_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4843 | { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4844 | |
| 4845 | { TEST_MM_LS(0x00), &dsi1_byte_clk.c }, |
| 4846 | { TEST_MM_LS(0x01), &dsi2_byte_clk.c }, |
| 4847 | { TEST_MM_LS(0x02), &cam1_clk.c }, |
| 4848 | { TEST_MM_LS(0x06), &_p_clk.c }, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4849 | { TEST_MM_LS(0x07), &csi_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4850 | { TEST_MM_LS(0x08), &dsi2_s_p_clk.c }, |
| 4851 | { TEST_MM_LS(0x09), &dsi1_m_p_clk.c }, |
| 4852 | { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c }, |
| 4853 | { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c }, |
| 4854 | { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c }, |
| 4855 | { TEST_MM_LS(0x0E), &gfx3d_p_clk.c }, |
| 4856 | { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c }, |
| 4857 | { TEST_MM_LS(0x10), &hdmi_s_p_clk.c }, |
| 4858 | { TEST_MM_LS(0x11), &ijpeg_p_clk.c }, |
| 4859 | { TEST_MM_LS(0x12), &imem_p_clk.c }, |
| 4860 | { TEST_MM_LS(0x13), &jpegd_p_clk.c }, |
| 4861 | { TEST_MM_LS(0x14), &mdp_p_clk.c }, |
| 4862 | { TEST_MM_LS(0x16), &rot_p_clk.c }, |
| 4863 | { TEST_MM_LS(0x17), &dsi1_esc_clk.c }, |
| 4864 | { TEST_MM_LS(0x18), &smmu_p_clk.c }, |
| 4865 | { TEST_MM_LS(0x19), &tv_enc_p_clk.c }, |
| 4866 | { TEST_MM_LS(0x1A), &vcodec_p_clk.c }, |
| 4867 | { TEST_MM_LS(0x1B), &vfe_p_clk.c }, |
| 4868 | { TEST_MM_LS(0x1C), &vpe_p_clk.c }, |
| 4869 | { TEST_MM_LS(0x1D), &cam0_clk.c }, |
| 4870 | { TEST_MM_LS(0x1F), &hdmi_app_clk.c }, |
| 4871 | { TEST_MM_LS(0x20), &mdp_vsync_clk.c }, |
| 4872 | { TEST_MM_LS(0x21), &tv_dac_clk.c }, |
| 4873 | { TEST_MM_LS(0x22), &tv_enc_clk.c }, |
| 4874 | { TEST_MM_LS(0x23), &dsi2_esc_clk.c }, |
| 4875 | { TEST_MM_LS(0x25), &mmfpb_clk.c }, |
| 4876 | { TEST_MM_LS(0x25), &mmfpb_a_clk.c }, |
| 4877 | { TEST_MM_LS(0x26), &dsi2_m_p_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4878 | { TEST_MM_LS(0x27), &cam2_clk.c }, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4879 | { TEST_MM_LS(0x28), &vcap_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4880 | |
| 4881 | { TEST_MM_HS(0x00), &csi0_clk.c }, |
| 4882 | { TEST_MM_HS(0x01), &csi1_clk.c }, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4883 | { TEST_MM_HS(0x04), &csi_vfe_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4884 | { TEST_MM_HS(0x05), &ijpeg_clk.c }, |
| 4885 | { TEST_MM_HS(0x06), &vfe_clk.c }, |
| 4886 | { TEST_MM_HS(0x07), &gfx2d0_clk.c }, |
| 4887 | { TEST_MM_HS(0x08), &gfx2d1_clk.c }, |
| 4888 | { TEST_MM_HS(0x09), &gfx3d_clk.c }, |
| 4889 | { TEST_MM_HS(0x0A), &jpegd_clk.c }, |
| 4890 | { TEST_MM_HS(0x0B), &vcodec_clk.c }, |
| 4891 | { TEST_MM_HS(0x0F), &mmfab_clk.c }, |
| 4892 | { TEST_MM_HS(0x0F), &mmfab_a_clk.c }, |
| 4893 | { TEST_MM_HS(0x11), &gmem_axi_clk.c }, |
| 4894 | { TEST_MM_HS(0x12), &ijpeg_axi_clk.c }, |
| 4895 | { TEST_MM_HS(0x13), &imem_axi_clk.c }, |
| 4896 | { TEST_MM_HS(0x14), &jpegd_axi_clk.c }, |
| 4897 | { TEST_MM_HS(0x15), &mdp_axi_clk.c }, |
| 4898 | { TEST_MM_HS(0x16), &rot_axi_clk.c }, |
| 4899 | { TEST_MM_HS(0x17), &vcodec_axi_clk.c }, |
| 4900 | { TEST_MM_HS(0x18), &vfe_axi_clk.c }, |
| 4901 | { TEST_MM_HS(0x19), &vpe_axi_clk.c }, |
| 4902 | { TEST_MM_HS(0x1A), &mdp_clk.c }, |
| 4903 | { TEST_MM_HS(0x1B), &rot_clk.c }, |
| 4904 | { TEST_MM_HS(0x1C), &vpe_clk.c }, |
| 4905 | { TEST_MM_HS(0x1E), &hdmi_tv_clk.c }, |
| 4906 | { TEST_MM_HS(0x1F), &mdp_tv_clk.c }, |
| 4907 | { TEST_MM_HS(0x24), &csi0_phy_clk.c }, |
| 4908 | { TEST_MM_HS(0x25), &csi1_phy_clk.c }, |
| 4909 | { TEST_MM_HS(0x26), &csi_pix_clk.c }, |
| 4910 | { TEST_MM_HS(0x27), &csi_rdi_clk.c }, |
| 4911 | { TEST_MM_HS(0x28), &lut_mdp_clk.c }, |
| 4912 | { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c }, |
| 4913 | { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c }, |
| 4914 | { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c }, |
| 4915 | { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4916 | { TEST_MM_HS(0x2D), &csi2_clk.c }, |
| 4917 | { TEST_MM_HS(0x2E), &csi2_phy_clk.c }, |
| 4918 | { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c }, |
| 4919 | { TEST_MM_HS(0x30), &csi_pix1_clk.c }, |
| 4920 | { TEST_MM_HS(0x31), &csi_rdi1_clk.c }, |
| 4921 | { TEST_MM_HS(0x32), &csi_rdi2_clk.c }, |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 4922 | { TEST_MM_HS(0x33), &vcap_clk.c }, |
| 4923 | { TEST_MM_HS(0x34), &vcap_npl_clk.c }, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 4924 | { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c }, |
Tianyi Gou | 7747a96 | 2012-02-03 15:03:55 -0800 | [diff] [blame] | 4925 | { TEST_MM_HS(0x35), &vcap_axi_clk.c }, |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 4926 | { TEST_MM_HS(0x36), &rgb_tv_clk.c }, |
| 4927 | { TEST_MM_HS(0x37), &npl_tv_clk.c }, |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 4928 | { TEST_MM_HS(0x38), &gfx3d_axi_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4929 | |
| 4930 | { TEST_LPA(0x0F), &mi2s_bit_clk.c }, |
| 4931 | { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c }, |
| 4932 | { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c }, |
| 4933 | { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c }, |
| 4934 | { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c }, |
| 4935 | { TEST_LPA(0x14), &pcm_clk.c }, |
| 4936 | { TEST_LPA(0x1D), &audio_slimbus_clk.c }, |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4937 | |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4938 | { TEST_LPA_HS(0x00), &q6_func_clk }, |
| 4939 | |
Stephen Boyd | 46fdf0d | 2011-11-22 12:25:09 -0800 | [diff] [blame] | 4940 | { TEST_CPUL2(0x2), &l2_m_clk }, |
| 4941 | { TEST_CPUL2(0x0), &krait0_m_clk }, |
| 4942 | { TEST_CPUL2(0x1), &krait1_m_clk }, |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 4943 | { TEST_CPUL2(0x4), &krait2_m_clk }, |
| 4944 | { TEST_CPUL2(0x5), &krait3_m_clk }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4945 | }; |
| 4946 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4947 | static struct measure_sel *find_measure_sel(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4948 | { |
| 4949 | int i; |
| 4950 | |
| 4951 | for (i = 0; i < ARRAY_SIZE(measure_mux); i++) |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4952 | if (measure_mux[i].c == c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4953 | return &measure_mux[i]; |
| 4954 | return NULL; |
| 4955 | } |
| 4956 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4957 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4958 | { |
| 4959 | int ret = 0; |
| 4960 | u32 clk_sel; |
| 4961 | struct measure_sel *p; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4962 | struct measure_clk *measure = to_measure_clk(c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4963 | unsigned long flags; |
| 4964 | |
| 4965 | if (!parent) |
| 4966 | return -EINVAL; |
| 4967 | |
| 4968 | p = find_measure_sel(parent); |
| 4969 | if (!p) |
| 4970 | return -EINVAL; |
| 4971 | |
| 4972 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4973 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4974 | /* |
| 4975 | * Program the test vector, measurement period (sample_ticks) |
| 4976 | * and scaling multiplier. |
| 4977 | */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4978 | measure->sample_ticks = 0x10000; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4979 | clk_sel = p->test_vector & TEST_CLK_SEL_MASK; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 4980 | measure->multiplier = 1; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4981 | switch (p->test_vector >> TEST_TYPE_SHIFT) { |
| 4982 | case TEST_TYPE_PER_LS: |
| 4983 | writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG); |
| 4984 | break; |
| 4985 | case TEST_TYPE_PER_HS: |
| 4986 | writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG); |
| 4987 | break; |
| 4988 | case TEST_TYPE_MM_LS: |
| 4989 | writel_relaxed(0x4030D97, CLK_TEST_REG); |
| 4990 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG); |
| 4991 | break; |
| 4992 | case TEST_TYPE_MM_HS: |
| 4993 | writel_relaxed(0x402B800, CLK_TEST_REG); |
| 4994 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG); |
| 4995 | break; |
| 4996 | case TEST_TYPE_LPA: |
| 4997 | writel_relaxed(0x4030D98, CLK_TEST_REG); |
| 4998 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), |
| 4999 | LCC_CLK_LS_DEBUG_CFG_REG); |
| 5000 | break; |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 5001 | case TEST_TYPE_LPA_HS: |
| 5002 | writel_relaxed(0x402BC00, CLK_TEST_REG); |
| 5003 | writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0), |
| 5004 | LCC_CLK_HS_DEBUG_CFG_REG); |
| 5005 | break; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5006 | case TEST_TYPE_CPUL2: |
| 5007 | writel_relaxed(0x4030400, CLK_TEST_REG); |
| 5008 | writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG); |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5009 | measure->sample_ticks = 0x4000; |
| 5010 | measure->multiplier = 2; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5011 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5012 | default: |
| 5013 | ret = -EPERM; |
| 5014 | } |
| 5015 | /* Make sure test vector is set before starting measurements. */ |
| 5016 | mb(); |
| 5017 | |
| 5018 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 5019 | |
| 5020 | return ret; |
| 5021 | } |
| 5022 | |
| 5023 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 5024 | static u32 run_measurement(unsigned ticks) |
| 5025 | { |
| 5026 | /* Stop counters and set the XO4 counter start value. */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5027 | writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG); |
| 5028 | |
| 5029 | /* Wait for timer to become ready. */ |
| 5030 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0) |
| 5031 | cpu_relax(); |
| 5032 | |
| 5033 | /* Run measurement and wait for completion. */ |
| 5034 | writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG); |
| 5035 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0) |
| 5036 | cpu_relax(); |
| 5037 | |
| 5038 | /* Stop counters. */ |
| 5039 | writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG); |
| 5040 | |
| 5041 | /* Return measured ticks. */ |
| 5042 | return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0); |
| 5043 | } |
| 5044 | |
| 5045 | |
| 5046 | /* Perform a hardware rate measurement for a given clock. |
| 5047 | FOR DEBUG USE ONLY: Measurements take ~15 ms! */ |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 5048 | static unsigned long measure_clk_get_rate(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5049 | { |
| 5050 | unsigned long flags; |
| 5051 | u32 pdm_reg_backup, ringosc_reg_backup; |
| 5052 | u64 raw_count_short, raw_count_full; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5053 | struct measure_clk *measure = to_measure_clk(c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5054 | unsigned ret; |
| 5055 | |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 5056 | ret = clk_prepare_enable(&cxo_clk.c); |
Stephen Boyd | 3a35f0b | 2012-01-11 16:18:26 -0800 | [diff] [blame] | 5057 | if (ret) { |
| 5058 | pr_warning("CXO clock failed to enable. Can't measure\n"); |
| 5059 | return 0; |
| 5060 | } |
| 5061 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5062 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 5063 | |
| 5064 | /* Enable CXO/4 and RINGOSC branch and root. */ |
| 5065 | pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG); |
| 5066 | ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG); |
| 5067 | writel_relaxed(0x2898, PDM_CLK_NS_REG); |
| 5068 | writel_relaxed(0xA00, RINGOSC_NS_REG); |
| 5069 | |
| 5070 | /* |
| 5071 | * The ring oscillator counter will not reset if the measured clock |
| 5072 | * is not running. To detect this, run a short measurement before |
| 5073 | * the full measurement. If the raw results of the two are the same |
| 5074 | * then the clock must be off. |
| 5075 | */ |
| 5076 | |
| 5077 | /* Run a short measurement. (~1 ms) */ |
| 5078 | raw_count_short = run_measurement(0x1000); |
| 5079 | /* Run a full measurement. (~14 ms) */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5080 | raw_count_full = run_measurement(measure->sample_ticks); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5081 | |
| 5082 | writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG); |
| 5083 | writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG); |
| 5084 | |
| 5085 | /* Return 0 if the clock is off. */ |
| 5086 | if (raw_count_full == raw_count_short) |
| 5087 | ret = 0; |
| 5088 | else { |
| 5089 | /* Compute rate in Hz. */ |
| 5090 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5091 | do_div(raw_count_full, ((measure->sample_ticks * 10) + 35)); |
| 5092 | ret = (raw_count_full * measure->multiplier); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5093 | } |
| 5094 | |
| 5095 | /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */ |
Stephen Boyd | 69da840 | 2011-07-14 17:45:31 -0700 | [diff] [blame] | 5096 | writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5097 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 5098 | |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 5099 | clk_disable_unprepare(&cxo_clk.c); |
Stephen Boyd | 3a35f0b | 2012-01-11 16:18:26 -0800 | [diff] [blame] | 5100 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5101 | return ret; |
| 5102 | } |
| 5103 | #else /* !CONFIG_DEBUG_FS */ |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5104 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5105 | { |
| 5106 | return -EINVAL; |
| 5107 | } |
| 5108 | |
Matt Wagantall | f82f294 | 2012-01-27 13:56:13 -0800 | [diff] [blame] | 5109 | static unsigned long measure_clk_get_rate(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5110 | { |
| 5111 | return 0; |
| 5112 | } |
| 5113 | #endif /* CONFIG_DEBUG_FS */ |
| 5114 | |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 5115 | static struct clk_ops clk_ops_measure = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5116 | .set_parent = measure_clk_set_parent, |
| 5117 | .get_rate = measure_clk_get_rate, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5118 | }; |
| 5119 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5120 | static struct measure_clk measure_clk = { |
| 5121 | .c = { |
| 5122 | .dbg_name = "measure_clk", |
Matt Wagantall | ae05322 | 2012-05-14 19:42:07 -0700 | [diff] [blame] | 5123 | .ops = &clk_ops_measure, |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5124 | CLK_INIT(measure_clk.c), |
| 5125 | }, |
| 5126 | .multiplier = 1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5127 | }; |
| 5128 | |
Tianyi Gou | a8b3cce | 2011-11-08 14:37:26 -0800 | [diff] [blame] | 5129 | static struct clk_lookup msm_clocks_8064[] = { |
Stephen Boyd | 72a8035 | 2012-01-26 15:57:38 -0800 | [diff] [blame] | 5130 | CLK_LOOKUP("xo", cxo_a_clk.c, ""), |
| 5131 | CLK_LOOKUP("xo", pxo_a_clk.c, ""), |
Mohan Pallaka | 804ca59 | 2012-06-14 14:37:38 +0530 | [diff] [blame] | 5132 | CLK_LOOKUP("pwm_clk", cxo_clk.c, "0-0048"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5133 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5134 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5135 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5136 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5137 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 5138 | CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"), |
Stephen Boyd | 69d35e3 | 2012-02-14 15:33:30 -0800 | [diff] [blame] | 5139 | CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"), |
Stephen Boyd | 5a190a8 | 2012-03-01 14:45:15 -0800 | [diff] [blame] | 5140 | CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"), |
David Collins | a7d2353 | 2012-08-02 10:48:16 -0700 | [diff] [blame] | 5141 | CLK_LOOKUP("vref_buff", cxo_clk.c, "rpm-regulator"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5142 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5143 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5144 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5145 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5146 | |
Matt Wagantall | d75f131 | 2012-05-23 16:17:35 -0700 | [diff] [blame] | 5147 | CLK_LOOKUP("bus_clk", afab_clk.c, ""), |
| 5148 | CLK_LOOKUP("bus_clk", afab_a_clk.c, ""), |
| 5149 | CLK_LOOKUP("bus_clk", cfpb_clk.c, ""), |
| 5150 | CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""), |
| 5151 | CLK_LOOKUP("bus_clk", dfab_clk.c, ""), |
| 5152 | CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""), |
| 5153 | CLK_LOOKUP("mem_clk", ebi1_clk.c, ""), |
| 5154 | CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""), |
| 5155 | CLK_LOOKUP("bus_clk", mmfab_clk.c, ""), |
| 5156 | CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""), |
| 5157 | CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""), |
| 5158 | CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""), |
| 5159 | CLK_LOOKUP("bus_clk", sfab_clk.c, ""), |
| 5160 | CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""), |
| 5161 | CLK_LOOKUP("bus_clk", sfpb_clk.c, ""), |
| 5162 | CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""), |
| 5163 | |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5164 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5165 | CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5166 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5167 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5168 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 5169 | CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5170 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5171 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5172 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5173 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5174 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5175 | CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"), |
Gagan Mac | bc5f81d | 2012-04-04 15:03:12 -0600 | [diff] [blame] | 5176 | CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"), |
| 5177 | CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"), |
Pratik Patel | f17b147 | 2012-05-25 22:23:52 -0700 | [diff] [blame] | 5178 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""), |
| 5179 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etb.0"), |
| 5180 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_tpiu.0"), |
| 5181 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_funnel.0"), |
| 5182 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_stm.0"), |
| 5183 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etm.0"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5184 | |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5185 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5186 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""), |
| 5187 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5188 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5189 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5190 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5191 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5192 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5193 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5194 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5195 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5196 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
| 5197 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""), |
| 5198 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5199 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"), |
David Keitel | 3c40fc5 | 2012-02-09 17:53:52 -0800 | [diff] [blame] | 5200 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5201 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
Jing Lin | 04601f9 | 2012-02-05 15:36:07 -0800 | [diff] [blame] | 5202 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5203 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
Stepan Moskovchenko | 6499900 | 2012-01-31 15:52:59 -0800 | [diff] [blame] | 5204 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"), |
Joel King | 8f839b9 | 2012-04-01 14:37:46 -0700 | [diff] [blame] | 5205 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.5"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5206 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5207 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5208 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
Tianyi Gou | 50f2381 | 2012-02-06 16:04:19 -0800 | [diff] [blame] | 5209 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 5210 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
Tianyi Gou | 43208a0 | 2011-09-27 15:35:13 -0700 | [diff] [blame] | 5211 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5212 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5213 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5214 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
Joel Nider | 6cbe66a | 2012-06-26 11:11:59 +0300 | [diff] [blame] | 5215 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"), |
| 5216 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.0"), |
| 5217 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.1"), |
| 5218 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5219 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5220 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5221 | CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"), |
| 5222 | CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5223 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5224 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5225 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5226 | CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""), |
| 5227 | CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""), |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 5228 | CLK_LOOKUP("src_clk", sata_src_clk.c, ""), |
| 5229 | CLK_LOOKUP("core_rxoob_clk", sata_rxoob_clk.c, ""), |
| 5230 | CLK_LOOKUP("core_pmalive_clk", sata_pmalive_clk.c, ""), |
| 5231 | CLK_LOOKUP("bus_clk", sata_a_clk.c, ""), |
| 5232 | CLK_LOOKUP("iface_clk", sata_p_clk.c, ""), |
| 5233 | CLK_LOOKUP("slave_iface_clk", sfab_sata_s_p_clk.c, ""), |
Ramesh Masavarapu | 2831191 | 2011-10-27 11:04:12 -0700 | [diff] [blame] | 5234 | CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"), |
| 5235 | CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"), |
| 5236 | CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"), |
| 5237 | CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"), |
| 5238 | CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"), |
| 5239 | CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5240 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5241 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"), |
David Keitel | 3c40fc5 | 2012-02-09 17:53:52 -0800 | [diff] [blame] | 5242 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5243 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
Jing Lin | 04601f9 | 2012-02-05 15:36:07 -0800 | [diff] [blame] | 5244 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5245 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
Stepan Moskovchenko | 6499900 | 2012-01-31 15:52:59 -0800 | [diff] [blame] | 5246 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"), |
Joel King | 8f839b9 | 2012-04-01 14:37:46 -0700 | [diff] [blame] | 5247 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "qup_i2c.5"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5248 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""), |
Jin Hong | 4bbbfba | 2012-02-02 21:48:07 -0800 | [diff] [blame] | 5249 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"), |
Joel Nider | 6d7d16c | 2012-05-30 18:02:42 +0300 | [diff] [blame] | 5250 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tspp.0"), |
| 5251 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tspp.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5252 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5253 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
Manu Gautam | 7483f17 | 2011-11-08 15:22:26 +0530 | [diff] [blame] | 5254 | CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"), |
| 5255 | CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"), |
Tianyi Gou | 43208a0 | 2011-09-27 15:35:13 -0700 | [diff] [blame] | 5256 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5257 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5258 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5259 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
Niranjana Vishwanathapura | 06f8933 | 2012-05-03 17:11:13 -0600 | [diff] [blame] | 5260 | CLK_LOOKUP("iface_clk", pcie_p_clk.c, "msm_pcie"), |
| 5261 | CLK_LOOKUP("ref_clk", pcie_phy_ref_clk.c, "msm_pcie"), |
| 5262 | CLK_LOOKUP("bus_clk", pcie_a_clk.c, "msm_pcie"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5263 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5264 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5265 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5266 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5267 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5268 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5269 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
Sreesudhan Ramakrish Ramkumar | 3381da7 | 2012-01-27 08:08:32 -0800 | [diff] [blame] | 5270 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"), |
Sreesudhan Ramakrish Ramkumar | 8002a79 | 2012-04-09 17:42:58 -0700 | [diff] [blame] | 5271 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"), |
Sreesudhan Ramakrish Ramkumar | 6c6f57c | 2012-02-21 15:12:44 -0800 | [diff] [blame] | 5272 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5273 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"), |
| 5274 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5275 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
| 5276 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"), |
| 5277 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5278 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
| 5279 | CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"), |
| 5280 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5281 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
| 5282 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"), |
| 5283 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5284 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5285 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
| 5286 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5287 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5288 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5289 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5290 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5291 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
| 5292 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5293 | csiphy_timer_src_clk.c, "msm_csiphy.2"), |
| 5294 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5295 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
| 5296 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5297 | CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"), |
| 5298 | CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"), |
| 5299 | CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"), |
| 5300 | CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"), |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 5301 | CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""), |
| 5302 | CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""), |
| 5303 | |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 5304 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5305 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5306 | CLK_LOOKUP("bus_clk", |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 5307 | gfx3d_axi_clk.c, "footswitch-8x60.2"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5308 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""), |
Terence Hampson | 2e1705f | 2012-04-11 19:55:29 -0400 | [diff] [blame] | 5309 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, "msm_vcap.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5310 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"), |
| 5311 | CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5312 | CLK_LOOKUP("core_clk", vcap_clk.c, ""), |
Terence Hampson | 2e1705f | 2012-04-11 19:55:29 -0400 | [diff] [blame] | 5313 | CLK_LOOKUP("core_clk", vcap_clk.c, "msm_vcap.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5314 | CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5315 | CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""), |
Terence Hampson | 2e1705f | 2012-04-11 19:55:29 -0400 | [diff] [blame] | 5316 | CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, "msm_vcap.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5317 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5318 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"), |
| 5319 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5320 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5321 | CLK_LOOKUP("core_clk", jpegd_clk.c, ""), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5322 | CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5323 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5324 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5325 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5326 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5327 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5328 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5329 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Matt Wagantall | 6128631 | 2012-02-22 15:55:09 -0800 | [diff] [blame] | 5330 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5331 | CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"), |
| 5332 | CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""), |
Greg Grisco | fa47b53 | 2011-11-11 10:32:06 -0800 | [diff] [blame] | 5333 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5334 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5335 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"), |
Tianyi Gou | 5191880 | 2012-01-26 14:05:43 -0800 | [diff] [blame] | 5336 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5337 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"), |
Aravind Venkateswaran | 0507c8c | 2012-02-16 17:16:05 -0800 | [diff] [blame] | 5338 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
Ujwal Patel | d041f98 | 2012-03-27 19:51:44 -0700 | [diff] [blame] | 5339 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5340 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5341 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5342 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5343 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5344 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5345 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5346 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5347 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5348 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5349 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5350 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5351 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"), |
| 5352 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5353 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 5354 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
| 5355 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5356 | CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"), |
| 5357 | CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"), |
| 5358 | CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"), |
| 5359 | CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"), |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 5360 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5361 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
Aravind Venkateswaran | 0507c8c | 2012-02-16 17:16:05 -0800 | [diff] [blame] | 5362 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 5363 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5364 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5365 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5366 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""), |
Matt Wagantall | 5d44ef2 | 2012-01-23 11:01:05 -0800 | [diff] [blame] | 5367 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5368 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5369 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame] | 5370 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5371 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5372 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
Greg Grisco | fa47b53 | 2011-11-11 10:32:06 -0800 | [diff] [blame] | 5373 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5374 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
Kevin Chan | d07220e | 2012-02-13 15:52:22 -0800 | [diff] [blame] | 5375 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5376 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
Kevin Chan | b20742b | 2012-02-27 15:47:35 -0800 | [diff] [blame] | 5377 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
Matt Wagantall | 6128631 | 2012-02-22 15:55:09 -0800 | [diff] [blame] | 5378 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5379 | |
Patrick Lai | 04baee94 | 2012-05-01 14:38:47 -0700 | [diff] [blame] | 5380 | CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, |
| 5381 | "msm-dai-q6-mi2s"), |
| 5382 | CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, |
| 5383 | "msm-dai-q6-mi2s"), |
Kuirong Wang | a9c3acc | 2012-02-09 17:00:45 -0800 | [diff] [blame] | 5384 | CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c, |
| 5385 | "msm-dai-q6.1"), |
| 5386 | CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c, |
| 5387 | "msm-dai-q6.1"), |
| 5388 | CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c, |
| 5389 | "msm-dai-q6.5"), |
| 5390 | CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c, |
| 5391 | "msm-dai-q6.5"), |
| 5392 | CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c, |
| 5393 | "msm-dai-q6.16384"), |
| 5394 | CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c, |
| 5395 | "msm-dai-q6.16384"), |
| 5396 | CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c, |
| 5397 | "msm-dai-q6.4"), |
| 5398 | CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c, |
| 5399 | "msm-dai-q6.4"), |
| 5400 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"), |
Kiran Kandi | 5f4ab69 | 2012-02-23 11:23:56 -0800 | [diff] [blame] | 5401 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5402 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""), |
Tianyi Gou | 44a81b0 | 2012-02-06 17:49:07 -0800 | [diff] [blame] | 5403 | CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5404 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""), |
| 5405 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""), |
| 5406 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""), |
| 5407 | CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""), |
| 5408 | CLK_LOOKUP("core_clk", rot_axi_clk.c, ""), |
| 5409 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""), |
| 5410 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""), |
| 5411 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""), |
| 5412 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""), |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 5413 | CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, ""), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5414 | |
| 5415 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
| 5416 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
| 5417 | CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"), |
| 5418 | CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"), |
| 5419 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 5420 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 5421 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 5422 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 5423 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
| 5424 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
| 5425 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
Ramesh Masavarapu | a1bc0e4 | 2012-03-05 07:42:48 -0800 | [diff] [blame] | 5426 | CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"), |
Tianyi Gou | 21a0e80 | 2012-02-04 22:34:10 -0800 | [diff] [blame] | 5427 | |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5428 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5429 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5430 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5431 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5432 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5433 | |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame] | 5434 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"), |
| 5435 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5436 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5437 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5438 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5439 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5440 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5441 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5442 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 5443 | CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.9"), |
| 5444 | CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"), |
| 5445 | |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame] | 5446 | CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"), |
| 5447 | |
Deepak Kotur | 954b178 | 2012-04-24 17:58:19 -0700 | [diff] [blame] | 5448 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 5449 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 5450 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 5451 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 5452 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
Stephen Boyd | 7b973de | 2012-03-09 12:26:16 -0800 | [diff] [blame] | 5453 | CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"), |
| 5454 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"), |
| 5455 | |
Jeff Ohlstein | 8c116c7 | 2011-10-27 17:34:48 -0700 | [diff] [blame] | 5456 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5457 | CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""), |
| 5458 | CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5459 | |
Matt Wagantall | c33c1ed | 2012-07-23 17:19:08 -0700 | [diff] [blame] | 5460 | CLK_LOOKUP("reset1_clk", dsi1_reset_clk.c, "footswitch-8x60.4"), |
| 5461 | CLK_LOOKUP("reset2_clk", dsi2_reset_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | 735e41b | 2012-07-23 17:18:58 -0700 | [diff] [blame] | 5462 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5463 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5464 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5465 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 5466 | CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""), |
| 5467 | CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5468 | }; |
| 5469 | |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 5470 | static struct clk_lookup msm_clocks_8960_common[] __initdata = { |
Stephen Boyd | 72a8035 | 2012-01-26 15:57:38 -0800 | [diff] [blame] | 5471 | CLK_LOOKUP("xo", cxo_a_clk.c, ""), |
| 5472 | CLK_LOOKUP("xo", pxo_a_clk.c, ""), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5473 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5474 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5475 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5476 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5477 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
Stephen Boyd | 69d35e3 | 2012-02-14 15:33:30 -0800 | [diff] [blame] | 5478 | CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"), |
Stephen Boyd | 5a190a8 | 2012-03-01 14:45:15 -0800 | [diff] [blame] | 5479 | CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"), |
David Collins | a7d2353 | 2012-08-02 10:48:16 -0700 | [diff] [blame] | 5480 | CLK_LOOKUP("vref_buff", cxo_clk.c, "rpm-regulator"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5481 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5482 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5483 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5484 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5485 | |
Matt Wagantall | d75f131 | 2012-05-23 16:17:35 -0700 | [diff] [blame] | 5486 | CLK_LOOKUP("bus_clk", afab_clk.c, ""), |
| 5487 | CLK_LOOKUP("bus_clk", afab_a_clk.c, ""), |
| 5488 | CLK_LOOKUP("bus_clk", cfpb_clk.c, ""), |
| 5489 | CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""), |
| 5490 | CLK_LOOKUP("bus_clk", dfab_clk.c, ""), |
| 5491 | CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""), |
| 5492 | CLK_LOOKUP("mem_clk", ebi1_clk.c, ""), |
| 5493 | CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""), |
| 5494 | CLK_LOOKUP("bus_clk", mmfab_clk.c, ""), |
| 5495 | CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""), |
| 5496 | CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""), |
| 5497 | CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""), |
| 5498 | CLK_LOOKUP("bus_clk", sfab_clk.c, ""), |
| 5499 | CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""), |
| 5500 | CLK_LOOKUP("bus_clk", sfpb_clk.c, ""), |
| 5501 | CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""), |
| 5502 | |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5503 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5504 | CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5505 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5506 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5507 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 5508 | CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5509 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5510 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5511 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5512 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5513 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5514 | CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"), |
Gagan Mac | bc5f81d | 2012-04-04 15:03:12 -0600 | [diff] [blame] | 5515 | CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"), |
| 5516 | CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"), |
Pratik Patel | f17b147 | 2012-05-25 22:23:52 -0700 | [diff] [blame] | 5517 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""), |
| 5518 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etb.0"), |
| 5519 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_tpiu.0"), |
| 5520 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_funnel.0"), |
| 5521 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_stm.0"), |
| 5522 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etm.0"), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5523 | |
| 5524 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5525 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL), |
| 5526 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5527 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5528 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5529 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5530 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5531 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
| 5532 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""), |
| 5533 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5534 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5535 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 5536 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"), |
| 5537 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5538 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), |
Mayank Rana | 1f02d95 | 2012-07-04 19:11:20 +0530 | [diff] [blame] | 5539 | /* used on 8960 SGLTE for console */ |
Stepan Moskovchenko | 2b4b1cd | 2012-03-29 18:21:04 -0700 | [diff] [blame] | 5540 | CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"), |
Mayank Rana | 1f02d95 | 2012-07-04 19:11:20 +0530 | [diff] [blame] | 5541 | /* used on 8960 standalone with Atheros Bluetooth */ |
| 5542 | CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hs.2"), |
Mayank Rana | e009c92 | 2012-03-22 03:02:06 +0530 | [diff] [blame] | 5543 | CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5544 | CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""), |
| 5545 | CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""), |
| 5546 | CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5547 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5548 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5549 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
| 5550 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5551 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""), |
| 5552 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5553 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5554 | CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5555 | CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5556 | CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5557 | CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5558 | CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5559 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
Vikram Mulukutla | dd0a237 | 2011-09-19 15:58:21 -0700 | [diff] [blame] | 5560 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
Matt Wagantall | c120529 | 2011-08-11 17:19:31 -0700 | [diff] [blame] | 5561 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5562 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5563 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5564 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5565 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
| 5566 | CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5567 | CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5568 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5569 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5570 | CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5571 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5572 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
| 5573 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5574 | CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""), |
| 5575 | CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""), |
| 5576 | CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5577 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5578 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5579 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5580 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5581 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 5582 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"), |
Matt Wagantall | e0b1145 | 2011-09-13 17:25:33 -0700 | [diff] [blame] | 5583 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 5584 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"), |
Matt Wagantall | e0b1145 | 2011-09-13 17:25:33 -0700 | [diff] [blame] | 5585 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5586 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5587 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5588 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5589 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
| 5590 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 5591 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"), |
| 5592 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5593 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""), |
Mayank Rana | 1f02d95 | 2012-07-04 19:11:20 +0530 | [diff] [blame] | 5594 | /* used on 8960 SGLTE for serial console */ |
Stepan Moskovchenko | 2b4b1cd | 2012-03-29 18:21:04 -0700 | [diff] [blame] | 5595 | CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"), |
Mayank Rana | 1f02d95 | 2012-07-04 19:11:20 +0530 | [diff] [blame] | 5596 | /* used on 8960 standalone with Atheros Bluetooth */ |
| 5597 | CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hs.2"), |
Mayank Rana | e009c92 | 2012-03-22 03:02:06 +0530 | [diff] [blame] | 5598 | CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5599 | CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5600 | CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5601 | CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5602 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
Joel Nider | 6d7d16c | 2012-05-30 18:02:42 +0300 | [diff] [blame] | 5603 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tspp.0"), |
| 5604 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tspp.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5605 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
| 5606 | CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5607 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5608 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5609 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5610 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5611 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
| 5612 | CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"), |
Matt Wagantall | e1a8606 | 2011-08-18 17:46:10 -0700 | [diff] [blame] | 5613 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5614 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5615 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5616 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5617 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5618 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
Kevin Chan | 09f4e66 | 2011-12-16 08:17:02 -0800 | [diff] [blame] | 5619 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
| 5620 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"), |
| 5621 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5622 | CLK_LOOKUP("cam_clk", cam2_clk.c, NULL), |
Sreesudhan Ramakrish Ramkumar | 8f11b8b | 2012-01-04 17:09:05 -0800 | [diff] [blame] | 5623 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"), |
Sreesudhan Ramakrish Ramkumar | 3381da7 | 2012-01-27 08:08:32 -0800 | [diff] [blame] | 5624 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5625 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5626 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5627 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5628 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5629 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5630 | CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5631 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5632 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5633 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"), |
Kevin Chan | e12c667 | 2011-10-26 11:55:26 -0700 | [diff] [blame] | 5634 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5635 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5636 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL), |
| 5637 | CLK_LOOKUP("csi_clk", csi2_clk.c, NULL), |
| 5638 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5639 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5640 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5641 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL), |
| 5642 | CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL), |
Kevin Chan | f6216f2 | 2011-10-25 18:40:11 -0700 | [diff] [blame] | 5643 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5644 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5645 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5646 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5647 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5648 | csiphy_timer_src_clk.c, "msm_csiphy.2"), |
Kevin Chan | f6216f2 | 2011-10-25 18:40:11 -0700 | [diff] [blame] | 5649 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5650 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5651 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5652 | CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"), |
| 5653 | CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"), |
| 5654 | CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"), |
| 5655 | CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5656 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5657 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
| 5658 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5659 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"), |
| 5660 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5661 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Kalyani Oruganti | 465d1e1 | 2012-05-15 10:23:05 -0700 | [diff] [blame] | 5662 | CLK_LOOKUP("core_clk", jpegd_clk.c, "msm_mercury.0"), |
| 5663 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, "msm_mercury.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5664 | CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5665 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5666 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5667 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5668 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5669 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5670 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5671 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5672 | CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"), |
| 5673 | CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5674 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | 3f7660b | 2011-08-17 21:25:13 -0700 | [diff] [blame] | 5675 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5676 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5677 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"), |
| 5678 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5679 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5680 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 5681 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
Kevin Chan | a085312 | 2011-11-07 19:48:44 -0800 | [diff] [blame] | 5682 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5683 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5684 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5685 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5686 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5687 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5688 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5689 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5690 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5691 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5692 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5693 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5694 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"), |
| 5695 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5696 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 5697 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
Sreesudhan Ramakrish Ramkumar | b1edcd0 | 2012-01-17 11:33:05 -0800 | [diff] [blame] | 5698 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5699 | CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"), |
| 5700 | CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"), |
| 5701 | CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"), |
| 5702 | CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5703 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5704 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 5705 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 5706 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5707 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5708 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5709 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""), |
Matt Wagantall | 5d44ef2 | 2012-01-23 11:01:05 -0800 | [diff] [blame] | 5710 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5711 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5712 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 5713 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5714 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5715 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
Matt Wagantall | 3f7660b | 2011-08-17 21:25:13 -0700 | [diff] [blame] | 5716 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5717 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5718 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5719 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
Kevin Chan | a085312 | 2011-11-07 19:48:44 -0800 | [diff] [blame] | 5720 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5721 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
Patrick Lai | 04baee94 | 2012-05-01 14:38:47 -0700 | [diff] [blame] | 5722 | CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, |
| 5723 | "msm-dai-q6-mi2s"), |
| 5724 | CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, |
| 5725 | "msm-dai-q6-mi2s"), |
Kuirong Wang | a9c3acc | 2012-02-09 17:00:45 -0800 | [diff] [blame] | 5726 | CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c, |
| 5727 | "msm-dai-q6.1"), |
| 5728 | CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c, |
| 5729 | "msm-dai-q6.1"), |
| 5730 | CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c, |
| 5731 | "msm-dai-q6.5"), |
| 5732 | CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c, |
| 5733 | "msm-dai-q6.5"), |
| 5734 | CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c, |
| 5735 | "msm-dai-q6.16384"), |
| 5736 | CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c, |
| 5737 | "msm-dai-q6.16384"), |
| 5738 | CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c, |
| 5739 | "msm-dai-q6.4"), |
| 5740 | CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c, |
| 5741 | "msm-dai-q6.4"), |
| 5742 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"), |
Kiran Kandi | 5f4ab69 | 2012-02-23 11:23:56 -0800 | [diff] [blame] | 5743 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5744 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL), |
Tianyi Gou | 44a81b0 | 2012-02-06 17:49:07 -0800 | [diff] [blame] | 5745 | CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 5746 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"), |
| 5747 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5748 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5749 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5750 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5751 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5752 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5753 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5754 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
| 5755 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"), |
Gopikrishnaiah Anandan | 4d05ed3 | 2012-01-13 11:08:44 -0800 | [diff] [blame] | 5756 | |
| 5757 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 5758 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 5759 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 5760 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 5761 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
Stephen Boyd | 7b973de | 2012-03-09 12:26:16 -0800 | [diff] [blame] | 5762 | CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"), |
| 5763 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"), |
Gopikrishnaiah Anandan | 4d05ed3 | 2012-01-13 11:08:44 -0800 | [diff] [blame] | 5764 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5765 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5766 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5767 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 5768 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 5769 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 5770 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 5771 | CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"), |
Yan He | 160633e | 2011-06-30 12:18:56 -0700 | [diff] [blame] | 5772 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
Stephen Boyd | 1c51a49 | 2011-10-26 12:11:47 -0700 | [diff] [blame] | 5773 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
Stephen Boyd | ef5d1c4 | 2011-12-15 20:47:14 -0800 | [diff] [blame] | 5774 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
Ramesh Masavarapu | a1bc0e4 | 2012-03-05 07:42:48 -0800 | [diff] [blame] | 5775 | CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5776 | |
Matt Wagantall | e1a8606 | 2011-08-18 17:46:10 -0700 | [diff] [blame] | 5777 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5778 | CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""), |
| 5779 | CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""), |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5780 | |
Matt Wagantall | c33c1ed | 2012-07-23 17:19:08 -0700 | [diff] [blame] | 5781 | CLK_LOOKUP("reset1_clk", dsi1_reset_clk.c, "footswitch-8x60.4"), |
| 5782 | CLK_LOOKUP("reset2_clk", dsi2_reset_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | 735e41b | 2012-07-23 17:18:58 -0700 | [diff] [blame] | 5783 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5784 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5785 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5786 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
| 5787 | CLK_LOOKUP("q6sw_clk", q6sw_clk, ""), |
| 5788 | CLK_LOOKUP("q6fw_clk", q6fw_clk, ""), |
| 5789 | CLK_LOOKUP("q6_func_clk", q6_func_clk, ""), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5790 | }; |
| 5791 | |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 5792 | static struct clk_lookup msm_clocks_8960_only[] __initdata = { |
| 5793 | CLK_LOOKUP("enc_clk", tv_enc_clk.c, "tvenc.0"), |
| 5794 | CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"), |
| 5795 | CLK_LOOKUP("iface_clk", tv_enc_p_clk.c, "tvenc.0"), |
| 5796 | |
| 5797 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"), |
| 5798 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"), |
| 5799 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"), |
| 5800 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"), |
| 5801 | CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"), |
| 5802 | CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"), |
| 5803 | CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"), |
| 5804 | CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"), |
| 5805 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"), |
| 5806 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"), |
| 5807 | }; |
| 5808 | |
| 5809 | static struct clk_lookup msm_clocks_8960ab_only[] __initdata = { |
| 5810 | CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"), |
| 5811 | CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""), |
| 5812 | }; |
| 5813 | |
| 5814 | static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_common) |
| 5815 | + ARRAY_SIZE(msm_clocks_8960_only) |
| 5816 | + ARRAY_SIZE(msm_clocks_8960ab_only)]; |
| 5817 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5818 | static struct clk_lookup msm_clocks_8930[] = { |
Stephen Boyd | be1a739 | 2012-04-02 20:17:11 -0700 | [diff] [blame] | 5819 | CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5820 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5821 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5822 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5823 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5824 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
| 5825 | CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"), |
David Collins | a7d2353 | 2012-08-02 10:48:16 -0700 | [diff] [blame] | 5826 | CLK_LOOKUP("vref_buff", cxo_clk.c, "rpm-regulator"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5827 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5828 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5829 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5830 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
| 5831 | |
Matt Wagantall | d75f131 | 2012-05-23 16:17:35 -0700 | [diff] [blame] | 5832 | CLK_LOOKUP("bus_clk", afab_clk.c, ""), |
| 5833 | CLK_LOOKUP("bus_clk", afab_a_clk.c, ""), |
| 5834 | CLK_LOOKUP("bus_clk", cfpb_clk.c, ""), |
| 5835 | CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""), |
| 5836 | CLK_LOOKUP("bus_clk", dfab_clk.c, ""), |
| 5837 | CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""), |
| 5838 | CLK_LOOKUP("mem_clk", ebi1_clk.c, ""), |
| 5839 | CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""), |
| 5840 | CLK_LOOKUP("bus_clk", mmfab_clk.c, ""), |
| 5841 | CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""), |
| 5842 | CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""), |
| 5843 | CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""), |
| 5844 | CLK_LOOKUP("bus_clk", sfab_clk.c, ""), |
| 5845 | CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""), |
| 5846 | CLK_LOOKUP("bus_clk", sfpb_clk.c, ""), |
| 5847 | CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""), |
| 5848 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5849 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5850 | CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5851 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5852 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5853 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
| 5854 | CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"), |
| 5855 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5856 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5857 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5858 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5859 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 5860 | CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"), |
Gagan Mac | bc5f81d | 2012-04-04 15:03:12 -0600 | [diff] [blame] | 5861 | CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"), |
| 5862 | CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"), |
Pratik Patel | f17b147 | 2012-05-25 22:23:52 -0700 | [diff] [blame] | 5863 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""), |
| 5864 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etb.0"), |
| 5865 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_tpiu.0"), |
| 5866 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_funnel.0"), |
| 5867 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_stm.0"), |
| 5868 | CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etm.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5869 | |
| 5870 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5871 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL), |
| 5872 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5873 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
| 5874 | |
| 5875 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5876 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5877 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
| 5878 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""), |
| 5879 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5880 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5881 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
| 5882 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"), |
| 5883 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"), |
| 5884 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), |
| 5885 | CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""), |
| 5886 | CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""), |
| 5887 | CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""), |
| 5888 | CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""), |
| 5889 | CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""), |
| 5890 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"), |
| 5891 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
| 5892 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
| 5893 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
| 5894 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""), |
| 5895 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5896 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5897 | CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""), |
| 5898 | CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"), |
| 5899 | CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"), |
| 5900 | CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""), |
| 5901 | CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"), |
| 5902 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
| 5903 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
| 5904 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
| 5905 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5906 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5907 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5908 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
| 5909 | CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"), |
| 5910 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""), |
| 5911 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
| 5912 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5913 | CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"), |
| 5914 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5915 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
| 5916 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5917 | CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""), |
| 5918 | CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""), |
| 5919 | CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""), |
| 5920 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5921 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5922 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5923 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5924 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
| 5925 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"), |
| 5926 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"), |
| 5927 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"), |
| 5928 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"), |
| 5929 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
| 5930 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"), |
| 5931 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
| 5932 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
| 5933 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
| 5934 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"), |
| 5935 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"), |
| 5936 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""), |
| 5937 | CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""), |
| 5938 | CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"), |
| 5939 | CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"), |
| 5940 | CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""), |
| 5941 | CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"), |
| 5942 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
| 5943 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
| 5944 | CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""), |
| 5945 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
| 5946 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5947 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5948 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5949 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
| 5950 | CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"), |
| 5951 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5952 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
| 5953 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5954 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5955 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5956 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5957 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
Hody Hung | 994f462 | 2012-04-24 10:27:45 -0700 | [diff] [blame] | 5958 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"), |
Sreesudhan Ramakrish Ramkumar | 981c82c | 2012-04-30 17:31:37 -0700 | [diff] [blame] | 5959 | CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5960 | CLK_LOOKUP("cam_clk", cam2_clk.c, NULL), |
| 5961 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"), |
| 5962 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5963 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
| 5964 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"), |
| 5965 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5966 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
| 5967 | CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"), |
| 5968 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5969 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
| 5970 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"), |
| 5971 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5972 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
| 5973 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL), |
| 5974 | CLK_LOOKUP("csi_clk", csi2_clk.c, NULL), |
| 5975 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5976 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5977 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5978 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL), |
| 5979 | CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL), |
| 5980 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5981 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5982 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5983 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
| 5984 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5985 | csiphy_timer_src_clk.c, "msm_csiphy.2"), |
| 5986 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5987 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
| 5988 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5989 | CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"), |
| 5990 | CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5991 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
| 5992 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
| 5993 | CLK_LOOKUP("bus_clk", |
| 5994 | gfx3d_axi_clk_8930.c, "footswitch-8x60.2"), |
| 5995 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 5996 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"), |
| 5997 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 5998 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 5999 | CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6000 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6001 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6002 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6003 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6004 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
| 6005 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
| 6006 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6007 | CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"), |
| 6008 | CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6009 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6010 | CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6011 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
| 6012 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6013 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"), |
| 6014 | CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6015 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6016 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6017 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
| 6018 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
| 6019 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
| 6020 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
| 6021 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
| 6022 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
| 6023 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 6024 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 6025 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 6026 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 6027 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 6028 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 6029 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6030 | CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6031 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 6032 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
| 6033 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6034 | CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"), |
| 6035 | CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6036 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
| 6037 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
| 6038 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 6039 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Matt Wagantall | f45cd36 | 2012-05-03 21:09:44 -0700 | [diff] [blame] | 6040 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6041 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
| 6042 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Ravishangar Kalyanam | 1b064f5 | 2012-03-15 18:17:54 -0700 | [diff] [blame] | 6043 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6044 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
| 6045 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
| 6046 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
| 6047 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
| 6048 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
| 6049 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
| 6050 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
| 6051 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
| 6052 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
| 6053 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
| 6054 | CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"), |
| 6055 | CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"), |
| 6056 | CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c, |
| 6057 | "msm-dai-q6.1"), |
| 6058 | CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c, |
| 6059 | "msm-dai-q6.1"), |
| 6060 | CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c, |
| 6061 | "msm-dai-q6.5"), |
| 6062 | CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c, |
| 6063 | "msm-dai-q6.5"), |
| 6064 | CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c, |
| 6065 | "msm-dai-q6.16384"), |
| 6066 | CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c, |
| 6067 | "msm-dai-q6.16384"), |
| 6068 | CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c, |
| 6069 | "msm-dai-q6.4"), |
| 6070 | CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c, |
| 6071 | "msm-dai-q6.4"), |
| 6072 | CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"), |
| 6073 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL), |
| 6074 | CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"), |
| 6075 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 6076 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 6077 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 6078 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 6079 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 6080 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 6081 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 6082 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
| 6083 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"), |
| 6084 | CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"), |
| 6085 | |
| 6086 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 6087 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 6088 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 6089 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 6090 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
Stephen Boyd | 7b973de | 2012-03-09 12:26:16 -0800 | [diff] [blame] | 6091 | CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"), |
| 6092 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6093 | |
| 6094 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
| 6095 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
| 6096 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 6097 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 6098 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 6099 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 6100 | CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"), |
| 6101 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
| 6102 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
| 6103 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
| 6104 | CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"), |
| 6105 | |
| 6106 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 33bac7e | 2012-05-22 14:59:05 -0700 | [diff] [blame] | 6107 | CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""), |
| 6108 | CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""), |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6109 | |
Matt Wagantall | c33c1ed | 2012-07-23 17:19:08 -0700 | [diff] [blame] | 6110 | CLK_LOOKUP("reset1_clk", dsi1_reset_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | 735e41b | 2012-07-23 17:18:58 -0700 | [diff] [blame] | 6111 | |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6112 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 6113 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 6114 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
| 6115 | CLK_LOOKUP("q6sw_clk", q6sw_clk, ""), |
| 6116 | CLK_LOOKUP("q6fw_clk", q6fw_clk, ""), |
| 6117 | CLK_LOOKUP("q6_func_clk", q6_func_clk, ""), |
| 6118 | }; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6119 | /* |
| 6120 | * Miscellaneous clock register initializations |
| 6121 | */ |
| 6122 | |
| 6123 | /* Read, modify, then write-back a register. */ |
| 6124 | static void __init rmwreg(uint32_t val, void *reg, uint32_t mask) |
| 6125 | { |
| 6126 | uint32_t regval = readl_relaxed(reg); |
| 6127 | regval &= ~mask; |
| 6128 | regval |= val; |
| 6129 | writel_relaxed(regval, reg); |
| 6130 | } |
| 6131 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6132 | static struct pll_config_regs pll4_regs __initdata = { |
| 6133 | .l_reg = LCC_PLL0_L_VAL_REG, |
| 6134 | .m_reg = LCC_PLL0_M_VAL_REG, |
| 6135 | .n_reg = LCC_PLL0_N_VAL_REG, |
| 6136 | .config_reg = LCC_PLL0_CONFIG_REG, |
| 6137 | .mode_reg = LCC_PLL0_MODE_REG, |
| 6138 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6139 | |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 6140 | static struct pll_config pll4_config_393 __initdata = { |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6141 | .l = 0xE, |
| 6142 | .m = 0x27A, |
| 6143 | .n = 0x465, |
| 6144 | .vco_val = 0x0, |
| 6145 | .vco_mask = BM(17, 16), |
| 6146 | .pre_div_val = 0x0, |
| 6147 | .pre_div_mask = BIT(19), |
| 6148 | .post_div_val = 0x0, |
| 6149 | .post_div_mask = BM(21, 20), |
| 6150 | .mn_ena_val = BIT(22), |
| 6151 | .mn_ena_mask = BIT(22), |
| 6152 | .main_output_val = BIT(23), |
| 6153 | .main_output_mask = BIT(23), |
| 6154 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6155 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6156 | static struct pll_config_regs pll15_regs __initdata = { |
| 6157 | .l_reg = MM_PLL3_L_VAL_REG, |
| 6158 | .m_reg = MM_PLL3_M_VAL_REG, |
| 6159 | .n_reg = MM_PLL3_N_VAL_REG, |
| 6160 | .config_reg = MM_PLL3_CONFIG_REG, |
| 6161 | .mode_reg = MM_PLL3_MODE_REG, |
| 6162 | }; |
Tianyi Gou | 358c386 | 2011-10-18 17:03:41 -0700 | [diff] [blame] | 6163 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6164 | static struct pll_config pll15_config __initdata = { |
| 6165 | .l = (0x24 | BVAL(31, 7, 0x620)), |
| 6166 | .m = 0x1, |
| 6167 | .n = 0x9, |
| 6168 | .vco_val = BVAL(17, 16, 0x2), |
| 6169 | .vco_mask = BM(17, 16), |
| 6170 | .pre_div_val = 0x0, |
| 6171 | .pre_div_mask = BIT(19), |
| 6172 | .post_div_val = 0x0, |
| 6173 | .post_div_mask = BM(21, 20), |
| 6174 | .mn_ena_val = BIT(22), |
| 6175 | .mn_ena_mask = BIT(22), |
| 6176 | .main_output_val = BIT(23), |
| 6177 | .main_output_mask = BIT(23), |
| 6178 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6179 | |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6180 | static struct pll_config_regs pll14_regs __initdata = { |
| 6181 | .l_reg = BB_PLL14_L_VAL_REG, |
| 6182 | .m_reg = BB_PLL14_M_VAL_REG, |
| 6183 | .n_reg = BB_PLL14_N_VAL_REG, |
| 6184 | .config_reg = BB_PLL14_CONFIG_REG, |
| 6185 | .mode_reg = BB_PLL14_MODE_REG, |
| 6186 | }; |
| 6187 | |
| 6188 | static struct pll_config pll14_config __initdata = { |
| 6189 | .l = (0x11 | BVAL(31, 7, 0x620)), |
| 6190 | .m = 0x7, |
| 6191 | .n = 0x9, |
| 6192 | .vco_val = 0x0, |
| 6193 | .vco_mask = BM(17, 16), |
| 6194 | .pre_div_val = 0x0, |
| 6195 | .pre_div_mask = BIT(19), |
| 6196 | .post_div_val = 0x0, |
| 6197 | .post_div_mask = BM(21, 20), |
| 6198 | .mn_ena_val = BIT(22), |
| 6199 | .mn_ena_mask = BIT(22), |
| 6200 | .main_output_val = BIT(23), |
| 6201 | .main_output_mask = BIT(23), |
| 6202 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6203 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6204 | static void __init reg_init(void) |
| 6205 | { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6206 | void __iomem *imem_reg; |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6207 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6208 | /* Deassert MM SW_RESET_ALL signal. */ |
| 6209 | writel_relaxed(0, SW_RESET_ALL_REG); |
| 6210 | |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6211 | /* |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6212 | * Some bits are only used on 8960 or 8064 or 8930 and are marked as |
| 6213 | * reserved bits on the other SoCs. Writing to these reserved bits |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6214 | * should have no effect. |
| 6215 | */ |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6216 | /* |
| 6217 | * Initialize MM AHB registers: Enable the FPB clock and disable HW |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6218 | * gating on 8627 and 8960 for all clocks. Also set VFE_AHB's |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6219 | * FORCE_CORE_ON bit to prevent its memory from being collapsed when |
| 6220 | * the clock is halted. The sleep and wake-up delays are set to safe |
| 6221 | * values. |
| 6222 | */ |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6223 | if (cpu_is_msm8627() || cpu_is_msm8960ab()) { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6224 | rmwreg(0x00000003, AHB_EN_REG, 0x6C000103); |
| 6225 | writel_relaxed(0x000007F9, AHB_EN2_REG); |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6226 | } else { |
| 6227 | rmwreg(0x44000000, AHB_EN_REG, 0x6C000103); |
| 6228 | writel_relaxed(0x3C7097F9, AHB_EN2_REG); |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6229 | } |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6230 | |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6231 | if (cpu_is_apq8064()) |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6232 | rmwreg(0x00000001, AHB_EN3_REG, 0x00000001); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6233 | |
| 6234 | /* Deassert all locally-owned MM AHB resets. */ |
| 6235 | rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6236 | rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6237 | |
| 6238 | /* Initialize MM AXI registers: Enable HW gating for all clocks that |
| 6239 | * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up |
| 6240 | * delays to safe values. */ |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6241 | if (cpu_is_msm8960ab() || (cpu_is_msm8960() && |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6242 | SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 3) || |
| 6243 | cpu_is_msm8627()) { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6244 | rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF); |
| 6245 | rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF); |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6246 | } else { |
| 6247 | rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF); |
| 6248 | rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF); |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6249 | } |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6250 | |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6251 | rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF); |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6252 | rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF); |
| 6253 | |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6254 | if (cpu_is_apq8064()) |
Tianyi Gou | f3095ea | 2012-05-22 14:16:06 -0700 | [diff] [blame] | 6255 | rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF); |
Stepan Moskovchenko | 0df9bb2 | 2012-07-06 18:19:15 -0700 | [diff] [blame] | 6256 | if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6257 | rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF); |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6258 | if (cpu_is_msm8960ab()) |
| 6259 | rmwreg(0x009FE000, MAXI_EN5_REG, 0x01FFE000); |
| 6260 | |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6261 | if (cpu_is_msm8627()) |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6262 | rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF); |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6263 | else if (cpu_is_msm8960ab()) |
| 6264 | rmwreg(0x000001C6, SAXI_EN_REG, 0x00001DF6); |
Tianyi Gou | 33caa5d | 2012-06-18 12:04:11 -0700 | [diff] [blame] | 6265 | else |
| 6266 | rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF); |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 6267 | |
| 6268 | /* Enable IMEM's clk_on signal */ |
| 6269 | imem_reg = ioremap(0x04b00040, 4); |
| 6270 | if (imem_reg) { |
| 6271 | writel_relaxed(0x3, imem_reg); |
| 6272 | iounmap(imem_reg); |
| 6273 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6274 | |
| 6275 | /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core |
| 6276 | * memories retain state even when not clocked. Also, set sleep and |
| 6277 | * wake-up delays to safe values. */ |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6278 | rmwreg(0x00000000, CSI0_CC_REG, 0x00000410); |
| 6279 | rmwreg(0x00000000, CSI1_CC_REG, 0x00000410); |
| 6280 | rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6281 | rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010); |
Tarun Karra | 6fbc00a | 2011-12-13 09:23:47 -0700 | [diff] [blame] | 6282 | rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6283 | rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6284 | rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010); |
| 6285 | rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010); |
| 6286 | rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6287 | rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF); |
| 6288 | rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010); |
| 6289 | rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010); |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 6290 | rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 6291 | rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010); |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6292 | if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()) { |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6293 | rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010); |
| 6294 | rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010); |
| 6295 | rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010); |
| 6296 | } |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6297 | if (cpu_is_msm8960ab()) |
| 6298 | rmwreg(0x00000001, DSI2_PIXEL_CC2_REG, 0x00000001); |
| 6299 | |
Stepan Moskovchenko | 0df9bb2 | 2012-07-06 18:19:15 -0700 | [diff] [blame] | 6300 | if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() || |
| 6301 | cpu_is_msm8627()) |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6302 | rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010); |
| 6303 | if (cpu_is_msm8960ab()) |
| 6304 | rmwreg(0x00000000, TV_CC_REG, 0x00004010); |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6305 | |
| 6306 | if (cpu_is_msm8960()) { |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6307 | rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010); |
| 6308 | rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6309 | } |
| 6310 | if (cpu_is_apq8064()) { |
| 6311 | rmwreg(0x00000000, TV_CC_REG, 0x00004010); |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 6312 | rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6313 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6314 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6315 | /* |
| 6316 | * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that |
| 6317 | * core remain active during halt state of the clk. Also, set sleep |
| 6318 | * and wake-up value to max. |
| 6319 | */ |
| 6320 | rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6321 | if (cpu_is_apq8064()) { |
| 6322 | rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F); |
| 6323 | rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F); |
| 6324 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6325 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6326 | /* De-assert MM AXI resets to all hardware blocks. */ |
| 6327 | writel_relaxed(0, SW_RESET_AXI_REG); |
| 6328 | |
| 6329 | /* Deassert all MM core resets. */ |
| 6330 | writel_relaxed(0, SW_RESET_CORE_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6331 | writel_relaxed(0, SW_RESET_CORE2_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6332 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6333 | /* Enable TSSC and PDM PXO sources. */ |
| 6334 | writel_relaxed(BIT(11), TSSC_CLK_CTL_REG); |
| 6335 | writel_relaxed(BIT(15), PDM_CLK_NS_REG); |
| 6336 | |
| 6337 | /* Source SLIMBus xo src from slimbus reference clock */ |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6338 | if (cpu_is_msm8960ab() || cpu_is_msm8960()) |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 6339 | writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6340 | |
| 6341 | /* Source the dsi_byte_clks from the DSI PHY PLLs */ |
| 6342 | rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7); |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6343 | if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()) |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6344 | rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6345 | |
Siddhartha Agrawal | 482459c | 2012-05-24 15:28:53 -0700 | [diff] [blame] | 6346 | /* Source the dsi1_esc_clk from the DSI1 PHY PLLs */ |
| 6347 | rmwreg(0x1, DSI1_ESC_NS_REG, 0x7); |
| 6348 | |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 6349 | /* |
| 6350 | * Source the sata_phy_ref_clk from PXO and set predivider of |
| 6351 | * sata_pmalive_clk to 1. |
| 6352 | */ |
| 6353 | if (cpu_is_apq8064()) { |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6354 | rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1); |
Tianyi Gou | 352955d | 2012-05-18 19:44:01 -0700 | [diff] [blame] | 6355 | rmwreg(0, SATA_PMALIVE_CLK_CTL_REG, 0x3); |
| 6356 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6357 | |
| 6358 | /* |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 6359 | * TODO: Programming below PLLs and prng_clk is temporary and |
| 6360 | * needs to be removed after bootloaders program them. |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6361 | */ |
| 6362 | if (cpu_is_apq8064()) { |
Tianyi Gou | 317aa86 | 2012-02-06 14:31:07 -0800 | [diff] [blame] | 6363 | u32 is_pll_enabled; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6364 | |
| 6365 | /* Program pxo_src_clk to source from PXO */ |
| 6366 | rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7); |
| 6367 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6368 | /* Check if PLL14 is active */ |
| 6369 | is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16); |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6370 | if (!is_pll_enabled) |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 6371 | /* Ref clk = 27MHz and program pll14 to 480MHz */ |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6372 | configure_pll(&pll14_config, &pll14_regs, 1); |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 6373 | |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 6374 | /* Program PLL15 to 975MHz with ref clk = 27MHz */ |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6375 | configure_pll(&pll15_config, &pll15_regs, 0); |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 6376 | |
| 6377 | /* Check if PLL4 is active */ |
| 6378 | is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16); |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6379 | if (!is_pll_enabled) |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 6380 | /* Ref clk = 27MHz and program pll4 to 393.2160MHz */ |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 6381 | configure_pll(&pll4_config_393, &pll4_regs, 1); |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 6382 | |
| 6383 | /* Enable PLL4 source on the LPASS Primary PLL Mux */ |
| 6384 | writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG); |
Tianyi Gou | 05e0110 | 2012-02-08 22:15:49 -0800 | [diff] [blame] | 6385 | |
| 6386 | /* Program prng_clk to 64MHz if it isn't configured */ |
| 6387 | if (!readl_relaxed(PRNG_CLK_NS_REG)) |
| 6388 | writel_relaxed(0x2B, PRNG_CLK_NS_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6389 | } |
Tianyi Gou | 65c536a | 2012-03-20 23:20:29 -0700 | [diff] [blame] | 6390 | |
| 6391 | /* |
| 6392 | * Program PLL15 to 900MHz with ref clk = 27MHz and |
| 6393 | * only enable PLL main output. |
| 6394 | */ |
Stepan Moskovchenko | 0df9bb2 | 2012-07-06 18:19:15 -0700 | [diff] [blame] | 6395 | if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) { |
Vikram Mulukutla | 5b14672 | 2012-04-23 18:17:50 -0700 | [diff] [blame] | 6396 | pll15_config.l = 0x21 | BVAL(31, 7, 0x600); |
| 6397 | pll15_config.m = 0x1; |
| 6398 | pll15_config.n = 0x3; |
| 6399 | configure_pll(&pll15_config, &pll15_regs, 0); |
| 6400 | /* Disable AUX and BIST outputs */ |
| 6401 | writel_relaxed(0, MM_PLL3_TEST_CTL_REG); |
Tianyi Gou | 65c536a | 2012-03-20 23:20:29 -0700 | [diff] [blame] | 6402 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6403 | } |
| 6404 | |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6405 | struct clock_init_data msm8960_clock_init_data __initdata; |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6406 | static void __init msm8960_clock_pre_init(void) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6407 | { |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 6408 | /* Initialize clock registers. */ |
| 6409 | reg_init(); |
| 6410 | |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 6411 | if (cpu_is_apq8064()) { |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 6412 | vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8064; |
Stepan Moskovchenko | 0df9bb2 | 2012-07-06 18:19:15 -0700 | [diff] [blame] | 6413 | } else if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) { |
Saravana Kannan | 298ec39 | 2012-02-08 19:21:47 -0800 | [diff] [blame] | 6414 | vdd_dig.set_vdd = set_vdd_dig_8930; |
Matt Wagantall | 82feaa1 | 2012-07-09 10:54:49 -0700 | [diff] [blame] | 6415 | vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8930; |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 6416 | } |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 6417 | |
Matt Wagantall | 86e0382 | 2011-12-12 10:59:24 -0800 | [diff] [blame] | 6418 | /* Detect PLL4 programmed for alternate 491.52MHz clock plan. */ |
| 6419 | if (readl_relaxed(LCC_PLL0_L_VAL_REG) == 0x12) { |
| 6420 | pll4_clk.c.rate = 491520000; |
| 6421 | audio_slimbus_clk.freq_tbl = clk_tbl_aif_osr_492; |
| 6422 | mi2s_osr_clk.freq_tbl = clk_tbl_aif_osr_492; |
| 6423 | codec_i2s_mic_osr_clk.freq_tbl = clk_tbl_aif_osr_492; |
| 6424 | spare_i2s_mic_osr_clk.freq_tbl = clk_tbl_aif_osr_492; |
| 6425 | codec_i2s_spkr_osr_clk.freq_tbl = clk_tbl_aif_osr_492; |
| 6426 | spare_i2s_spkr_osr_clk.freq_tbl = clk_tbl_aif_osr_492; |
| 6427 | pcm_clk.freq_tbl = clk_tbl_pcm_492; |
| 6428 | } |
| 6429 | |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6430 | if (cpu_is_msm8960() || cpu_is_msm8960ab()) |
| 6431 | memcpy(msm_clocks_8960, msm_clocks_8960_common, |
| 6432 | sizeof(msm_clocks_8960_common)); |
| 6433 | if (cpu_is_msm8960ab()) { |
| 6434 | pll3_clk.c.rate = 650000000; |
| 6435 | gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960ab; |
| 6436 | gfx3d_clk.c.fmax[VDD_DIG_LOW] = 192000000; |
| 6437 | gfx3d_clk.c.fmax[VDD_DIG_NOMINAL] = 325000000; |
| 6438 | gfx3d_clk.c.fmax[VDD_DIG_HIGH] = 400000000; |
| 6439 | mdp_clk.freq_tbl = clk_tbl_mdp_8960ab; |
| 6440 | mdp_clk.c.fmax[VDD_DIG_LOW] = 128000000; |
| 6441 | mdp_clk.c.fmax[VDD_DIG_NOMINAL] = 266667000; |
| 6442 | |
| 6443 | memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common), |
| 6444 | msm_clocks_8960ab_only, sizeof(msm_clocks_8960ab_only)); |
| 6445 | msm8960_clock_init_data.size -= |
| 6446 | ARRAY_SIZE(msm_clocks_8960_only); |
| 6447 | } else if (cpu_is_msm8960()) { |
| 6448 | memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common), |
| 6449 | msm_clocks_8960_only, sizeof(msm_clocks_8960_only)); |
| 6450 | msm8960_clock_init_data.size -= |
| 6451 | ARRAY_SIZE(msm_clocks_8960ab_only); |
| 6452 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6453 | /* |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6454 | * Change the freq tables for and voltage requirements for |
| 6455 | * clocks which differ between 8960 and 8064. |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6456 | */ |
| 6457 | if (cpu_is_apq8064()) { |
| 6458 | gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6459 | |
| 6460 | memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064, |
| 6461 | sizeof(gfx3d_clk.c.fmax)); |
| 6462 | memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064, |
| 6463 | sizeof(ijpeg_clk.c.fmax)); |
| 6464 | memcpy(mdp_clk.c.fmax, fmax_mdp_8064, |
| 6465 | sizeof(ijpeg_clk.c.fmax)); |
| 6466 | memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064, |
| 6467 | sizeof(tv_src_clk.c.fmax)); |
| 6468 | memcpy(vfe_clk.c.fmax, fmax_vfe_8064, |
| 6469 | sizeof(vfe_clk.c.fmax)); |
| 6470 | |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6471 | gmem_axi_clk.c.depends = &gfx3d_axi_clk.c; |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6472 | } |
| 6473 | |
| 6474 | /* |
| 6475 | * Change the freq tables and voltage requirements for |
| 6476 | * clocks which differ between 8960 and 8930. |
| 6477 | */ |
Stepan Moskovchenko | 0df9bb2 | 2012-07-06 18:19:15 -0700 | [diff] [blame] | 6478 | if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) { |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6479 | gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930; |
| 6480 | |
| 6481 | memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930, |
| 6482 | sizeof(gfx3d_clk.c.fmax)); |
| 6483 | |
| 6484 | pll15_clk.c.rate = 900000000; |
| 6485 | gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6486 | } |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 6487 | if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B) |
| 6488 | prng_clk.freq_tbl = clk_tbl_prng_64; |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 6489 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6490 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6491 | |
Vikram Mulukutla | 681d868 | 2012-03-09 23:56:20 -0800 | [diff] [blame] | 6492 | clk_ops_local_pll.enable = sr_pll_clk_enable; |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6493 | } |
| 6494 | |
| 6495 | static void __init msm8960_clock_post_init(void) |
| 6496 | { |
| 6497 | /* Keep PXO on whenever APPS cpu is active */ |
| 6498 | clk_prepare_enable(&pxo_a_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6499 | |
Matt Wagantall | e655cd7 | 2012-04-09 10:15:03 -0700 | [diff] [blame] | 6500 | /* Reset 3D core while clocked to ensure it resets completely. */ |
| 6501 | clk_set_rate(&gfx3d_clk.c, 27000000); |
| 6502 | clk_prepare_enable(&gfx3d_clk.c); |
| 6503 | clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT); |
| 6504 | udelay(5); |
| 6505 | clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT); |
| 6506 | clk_disable_unprepare(&gfx3d_clk.c); |
| 6507 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6508 | /* Initialize rates for clocks that only support one. */ |
| 6509 | clk_set_rate(&pdm_clk.c, 27000000); |
Stephen Boyd | 842a1f6 | 2012-04-26 19:07:38 -0700 | [diff] [blame] | 6510 | clk_set_rate(&prng_clk.c, prng_clk.freq_tbl->freq_hz); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6511 | clk_set_rate(&mdp_vsync_clk.c, 27000000); |
| 6512 | clk_set_rate(&tsif_ref_clk.c, 105000); |
| 6513 | clk_set_rate(&tssc_clk.c, 27000000); |
| 6514 | clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6515 | if (cpu_is_apq8064()) { |
| 6516 | clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000); |
| 6517 | clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000); |
| 6518 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6519 | clk_set_rate(&usb_fs1_src_clk.c, 60000000); |
Patrick Daly | e6f48904 | 2012-07-11 15:29:15 -0700 | [diff] [blame] | 6520 | if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_msm8930() || |
| 6521 | cpu_is_msm8930aa() || cpu_is_msm8627()) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6522 | clk_set_rate(&usb_fs2_src_clk.c, 60000000); |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 6523 | clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000); |
| 6524 | clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000); |
| 6525 | clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000); |
Lena Salman | 127823f | 2012-02-14 17:13:53 +0200 | [diff] [blame] | 6526 | clk_set_rate(&usb_hsic_system_clk.c, 60000000); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 6527 | /* |
| 6528 | * Set the CSI rates to a safe default to avoid warnings when |
| 6529 | * switching csi pix and rdi clocks. |
| 6530 | */ |
| 6531 | clk_set_rate(&csi0_src_clk.c, 27000000); |
| 6532 | clk_set_rate(&csi1_src_clk.c, 27000000); |
| 6533 | clk_set_rate(&csi2_src_clk.c, 27000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6534 | |
| 6535 | /* |
Stephen Boyd | 60496bb | 2011-10-17 13:51:37 -0700 | [diff] [blame] | 6536 | * The halt status bits for these clocks may be incorrect at boot. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6537 | * Toggle these clocks on and off to refresh them. |
| 6538 | */ |
Stephen Boyd | 409b8b4 | 2012-04-10 12:12:56 -0700 | [diff] [blame] | 6539 | clk_prepare_enable(&pdm_clk.c); |
| 6540 | clk_disable_unprepare(&pdm_clk.c); |
| 6541 | clk_prepare_enable(&tssc_clk.c); |
| 6542 | clk_disable_unprepare(&tssc_clk.c); |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6543 | clk_prepare_enable(&usb_hsic_hsic_clk.c); |
| 6544 | clk_disable_unprepare(&usb_hsic_hsic_clk.c); |
Stephen Boyd | d7a143a | 2012-02-16 17:59:26 -0800 | [diff] [blame] | 6545 | |
| 6546 | /* |
| 6547 | * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all |
| 6548 | * times when Apps CPU is active. This ensures the timer's requirement |
| 6549 | * of Krait AHB running 4 times as fast as the timer itself. |
| 6550 | */ |
| 6551 | clk_set_rate(&sfab_tmr_a_clk.c, 54000000); |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6552 | clk_prepare_enable(&sfab_tmr_a_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6553 | } |
| 6554 | |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 6555 | static int __init msm8960_clock_late_init(void) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6556 | { |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6557 | int rc; |
| 6558 | struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk"); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6559 | struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk"); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6560 | |
| 6561 | /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */ |
| 6562 | if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n", |
| 6563 | PTR_ERR(mmfpb_a_clk))) |
| 6564 | return PTR_ERR(mmfpb_a_clk); |
Matt Wagantall | de555f56 | 2011-11-08 14:18:07 -0800 | [diff] [blame] | 6565 | rc = clk_set_rate(mmfpb_a_clk, 76800000); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6566 | if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc)) |
| 6567 | return rc; |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6568 | rc = clk_prepare_enable(mmfpb_a_clk); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6569 | if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc)) |
| 6570 | return rc; |
| 6571 | |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6572 | /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */ |
| 6573 | if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n", |
| 6574 | PTR_ERR(cfpb_a_clk))) |
| 6575 | return PTR_ERR(cfpb_a_clk); |
Matt Wagantall | de555f56 | 2011-11-08 14:18:07 -0800 | [diff] [blame] | 6576 | rc = clk_set_rate(cfpb_a_clk, 64000000); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6577 | if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc)) |
| 6578 | return rc; |
Stephen Boyd | e334aeb | 2012-01-24 12:17:29 -0800 | [diff] [blame] | 6579 | rc = clk_prepare_enable(cfpb_a_clk); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 6580 | if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc)) |
| 6581 | return rc; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 6582 | |
| 6583 | return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 6584 | } |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 6585 | |
| 6586 | struct clock_init_data msm8960_clock_init_data __initdata = { |
| 6587 | .table = msm_clocks_8960, |
| 6588 | .size = ARRAY_SIZE(msm_clocks_8960), |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6589 | .pre_init = msm8960_clock_pre_init, |
| 6590 | .post_init = msm8960_clock_post_init, |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 6591 | .late_init = msm8960_clock_late_init, |
| 6592 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6593 | |
| 6594 | struct clock_init_data apq8064_clock_init_data __initdata = { |
| 6595 | .table = msm_clocks_8064, |
| 6596 | .size = ARRAY_SIZE(msm_clocks_8064), |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6597 | .pre_init = msm8960_clock_pre_init, |
| 6598 | .post_init = msm8960_clock_post_init, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 6599 | .late_init = msm8960_clock_late_init, |
| 6600 | }; |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6601 | |
| 6602 | struct clock_init_data msm8930_clock_init_data __initdata = { |
| 6603 | .table = msm_clocks_8930, |
| 6604 | .size = ARRAY_SIZE(msm_clocks_8930), |
Matt Wagantall | b64888f | 2012-04-02 21:35:07 -0700 | [diff] [blame] | 6605 | .pre_init = msm8960_clock_pre_init, |
| 6606 | .post_init = msm8960_clock_post_init, |
Tianyi Gou | e3d4f54 | 2012-03-15 17:06:45 -0700 | [diff] [blame] | 6607 | .late_init = msm8960_clock_late_init, |
| 6608 | }; |