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gerrit-public.fairphone.software / kernel / msm / 3e862dd5c94cc53ba6494804c7388303e3d25403 / . / drivers / video / via / chip.h
blob: dde95edc387a6656f44c37442690379d863ff334 [file] [log] [blame]
Joseph Chanae35e812008-10-15 22:03:22 -0700[diff] [blame]1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#ifndef __CHIP_H__
22#define __CHIP_H__
23
24#include "global.h"
25
26/***************************************/
27/* Definition Graphic Chip Information */
28/***************************************/
29
30#define PCI_VIA_VENDOR_ID 0x1106
31
32/* Define VIA Graphic Chip Name */
33#define UNICHROME_CLE266 1
34#define UNICHROME_CLE266_DID 0x3122
35#define CLE266_REVISION_AX 0x0A
36#define CLE266_REVISION_CX 0x0C
37
38#define UNICHROME_K400 2
39#define UNICHROME_K400_DID 0x7205
40
41#define UNICHROME_K800 3
42#define UNICHROME_K800_DID 0x3108
43
44#define UNICHROME_PM800 4
45#define UNICHROME_PM800_DID 0x3118
46
47#define UNICHROME_CN700 5
48#define UNICHROME_CN700_DID 0x3344
49
50#define UNICHROME_CX700 6
51#define UNICHROME_CX700_DID 0x3157
52#define CX700_REVISION_700 0x0
53#define CX700_REVISION_700M 0x1
54#define CX700_REVISION_700M2 0x2
55
56#define UNICHROME_CN750 7
57#define UNICHROME_CN750_DID 0x3225
58
59#define UNICHROME_K8M890 8
60#define UNICHROME_K8M890_DID 0x3230
61
62#define UNICHROME_P4M890 9
63#define UNICHROME_P4M890_DID 0x3343
64
65#define UNICHROME_P4M900 10
66#define UNICHROME_P4M900_DID 0x3371
67
68#define UNICHROME_VX800 11
69#define UNICHROME_VX800_DID 0x1122
70
71/**************************************************/
72/* Definition TMDS Trasmitter Information */
73/**************************************************/
74
75/* Definition TMDS Trasmitter Index */
76#define NON_TMDS_TRANSMITTER 0x00
77#define VT1632_TMDS 0x01
78#define INTEGRATED_TMDS 0x42
79
80/* Definition TMDS Trasmitter I2C Slave Address */
81#define VT1632_TMDS_I2C_ADDR 0x10
82
83/**************************************************/
84/* Definition LVDS Trasmitter Information */
85/**************************************************/
86
87/* Definition LVDS Trasmitter Index */
88#define NON_LVDS_TRANSMITTER 0x00
89#define VT1631_LVDS 0x01
90#define VT1636_LVDS 0x0E
91#define INTEGRATED_LVDS 0x41
92
93/* Definition Digital Transmitter Mode */
94#define TX_DATA_12_BITS 0x01
95#define TX_DATA_24_BITS 0x02
96#define TX_DATA_DDR_MODE 0x04
97#define TX_DATA_SDR_MODE 0x08
98
99/* Definition LVDS Trasmitter I2C Slave Address */
100#define VT1631_LVDS_I2C_ADDR 0x70
101#define VT3271_LVDS_I2C_ADDR 0x80
102#define VT1636_LVDS_I2C_ADDR 0x80
103
104struct tmds_chip_information {
105 int tmds_chip_name;
106 int tmds_chip_slave_addr;
107 int dvi_panel_id;
108 int data_mode;
109 int output_interface;
110 int i2c_port;
111 int device_type;
112};
113
114struct lvds_chip_information {
115 int lvds_chip_name;
116 int lvds_chip_slave_addr;
117 int data_mode;
118 int output_interface;
119 int i2c_port;
120};
121
122struct chip_information {
123 int gfx_chip_name;
124 int gfx_chip_revision;
125 int chip_on_slot;
126 struct tmds_chip_information tmds_chip_info;
127 struct lvds_chip_information lvds_chip_info;
128 struct lvds_chip_information lvds_chip_info2;
129};
130
131struct crt_setting_information {
132 int iga_path;
133 int h_active;
134 int v_active;
135 int bpp;
136 int refresh_rate;
137};
138
139struct tmds_setting_information {
140 int iga_path;
141 int h_active;
142 int v_active;
143 int bpp;
144 int refresh_rate;
145 int get_dvi_size_method;
146 int max_pixel_clock;
147 int dvi_panel_size;
148 int dvi_panel_hres;
149 int dvi_panel_vres;
150 int native_size;
151};
152
153struct lvds_setting_information {
154 int iga_path;
155 int h_active;
156 int v_active;
157 int bpp;
158 int refresh_rate;
159 int get_lcd_size_method;
160 int lcd_panel_id;
161 int lcd_panel_size;
162 int lcd_panel_hres;
163 int lcd_panel_vres;
164 int display_method;
165 int device_lcd_dualedge;
166 int LCDDithering;
167 int lcd_mode;
168 u32 vclk; /*panel mode clock value */
169};
170
171struct GFX_DPA_SETTING {
172 int ClkRangeIndex;
173 u8 DVP0; /* CR96[3:0] */
174 u8 DVP0DataDri_S1; /* SR2A[5] */
175 u8 DVP0DataDri_S; /* SR1B[1] */
176 u8 DVP0ClockDri_S1; /* SR2A[4] */
177 u8 DVP0ClockDri_S; /* SR1E[2] */
178 u8 DVP1; /* CR9B[3:0] */
179 u8 DVP1Driving; /* SR65[3:0], Data and Clock driving */
180 u8 DFPHigh; /* CR97[3:0] */
181 u8 DFPLow; /* CR99[3:0] */
182
183};
184
185struct VT1636_DPA_SETTING {
186 int PanelSizeID;
187 u8 CLK_SEL_ST1;
188 u8 CLK_SEL_ST2;
189};
190#endif /* __CHIP_H__ */