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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __MV643XX_ETH_H__
2#define __MV643XX_ETH_H__
3
4#include <linux/version.h>
5#include <linux/module.h>
6#include <linux/kernel.h>
7#include <linux/spinlock.h>
8#include <linux/workqueue.h>
9
10#include <linux/mv643xx.h>
11
12#define BIT0 0x00000001
13#define BIT1 0x00000002
14#define BIT2 0x00000004
15#define BIT3 0x00000008
16#define BIT4 0x00000010
17#define BIT5 0x00000020
18#define BIT6 0x00000040
19#define BIT7 0x00000080
20#define BIT8 0x00000100
21#define BIT9 0x00000200
22#define BIT10 0x00000400
23#define BIT11 0x00000800
24#define BIT12 0x00001000
25#define BIT13 0x00002000
26#define BIT14 0x00004000
27#define BIT15 0x00008000
28#define BIT16 0x00010000
29#define BIT17 0x00020000
30#define BIT18 0x00040000
31#define BIT19 0x00080000
32#define BIT20 0x00100000
33#define BIT21 0x00200000
34#define BIT22 0x00400000
35#define BIT23 0x00800000
36#define BIT24 0x01000000
37#define BIT25 0x02000000
38#define BIT26 0x04000000
39#define BIT27 0x08000000
40#define BIT28 0x10000000
41#define BIT29 0x20000000
42#define BIT30 0x40000000
43#define BIT31 0x80000000
44
45/*
46 * The first part is the high level driver of the gigE ethernet ports.
47 */
48
49/* Checksum offload for Tx works for most packets, but
50 * fails if previous packet sent did not use hw csum
51 */
Dale Farnsworth26006362005-08-22 15:53:29 -070052#define MV643XX_CHECKSUM_OFFLOAD_TX
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define MV643XX_NAPI
54#define MV643XX_TX_FAST_REFILL
55#undef MV643XX_RX_QUEUE_FILL_ON_TASK /* Does not work, yet */
56#undef MV643XX_COAL
57
58/*
59 * Number of RX / TX descriptors on RX / TX rings.
60 * Note that allocating RX descriptors is done by allocating the RX
61 * ring AND a preallocated RX buffers (skb's) for each descriptor.
62 * The TX descriptors only allocates the TX descriptors ring,
63 * with no pre allocated TX buffers (skb's are allocated by higher layers.
64 */
65
66/* Default TX ring size is 1000 descriptors */
67#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
68
69/* Default RX ring size is 400 descriptors */
70#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
71
72#define MV643XX_TX_COAL 100
73#ifdef MV643XX_COAL
74#define MV643XX_RX_COAL 100
75#endif
76
77/*
78 * The second part is the low level driver of the gigE ethernet ports.
79 */
80
81/*
82 * Header File for : MV-643xx network interface header
83 *
84 * DESCRIPTION:
85 * This header file contains macros typedefs and function declaration for
86 * the Marvell Gig Bit Ethernet Controller.
87 *
88 * DEPENDENCIES:
89 * None.
90 *
91 */
92
93/* MAC accepet/reject macros */
94#define ACCEPT_MAC_ADDR 0
95#define REJECT_MAC_ADDR 1
96
97/* Buffer offset from buffer pointer */
98#define RX_BUF_OFFSET 0x2
99
100/* Gigabit Ethernet Unit Global Registers */
101
102/* MIB Counters register definitions */
103#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
104#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
105#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
106#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
107#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
108#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
109#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
110#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
111#define ETH_MIB_FRAMES_64_OCTETS 0x20
112#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
113#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
114#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
115#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
116#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
117#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
118#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
119#define ETH_MIB_GOOD_FRAMES_SENT 0x40
120#define ETH_MIB_EXCESSIVE_COLLISION 0x44
121#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
122#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
123#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
124#define ETH_MIB_FC_SENT 0x54
125#define ETH_MIB_GOOD_FC_RECEIVED 0x58
126#define ETH_MIB_BAD_FC_RECEIVED 0x5c
127#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
128#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
129#define ETH_MIB_OVERSIZE_RECEIVED 0x68
130#define ETH_MIB_JABBER_RECEIVED 0x6c
131#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
132#define ETH_MIB_BAD_CRC_EVENT 0x74
133#define ETH_MIB_COLLISION 0x78
134#define ETH_MIB_LATE_COLLISION 0x7c
135
136/* Port serial status reg (PSR) */
137#define ETH_INTERFACE_GMII_MII 0
138#define ETH_INTERFACE_PCM BIT0
139#define ETH_LINK_IS_DOWN 0
140#define ETH_LINK_IS_UP BIT1
141#define ETH_PORT_AT_HALF_DUPLEX 0
142#define ETH_PORT_AT_FULL_DUPLEX BIT2
143#define ETH_RX_FLOW_CTRL_DISABLED 0
144#define ETH_RX_FLOW_CTRL_ENBALED BIT3
145#define ETH_GMII_SPEED_100_10 0
146#define ETH_GMII_SPEED_1000 BIT4
147#define ETH_MII_SPEED_10 0
148#define ETH_MII_SPEED_100 BIT5
149#define ETH_NO_TX 0
150#define ETH_TX_IN_PROGRESS BIT7
151#define ETH_BYPASS_NO_ACTIVE 0
152#define ETH_BYPASS_ACTIVE BIT8
153#define ETH_PORT_NOT_AT_PARTITION_STATE 0
154#define ETH_PORT_AT_PARTITION_STATE BIT9
155#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
156#define ETH_PORT_TX_FIFO_EMPTY BIT10
157
158#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
159#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
160#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
161#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
162#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
163
164/* SMI reg */
165#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
166#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
167#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
168#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
169
170/* SDMA command status fields macros */
171
172/* Tx & Rx descriptors status */
173#define ETH_ERROR_SUMMARY (BIT0)
174
175/* Tx & Rx descriptors command */
176#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
177
178/* Tx descriptors status */
179#define ETH_LC_ERROR (0 )
180#define ETH_UR_ERROR (BIT1 )
181#define ETH_RL_ERROR (BIT2 )
182#define ETH_LLC_SNAP_FORMAT (BIT9 )
183
184/* Rx descriptors status */
185#define ETH_CRC_ERROR (0 )
186#define ETH_OVERRUN_ERROR (BIT1 )
187#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
188#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
189#define ETH_VLAN_TAGGED (BIT19)
190#define ETH_BPDU_FRAME (BIT20)
191#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
192#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
193#define ETH_OTHER_FRAME_TYPE (BIT22)
194#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
195#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
196#define ETH_FRAME_HEADER_OK (BIT25)
197#define ETH_RX_LAST_DESC (BIT26)
198#define ETH_RX_FIRST_DESC (BIT27)
199#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
200#define ETH_RX_ENABLE_INTERRUPT (BIT29)
201#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
202
203/* Rx descriptors byte count */
204#define ETH_FRAME_FRAGMENTED (BIT2)
205
206/* Tx descriptors command */
207#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
208#define ETH_FRAME_SET_TO_VLAN (BIT15)
209#define ETH_TCP_FRAME (0 )
210#define ETH_UDP_FRAME (BIT16)
211#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
212#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
213#define ETH_ZERO_PADDING (BIT19)
214#define ETH_TX_LAST_DESC (BIT20)
215#define ETH_TX_FIRST_DESC (BIT21)
216#define ETH_GEN_CRC (BIT22)
217#define ETH_TX_ENABLE_INTERRUPT (BIT23)
218#define ETH_AUTO_MODE (BIT30)
219
Dale Farnsworth26006362005-08-22 15:53:29 -0700220#define ETH_TX_IHL_SHIFT 11
221
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222/* typedefs */
223
224typedef enum _eth_func_ret_status {
225 ETH_OK, /* Returned as expected. */
226 ETH_ERROR, /* Fundamental error. */
227 ETH_RETRY, /* Could not process request. Try later.*/
228 ETH_END_OF_JOB, /* Ring has nothing to process. */
229 ETH_QUEUE_FULL, /* Ring resource error. */
230 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
231} ETH_FUNC_RET_STATUS;
232
233typedef enum _eth_target {
234 ETH_TARGET_DRAM,
235 ETH_TARGET_DEVICE,
236 ETH_TARGET_CBS,
237 ETH_TARGET_PCI0,
238 ETH_TARGET_PCI1
239} ETH_TARGET;
240
241/* These are for big-endian machines. Little endian needs different
242 * definitions.
243 */
244#if defined(__BIG_ENDIAN)
245struct eth_rx_desc {
246 u16 byte_cnt; /* Descriptor buffer byte count */
247 u16 buf_size; /* Buffer size */
248 u32 cmd_sts; /* Descriptor command status */
249 u32 next_desc_ptr; /* Next descriptor pointer */
250 u32 buf_ptr; /* Descriptor buffer pointer */
251};
252
253struct eth_tx_desc {
254 u16 byte_cnt; /* buffer byte count */
255 u16 l4i_chk; /* CPU provided TCP checksum */
256 u32 cmd_sts; /* Command/status field */
257 u32 next_desc_ptr; /* Pointer to next descriptor */
258 u32 buf_ptr; /* pointer to buffer for this descriptor*/
259};
260
261#elif defined(__LITTLE_ENDIAN)
262struct eth_rx_desc {
263 u32 cmd_sts; /* Descriptor command status */
264 u16 buf_size; /* Buffer size */
265 u16 byte_cnt; /* Descriptor buffer byte count */
266 u32 buf_ptr; /* Descriptor buffer pointer */
267 u32 next_desc_ptr; /* Next descriptor pointer */
268};
269
270struct eth_tx_desc {
271 u32 cmd_sts; /* Command/status field */
272 u16 l4i_chk; /* CPU provided TCP checksum */
273 u16 byte_cnt; /* buffer byte count */
274 u32 buf_ptr; /* pointer to buffer for this descriptor*/
275 u32 next_desc_ptr; /* Pointer to next descriptor */
276};
277#else
278#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
279#endif
280
281/* Unified struct for Rx and Tx operations. The user is not required to */
282/* be familier with neither Tx nor Rx descriptors. */
283struct pkt_info {
284 unsigned short byte_cnt; /* Descriptor buffer byte count */
285 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
286 unsigned int cmd_sts; /* Descriptor command status */
287 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
288 struct sk_buff *return_info; /* User resource return information */
289};
290
291/* Ethernet port specific infomation */
292
293struct mv643xx_mib_counters {
294 u64 good_octets_received;
295 u32 bad_octets_received;
296 u32 internal_mac_transmit_err;
297 u32 good_frames_received;
298 u32 bad_frames_received;
299 u32 broadcast_frames_received;
300 u32 multicast_frames_received;
301 u32 frames_64_octets;
302 u32 frames_65_to_127_octets;
303 u32 frames_128_to_255_octets;
304 u32 frames_256_to_511_octets;
305 u32 frames_512_to_1023_octets;
306 u32 frames_1024_to_max_octets;
307 u64 good_octets_sent;
308 u32 good_frames_sent;
309 u32 excessive_collision;
310 u32 multicast_frames_sent;
311 u32 broadcast_frames_sent;
312 u32 unrec_mac_control_received;
313 u32 fc_sent;
314 u32 good_fc_received;
315 u32 bad_fc_received;
316 u32 undersize_received;
317 u32 fragments_received;
318 u32 oversize_received;
319 u32 jabber_received;
320 u32 mac_receive_error;
321 u32 bad_crc_event;
322 u32 collision;
323 u32 late_collision;
324};
325
326struct mv643xx_private {
327 int port_num; /* User Ethernet port number */
328 u8 port_mac_addr[6]; /* User defined port MAC address.*/
329 u32 port_config; /* User port configuration value*/
330 u32 port_config_extend; /* User port config extend value*/
331 u32 port_sdma_config; /* User port SDMA config value */
332 u32 port_serial_control; /* User port serial control value */
333 u32 port_tx_queue_command; /* Port active Tx queues summary*/
334 u32 port_rx_queue_command; /* Port active Rx queues summary*/
335
336 u32 rx_sram_addr; /* Base address of rx sram area */
337 u32 rx_sram_size; /* Size of rx sram area */
338 u32 tx_sram_addr; /* Base address of tx sram area */
339 u32 tx_sram_size; /* Size of tx sram area */
340
341 int rx_resource_err; /* Rx ring resource error flag */
342 int tx_resource_err; /* Tx ring resource error flag */
343
344 /* Tx/Rx rings managment indexes fields. For driver use */
345
346 /* Next available and first returning Rx resource */
347 int rx_curr_desc_q, rx_used_desc_q;
348
349 /* Next available and first returning Tx resource */
350 int tx_curr_desc_q, tx_used_desc_q;
351#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
352 int tx_first_desc_q;
353 u32 tx_first_command;
354#endif
355
356#ifdef MV643XX_TX_FAST_REFILL
357 u32 tx_clean_threshold;
358#endif
359
360 struct eth_rx_desc *p_rx_desc_area;
361 dma_addr_t rx_desc_dma;
362 unsigned int rx_desc_area_size;
363 struct sk_buff **rx_skb;
364
365 struct eth_tx_desc *p_tx_desc_area;
366 dma_addr_t tx_desc_dma;
367 unsigned int tx_desc_area_size;
368 struct sk_buff **tx_skb;
369
370 struct work_struct tx_timeout_task;
371
372 /*
373 * Former struct mv643xx_eth_priv members start here
374 */
375 struct net_device_stats stats;
376 struct mv643xx_mib_counters mib_counters;
377 spinlock_t lock;
378 /* Size of Tx Ring per queue */
379 unsigned int tx_ring_size;
380 /* Ammont of SKBs outstanding on Tx queue */
381 unsigned int tx_ring_skbs;
382 /* Size of Rx Ring per queue */
383 unsigned int rx_ring_size;
384 /* Ammount of SKBs allocated to Rx Ring per queue */
385 unsigned int rx_ring_skbs;
386
387 /*
388 * rx_task used to fill RX ring out of bottom half context
389 */
390 struct work_struct rx_task;
391
392 /*
393 * Used in case RX Ring is empty, which can be caused when
394 * system does not have resources (skb's)
395 */
396 struct timer_list timeout;
397 long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
398 unsigned rx_timer_flag;
399
400 u32 rx_int_coal;
401 u32 tx_int_coal;
402};
403
404/* ethernet.h API list */
405
406/* Port operation control routines */
407static void eth_port_init(struct mv643xx_private *mp);
408static void eth_port_reset(unsigned int eth_port_num);
409static void eth_port_start(struct mv643xx_private *mp);
410
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411/* Port MAC address routines */
412static void eth_port_uc_addr_set(unsigned int eth_port_num,
413 unsigned char *p_addr);
414
415/* PHY and MIB routines */
416static void ethernet_phy_reset(unsigned int eth_port_num);
417
418static void eth_port_write_smi_reg(unsigned int eth_port_num,
419 unsigned int phy_reg, unsigned int value);
420
421static void eth_port_read_smi_reg(unsigned int eth_port_num,
422 unsigned int phy_reg, unsigned int *value);
423
424static void eth_clear_mib_counters(unsigned int eth_port_num);
425
426/* Port data flow control routines */
427static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
428 struct pkt_info *p_pkt_info);
429static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
430 struct pkt_info *p_pkt_info);
431static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
432 struct pkt_info *p_pkt_info);
433static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
434 struct pkt_info *p_pkt_info);
435
436#endif /* __MV643XX_ETH_H__ */