Blame - include/asm-powerpc/cputable.h - kernel/msm

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Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	1	#ifndef __ASM_POWERPC_CPUTABLE_H
				2	#define __ASM_POWERPC_CPUTABLE_H
				3
David Gibson	3ddfbcf	2005-11-10 12:56:55 +1100	[diff] [blame]	4	#include <asm/asm-compat.h>
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	5
				6	#define PPC_FEATURE_32 0x80000000
				7	#define PPC_FEATURE_64 0x40000000
				8	#define PPC_FEATURE_601_INSTR 0x20000000
				9	#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
				10	#define PPC_FEATURE_HAS_FPU 0x08000000
				11	#define PPC_FEATURE_HAS_MMU 0x04000000
				12	#define PPC_FEATURE_HAS_4xxMAC 0x02000000
				13	#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
				14	#define PPC_FEATURE_HAS_SPE 0x00800000
				15	#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
				16	#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras	9859901	2005-10-22 16:51:34 +1000	[diff] [blame]	17	#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerras	a7ddc5e	2005-11-10 14:29:18 +1100	[diff] [blame]	18	#define PPC_FEATURE_POWER4 0x00080000
				19	#define PPC_FEATURE_POWER5 0x00040000
				20	#define PPC_FEATURE_POWER5_PLUS 0x00020000
				21	#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	22	#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidt	aa5cb02	2006-03-01 15:07:07 +1100	[diff] [blame]	23	#define PPC_FEATURE_SMT 0x00004000
				24	#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	25	#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johansson	b3ebd1d	2006-09-06 14:35:57 -0500	[diff] [blame]	26	#define PPC_FEATURE_PA6T 0x00000800
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	27	#define PPC_FEATURE_HAS_DFP 0x00000400
				28	#define PPC_FEATURE_POWER6_EXT 0x00000200
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	29
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	30	#define PPC_FEATURE_TRUE_LE 0x00000002
				31	#define PPC_FEATURE_PPC_LE 0x00000001
				32
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	33	#ifdef __KERNEL__
				34	#ifndef __ASSEMBLY__
				35
				36	/* This structure can grow, it's real size is used by head.S code
				37	* via the mkdefs mechanism.
				38	*/
				39	struct cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	40
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	41	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	42	typedef void (*cpu_restore_t)(void);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	43
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	44	enum powerpc_oprofile_type {
Andy Whitcroft	7a45fb1	2006-01-13 12:35:49 +0000	[diff] [blame]	45	PPC_OPROFILE_INVALID = 0,
				46	PPC_OPROFILE_RS64 = 1,
				47	PPC_OPROFILE_POWER4 = 2,
				48	PPC_OPROFILE_G4 = 3,
				49	PPC_OPROFILE_BOOKE = 4,
Maynard Johnson	18f2190	2006-11-20 18:45:16 +0100	[diff] [blame]	50	PPC_OPROFILE_CELL = 5,
Olof Johansson	25fc530	2007-04-18 16:38:21 +1000	[diff] [blame]	51	PPC_OPROFILE_PA6T = 6,
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	52	};
				53
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	54	enum powerpc_pmc_type {
				55	PPC_PMC_DEFAULT = 0,
				56	PPC_PMC_IBM = 1,
				57	PPC_PMC_PA6T = 2,
				58	};
				59
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	60	struct cpu_spec {
				61	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
				62	unsigned int pvr_mask;
				63	unsigned int pvr_value;
				64
				65	char *cpu_name;
				66	unsigned long cpu_features; /* Kernel features */
				67	unsigned int cpu_user_features; /* Userland features */
				68
				69	/* cache line sizes */
				70	unsigned int icache_bsize;
				71	unsigned int dcache_bsize;
				72
				73	/* number of performance monitor counters */
				74	unsigned int num_pmcs;
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	75	enum powerpc_pmc_type pmc_type;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	76
				77	/* this is called to initialize various CPU bits like L1 cache,
				78	* BHT, SPD, etc... from head.S before branching to identify_machine
				79	*/
				80	cpu_setup_t cpu_setup;
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	81	/* Used to restore cpu setup on secondary processors and at resume */
				82	cpu_restore_t cpu_restore;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	83
				84	/* Used by oprofile userspace to select the right counters */
				85	char *oprofile_cpu_type;
				86
				87	/* Processor specific oprofile operations */
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	88	enum powerpc_oprofile_type oprofile_type;
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	89
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	90	/* Bit locations inside the mmcra change */
				91	unsigned long oprofile_mmcra_sihv;
				92	unsigned long oprofile_mmcra_sipr;
				93
				94	/* Bits to clear during an oprofile exception */
				95	unsigned long oprofile_mmcra_clear;
				96
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	97	/* Name of processor class, for the ELF AT_PLATFORM entry */
				98	char *platform;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	99	};
				100
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	101	extern struct cpu_spec *cur_cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	102
Benjamin Herrenschmidt	42c4aaa	2006-10-24 16:42:40 +1000	[diff] [blame]	103	extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
				104
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	105	extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	106	extern void do_feature_fixups(unsigned long value, void *fixup_start,
				107	void *fixup_end);
Paul Mackerras	9b6b563	2005-10-06 12:06:20 +1000	[diff] [blame]	108
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	109	#endif /* __ASSEMBLY__ */
				110
				111	/* CPU kernel features */
				112
				113	/* Retain the 32b definitions all use bottom half of word */
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	114	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	115	#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
				116	#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
				117	#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
				118	#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
				119	#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
				120	#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
				121	#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
				122	#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
				123	#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
				124	#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
				125	#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
				126	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
				127	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
				128	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
				129	#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
				130	#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
				131	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
				132	#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
				133	#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman	3d15910	2006-03-21 20:45:58 +1100	[diff] [blame]	134	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	135	#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
				136	#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	137	#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	138	#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	139
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	140	/*
				141	* Add the 64-bit processor unique features in the top half of the word;
				142	* on 32-bit, make the names available but defined to be 0.
				143	*/
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	144	#ifdef __powerpc64__
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	145	#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	146	#else
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	147	#define LONG_ASM_CONST(x) 0
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	148	#endif
				149
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	150	#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
				151	#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
				152	#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
				153	#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
				154	#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
				155	#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
				156	#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
				157	#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	158	#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
				159	#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
				160	#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
				161	#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt	859deea	2006-10-20 14:37:05 +1000	[diff] [blame]	162	#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	163	#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	164	#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	165
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	166	#ifndef __ASSEMBLY__
				167
Stephen Rothwell	0470466	2006-11-30 11:46:22 +1100	[diff] [blame]	168	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB \| \
				169	CPU_FTR_TLBIEL \| CPU_FTR_NOEXECUTE \| \
				170	CPU_FTR_NODSISRALIGN \| CPU_FTR_16M_PAGE)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	171
				172	/* We only set the altivec features if the kernel was compiled with altivec
				173	* support
				174	*/
				175	#ifdef CONFIG_ALTIVEC
				176	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
				177	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
				178	#else
				179	#define CPU_FTR_ALTIVEC_COMP 0
				180	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
				181	#endif
				182
				183	/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala	1775dbb	2006-02-22 09:46:02 -0600	[diff] [blame]	184	* have a 74[45]x and an MPC107 host bridge. Also 83xx requires
				185	* it for PCI "streaming/prefetch" to work properly.
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	186	*/
Kumar Gala	1775dbb	2006-02-22 09:46:02 -0600	[diff] [blame]	187	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
				188	\|\| defined(CONFIG_PPC_83xx)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	189	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
				190	#else
				191	#define CPU_FTR_COMMON 0
				192	#endif
				193
				194	/* The powersave features NAP & DOZE seems to confuse BDI when
				195	debugging. So if a BDI is used, disable theses
				196	*/
				197	#ifndef CONFIG_BDI_SWITCH
				198	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
				199	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
				200	#else
				201	#define CPU_FTR_MAYBE_CAN_DOZE 0
				202	#define CPU_FTR_MAYBE_CAN_NAP 0
				203	#endif
				204
				205	#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
				206	!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
				207	!defined(CONFIG_BOOKE))
				208
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	209	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| CPU_FTR_HPTE_TABLE \| \
				210	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_UNIFIED_ID_CACHE)
				211	#define CPU_FTRS_603 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	212	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	213	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	214	#define CPU_FTRS_604 (CPU_FTR_COMMON \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	215	CPU_FTR_USE_TB \| CPU_FTR_604_PERF_MON \| CPU_FTR_HPTE_TABLE \| \
				216	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	217	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	218	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	219	CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	220	#define CPU_FTRS_740 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	221	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	222	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
				223	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	224	#define CPU_FTRS_750 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	225	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	226	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
				227	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	228	#define CPU_FTRS_750CL (CPU_FTR_COMMON \| \
Josh Boyer	a14c450	2007-04-13 04:33:25 +1000	[diff] [blame]	229	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				230	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
				231	CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	232	#define CPU_FTRS_750FX1 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	233	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				234	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	235	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	236	#define CPU_FTRS_750FX2 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	237	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				238	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	239	CPU_FTR_NO_DPM \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	240	#define CPU_FTRS_750FX (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	241	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				242	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	243	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	244	#define CPU_FTRS_750GX (CPU_FTR_COMMON \| \
Josh Boyer	a14c450	2007-04-13 04:33:25 +1000	[diff] [blame]	245	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				246	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	247	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	248	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	249	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				250	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	251	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	252	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	253	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
				254	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	255	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	256	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	257	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				258	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	259	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	260	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	261	CPU_FTR_USE_TB \| \
				262	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				263	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				264	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	265	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	266	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	267	CPU_FTR_USE_TB \| \
				268	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				269	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	270	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	271	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	272	CPU_FTR_USE_TB \| \
				273	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
				274	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| CPU_FTR_HAS_HIGH_BATS \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	275	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	276	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	277	CPU_FTR_USE_TB \| \
				278	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				279	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				280	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	281	CPU_FTR_NEED_COHERENT \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	282	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	283	CPU_FTR_USE_TB \| \
				284	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				285	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				286	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	287	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	288	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	289	CPU_FTR_USE_TB \| \
				290	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				291	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				292	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	293	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	294	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	295	CPU_FTR_USE_TB \| \
				296	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				297	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				298	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	299	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	300	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	301	CPU_FTR_USE_TB \| \
				302	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				303	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				304	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	305	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	306	#define CPU_FTRS_7448 (CPU_FTR_COMMON \| \
James.Yang	3d37254	2007-05-02 16:34:43 -0500	[diff] [blame]	307	CPU_FTR_USE_TB \| \
				308	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
				309	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
				310	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
				311	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	312	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	313	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	314	#define CPU_FTRS_G2_LE (CPU_FTR_MAYBE_CAN_DOZE \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	315	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	316	#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	317	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS \| \
				318	CPU_FTR_COMMON)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	319	#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE \| \
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	320	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS \| \
				321	CPU_FTR_COMMON \| CPU_FTR_FPU_UNAVAILABLE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	322	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	323	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	324	#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
				325	#define CPU_FTRS_40X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN)
				326	#define CPU_FTRS_44X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN)
				327	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				328	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_UNIFIED_ID_CACHE)
				329	#define CPU_FTRS_E500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN)
				330	#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	331	CPU_FTR_BIG_PHYS \| CPU_FTR_NODSISRALIGN)
				332	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
Michael Ellerman	0b8e2e1	2006-11-23 00:46:46 +0100	[diff] [blame]	333
				334	/* 64-bit CPUs */
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	335	#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	336	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	337	#define CPU_FTRS_RS64 (CPU_FTR_USE_TB \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	338	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| \
				339	CPU_FTR_MMCRA \| CPU_FTR_CTRL)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	340	#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	341	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
				342	CPU_FTR_MMCRA)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	343	#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	344	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	345	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	346	#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	347	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	348	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				349	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	350	CPU_FTR_PURR)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	351	#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	352	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	353	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				354	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	355	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
				356	CPU_FTR_DSCR)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	357	#define CPU_FTRS_CELL (CPU_FTR_USE_TB \| \
Olof Johansson	0024300	2006-09-06 14:35:19 -0500	[diff] [blame]	358	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	359	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Benjamin Herrenschmidt	859deea	2006-10-20 14:37:05 +1000	[diff] [blame]	360	CPU_FTR_PAUSE_ZERO \| CPU_FTR_CI_LARGE_PAGE \| CPU_FTR_CELL_TB_BUG)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	361	#define CPU_FTRS_PA6T (CPU_FTR_USE_TB \| \
Olof Johansson	b3ebd1d	2006-09-06 14:35:57 -0500	[diff] [blame]	362	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| \
				363	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CI_LARGE_PAGE \| \
				364	CPU_FTR_PURR \| CPU_FTR_REAL_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame^]	365	#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	366	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	367
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	368	#ifdef __powerpc64__
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	369	#define CPU_FTRS_POSSIBLE \
				370	(CPU_FTRS_POWER3 \| CPU_FTRS_RS64 \| CPU_FTRS_POWER4 \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	371	CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| CPU_FTRS_POWER6 \| \
Olof Johansson	b3ebd1d	2006-09-06 14:35:57 -0500	[diff] [blame]	372	CPU_FTRS_CELL \| CPU_FTRS_PA6T)
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	373	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	374	enum {
				375	CPU_FTRS_POSSIBLE =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	376	#if CLASSIC_PPC
				377	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
				378	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
				379	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
				380	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
				381	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
				382	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
				383	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	384	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_E300C2 \|
				385	CPU_FTRS_CLASSIC32 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	386	#else
				387	CPU_FTRS_GENERIC_32 \|
				388	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	389	#ifdef CONFIG_8xx
				390	CPU_FTRS_8XX \|
				391	#endif
				392	#ifdef CONFIG_40x
				393	CPU_FTRS_40X \|
				394	#endif
				395	#ifdef CONFIG_44x
				396	CPU_FTRS_44X \|
				397	#endif
				398	#ifdef CONFIG_E200
				399	CPU_FTRS_E200 \|
				400	#endif
				401	#ifdef CONFIG_E500
				402	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \|
				403	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	404	0,
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	405	};
				406	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	407
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	408	#ifdef __powerpc64__
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	409	#define CPU_FTRS_ALWAYS \
				410	(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	411	CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Olof Johansson	b3ebd1d	2006-09-06 14:35:57 -0500	[diff] [blame]	412	CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	413	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	414	enum {
				415	CPU_FTRS_ALWAYS =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	416	#if CLASSIC_PPC
				417	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
				418	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
				419	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
				420	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
				421	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
				422	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
				423	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	424	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
				425	CPU_FTRS_CLASSIC32 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	426	#else
				427	CPU_FTRS_GENERIC_32 &
				428	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	429	#ifdef CONFIG_8xx
				430	CPU_FTRS_8XX &
				431	#endif
				432	#ifdef CONFIG_40x
				433	CPU_FTRS_40X &
				434	#endif
				435	#ifdef CONFIG_44x
				436	CPU_FTRS_44X &
				437	#endif
				438	#ifdef CONFIG_E200
				439	CPU_FTRS_E200 &
				440	#endif
				441	#ifdef CONFIG_E500
				442	CPU_FTRS_E500 & CPU_FTRS_E500_2 &
				443	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	444	CPU_FTRS_POSSIBLE,
				445	};
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	446	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	447
				448	static inline int cpu_has_feature(unsigned long feature)
				449	{
				450	return (CPU_FTRS_ALWAYS & feature) \|\|
				451	(CPU_FTRS_POSSIBLE
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	452	& cur_cpu_spec->cpu_features
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	453	& feature);
				454	}
				455
				456	#endif /* !__ASSEMBLY__ */
				457
				458	#ifdef __ASSEMBLY__
				459
Benjamin Herrenschmidt	7aeb732	2006-10-20 11:47:16 +1000	[diff] [blame]	460	#define BEGIN_FTR_SECTION_NESTED(label) label:
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	461	#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
Benjamin Herrenschmidt	7aeb732	2006-10-20 11:47:16 +1000	[diff] [blame]	462	#define END_FTR_SECTION_NESTED(msk, val, label) \
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	463	MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
Benjamin Herrenschmidt	7aeb732	2006-10-20 11:47:16 +1000	[diff] [blame]	464	#define END_FTR_SECTION(msk, val) \
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	465	END_FTR_SECTION_NESTED(msk, val, 97)
Benjamin Herrenschmidt	7aeb732	2006-10-20 11:47:16 +1000	[diff] [blame]	466
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	467	#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
				468	#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
				469	#endif /* __ASSEMBLY__ */
				470
				471	#endif /* __KERNEL__ */
				472	#endif /* __ASM_POWERPC_CPUTABLE_H */