Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | |
Malli Chilakala | 2648345 | 2005-04-28 19:44:46 -0700 | [diff] [blame] | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms of the GNU General Public License as published by the Free |
| 8 | Software Foundation; either version 2 of the License, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License along with |
| 17 | this program; if not, write to the Free Software Foundation, Inc., 59 |
| 18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | |
| 20 | The full GNU General Public License is included in this distribution in the |
| 21 | file called LICENSE. |
| 22 | |
| 23 | Contact Information: |
| 24 | Linux NICS <linux.nics@intel.com> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | /* e1000_hw.c |
| 30 | * Shared functions for accessing and configuring the MAC |
| 31 | */ |
| 32 | |
| 33 | #include "e1000_hw.h" |
| 34 | |
| 35 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); |
| 36 | static void e1000_phy_init_script(struct e1000_hw *hw); |
| 37 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); |
| 38 | static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); |
| 39 | static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); |
| 40 | static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
| 41 | static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); |
| 42 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
| 43 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
| 44 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, |
| 45 | uint16_t count); |
| 46 | static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
| 47 | static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); |
| 48 | static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, |
| 49 | uint16_t words, uint16_t *data); |
| 50 | static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, |
| 51 | uint16_t offset, uint16_t words, |
| 52 | uint16_t *data); |
| 53 | static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); |
| 54 | static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
| 55 | static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
| 56 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, |
| 57 | uint16_t count); |
| 58 | static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
| 59 | uint16_t phy_data); |
| 60 | static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, |
| 61 | uint16_t *phy_data); |
| 62 | static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); |
| 63 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); |
| 64 | static void e1000_release_eeprom(struct e1000_hw *hw); |
| 65 | static void e1000_standby_eeprom(struct e1000_hw *hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
| 67 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
| 68 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 69 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
| 70 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 71 | static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); |
| 72 | static int32_t e1000_check_downshift(struct e1000_hw *hw); |
| 73 | static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity); |
| 74 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
| 75 | static void e1000_clear_vfta(struct e1000_hw *hw); |
| 76 | static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); |
| 77 | static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
| 78 | boolean_t link_up); |
| 79 | static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); |
| 80 | static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); |
| 81 | static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); |
| 82 | static int32_t e1000_get_cable_length(struct e1000_hw *hw, |
| 83 | uint16_t *min_length, |
| 84 | uint16_t *max_length); |
| 85 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
| 86 | static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); |
| 87 | static int32_t e1000_id_led_init(struct e1000_hw * hw); |
| 88 | static void e1000_init_rx_addrs(struct e1000_hw *hw); |
| 89 | static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); |
| 90 | static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); |
| 91 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); |
| 92 | static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, |
| 93 | uint16_t words, uint16_t *data); |
| 94 | static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); |
| 95 | static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); |
| 96 | static int32_t e1000_wait_autoneg(struct e1000_hw *hw); |
| 97 | |
| 98 | static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, |
| 99 | uint32_t value); |
| 100 | |
| 101 | #define E1000_WRITE_REG_IO(a, reg, val) \ |
| 102 | e1000_write_reg_io((a), E1000_##reg, val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
| 104 | /* IGP cable length table */ |
| 105 | static const |
| 106 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
| 107 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
| 108 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
| 109 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
| 110 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
| 111 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
| 112 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
| 113 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
| 114 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; |
| 115 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 116 | static const |
| 117 | uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 118 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
| 119 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, |
| 120 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, |
| 121 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, |
| 122 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, |
| 123 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, |
| 124 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, |
| 125 | 104, 109, 114, 118, 121, 124}; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 126 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | |
| 128 | /****************************************************************************** |
| 129 | * Set the phy type member in the hw struct. |
| 130 | * |
| 131 | * hw - Struct containing variables accessed by shared code |
| 132 | *****************************************************************************/ |
| 133 | int32_t |
| 134 | e1000_set_phy_type(struct e1000_hw *hw) |
| 135 | { |
| 136 | DEBUGFUNC("e1000_set_phy_type"); |
| 137 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 138 | if(hw->mac_type == e1000_undefined) |
| 139 | return -E1000_ERR_PHY_TYPE; |
| 140 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | switch(hw->phy_id) { |
| 142 | case M88E1000_E_PHY_ID: |
| 143 | case M88E1000_I_PHY_ID: |
| 144 | case M88E1011_I_PHY_ID: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 145 | case M88E1111_I_PHY_ID: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | hw->phy_type = e1000_phy_m88; |
| 147 | break; |
| 148 | case IGP01E1000_I_PHY_ID: |
| 149 | if(hw->mac_type == e1000_82541 || |
| 150 | hw->mac_type == e1000_82541_rev_2 || |
| 151 | hw->mac_type == e1000_82547 || |
| 152 | hw->mac_type == e1000_82547_rev_2) { |
| 153 | hw->phy_type = e1000_phy_igp; |
| 154 | break; |
| 155 | } |
| 156 | /* Fall Through */ |
| 157 | default: |
| 158 | /* Should never have loaded on this device */ |
| 159 | hw->phy_type = e1000_phy_undefined; |
| 160 | return -E1000_ERR_PHY_TYPE; |
| 161 | } |
| 162 | |
| 163 | return E1000_SUCCESS; |
| 164 | } |
| 165 | |
| 166 | /****************************************************************************** |
| 167 | * IGP phy init script - initializes the GbE PHY |
| 168 | * |
| 169 | * hw - Struct containing variables accessed by shared code |
| 170 | *****************************************************************************/ |
| 171 | static void |
| 172 | e1000_phy_init_script(struct e1000_hw *hw) |
| 173 | { |
| 174 | uint32_t ret_val; |
| 175 | uint16_t phy_saved_data; |
| 176 | |
| 177 | DEBUGFUNC("e1000_phy_init_script"); |
| 178 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | if(hw->phy_init_script) { |
| 180 | msec_delay(20); |
| 181 | |
| 182 | /* Save off the current value of register 0x2F5B to be restored at |
| 183 | * the end of this routine. */ |
| 184 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 185 | |
| 186 | /* Disabled the PHY transmitter */ |
| 187 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 188 | |
| 189 | msec_delay(20); |
| 190 | |
| 191 | e1000_write_phy_reg(hw,0x0000,0x0140); |
| 192 | |
| 193 | msec_delay(5); |
| 194 | |
| 195 | switch(hw->mac_type) { |
| 196 | case e1000_82541: |
| 197 | case e1000_82547: |
| 198 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
| 199 | |
| 200 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
| 201 | |
| 202 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
| 203 | |
| 204 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
| 205 | |
| 206 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
| 207 | |
| 208 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
| 209 | |
| 210 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
| 211 | |
| 212 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
| 213 | |
| 214 | e1000_write_phy_reg(hw, 0x2010, 0x0008); |
| 215 | break; |
| 216 | |
| 217 | case e1000_82541_rev_2: |
| 218 | case e1000_82547_rev_2: |
| 219 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
| 220 | break; |
| 221 | default: |
| 222 | break; |
| 223 | } |
| 224 | |
| 225 | e1000_write_phy_reg(hw, 0x0000, 0x3300); |
| 226 | |
| 227 | msec_delay(20); |
| 228 | |
| 229 | /* Now enable the transmitter */ |
| 230 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 231 | |
| 232 | if(hw->mac_type == e1000_82547) { |
| 233 | uint16_t fused, fine, coarse; |
| 234 | |
| 235 | /* Move to analog registers page */ |
| 236 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); |
| 237 | |
| 238 | if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
| 239 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
| 240 | |
| 241 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
| 242 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
| 243 | |
| 244 | if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
| 245 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
| 246 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
| 247 | } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
| 248 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
| 249 | |
| 250 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
| 251 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
| 252 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
| 253 | |
| 254 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); |
| 255 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, |
| 256 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
| 257 | } |
| 258 | } |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | /****************************************************************************** |
| 263 | * Set the mac type member in the hw struct. |
| 264 | * |
| 265 | * hw - Struct containing variables accessed by shared code |
| 266 | *****************************************************************************/ |
| 267 | int32_t |
| 268 | e1000_set_mac_type(struct e1000_hw *hw) |
| 269 | { |
| 270 | DEBUGFUNC("e1000_set_mac_type"); |
| 271 | |
| 272 | switch (hw->device_id) { |
| 273 | case E1000_DEV_ID_82542: |
| 274 | switch (hw->revision_id) { |
| 275 | case E1000_82542_2_0_REV_ID: |
| 276 | hw->mac_type = e1000_82542_rev2_0; |
| 277 | break; |
| 278 | case E1000_82542_2_1_REV_ID: |
| 279 | hw->mac_type = e1000_82542_rev2_1; |
| 280 | break; |
| 281 | default: |
| 282 | /* Invalid 82542 revision ID */ |
| 283 | return -E1000_ERR_MAC_TYPE; |
| 284 | } |
| 285 | break; |
| 286 | case E1000_DEV_ID_82543GC_FIBER: |
| 287 | case E1000_DEV_ID_82543GC_COPPER: |
| 288 | hw->mac_type = e1000_82543; |
| 289 | break; |
| 290 | case E1000_DEV_ID_82544EI_COPPER: |
| 291 | case E1000_DEV_ID_82544EI_FIBER: |
| 292 | case E1000_DEV_ID_82544GC_COPPER: |
| 293 | case E1000_DEV_ID_82544GC_LOM: |
| 294 | hw->mac_type = e1000_82544; |
| 295 | break; |
| 296 | case E1000_DEV_ID_82540EM: |
| 297 | case E1000_DEV_ID_82540EM_LOM: |
| 298 | case E1000_DEV_ID_82540EP: |
| 299 | case E1000_DEV_ID_82540EP_LOM: |
| 300 | case E1000_DEV_ID_82540EP_LP: |
| 301 | hw->mac_type = e1000_82540; |
| 302 | break; |
| 303 | case E1000_DEV_ID_82545EM_COPPER: |
| 304 | case E1000_DEV_ID_82545EM_FIBER: |
| 305 | hw->mac_type = e1000_82545; |
| 306 | break; |
| 307 | case E1000_DEV_ID_82545GM_COPPER: |
| 308 | case E1000_DEV_ID_82545GM_FIBER: |
| 309 | case E1000_DEV_ID_82545GM_SERDES: |
| 310 | hw->mac_type = e1000_82545_rev_3; |
| 311 | break; |
| 312 | case E1000_DEV_ID_82546EB_COPPER: |
| 313 | case E1000_DEV_ID_82546EB_FIBER: |
| 314 | case E1000_DEV_ID_82546EB_QUAD_COPPER: |
| 315 | hw->mac_type = e1000_82546; |
| 316 | break; |
| 317 | case E1000_DEV_ID_82546GB_COPPER: |
| 318 | case E1000_DEV_ID_82546GB_FIBER: |
| 319 | case E1000_DEV_ID_82546GB_SERDES: |
| 320 | case E1000_DEV_ID_82546GB_PCIE: |
Jeff Kirsher | b7ee49d | 2006-01-12 16:51:21 -0800 | [diff] [blame] | 321 | case E1000_DEV_ID_82546GB_QUAD_COPPER: |
| 322 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | hw->mac_type = e1000_82546_rev_3; |
| 324 | break; |
| 325 | case E1000_DEV_ID_82541EI: |
| 326 | case E1000_DEV_ID_82541EI_MOBILE: |
| 327 | hw->mac_type = e1000_82541; |
| 328 | break; |
| 329 | case E1000_DEV_ID_82541ER: |
| 330 | case E1000_DEV_ID_82541GI: |
| 331 | case E1000_DEV_ID_82541GI_LF: |
| 332 | case E1000_DEV_ID_82541GI_MOBILE: |
| 333 | hw->mac_type = e1000_82541_rev_2; |
| 334 | break; |
| 335 | case E1000_DEV_ID_82547EI: |
| 336 | hw->mac_type = e1000_82547; |
| 337 | break; |
| 338 | case E1000_DEV_ID_82547GI: |
| 339 | hw->mac_type = e1000_82547_rev_2; |
| 340 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 341 | case E1000_DEV_ID_82571EB_COPPER: |
| 342 | case E1000_DEV_ID_82571EB_FIBER: |
| 343 | case E1000_DEV_ID_82571EB_SERDES: |
| 344 | hw->mac_type = e1000_82571; |
| 345 | break; |
| 346 | case E1000_DEV_ID_82572EI_COPPER: |
| 347 | case E1000_DEV_ID_82572EI_FIBER: |
| 348 | case E1000_DEV_ID_82572EI_SERDES: |
| 349 | hw->mac_type = e1000_82572; |
| 350 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 351 | case E1000_DEV_ID_82573E: |
| 352 | case E1000_DEV_ID_82573E_IAMT: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 353 | case E1000_DEV_ID_82573L: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 354 | hw->mac_type = e1000_82573; |
| 355 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | default: |
| 357 | /* Should never have loaded on this device */ |
| 358 | return -E1000_ERR_MAC_TYPE; |
| 359 | } |
| 360 | |
| 361 | switch(hw->mac_type) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 362 | case e1000_82571: |
| 363 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 364 | case e1000_82573: |
| 365 | hw->eeprom_semaphore_present = TRUE; |
| 366 | /* fall through */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | case e1000_82541: |
| 368 | case e1000_82547: |
| 369 | case e1000_82541_rev_2: |
| 370 | case e1000_82547_rev_2: |
| 371 | hw->asf_firmware_present = TRUE; |
| 372 | break; |
| 373 | default: |
| 374 | break; |
| 375 | } |
| 376 | |
| 377 | return E1000_SUCCESS; |
| 378 | } |
| 379 | |
| 380 | /***************************************************************************** |
| 381 | * Set media type and TBI compatibility. |
| 382 | * |
| 383 | * hw - Struct containing variables accessed by shared code |
| 384 | * **************************************************************************/ |
| 385 | void |
| 386 | e1000_set_media_type(struct e1000_hw *hw) |
| 387 | { |
| 388 | uint32_t status; |
| 389 | |
| 390 | DEBUGFUNC("e1000_set_media_type"); |
| 391 | |
| 392 | if(hw->mac_type != e1000_82543) { |
| 393 | /* tbi_compatibility is only valid on 82543 */ |
| 394 | hw->tbi_compatibility_en = FALSE; |
| 395 | } |
| 396 | |
| 397 | switch (hw->device_id) { |
| 398 | case E1000_DEV_ID_82545GM_SERDES: |
| 399 | case E1000_DEV_ID_82546GB_SERDES: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 400 | case E1000_DEV_ID_82571EB_SERDES: |
| 401 | case E1000_DEV_ID_82572EI_SERDES: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | hw->media_type = e1000_media_type_internal_serdes; |
| 403 | break; |
| 404 | default: |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 405 | switch (hw->mac_type) { |
| 406 | case e1000_82542_rev2_0: |
| 407 | case e1000_82542_rev2_1: |
| 408 | hw->media_type = e1000_media_type_fiber; |
| 409 | break; |
| 410 | case e1000_82573: |
| 411 | /* The STATUS_TBIMODE bit is reserved or reused for the this |
| 412 | * device. |
| 413 | */ |
| 414 | hw->media_type = e1000_media_type_copper; |
| 415 | break; |
| 416 | default: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | status = E1000_READ_REG(hw, STATUS); |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 418 | if (status & E1000_STATUS_TBIMODE) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | hw->media_type = e1000_media_type_fiber; |
| 420 | /* tbi_compatibility not valid on fiber */ |
| 421 | hw->tbi_compatibility_en = FALSE; |
| 422 | } else { |
| 423 | hw->media_type = e1000_media_type_copper; |
| 424 | } |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 425 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 426 | } |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | /****************************************************************************** |
| 431 | * Reset the transmit and receive units; mask and clear all interrupts. |
| 432 | * |
| 433 | * hw - Struct containing variables accessed by shared code |
| 434 | *****************************************************************************/ |
| 435 | int32_t |
| 436 | e1000_reset_hw(struct e1000_hw *hw) |
| 437 | { |
| 438 | uint32_t ctrl; |
| 439 | uint32_t ctrl_ext; |
| 440 | uint32_t icr; |
| 441 | uint32_t manc; |
| 442 | uint32_t led_ctrl; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 443 | uint32_t timeout; |
| 444 | uint32_t extcnf_ctrl; |
| 445 | int32_t ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | |
| 447 | DEBUGFUNC("e1000_reset_hw"); |
| 448 | |
| 449 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
| 450 | if(hw->mac_type == e1000_82542_rev2_0) { |
| 451 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
| 452 | e1000_pci_clear_mwi(hw); |
| 453 | } |
| 454 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 455 | if(hw->bus_type == e1000_bus_type_pci_express) { |
| 456 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
| 457 | * on the last TLP read/write transaction when MAC is reset. |
| 458 | */ |
| 459 | if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { |
| 460 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
| 461 | } |
| 462 | } |
| 463 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 465 | DEBUGOUT("Masking off all interrupts\n"); |
| 466 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 467 | |
| 468 | /* Disable the Transmit and Receive units. Then delay to allow |
| 469 | * any pending transactions to complete before we hit the MAC with |
| 470 | * the global reset. |
| 471 | */ |
| 472 | E1000_WRITE_REG(hw, RCTL, 0); |
| 473 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); |
| 474 | E1000_WRITE_FLUSH(hw); |
| 475 | |
| 476 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
| 477 | hw->tbi_compatibility_on = FALSE; |
| 478 | |
| 479 | /* Delay to allow any outstanding PCI transactions to complete before |
| 480 | * resetting the device |
| 481 | */ |
| 482 | msec_delay(10); |
| 483 | |
| 484 | ctrl = E1000_READ_REG(hw, CTRL); |
| 485 | |
| 486 | /* Must reset the PHY before resetting the MAC */ |
| 487 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 488 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | msec_delay(5); |
| 490 | } |
| 491 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 492 | /* Must acquire the MDIO ownership before MAC reset. |
| 493 | * Ownership defaults to firmware after a reset. */ |
| 494 | if(hw->mac_type == e1000_82573) { |
| 495 | timeout = 10; |
| 496 | |
| 497 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 498 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
| 499 | |
| 500 | do { |
| 501 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
| 502 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 503 | |
| 504 | if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
| 505 | break; |
| 506 | else |
| 507 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
| 508 | |
| 509 | msec_delay(2); |
| 510 | timeout--; |
| 511 | } while(timeout); |
| 512 | } |
| 513 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | /* Issue a global reset to the MAC. This will reset the chip's |
| 515 | * transmit, receive, DMA, and link units. It will not effect |
| 516 | * the current PCI configuration. The global reset bit is self- |
| 517 | * clearing, and should clear within a microsecond. |
| 518 | */ |
| 519 | DEBUGOUT("Issuing a global reset to MAC\n"); |
| 520 | |
| 521 | switch(hw->mac_type) { |
| 522 | case e1000_82544: |
| 523 | case e1000_82540: |
| 524 | case e1000_82545: |
| 525 | case e1000_82546: |
| 526 | case e1000_82541: |
| 527 | case e1000_82541_rev_2: |
| 528 | /* These controllers can't ack the 64-bit write when issuing the |
| 529 | * reset, so use IO-mapping as a workaround to issue the reset */ |
| 530 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
| 531 | break; |
| 532 | case e1000_82545_rev_3: |
| 533 | case e1000_82546_rev_3: |
| 534 | /* Reset is performed on a shadow of the control register */ |
| 535 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
| 536 | break; |
| 537 | default: |
| 538 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
| 539 | break; |
| 540 | } |
| 541 | |
| 542 | /* After MAC reset, force reload of EEPROM to restore power-on settings to |
| 543 | * device. Later controllers reload the EEPROM automatically, so just wait |
| 544 | * for reload to complete. |
| 545 | */ |
| 546 | switch(hw->mac_type) { |
| 547 | case e1000_82542_rev2_0: |
| 548 | case e1000_82542_rev2_1: |
| 549 | case e1000_82543: |
| 550 | case e1000_82544: |
| 551 | /* Wait for reset to complete */ |
| 552 | udelay(10); |
| 553 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 554 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 555 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 556 | E1000_WRITE_FLUSH(hw); |
| 557 | /* Wait for EEPROM reload */ |
| 558 | msec_delay(2); |
| 559 | break; |
| 560 | case e1000_82541: |
| 561 | case e1000_82541_rev_2: |
| 562 | case e1000_82547: |
| 563 | case e1000_82547_rev_2: |
| 564 | /* Wait for EEPROM reload */ |
| 565 | msec_delay(20); |
| 566 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 567 | case e1000_82573: |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 568 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
| 569 | udelay(10); |
| 570 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 571 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 572 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 573 | E1000_WRITE_FLUSH(hw); |
| 574 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 575 | /* fall through */ |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 576 | case e1000_82571: |
| 577 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 578 | ret_val = e1000_get_auto_rd_done(hw); |
| 579 | if(ret_val) |
| 580 | /* We don't want to continue accessing MAC registers. */ |
| 581 | return ret_val; |
| 582 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | default: |
| 584 | /* Wait for EEPROM reload (it happens automatically) */ |
| 585 | msec_delay(5); |
| 586 | break; |
| 587 | } |
| 588 | |
| 589 | /* Disable HW ARPs on ASF enabled adapters */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 590 | if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | manc = E1000_READ_REG(hw, MANC); |
| 592 | manc &= ~(E1000_MANC_ARP_EN); |
| 593 | E1000_WRITE_REG(hw, MANC, manc); |
| 594 | } |
| 595 | |
| 596 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
| 597 | e1000_phy_init_script(hw); |
| 598 | |
| 599 | /* Configure activity LED after PHY reset */ |
| 600 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 601 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 602 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 603 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 604 | } |
| 605 | |
| 606 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 607 | DEBUGOUT("Masking off all interrupts\n"); |
| 608 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 609 | |
| 610 | /* Clear any pending interrupt events. */ |
| 611 | icr = E1000_READ_REG(hw, ICR); |
| 612 | |
| 613 | /* If MWI was previously enabled, reenable it. */ |
| 614 | if(hw->mac_type == e1000_82542_rev2_0) { |
| 615 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) |
| 616 | e1000_pci_set_mwi(hw); |
| 617 | } |
| 618 | |
| 619 | return E1000_SUCCESS; |
| 620 | } |
| 621 | |
| 622 | /****************************************************************************** |
| 623 | * Performs basic configuration of the adapter. |
| 624 | * |
| 625 | * hw - Struct containing variables accessed by shared code |
| 626 | * |
| 627 | * Assumes that the controller has previously been reset and is in a |
| 628 | * post-reset uninitialized state. Initializes the receive address registers, |
| 629 | * multicast table, and VLAN filter table. Calls routines to setup link |
| 630 | * configuration and flow control settings. Clears all on-chip counters. Leaves |
| 631 | * the transmit and receive units disabled and uninitialized. |
| 632 | *****************************************************************************/ |
| 633 | int32_t |
| 634 | e1000_init_hw(struct e1000_hw *hw) |
| 635 | { |
| 636 | uint32_t ctrl; |
| 637 | uint32_t i; |
| 638 | int32_t ret_val; |
| 639 | uint16_t pcix_cmd_word; |
| 640 | uint16_t pcix_stat_hi_word; |
| 641 | uint16_t cmd_mmrbc; |
| 642 | uint16_t stat_mmrbc; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 643 | uint32_t mta_size; |
Jeff Kirsher | b7ee49d | 2006-01-12 16:51:21 -0800 | [diff] [blame] | 644 | uint32_t ctrl_ext; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 645 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | DEBUGFUNC("e1000_init_hw"); |
| 647 | |
| 648 | /* Initialize Identification LED */ |
| 649 | ret_val = e1000_id_led_init(hw); |
| 650 | if(ret_val) { |
| 651 | DEBUGOUT("Error Initializing Identification LED\n"); |
| 652 | return ret_val; |
| 653 | } |
| 654 | |
| 655 | /* Set the media type and TBI compatibility */ |
| 656 | e1000_set_media_type(hw); |
| 657 | |
| 658 | /* Disabling VLAN filtering. */ |
| 659 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 660 | if (hw->mac_type < e1000_82545_rev_3) |
| 661 | E1000_WRITE_REG(hw, VET, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | e1000_clear_vfta(hw); |
| 663 | |
| 664 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
| 665 | if(hw->mac_type == e1000_82542_rev2_0) { |
| 666 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
| 667 | e1000_pci_clear_mwi(hw); |
| 668 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
| 669 | E1000_WRITE_FLUSH(hw); |
| 670 | msec_delay(5); |
| 671 | } |
| 672 | |
| 673 | /* Setup the receive address. This involves initializing all of the Receive |
| 674 | * Address Registers (RARs 0 - 15). |
| 675 | */ |
| 676 | e1000_init_rx_addrs(hw); |
| 677 | |
| 678 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
| 679 | if(hw->mac_type == e1000_82542_rev2_0) { |
| 680 | E1000_WRITE_REG(hw, RCTL, 0); |
| 681 | E1000_WRITE_FLUSH(hw); |
| 682 | msec_delay(1); |
| 683 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) |
| 684 | e1000_pci_set_mwi(hw); |
| 685 | } |
| 686 | |
| 687 | /* Zero out the Multicast HASH table */ |
| 688 | DEBUGOUT("Zeroing the MTA\n"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 689 | mta_size = E1000_MC_TBL_SIZE; |
| 690 | for(i = 0; i < mta_size; i++) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 691 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
| 692 | |
| 693 | /* Set the PCI priority bit correctly in the CTRL register. This |
| 694 | * determines if the adapter gives priority to receives, or if it |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 695 | * gives equal priority to transmits and receives. Valid only on |
| 696 | * 82542 and 82543 silicon. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 698 | if(hw->dma_fairness && hw->mac_type <= e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | ctrl = E1000_READ_REG(hw, CTRL); |
| 700 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); |
| 701 | } |
| 702 | |
| 703 | switch(hw->mac_type) { |
| 704 | case e1000_82545_rev_3: |
| 705 | case e1000_82546_rev_3: |
| 706 | break; |
| 707 | default: |
| 708 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
| 709 | if(hw->bus_type == e1000_bus_type_pcix) { |
| 710 | e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); |
| 711 | e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, |
| 712 | &pcix_stat_hi_word); |
| 713 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> |
| 714 | PCIX_COMMAND_MMRBC_SHIFT; |
| 715 | stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> |
| 716 | PCIX_STATUS_HI_MMRBC_SHIFT; |
| 717 | if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) |
| 718 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; |
| 719 | if(cmd_mmrbc > stat_mmrbc) { |
| 720 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; |
| 721 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; |
| 722 | e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, |
| 723 | &pcix_cmd_word); |
| 724 | } |
| 725 | } |
| 726 | break; |
| 727 | } |
| 728 | |
| 729 | /* Call a subroutine to configure the link and setup flow control. */ |
| 730 | ret_val = e1000_setup_link(hw); |
| 731 | |
| 732 | /* Set the transmit descriptor write-back policy */ |
| 733 | if(hw->mac_type > e1000_82544) { |
| 734 | ctrl = E1000_READ_REG(hw, TXDCTL); |
| 735 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 736 | switch (hw->mac_type) { |
| 737 | default: |
| 738 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 739 | case e1000_82571: |
| 740 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 741 | case e1000_82573: |
| 742 | ctrl |= E1000_TXDCTL_COUNT_DESC; |
| 743 | break; |
| 744 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
| 746 | } |
| 747 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 748 | if (hw->mac_type == e1000_82573) { |
| 749 | e1000_enable_tx_pkt_filtering(hw); |
| 750 | } |
| 751 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 752 | switch (hw->mac_type) { |
| 753 | default: |
| 754 | break; |
| 755 | case e1000_82571: |
Mallikarjuna R Chilakala | a7990ba | 2005-10-04 07:08:19 -0400 | [diff] [blame] | 756 | case e1000_82572: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 757 | ctrl = E1000_READ_REG(hw, TXDCTL1); |
| 758 | ctrl &= ~E1000_TXDCTL_WTHRESH; |
| 759 | ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB; |
| 760 | ctrl |= (1 << 22); |
| 761 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
| 762 | break; |
| 763 | } |
| 764 | |
| 765 | |
| 766 | |
| 767 | if (hw->mac_type == e1000_82573) { |
| 768 | uint32_t gcr = E1000_READ_REG(hw, GCR); |
| 769 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
| 770 | E1000_WRITE_REG(hw, GCR, gcr); |
| 771 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 772 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | /* Clear all of the statistics registers (clear on read). It is |
| 774 | * important that we do this after we have tried to establish link |
| 775 | * because the symbol error count will increment wildly if there |
| 776 | * is no link. |
| 777 | */ |
| 778 | e1000_clear_hw_cntrs(hw); |
| 779 | |
Jeff Kirsher | b7ee49d | 2006-01-12 16:51:21 -0800 | [diff] [blame] | 780 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
| 781 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
| 782 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 783 | /* Relaxed ordering must be disabled to avoid a parity |
| 784 | * error crash in a PCI slot. */ |
| 785 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
| 786 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 787 | } |
| 788 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 789 | return ret_val; |
| 790 | } |
| 791 | |
| 792 | /****************************************************************************** |
| 793 | * Adjust SERDES output amplitude based on EEPROM setting. |
| 794 | * |
| 795 | * hw - Struct containing variables accessed by shared code. |
| 796 | *****************************************************************************/ |
| 797 | static int32_t |
| 798 | e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
| 799 | { |
| 800 | uint16_t eeprom_data; |
| 801 | int32_t ret_val; |
| 802 | |
| 803 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); |
| 804 | |
| 805 | if(hw->media_type != e1000_media_type_internal_serdes) |
| 806 | return E1000_SUCCESS; |
| 807 | |
| 808 | switch(hw->mac_type) { |
| 809 | case e1000_82545_rev_3: |
| 810 | case e1000_82546_rev_3: |
| 811 | break; |
| 812 | default: |
| 813 | return E1000_SUCCESS; |
| 814 | } |
| 815 | |
| 816 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); |
| 817 | if (ret_val) { |
| 818 | return ret_val; |
| 819 | } |
| 820 | |
| 821 | if(eeprom_data != EEPROM_RESERVED_WORD) { |
| 822 | /* Adjust SERDES output amplitude only. */ |
| 823 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
| 824 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
| 825 | if(ret_val) |
| 826 | return ret_val; |
| 827 | } |
| 828 | |
| 829 | return E1000_SUCCESS; |
| 830 | } |
| 831 | |
| 832 | /****************************************************************************** |
| 833 | * Configures flow control and link settings. |
| 834 | * |
| 835 | * hw - Struct containing variables accessed by shared code |
| 836 | * |
| 837 | * Determines which flow control settings to use. Calls the apropriate media- |
| 838 | * specific link configuration function. Configures the flow control settings. |
| 839 | * Assuming the adapter has a valid link partner, a valid link should be |
| 840 | * established. Assumes the hardware has previously been reset and the |
| 841 | * transmitter and receiver are not enabled. |
| 842 | *****************************************************************************/ |
| 843 | int32_t |
| 844 | e1000_setup_link(struct e1000_hw *hw) |
| 845 | { |
| 846 | uint32_t ctrl_ext; |
| 847 | int32_t ret_val; |
| 848 | uint16_t eeprom_data; |
| 849 | |
| 850 | DEBUGFUNC("e1000_setup_link"); |
| 851 | |
Jeff Kirsher | 526f995 | 2006-01-12 16:50:46 -0800 | [diff] [blame] | 852 | /* In the case of the phy reset being blocked, we already have a link. |
| 853 | * We do not have to set it up again. */ |
| 854 | if (e1000_check_phy_reset_block(hw)) |
| 855 | return E1000_SUCCESS; |
| 856 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
| 858 | * that determine the hardware's default PAUSE (flow control) mode, |
| 859 | * a bit that determines whether the HW defaults to enabling or |
| 860 | * disabling auto-negotiation, and the direction of the |
| 861 | * SW defined pins. If there is no SW over-ride of the flow |
| 862 | * control setting, then the variable hw->fc will |
| 863 | * be initialized based on a value in the EEPROM. |
| 864 | */ |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 865 | if (hw->fc == e1000_fc_default) { |
| 866 | switch (hw->mac_type) { |
| 867 | case e1000_82573: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 868 | hw->fc = e1000_fc_full; |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 869 | break; |
| 870 | default: |
| 871 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
| 872 | 1, &eeprom_data); |
| 873 | if (ret_val) { |
| 874 | DEBUGOUT("EEPROM Read Error\n"); |
| 875 | return -E1000_ERR_EEPROM; |
| 876 | } |
| 877 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
| 878 | hw->fc = e1000_fc_none; |
| 879 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
| 880 | EEPROM_WORD0F_ASM_DIR) |
| 881 | hw->fc = e1000_fc_tx_pause; |
| 882 | else |
| 883 | hw->fc = e1000_fc_full; |
| 884 | break; |
| 885 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | /* We want to save off the original Flow Control configuration just |
| 889 | * in case we get disconnected and then reconnected into a different |
| 890 | * hub or switch with different Flow Control capabilities. |
| 891 | */ |
| 892 | if(hw->mac_type == e1000_82542_rev2_0) |
| 893 | hw->fc &= (~e1000_fc_tx_pause); |
| 894 | |
| 895 | if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
| 896 | hw->fc &= (~e1000_fc_rx_pause); |
| 897 | |
| 898 | hw->original_fc = hw->fc; |
| 899 | |
| 900 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); |
| 901 | |
| 902 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
| 903 | * polarity value for the SW controlled pins, and setup the |
| 904 | * Extended Device Control reg with that info. |
| 905 | * This is needed because one of the SW controlled pins is used for |
| 906 | * signal detection. So this should be done before e1000_setup_pcs_link() |
| 907 | * or e1000_phy_setup() is called. |
| 908 | */ |
| 909 | if(hw->mac_type == e1000_82543) { |
| 910 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
| 911 | SWDPIO__EXT_SHIFT); |
| 912 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 913 | } |
| 914 | |
| 915 | /* Call the necessary subroutine to configure the link. */ |
| 916 | ret_val = (hw->media_type == e1000_media_type_copper) ? |
| 917 | e1000_setup_copper_link(hw) : |
| 918 | e1000_setup_fiber_serdes_link(hw); |
| 919 | |
| 920 | /* Initialize the flow control address, type, and PAUSE timer |
| 921 | * registers to their default values. This is done even if flow |
| 922 | * control is disabled, because it does not hurt anything to |
| 923 | * initialize these registers. |
| 924 | */ |
| 925 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); |
| 926 | |
| 927 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 928 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 929 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 930 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
| 932 | |
| 933 | /* Set the flow control receive threshold registers. Normally, |
| 934 | * these registers will be set to a default threshold that may be |
| 935 | * adjusted later by the driver's runtime code. However, if the |
| 936 | * ability to transmit pause frames in not enabled, then these |
| 937 | * registers will be set to 0. |
| 938 | */ |
| 939 | if(!(hw->fc & e1000_fc_tx_pause)) { |
| 940 | E1000_WRITE_REG(hw, FCRTL, 0); |
| 941 | E1000_WRITE_REG(hw, FCRTH, 0); |
| 942 | } else { |
| 943 | /* We need to set up the Receive Threshold high and low water marks |
| 944 | * as well as (optionally) enabling the transmission of XON frames. |
| 945 | */ |
| 946 | if(hw->fc_send_xon) { |
| 947 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
| 948 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
| 949 | } else { |
| 950 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); |
| 951 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
| 952 | } |
| 953 | } |
| 954 | return ret_val; |
| 955 | } |
| 956 | |
| 957 | /****************************************************************************** |
| 958 | * Sets up link for a fiber based or serdes based adapter |
| 959 | * |
| 960 | * hw - Struct containing variables accessed by shared code |
| 961 | * |
| 962 | * Manipulates Physical Coding Sublayer functions in order to configure |
| 963 | * link. Assumes the hardware has been previously reset and the transmitter |
| 964 | * and receiver are not enabled. |
| 965 | *****************************************************************************/ |
| 966 | static int32_t |
| 967 | e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
| 968 | { |
| 969 | uint32_t ctrl; |
| 970 | uint32_t status; |
| 971 | uint32_t txcw = 0; |
| 972 | uint32_t i; |
| 973 | uint32_t signal = 0; |
| 974 | int32_t ret_val; |
| 975 | |
| 976 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); |
| 977 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 978 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
| 979 | * until explicitly turned off or a power cycle is performed. A read to |
| 980 | * the register does not indicate its status. Therefore, we ensure |
| 981 | * loopback mode is disabled during initialization. |
| 982 | */ |
| 983 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) |
| 984 | E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); |
| 985 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
| 987 | * set when the optics detect a signal. On older adapters, it will be |
| 988 | * cleared when there is a signal. This applies to fiber media only. |
| 989 | * If we're on serdes media, adjust the output amplitude to value set in |
| 990 | * the EEPROM. |
| 991 | */ |
| 992 | ctrl = E1000_READ_REG(hw, CTRL); |
| 993 | if(hw->media_type == e1000_media_type_fiber) |
| 994 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
| 995 | |
| 996 | ret_val = e1000_adjust_serdes_amplitude(hw); |
| 997 | if(ret_val) |
| 998 | return ret_val; |
| 999 | |
| 1000 | /* Take the link out of reset */ |
| 1001 | ctrl &= ~(E1000_CTRL_LRST); |
| 1002 | |
| 1003 | /* Adjust VCO speed to improve BER performance */ |
| 1004 | ret_val = e1000_set_vco_speed(hw); |
| 1005 | if(ret_val) |
| 1006 | return ret_val; |
| 1007 | |
| 1008 | e1000_config_collision_dist(hw); |
| 1009 | |
| 1010 | /* Check for a software override of the flow control settings, and setup |
| 1011 | * the device accordingly. If auto-negotiation is enabled, then software |
| 1012 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
| 1013 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
| 1014 | * auto-negotiation is disabled, then software will have to manually |
| 1015 | * configure the two flow control enable bits in the CTRL register. |
| 1016 | * |
| 1017 | * The possible values of the "fc" parameter are: |
| 1018 | * 0: Flow control is completely disabled |
| 1019 | * 1: Rx flow control is enabled (we can receive pause frames, but |
| 1020 | * not send pause frames). |
| 1021 | * 2: Tx flow control is enabled (we can send pause frames but we do |
| 1022 | * not support receiving pause frames). |
| 1023 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
| 1024 | */ |
| 1025 | switch (hw->fc) { |
| 1026 | case e1000_fc_none: |
| 1027 | /* Flow control is completely disabled by a software over-ride. */ |
| 1028 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
| 1029 | break; |
| 1030 | case e1000_fc_rx_pause: |
| 1031 | /* RX Flow control is enabled and TX Flow control is disabled by a |
| 1032 | * software over-ride. Since there really isn't a way to advertise |
| 1033 | * that we are capable of RX Pause ONLY, we will advertise that we |
| 1034 | * support both symmetric and asymmetric RX PAUSE. Later, we will |
| 1035 | * disable the adapter's ability to send PAUSE frames. |
| 1036 | */ |
| 1037 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 1038 | break; |
| 1039 | case e1000_fc_tx_pause: |
| 1040 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
| 1041 | * software over-ride. |
| 1042 | */ |
| 1043 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
| 1044 | break; |
| 1045 | case e1000_fc_full: |
| 1046 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
| 1047 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 1048 | break; |
| 1049 | default: |
| 1050 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 1051 | return -E1000_ERR_CONFIG; |
| 1052 | break; |
| 1053 | } |
| 1054 | |
| 1055 | /* Since auto-negotiation is enabled, take the link out of reset (the link |
| 1056 | * will be in reset, because we previously reset the chip). This will |
| 1057 | * restart auto-negotiation. If auto-neogtiation is successful then the |
| 1058 | * link-up status bit will be set and the flow control enable bits (RFCE |
| 1059 | * and TFCE) will be set according to their negotiated value. |
| 1060 | */ |
| 1061 | DEBUGOUT("Auto-negotiation enabled\n"); |
| 1062 | |
| 1063 | E1000_WRITE_REG(hw, TXCW, txcw); |
| 1064 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 1065 | E1000_WRITE_FLUSH(hw); |
| 1066 | |
| 1067 | hw->txcw = txcw; |
| 1068 | msec_delay(1); |
| 1069 | |
| 1070 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
| 1071 | * indication in the Device Status Register. Time-out if a link isn't |
| 1072 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
| 1073 | * less than 500 milliseconds even if the other end is doing it in SW). |
| 1074 | * For internal serdes, we just assume a signal is present, then poll. |
| 1075 | */ |
| 1076 | if(hw->media_type == e1000_media_type_internal_serdes || |
| 1077 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
| 1078 | DEBUGOUT("Looking for Link\n"); |
| 1079 | for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
| 1080 | msec_delay(10); |
| 1081 | status = E1000_READ_REG(hw, STATUS); |
| 1082 | if(status & E1000_STATUS_LU) break; |
| 1083 | } |
| 1084 | if(i == (LINK_UP_TIMEOUT / 10)) { |
| 1085 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
| 1086 | hw->autoneg_failed = 1; |
| 1087 | /* AutoNeg failed to achieve a link, so we'll call |
| 1088 | * e1000_check_for_link. This routine will force the link up if |
| 1089 | * we detect a signal. This will allow us to communicate with |
| 1090 | * non-autonegotiating link partners. |
| 1091 | */ |
| 1092 | ret_val = e1000_check_for_link(hw); |
| 1093 | if(ret_val) { |
| 1094 | DEBUGOUT("Error while checking for link\n"); |
| 1095 | return ret_val; |
| 1096 | } |
| 1097 | hw->autoneg_failed = 0; |
| 1098 | } else { |
| 1099 | hw->autoneg_failed = 0; |
| 1100 | DEBUGOUT("Valid Link Found\n"); |
| 1101 | } |
| 1102 | } else { |
| 1103 | DEBUGOUT("No Signal Detected\n"); |
| 1104 | } |
| 1105 | return E1000_SUCCESS; |
| 1106 | } |
| 1107 | |
| 1108 | /****************************************************************************** |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1109 | * Make sure we have a valid PHY and change PHY mode before link setup. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1110 | * |
| 1111 | * hw - Struct containing variables accessed by shared code |
| 1112 | ******************************************************************************/ |
| 1113 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1114 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | { |
| 1116 | uint32_t ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | int32_t ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | uint16_t phy_data; |
| 1119 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1120 | DEBUGFUNC("e1000_copper_link_preconfig"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | |
| 1122 | ctrl = E1000_READ_REG(hw, CTRL); |
| 1123 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
| 1124 | * the PHY speed and duplex configuration is. In addition, we need to |
| 1125 | * perform a hardware reset on the PHY to take it out of reset. |
| 1126 | */ |
| 1127 | if(hw->mac_type > e1000_82543) { |
| 1128 | ctrl |= E1000_CTRL_SLU; |
| 1129 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1130 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 1131 | } else { |
| 1132 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
| 1133 | E1000_WRITE_REG(hw, CTRL, ctrl); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1134 | ret_val = e1000_phy_hw_reset(hw); |
| 1135 | if(ret_val) |
| 1136 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1137 | } |
| 1138 | |
| 1139 | /* Make sure we have a valid PHY */ |
| 1140 | ret_val = e1000_detect_gig_phy(hw); |
| 1141 | if(ret_val) { |
| 1142 | DEBUGOUT("Error, did not detect valid phy.\n"); |
| 1143 | return ret_val; |
| 1144 | } |
| 1145 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
| 1146 | |
| 1147 | /* Set PHY to class A mode (if necessary) */ |
| 1148 | ret_val = e1000_set_phy_mode(hw); |
| 1149 | if(ret_val) |
| 1150 | return ret_val; |
| 1151 | |
| 1152 | if((hw->mac_type == e1000_82545_rev_3) || |
| 1153 | (hw->mac_type == e1000_82546_rev_3)) { |
| 1154 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1155 | phy_data |= 0x00000008; |
| 1156 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1157 | } |
| 1158 | |
| 1159 | if(hw->mac_type <= e1000_82543 || |
| 1160 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
| 1161 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) |
| 1162 | hw->phy_reset_disable = FALSE; |
| 1163 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1164 | return E1000_SUCCESS; |
| 1165 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1167 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1168 | /******************************************************************** |
| 1169 | * Copper link setup for e1000_phy_igp series. |
| 1170 | * |
| 1171 | * hw - Struct containing variables accessed by shared code |
| 1172 | *********************************************************************/ |
| 1173 | static int32_t |
| 1174 | e1000_copper_link_igp_setup(struct e1000_hw *hw) |
| 1175 | { |
| 1176 | uint32_t led_ctrl; |
| 1177 | int32_t ret_val; |
| 1178 | uint16_t phy_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1180 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1182 | if (hw->phy_reset_disable) |
| 1183 | return E1000_SUCCESS; |
| 1184 | |
| 1185 | ret_val = e1000_phy_reset(hw); |
| 1186 | if (ret_val) { |
| 1187 | DEBUGOUT("Error Resetting the PHY\n"); |
| 1188 | return ret_val; |
| 1189 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1190 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1191 | /* Wait 10ms for MAC to configure PHY from eeprom settings */ |
| 1192 | msec_delay(15); |
| 1193 | |
| 1194 | /* Configure activity LED after PHY reset */ |
| 1195 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 1196 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 1197 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 1198 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 1199 | |
| 1200 | /* disable lplu d3 during driver init */ |
| 1201 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); |
| 1202 | if (ret_val) { |
| 1203 | DEBUGOUT("Error Disabling LPLU D3\n"); |
| 1204 | return ret_val; |
| 1205 | } |
| 1206 | |
| 1207 | /* disable lplu d0 during driver init */ |
| 1208 | ret_val = e1000_set_d0_lplu_state(hw, FALSE); |
| 1209 | if (ret_val) { |
| 1210 | DEBUGOUT("Error Disabling LPLU D0\n"); |
| 1211 | return ret_val; |
| 1212 | } |
| 1213 | /* Configure mdi-mdix settings */ |
| 1214 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
| 1215 | if (ret_val) |
| 1216 | return ret_val; |
| 1217 | |
| 1218 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
| 1219 | hw->dsp_config_state = e1000_dsp_config_disabled; |
| 1220 | /* Force MDI for earlier revs of the IGP PHY */ |
| 1221 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
| 1222 | hw->mdix = 1; |
| 1223 | |
| 1224 | } else { |
| 1225 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 1226 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 1227 | |
| 1228 | switch (hw->mdix) { |
| 1229 | case 1: |
| 1230 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1231 | break; |
| 1232 | case 2: |
| 1233 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1234 | break; |
| 1235 | case 0: |
| 1236 | default: |
| 1237 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
| 1238 | break; |
| 1239 | } |
| 1240 | } |
| 1241 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
| 1242 | if(ret_val) |
| 1243 | return ret_val; |
| 1244 | |
| 1245 | /* set auto-master slave resolution settings */ |
| 1246 | if(hw->autoneg) { |
| 1247 | e1000_ms_type phy_ms_setting = hw->master_slave; |
| 1248 | |
| 1249 | if(hw->ffe_config_state == e1000_ffe_config_active) |
| 1250 | hw->ffe_config_state = e1000_ffe_config_enabled; |
| 1251 | |
| 1252 | if(hw->dsp_config_state == e1000_dsp_config_activated) |
| 1253 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 1254 | |
| 1255 | /* when autonegotiation advertisment is only 1000Mbps then we |
| 1256 | * should disable SmartSpeed and enable Auto MasterSlave |
| 1257 | * resolution as hardware default. */ |
| 1258 | if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
| 1259 | /* Disable SmartSpeed */ |
| 1260 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | if(ret_val) |
| 1262 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1263 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1264 | ret_val = e1000_write_phy_reg(hw, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | IGP01E1000_PHY_PORT_CONFIG, |
| 1266 | phy_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1267 | if(ret_val) |
| 1268 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1269 | /* Set auto Master/Slave resolution process */ |
| 1270 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
| 1271 | if(ret_val) |
| 1272 | return ret_val; |
| 1273 | phy_data &= ~CR_1000T_MS_ENABLE; |
| 1274 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
| 1275 | if(ret_val) |
| 1276 | return ret_val; |
| 1277 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1279 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
| 1280 | if(ret_val) |
| 1281 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1282 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1283 | /* load defaults for future use */ |
| 1284 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
| 1285 | ((phy_data & CR_1000T_MS_VALUE) ? |
| 1286 | e1000_ms_force_master : |
| 1287 | e1000_ms_force_slave) : |
| 1288 | e1000_ms_auto; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1290 | switch (phy_ms_setting) { |
| 1291 | case e1000_ms_force_master: |
| 1292 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
| 1293 | break; |
| 1294 | case e1000_ms_force_slave: |
| 1295 | phy_data |= CR_1000T_MS_ENABLE; |
| 1296 | phy_data &= ~(CR_1000T_MS_VALUE); |
| 1297 | break; |
| 1298 | case e1000_ms_auto: |
| 1299 | phy_data &= ~CR_1000T_MS_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1300 | default: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1301 | break; |
| 1302 | } |
| 1303 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
| 1304 | if(ret_val) |
| 1305 | return ret_val; |
Malli Chilakala | 2b02893 | 2005-06-17 17:46:06 -0700 | [diff] [blame] | 1306 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1307 | |
Malli Chilakala | 2b02893 | 2005-06-17 17:46:06 -0700 | [diff] [blame] | 1308 | return E1000_SUCCESS; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1309 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1310 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1311 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1312 | /******************************************************************** |
| 1313 | * Copper link setup for e1000_phy_m88 series. |
| 1314 | * |
| 1315 | * hw - Struct containing variables accessed by shared code |
| 1316 | *********************************************************************/ |
| 1317 | static int32_t |
| 1318 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
| 1319 | { |
| 1320 | int32_t ret_val; |
| 1321 | uint16_t phy_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1322 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1323 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
| 1324 | |
| 1325 | if(hw->phy_reset_disable) |
| 1326 | return E1000_SUCCESS; |
| 1327 | |
| 1328 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 1329 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1330 | if(ret_val) |
| 1331 | return ret_val; |
| 1332 | |
| 1333 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 1334 | |
| 1335 | /* Options: |
| 1336 | * MDI/MDI-X = 0 (default) |
| 1337 | * 0 - Auto for all speeds |
| 1338 | * 1 - MDI mode |
| 1339 | * 2 - MDI-X mode |
| 1340 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 1341 | */ |
| 1342 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 1343 | |
| 1344 | switch (hw->mdix) { |
| 1345 | case 1: |
| 1346 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 1347 | break; |
| 1348 | case 2: |
| 1349 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 1350 | break; |
| 1351 | case 3: |
| 1352 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 1353 | break; |
| 1354 | case 0: |
| 1355 | default: |
| 1356 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 1357 | break; |
| 1358 | } |
| 1359 | |
| 1360 | /* Options: |
| 1361 | * disable_polarity_correction = 0 (default) |
| 1362 | * Automatic Correction for Reversed Cable Polarity |
| 1363 | * 0 - Disabled |
| 1364 | * 1 - Enabled |
| 1365 | */ |
| 1366 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
| 1367 | if(hw->disable_polarity_correction == 1) |
| 1368 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
| 1369 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1370 | if(ret_val) |
| 1371 | return ret_val; |
| 1372 | |
| 1373 | /* Force TX_CLK in the Extended PHY Specific Control Register |
| 1374 | * to 25MHz clock. |
| 1375 | */ |
| 1376 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 1377 | if(ret_val) |
| 1378 | return ret_val; |
| 1379 | |
| 1380 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 1381 | |
| 1382 | if (hw->phy_revision < M88E1011_I_REV_4) { |
| 1383 | /* Configure Master and Slave downshift values */ |
| 1384 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1385 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1386 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1388 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 1389 | if(ret_val) |
| 1390 | return ret_val; |
| 1391 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1392 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1393 | /* SW Reset the PHY so all changes take effect */ |
| 1394 | ret_val = e1000_phy_reset(hw); |
| 1395 | if(ret_val) { |
| 1396 | DEBUGOUT("Error Resetting the PHY\n"); |
| 1397 | return ret_val; |
| 1398 | } |
| 1399 | |
| 1400 | return E1000_SUCCESS; |
| 1401 | } |
| 1402 | |
| 1403 | /******************************************************************** |
| 1404 | * Setup auto-negotiation and flow control advertisements, |
| 1405 | * and then perform auto-negotiation. |
| 1406 | * |
| 1407 | * hw - Struct containing variables accessed by shared code |
| 1408 | *********************************************************************/ |
| 1409 | static int32_t |
| 1410 | e1000_copper_link_autoneg(struct e1000_hw *hw) |
| 1411 | { |
| 1412 | int32_t ret_val; |
| 1413 | uint16_t phy_data; |
| 1414 | |
| 1415 | DEBUGFUNC("e1000_copper_link_autoneg"); |
| 1416 | |
| 1417 | /* Perform some bounds checking on the hw->autoneg_advertised |
| 1418 | * parameter. If this variable is zero, then set it to the default. |
| 1419 | */ |
| 1420 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 1421 | |
| 1422 | /* If autoneg_advertised is zero, we assume it was not defaulted |
| 1423 | * by the calling code so we set to advertise full capability. |
| 1424 | */ |
| 1425 | if(hw->autoneg_advertised == 0) |
| 1426 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 1427 | |
| 1428 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
| 1429 | ret_val = e1000_phy_setup_autoneg(hw); |
| 1430 | if(ret_val) { |
| 1431 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
| 1432 | return ret_val; |
| 1433 | } |
| 1434 | DEBUGOUT("Restarting Auto-Neg\n"); |
| 1435 | |
| 1436 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
| 1437 | * the Auto Neg Restart bit in the PHY control register. |
| 1438 | */ |
| 1439 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
| 1440 | if(ret_val) |
| 1441 | return ret_val; |
| 1442 | |
| 1443 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
| 1444 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
| 1445 | if(ret_val) |
| 1446 | return ret_val; |
| 1447 | |
| 1448 | /* Does the user want to wait for Auto-Neg to complete here, or |
| 1449 | * check at a later time (for example, callback routine). |
| 1450 | */ |
| 1451 | if(hw->wait_autoneg_complete) { |
| 1452 | ret_val = e1000_wait_autoneg(hw); |
| 1453 | if(ret_val) { |
| 1454 | DEBUGOUT("Error while waiting for autoneg to complete\n"); |
| 1455 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1456 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1457 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1458 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1459 | hw->get_link_status = TRUE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1460 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1461 | return E1000_SUCCESS; |
| 1462 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1463 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1464 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1465 | /****************************************************************************** |
| 1466 | * Config the MAC and the PHY after link is up. |
| 1467 | * 1) Set up the MAC to the current PHY speed/duplex |
| 1468 | * if we are on 82543. If we |
| 1469 | * are on newer silicon, we only need to configure |
| 1470 | * collision distance in the Transmit Control Register. |
| 1471 | * 2) Set up flow control on the MAC to that established with |
| 1472 | * the link partner. |
| 1473 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
| 1474 | * |
| 1475 | * hw - Struct containing variables accessed by shared code |
| 1476 | ******************************************************************************/ |
| 1477 | static int32_t |
| 1478 | e1000_copper_link_postconfig(struct e1000_hw *hw) |
| 1479 | { |
| 1480 | int32_t ret_val; |
| 1481 | DEBUGFUNC("e1000_copper_link_postconfig"); |
| 1482 | |
| 1483 | if(hw->mac_type >= e1000_82544) { |
| 1484 | e1000_config_collision_dist(hw); |
| 1485 | } else { |
| 1486 | ret_val = e1000_config_mac_to_phy(hw); |
| 1487 | if(ret_val) { |
| 1488 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
| 1489 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1490 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1491 | } |
| 1492 | ret_val = e1000_config_fc_after_link_up(hw); |
| 1493 | if(ret_val) { |
| 1494 | DEBUGOUT("Error Configuring Flow Control\n"); |
| 1495 | return ret_val; |
| 1496 | } |
| 1497 | |
| 1498 | /* Config DSP to improve Giga link quality */ |
| 1499 | if(hw->phy_type == e1000_phy_igp) { |
| 1500 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); |
| 1501 | if(ret_val) { |
| 1502 | DEBUGOUT("Error Configuring DSP after link up\n"); |
| 1503 | return ret_val; |
| 1504 | } |
| 1505 | } |
| 1506 | |
| 1507 | return E1000_SUCCESS; |
| 1508 | } |
| 1509 | |
| 1510 | /****************************************************************************** |
| 1511 | * Detects which PHY is present and setup the speed and duplex |
| 1512 | * |
| 1513 | * hw - Struct containing variables accessed by shared code |
| 1514 | ******************************************************************************/ |
| 1515 | static int32_t |
| 1516 | e1000_setup_copper_link(struct e1000_hw *hw) |
| 1517 | { |
| 1518 | int32_t ret_val; |
| 1519 | uint16_t i; |
| 1520 | uint16_t phy_data; |
| 1521 | |
| 1522 | DEBUGFUNC("e1000_setup_copper_link"); |
| 1523 | |
| 1524 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
| 1525 | ret_val = e1000_copper_link_preconfig(hw); |
| 1526 | if(ret_val) |
| 1527 | return ret_val; |
| 1528 | |
| 1529 | if (hw->phy_type == e1000_phy_igp || |
| 1530 | hw->phy_type == e1000_phy_igp_2) { |
| 1531 | ret_val = e1000_copper_link_igp_setup(hw); |
| 1532 | if(ret_val) |
| 1533 | return ret_val; |
| 1534 | } else if (hw->phy_type == e1000_phy_m88) { |
| 1535 | ret_val = e1000_copper_link_mgp_setup(hw); |
| 1536 | if(ret_val) |
| 1537 | return ret_val; |
| 1538 | } |
| 1539 | |
| 1540 | if(hw->autoneg) { |
| 1541 | /* Setup autoneg and flow control advertisement |
| 1542 | * and perform autonegotiation */ |
| 1543 | ret_val = e1000_copper_link_autoneg(hw); |
| 1544 | if(ret_val) |
| 1545 | return ret_val; |
| 1546 | } else { |
| 1547 | /* PHY will be set to 10H, 10F, 100H,or 100F |
| 1548 | * depending on value from forced_speed_duplex. */ |
| 1549 | DEBUGOUT("Forcing speed and duplex\n"); |
| 1550 | ret_val = e1000_phy_force_speed_duplex(hw); |
| 1551 | if(ret_val) { |
| 1552 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
| 1553 | return ret_val; |
| 1554 | } |
| 1555 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1556 | |
| 1557 | /* Check link status. Wait up to 100 microseconds for link to become |
| 1558 | * valid. |
| 1559 | */ |
| 1560 | for(i = 0; i < 10; i++) { |
| 1561 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 1562 | if(ret_val) |
| 1563 | return ret_val; |
| 1564 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 1565 | if(ret_val) |
| 1566 | return ret_val; |
| 1567 | |
| 1568 | if(phy_data & MII_SR_LINK_STATUS) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1569 | /* Config the MAC and PHY after link is up */ |
| 1570 | ret_val = e1000_copper_link_postconfig(hw); |
| 1571 | if(ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1572 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1573 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1574 | DEBUGOUT("Valid link established!!!\n"); |
| 1575 | return E1000_SUCCESS; |
| 1576 | } |
| 1577 | udelay(10); |
| 1578 | } |
| 1579 | |
| 1580 | DEBUGOUT("Unable to establish link!!!\n"); |
| 1581 | return E1000_SUCCESS; |
| 1582 | } |
| 1583 | |
| 1584 | /****************************************************************************** |
| 1585 | * Configures PHY autoneg and flow control advertisement settings |
| 1586 | * |
| 1587 | * hw - Struct containing variables accessed by shared code |
| 1588 | ******************************************************************************/ |
| 1589 | int32_t |
| 1590 | e1000_phy_setup_autoneg(struct e1000_hw *hw) |
| 1591 | { |
| 1592 | int32_t ret_val; |
| 1593 | uint16_t mii_autoneg_adv_reg; |
| 1594 | uint16_t mii_1000t_ctrl_reg; |
| 1595 | |
| 1596 | DEBUGFUNC("e1000_phy_setup_autoneg"); |
| 1597 | |
| 1598 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
| 1599 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
| 1600 | if(ret_val) |
| 1601 | return ret_val; |
| 1602 | |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 1603 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
| 1604 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
| 1605 | if(ret_val) |
| 1606 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1607 | |
| 1608 | /* Need to parse both autoneg_advertised and fc and set up |
| 1609 | * the appropriate PHY registers. First we will parse for |
| 1610 | * autoneg_advertised software override. Since we can advertise |
| 1611 | * a plethora of combinations, we need to check each bit |
| 1612 | * individually. |
| 1613 | */ |
| 1614 | |
| 1615 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
| 1616 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
| 1617 | * the 1000Base-T Control Register (Address 9). |
| 1618 | */ |
| 1619 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
| 1620 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
| 1621 | |
| 1622 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
| 1623 | |
| 1624 | /* Do we want to advertise 10 Mb Half Duplex? */ |
| 1625 | if(hw->autoneg_advertised & ADVERTISE_10_HALF) { |
| 1626 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
| 1627 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
| 1628 | } |
| 1629 | |
| 1630 | /* Do we want to advertise 10 Mb Full Duplex? */ |
| 1631 | if(hw->autoneg_advertised & ADVERTISE_10_FULL) { |
| 1632 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
| 1633 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
| 1634 | } |
| 1635 | |
| 1636 | /* Do we want to advertise 100 Mb Half Duplex? */ |
| 1637 | if(hw->autoneg_advertised & ADVERTISE_100_HALF) { |
| 1638 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
| 1639 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
| 1640 | } |
| 1641 | |
| 1642 | /* Do we want to advertise 100 Mb Full Duplex? */ |
| 1643 | if(hw->autoneg_advertised & ADVERTISE_100_FULL) { |
| 1644 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
| 1645 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
| 1646 | } |
| 1647 | |
| 1648 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
| 1649 | if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
| 1650 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
| 1651 | } |
| 1652 | |
| 1653 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
| 1654 | if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
| 1655 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
| 1656 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
| 1657 | } |
| 1658 | |
| 1659 | /* Check for a software override of the flow control settings, and |
| 1660 | * setup the PHY advertisement registers accordingly. If |
| 1661 | * auto-negotiation is enabled, then software will have to set the |
| 1662 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
| 1663 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
| 1664 | * |
| 1665 | * The possible values of the "fc" parameter are: |
| 1666 | * 0: Flow control is completely disabled |
| 1667 | * 1: Rx flow control is enabled (we can receive pause frames |
| 1668 | * but not send pause frames). |
| 1669 | * 2: Tx flow control is enabled (we can send pause frames |
| 1670 | * but we do not support receiving pause frames). |
| 1671 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
| 1672 | * other: No software override. The flow control configuration |
| 1673 | * in the EEPROM is used. |
| 1674 | */ |
| 1675 | switch (hw->fc) { |
| 1676 | case e1000_fc_none: /* 0 */ |
| 1677 | /* Flow control (RX & TX) is completely disabled by a |
| 1678 | * software over-ride. |
| 1679 | */ |
| 1680 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 1681 | break; |
| 1682 | case e1000_fc_rx_pause: /* 1 */ |
| 1683 | /* RX Flow control is enabled, and TX Flow control is |
| 1684 | * disabled, by a software over-ride. |
| 1685 | */ |
| 1686 | /* Since there really isn't a way to advertise that we are |
| 1687 | * capable of RX Pause ONLY, we will advertise that we |
| 1688 | * support both symmetric and asymmetric RX PAUSE. Later |
| 1689 | * (in e1000_config_fc_after_link_up) we will disable the |
| 1690 | *hw's ability to send PAUSE frames. |
| 1691 | */ |
| 1692 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 1693 | break; |
| 1694 | case e1000_fc_tx_pause: /* 2 */ |
| 1695 | /* TX Flow control is enabled, and RX Flow control is |
| 1696 | * disabled, by a software over-ride. |
| 1697 | */ |
| 1698 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
| 1699 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
| 1700 | break; |
| 1701 | case e1000_fc_full: /* 3 */ |
| 1702 | /* Flow control (both RX and TX) is enabled by a software |
| 1703 | * over-ride. |
| 1704 | */ |
| 1705 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 1706 | break; |
| 1707 | default: |
| 1708 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 1709 | return -E1000_ERR_CONFIG; |
| 1710 | } |
| 1711 | |
| 1712 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
| 1713 | if(ret_val) |
| 1714 | return ret_val; |
| 1715 | |
| 1716 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
| 1717 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1718 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | if(ret_val) |
| 1720 | return ret_val; |
| 1721 | |
| 1722 | return E1000_SUCCESS; |
| 1723 | } |
| 1724 | |
| 1725 | /****************************************************************************** |
| 1726 | * Force PHY speed and duplex settings to hw->forced_speed_duplex |
| 1727 | * |
| 1728 | * hw - Struct containing variables accessed by shared code |
| 1729 | ******************************************************************************/ |
| 1730 | static int32_t |
| 1731 | e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
| 1732 | { |
| 1733 | uint32_t ctrl; |
| 1734 | int32_t ret_val; |
| 1735 | uint16_t mii_ctrl_reg; |
| 1736 | uint16_t mii_status_reg; |
| 1737 | uint16_t phy_data; |
| 1738 | uint16_t i; |
| 1739 | |
| 1740 | DEBUGFUNC("e1000_phy_force_speed_duplex"); |
| 1741 | |
| 1742 | /* Turn off Flow control if we are forcing speed and duplex. */ |
| 1743 | hw->fc = e1000_fc_none; |
| 1744 | |
| 1745 | DEBUGOUT1("hw->fc = %d\n", hw->fc); |
| 1746 | |
| 1747 | /* Read the Device Control Register. */ |
| 1748 | ctrl = E1000_READ_REG(hw, CTRL); |
| 1749 | |
| 1750 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
| 1751 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1752 | ctrl &= ~(DEVICE_SPEED_MASK); |
| 1753 | |
| 1754 | /* Clear the Auto Speed Detect Enable bit. */ |
| 1755 | ctrl &= ~E1000_CTRL_ASDE; |
| 1756 | |
| 1757 | /* Read the MII Control Register. */ |
| 1758 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
| 1759 | if(ret_val) |
| 1760 | return ret_val; |
| 1761 | |
| 1762 | /* We need to disable autoneg in order to force link and duplex. */ |
| 1763 | |
| 1764 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
| 1765 | |
| 1766 | /* Are we forcing Full or Half Duplex? */ |
| 1767 | if(hw->forced_speed_duplex == e1000_100_full || |
| 1768 | hw->forced_speed_duplex == e1000_10_full) { |
| 1769 | /* We want to force full duplex so we SET the full duplex bits in the |
| 1770 | * Device and MII Control Registers. |
| 1771 | */ |
| 1772 | ctrl |= E1000_CTRL_FD; |
| 1773 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
| 1774 | DEBUGOUT("Full Duplex\n"); |
| 1775 | } else { |
| 1776 | /* We want to force half duplex so we CLEAR the full duplex bits in |
| 1777 | * the Device and MII Control Registers. |
| 1778 | */ |
| 1779 | ctrl &= ~E1000_CTRL_FD; |
| 1780 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
| 1781 | DEBUGOUT("Half Duplex\n"); |
| 1782 | } |
| 1783 | |
| 1784 | /* Are we forcing 100Mbps??? */ |
| 1785 | if(hw->forced_speed_duplex == e1000_100_full || |
| 1786 | hw->forced_speed_duplex == e1000_100_half) { |
| 1787 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
| 1788 | ctrl |= E1000_CTRL_SPD_100; |
| 1789 | mii_ctrl_reg |= MII_CR_SPEED_100; |
| 1790 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
| 1791 | DEBUGOUT("Forcing 100mb "); |
| 1792 | } else { |
| 1793 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
| 1794 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
| 1795 | mii_ctrl_reg |= MII_CR_SPEED_10; |
| 1796 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
| 1797 | DEBUGOUT("Forcing 10mb "); |
| 1798 | } |
| 1799 | |
| 1800 | e1000_config_collision_dist(hw); |
| 1801 | |
| 1802 | /* Write the configured values back to the Device Control Reg. */ |
| 1803 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 1804 | |
| 1805 | if (hw->phy_type == e1000_phy_m88) { |
| 1806 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1807 | if(ret_val) |
| 1808 | return ret_val; |
| 1809 | |
| 1810 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
| 1811 | * forced whenever speed are duplex are forced. |
| 1812 | */ |
| 1813 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 1814 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1815 | if(ret_val) |
| 1816 | return ret_val; |
| 1817 | |
| 1818 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); |
| 1819 | |
| 1820 | /* Need to reset the PHY or these changes will be ignored */ |
| 1821 | mii_ctrl_reg |= MII_CR_RESET; |
| 1822 | } else { |
| 1823 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
| 1824 | * forced whenever speed or duplex are forced. |
| 1825 | */ |
| 1826 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
| 1827 | if(ret_val) |
| 1828 | return ret_val; |
| 1829 | |
| 1830 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 1831 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1832 | |
| 1833 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
| 1834 | if(ret_val) |
| 1835 | return ret_val; |
| 1836 | } |
| 1837 | |
| 1838 | /* Write back the modified PHY MII control register. */ |
| 1839 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
| 1840 | if(ret_val) |
| 1841 | return ret_val; |
| 1842 | |
| 1843 | udelay(1); |
| 1844 | |
| 1845 | /* The wait_autoneg_complete flag may be a little misleading here. |
| 1846 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
| 1847 | * But we do want to delay for a period while forcing only so we |
| 1848 | * don't generate false No Link messages. So we will wait here |
| 1849 | * only if the user has set wait_autoneg_complete to 1, which is |
| 1850 | * the default. |
| 1851 | */ |
| 1852 | if(hw->wait_autoneg_complete) { |
| 1853 | /* We will wait for autoneg to complete. */ |
| 1854 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
| 1855 | mii_status_reg = 0; |
| 1856 | |
| 1857 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
| 1858 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
| 1859 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
| 1860 | * to be set. |
| 1861 | */ |
| 1862 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 1863 | if(ret_val) |
| 1864 | return ret_val; |
| 1865 | |
| 1866 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 1867 | if(ret_val) |
| 1868 | return ret_val; |
| 1869 | |
| 1870 | if(mii_status_reg & MII_SR_LINK_STATUS) break; |
| 1871 | msec_delay(100); |
| 1872 | } |
| 1873 | if((i == 0) && |
| 1874 | (hw->phy_type == e1000_phy_m88)) { |
| 1875 | /* We didn't get link. Reset the DSP and wait again for link. */ |
| 1876 | ret_val = e1000_phy_reset_dsp(hw); |
| 1877 | if(ret_val) { |
| 1878 | DEBUGOUT("Error Resetting PHY DSP\n"); |
| 1879 | return ret_val; |
| 1880 | } |
| 1881 | } |
| 1882 | /* This loop will early-out if the link condition has been met. */ |
| 1883 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
| 1884 | if(mii_status_reg & MII_SR_LINK_STATUS) break; |
| 1885 | msec_delay(100); |
| 1886 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
| 1887 | * to be set. |
| 1888 | */ |
| 1889 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 1890 | if(ret_val) |
| 1891 | return ret_val; |
| 1892 | |
| 1893 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 1894 | if(ret_val) |
| 1895 | return ret_val; |
| 1896 | } |
| 1897 | } |
| 1898 | |
| 1899 | if (hw->phy_type == e1000_phy_m88) { |
| 1900 | /* Because we reset the PHY above, we need to re-force TX_CLK in the |
| 1901 | * Extended PHY Specific Control Register to 25MHz clock. This value |
| 1902 | * defaults back to a 2.5MHz clock when the PHY is reset. |
| 1903 | */ |
| 1904 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 1905 | if(ret_val) |
| 1906 | return ret_val; |
| 1907 | |
| 1908 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 1909 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 1910 | if(ret_val) |
| 1911 | return ret_val; |
| 1912 | |
| 1913 | /* In addition, because of the s/w reset above, we need to enable CRS on |
| 1914 | * TX. This must be set for both full and half duplex operation. |
| 1915 | */ |
| 1916 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1917 | if(ret_val) |
| 1918 | return ret_val; |
| 1919 | |
| 1920 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 1921 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1922 | if(ret_val) |
| 1923 | return ret_val; |
| 1924 | |
| 1925 | if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
| 1926 | (!hw->autoneg) && |
| 1927 | (hw->forced_speed_duplex == e1000_10_full || |
| 1928 | hw->forced_speed_duplex == e1000_10_half)) { |
| 1929 | ret_val = e1000_polarity_reversal_workaround(hw); |
| 1930 | if(ret_val) |
| 1931 | return ret_val; |
| 1932 | } |
| 1933 | } |
| 1934 | return E1000_SUCCESS; |
| 1935 | } |
| 1936 | |
| 1937 | /****************************************************************************** |
| 1938 | * Sets the collision distance in the Transmit Control register |
| 1939 | * |
| 1940 | * hw - Struct containing variables accessed by shared code |
| 1941 | * |
| 1942 | * Link should have been established previously. Reads the speed and duplex |
| 1943 | * information from the Device Status register. |
| 1944 | ******************************************************************************/ |
| 1945 | void |
| 1946 | e1000_config_collision_dist(struct e1000_hw *hw) |
| 1947 | { |
Jeff Kirsher | 0fadb05 | 2006-01-12 16:51:05 -0800 | [diff] [blame] | 1948 | uint32_t tctl, coll_dist; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1949 | |
| 1950 | DEBUGFUNC("e1000_config_collision_dist"); |
| 1951 | |
Jeff Kirsher | 0fadb05 | 2006-01-12 16:51:05 -0800 | [diff] [blame] | 1952 | if (hw->mac_type < e1000_82543) |
| 1953 | coll_dist = E1000_COLLISION_DISTANCE_82542; |
| 1954 | else |
| 1955 | coll_dist = E1000_COLLISION_DISTANCE; |
| 1956 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1957 | tctl = E1000_READ_REG(hw, TCTL); |
| 1958 | |
| 1959 | tctl &= ~E1000_TCTL_COLD; |
Jeff Kirsher | 0fadb05 | 2006-01-12 16:51:05 -0800 | [diff] [blame] | 1960 | tctl |= coll_dist << E1000_COLD_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1961 | |
| 1962 | E1000_WRITE_REG(hw, TCTL, tctl); |
| 1963 | E1000_WRITE_FLUSH(hw); |
| 1964 | } |
| 1965 | |
| 1966 | /****************************************************************************** |
| 1967 | * Sets MAC speed and duplex settings to reflect the those in the PHY |
| 1968 | * |
| 1969 | * hw - Struct containing variables accessed by shared code |
| 1970 | * mii_reg - data to write to the MII control register |
| 1971 | * |
| 1972 | * The contents of the PHY register containing the needed information need to |
| 1973 | * be passed in. |
| 1974 | ******************************************************************************/ |
| 1975 | static int32_t |
| 1976 | e1000_config_mac_to_phy(struct e1000_hw *hw) |
| 1977 | { |
| 1978 | uint32_t ctrl; |
| 1979 | int32_t ret_val; |
| 1980 | uint16_t phy_data; |
| 1981 | |
| 1982 | DEBUGFUNC("e1000_config_mac_to_phy"); |
| 1983 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1984 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
| 1985 | * MAC speed/duplex configuration.*/ |
| 1986 | if (hw->mac_type >= e1000_82544) |
| 1987 | return E1000_SUCCESS; |
| 1988 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1989 | /* Read the Device Control Register and set the bits to Force Speed |
| 1990 | * and Duplex. |
| 1991 | */ |
| 1992 | ctrl = E1000_READ_REG(hw, CTRL); |
| 1993 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1994 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
| 1995 | |
| 1996 | /* Set up duplex in the Device Control and Transmit Control |
| 1997 | * registers depending on negotiated values. |
| 1998 | */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1999 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
| 2000 | if(ret_val) |
| 2001 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2002 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2003 | if(phy_data & M88E1000_PSSR_DPLX) |
| 2004 | ctrl |= E1000_CTRL_FD; |
| 2005 | else |
| 2006 | ctrl &= ~E1000_CTRL_FD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2007 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2008 | e1000_config_collision_dist(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2009 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2010 | /* Set up speed in the Device Control register depending on |
| 2011 | * negotiated values. |
| 2012 | */ |
| 2013 | if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
| 2014 | ctrl |= E1000_CTRL_SPD_1000; |
| 2015 | else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
| 2016 | ctrl |= E1000_CTRL_SPD_100; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2017 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2018 | /* Write the configured values back to the Device Control Reg. */ |
| 2019 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2020 | return E1000_SUCCESS; |
| 2021 | } |
| 2022 | |
| 2023 | /****************************************************************************** |
| 2024 | * Forces the MAC's flow control settings. |
| 2025 | * |
| 2026 | * hw - Struct containing variables accessed by shared code |
| 2027 | * |
| 2028 | * Sets the TFCE and RFCE bits in the device control register to reflect |
| 2029 | * the adapter settings. TFCE and RFCE need to be explicitly set by |
| 2030 | * software when a Copper PHY is used because autonegotiation is managed |
| 2031 | * by the PHY rather than the MAC. Software must also configure these |
| 2032 | * bits when link is forced on a fiber connection. |
| 2033 | *****************************************************************************/ |
| 2034 | int32_t |
| 2035 | e1000_force_mac_fc(struct e1000_hw *hw) |
| 2036 | { |
| 2037 | uint32_t ctrl; |
| 2038 | |
| 2039 | DEBUGFUNC("e1000_force_mac_fc"); |
| 2040 | |
| 2041 | /* Get the current configuration of the Device Control Register */ |
| 2042 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2043 | |
| 2044 | /* Because we didn't get link via the internal auto-negotiation |
| 2045 | * mechanism (we either forced link or we got link via PHY |
| 2046 | * auto-neg), we have to manually enable/disable transmit an |
| 2047 | * receive flow control. |
| 2048 | * |
| 2049 | * The "Case" statement below enables/disable flow control |
| 2050 | * according to the "hw->fc" parameter. |
| 2051 | * |
| 2052 | * The possible values of the "fc" parameter are: |
| 2053 | * 0: Flow control is completely disabled |
| 2054 | * 1: Rx flow control is enabled (we can receive pause |
| 2055 | * frames but not send pause frames). |
| 2056 | * 2: Tx flow control is enabled (we can send pause frames |
| 2057 | * frames but we do not receive pause frames). |
| 2058 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
| 2059 | * other: No other values should be possible at this point. |
| 2060 | */ |
| 2061 | |
| 2062 | switch (hw->fc) { |
| 2063 | case e1000_fc_none: |
| 2064 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 2065 | break; |
| 2066 | case e1000_fc_rx_pause: |
| 2067 | ctrl &= (~E1000_CTRL_TFCE); |
| 2068 | ctrl |= E1000_CTRL_RFCE; |
| 2069 | break; |
| 2070 | case e1000_fc_tx_pause: |
| 2071 | ctrl &= (~E1000_CTRL_RFCE); |
| 2072 | ctrl |= E1000_CTRL_TFCE; |
| 2073 | break; |
| 2074 | case e1000_fc_full: |
| 2075 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 2076 | break; |
| 2077 | default: |
| 2078 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 2079 | return -E1000_ERR_CONFIG; |
| 2080 | } |
| 2081 | |
| 2082 | /* Disable TX Flow Control for 82542 (rev 2.0) */ |
| 2083 | if(hw->mac_type == e1000_82542_rev2_0) |
| 2084 | ctrl &= (~E1000_CTRL_TFCE); |
| 2085 | |
| 2086 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2087 | return E1000_SUCCESS; |
| 2088 | } |
| 2089 | |
| 2090 | /****************************************************************************** |
| 2091 | * Configures flow control settings after link is established |
| 2092 | * |
| 2093 | * hw - Struct containing variables accessed by shared code |
| 2094 | * |
| 2095 | * Should be called immediately after a valid link has been established. |
| 2096 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
| 2097 | * and autonegotiation is enabled, the MAC flow control settings will be set |
| 2098 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
| 2099 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. |
| 2100 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 2101 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2102 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
| 2103 | { |
| 2104 | int32_t ret_val; |
| 2105 | uint16_t mii_status_reg; |
| 2106 | uint16_t mii_nway_adv_reg; |
| 2107 | uint16_t mii_nway_lp_ability_reg; |
| 2108 | uint16_t speed; |
| 2109 | uint16_t duplex; |
| 2110 | |
| 2111 | DEBUGFUNC("e1000_config_fc_after_link_up"); |
| 2112 | |
| 2113 | /* Check for the case where we have fiber media and auto-neg failed |
| 2114 | * so we had to force link. In this case, we need to force the |
| 2115 | * configuration of the MAC to match the "fc" parameter. |
| 2116 | */ |
| 2117 | if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || |
| 2118 | ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || |
| 2119 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { |
| 2120 | ret_val = e1000_force_mac_fc(hw); |
| 2121 | if(ret_val) { |
| 2122 | DEBUGOUT("Error forcing flow control settings\n"); |
| 2123 | return ret_val; |
| 2124 | } |
| 2125 | } |
| 2126 | |
| 2127 | /* Check for the case where we have copper media and auto-neg is |
| 2128 | * enabled. In this case, we need to check and see if Auto-Neg |
| 2129 | * has completed, and if so, how the PHY and link partner has |
| 2130 | * flow control configured. |
| 2131 | */ |
| 2132 | if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
| 2133 | /* Read the MII Status Register and check to see if AutoNeg |
| 2134 | * has completed. We read this twice because this reg has |
| 2135 | * some "sticky" (latched) bits. |
| 2136 | */ |
| 2137 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 2138 | if(ret_val) |
| 2139 | return ret_val; |
| 2140 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 2141 | if(ret_val) |
| 2142 | return ret_val; |
| 2143 | |
| 2144 | if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
| 2145 | /* The AutoNeg process has completed, so we now need to |
| 2146 | * read both the Auto Negotiation Advertisement Register |
| 2147 | * (Address 4) and the Auto_Negotiation Base Page Ability |
| 2148 | * Register (Address 5) to determine how flow control was |
| 2149 | * negotiated. |
| 2150 | */ |
| 2151 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
| 2152 | &mii_nway_adv_reg); |
| 2153 | if(ret_val) |
| 2154 | return ret_val; |
| 2155 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
| 2156 | &mii_nway_lp_ability_reg); |
| 2157 | if(ret_val) |
| 2158 | return ret_val; |
| 2159 | |
| 2160 | /* Two bits in the Auto Negotiation Advertisement Register |
| 2161 | * (Address 4) and two bits in the Auto Negotiation Base |
| 2162 | * Page Ability Register (Address 5) determine flow control |
| 2163 | * for both the PHY and the link partner. The following |
| 2164 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 2165 | * 1999, describes these PAUSE resolution bits and how flow |
| 2166 | * control is determined based upon these settings. |
| 2167 | * NOTE: DC = Don't Care |
| 2168 | * |
| 2169 | * LOCAL DEVICE | LINK PARTNER |
| 2170 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 2171 | *-------|---------|-------|---------|-------------------- |
| 2172 | * 0 | 0 | DC | DC | e1000_fc_none |
| 2173 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 2174 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 2175 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 2176 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 2177 | * 1 | DC | 1 | DC | e1000_fc_full |
| 2178 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 2179 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 2180 | * |
| 2181 | */ |
| 2182 | /* Are both PAUSE bits set to 1? If so, this implies |
| 2183 | * Symmetric Flow Control is enabled at both ends. The |
| 2184 | * ASM_DIR bits are irrelevant per the spec. |
| 2185 | * |
| 2186 | * For Symmetric Flow Control: |
| 2187 | * |
| 2188 | * LOCAL DEVICE | LINK PARTNER |
| 2189 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 2190 | *-------|---------|-------|---------|-------------------- |
| 2191 | * 1 | DC | 1 | DC | e1000_fc_full |
| 2192 | * |
| 2193 | */ |
| 2194 | if((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 2195 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
| 2196 | /* Now we need to check if the user selected RX ONLY |
| 2197 | * of pause frames. In this case, we had to advertise |
| 2198 | * FULL flow control because we could not advertise RX |
| 2199 | * ONLY. Hence, we must now check to see if we need to |
| 2200 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 2201 | */ |
| 2202 | if(hw->original_fc == e1000_fc_full) { |
| 2203 | hw->fc = e1000_fc_full; |
| 2204 | DEBUGOUT("Flow Control = FULL.\r\n"); |
| 2205 | } else { |
| 2206 | hw->fc = e1000_fc_rx_pause; |
| 2207 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); |
| 2208 | } |
| 2209 | } |
| 2210 | /* For receiving PAUSE frames ONLY. |
| 2211 | * |
| 2212 | * LOCAL DEVICE | LINK PARTNER |
| 2213 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 2214 | *-------|---------|-------|---------|-------------------- |
| 2215 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 2216 | * |
| 2217 | */ |
| 2218 | else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 2219 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 2220 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 2221 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
| 2222 | hw->fc = e1000_fc_tx_pause; |
| 2223 | DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); |
| 2224 | } |
| 2225 | /* For transmitting PAUSE frames ONLY. |
| 2226 | * |
| 2227 | * LOCAL DEVICE | LINK PARTNER |
| 2228 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 2229 | *-------|---------|-------|---------|-------------------- |
| 2230 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 2231 | * |
| 2232 | */ |
| 2233 | else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 2234 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 2235 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 2236 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
| 2237 | hw->fc = e1000_fc_rx_pause; |
| 2238 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); |
| 2239 | } |
| 2240 | /* Per the IEEE spec, at this point flow control should be |
| 2241 | * disabled. However, we want to consider that we could |
| 2242 | * be connected to a legacy switch that doesn't advertise |
| 2243 | * desired flow control, but can be forced on the link |
| 2244 | * partner. So if we advertised no flow control, that is |
| 2245 | * what we will resolve to. If we advertised some kind of |
| 2246 | * receive capability (Rx Pause Only or Full Flow Control) |
| 2247 | * and the link partner advertised none, we will configure |
| 2248 | * ourselves to enable Rx Flow Control only. We can do |
| 2249 | * this safely for two reasons: If the link partner really |
| 2250 | * didn't want flow control enabled, and we enable Rx, no |
| 2251 | * harm done since we won't be receiving any PAUSE frames |
| 2252 | * anyway. If the intent on the link partner was to have |
| 2253 | * flow control enabled, then by us enabling RX only, we |
| 2254 | * can at least receive pause frames and process them. |
| 2255 | * This is a good idea because in most cases, since we are |
| 2256 | * predominantly a server NIC, more times than not we will |
| 2257 | * be asked to delay transmission of packets than asking |
| 2258 | * our link partner to pause transmission of frames. |
| 2259 | */ |
| 2260 | else if((hw->original_fc == e1000_fc_none || |
| 2261 | hw->original_fc == e1000_fc_tx_pause) || |
| 2262 | hw->fc_strict_ieee) { |
| 2263 | hw->fc = e1000_fc_none; |
| 2264 | DEBUGOUT("Flow Control = NONE.\r\n"); |
| 2265 | } else { |
| 2266 | hw->fc = e1000_fc_rx_pause; |
| 2267 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); |
| 2268 | } |
| 2269 | |
| 2270 | /* Now we need to do one last check... If we auto- |
| 2271 | * negotiated to HALF DUPLEX, flow control should not be |
| 2272 | * enabled per IEEE 802.3 spec. |
| 2273 | */ |
| 2274 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
| 2275 | if(ret_val) { |
| 2276 | DEBUGOUT("Error getting link speed and duplex\n"); |
| 2277 | return ret_val; |
| 2278 | } |
| 2279 | |
| 2280 | if(duplex == HALF_DUPLEX) |
| 2281 | hw->fc = e1000_fc_none; |
| 2282 | |
| 2283 | /* Now we call a subroutine to actually force the MAC |
| 2284 | * controller to use the correct flow control settings. |
| 2285 | */ |
| 2286 | ret_val = e1000_force_mac_fc(hw); |
| 2287 | if(ret_val) { |
| 2288 | DEBUGOUT("Error forcing flow control settings\n"); |
| 2289 | return ret_val; |
| 2290 | } |
| 2291 | } else { |
| 2292 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n"); |
| 2293 | } |
| 2294 | } |
| 2295 | return E1000_SUCCESS; |
| 2296 | } |
| 2297 | |
| 2298 | /****************************************************************************** |
| 2299 | * Checks to see if the link status of the hardware has changed. |
| 2300 | * |
| 2301 | * hw - Struct containing variables accessed by shared code |
| 2302 | * |
| 2303 | * Called by any function that needs to check the link status of the adapter. |
| 2304 | *****************************************************************************/ |
| 2305 | int32_t |
| 2306 | e1000_check_for_link(struct e1000_hw *hw) |
| 2307 | { |
| 2308 | uint32_t rxcw = 0; |
| 2309 | uint32_t ctrl; |
| 2310 | uint32_t status; |
| 2311 | uint32_t rctl; |
| 2312 | uint32_t icr; |
| 2313 | uint32_t signal = 0; |
| 2314 | int32_t ret_val; |
| 2315 | uint16_t phy_data; |
| 2316 | |
| 2317 | DEBUGFUNC("e1000_check_for_link"); |
| 2318 | |
| 2319 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2320 | status = E1000_READ_REG(hw, STATUS); |
| 2321 | |
| 2322 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
| 2323 | * set when the optics detect a signal. On older adapters, it will be |
| 2324 | * cleared when there is a signal. This applies to fiber media only. |
| 2325 | */ |
| 2326 | if((hw->media_type == e1000_media_type_fiber) || |
| 2327 | (hw->media_type == e1000_media_type_internal_serdes)) { |
| 2328 | rxcw = E1000_READ_REG(hw, RXCW); |
| 2329 | |
| 2330 | if(hw->media_type == e1000_media_type_fiber) { |
| 2331 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
| 2332 | if(status & E1000_STATUS_LU) |
| 2333 | hw->get_link_status = FALSE; |
| 2334 | } |
| 2335 | } |
| 2336 | |
| 2337 | /* If we have a copper PHY then we only want to go out to the PHY |
| 2338 | * registers to see if Auto-Neg has completed and/or if our link |
| 2339 | * status has changed. The get_link_status flag will be set if we |
| 2340 | * receive a Link Status Change interrupt or we have Rx Sequence |
| 2341 | * Errors. |
| 2342 | */ |
| 2343 | if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
| 2344 | /* First we want to see if the MII Status Register reports |
| 2345 | * link. If so, then we want to get the current speed/duplex |
| 2346 | * of the PHY. |
| 2347 | * Read the register twice since the link bit is sticky. |
| 2348 | */ |
| 2349 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 2350 | if(ret_val) |
| 2351 | return ret_val; |
| 2352 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 2353 | if(ret_val) |
| 2354 | return ret_val; |
| 2355 | |
| 2356 | if(phy_data & MII_SR_LINK_STATUS) { |
| 2357 | hw->get_link_status = FALSE; |
| 2358 | /* Check if there was DownShift, must be checked immediately after |
| 2359 | * link-up */ |
| 2360 | e1000_check_downshift(hw); |
| 2361 | |
| 2362 | /* If we are on 82544 or 82543 silicon and speed/duplex |
| 2363 | * are forced to 10H or 10F, then we will implement the polarity |
| 2364 | * reversal workaround. We disable interrupts first, and upon |
| 2365 | * returning, place the devices interrupt state to its previous |
| 2366 | * value except for the link status change interrupt which will |
| 2367 | * happen due to the execution of this workaround. |
| 2368 | */ |
| 2369 | |
| 2370 | if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
| 2371 | (!hw->autoneg) && |
| 2372 | (hw->forced_speed_duplex == e1000_10_full || |
| 2373 | hw->forced_speed_duplex == e1000_10_half)) { |
| 2374 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 2375 | ret_val = e1000_polarity_reversal_workaround(hw); |
| 2376 | icr = E1000_READ_REG(hw, ICR); |
| 2377 | E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); |
| 2378 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); |
| 2379 | } |
| 2380 | |
| 2381 | } else { |
| 2382 | /* No link detected */ |
| 2383 | e1000_config_dsp_after_link_change(hw, FALSE); |
| 2384 | return 0; |
| 2385 | } |
| 2386 | |
| 2387 | /* If we are forcing speed/duplex, then we simply return since |
| 2388 | * we have already determined whether we have link or not. |
| 2389 | */ |
| 2390 | if(!hw->autoneg) return -E1000_ERR_CONFIG; |
| 2391 | |
| 2392 | /* optimize the dsp settings for the igp phy */ |
| 2393 | e1000_config_dsp_after_link_change(hw, TRUE); |
| 2394 | |
| 2395 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
| 2396 | * have Si on board that is 82544 or newer, Auto |
| 2397 | * Speed Detection takes care of MAC speed/duplex |
| 2398 | * configuration. So we only need to configure Collision |
| 2399 | * Distance in the MAC. Otherwise, we need to force |
| 2400 | * speed/duplex on the MAC to the current PHY speed/duplex |
| 2401 | * settings. |
| 2402 | */ |
| 2403 | if(hw->mac_type >= e1000_82544) |
| 2404 | e1000_config_collision_dist(hw); |
| 2405 | else { |
| 2406 | ret_val = e1000_config_mac_to_phy(hw); |
| 2407 | if(ret_val) { |
| 2408 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
| 2409 | return ret_val; |
| 2410 | } |
| 2411 | } |
| 2412 | |
| 2413 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
| 2414 | * need to restore the desired flow control settings because we may |
| 2415 | * have had to re-autoneg with a different link partner. |
| 2416 | */ |
| 2417 | ret_val = e1000_config_fc_after_link_up(hw); |
| 2418 | if(ret_val) { |
| 2419 | DEBUGOUT("Error configuring flow control\n"); |
| 2420 | return ret_val; |
| 2421 | } |
| 2422 | |
| 2423 | /* At this point we know that we are on copper and we have |
| 2424 | * auto-negotiated link. These are conditions for checking the link |
| 2425 | * partner capability register. We use the link speed to determine if |
| 2426 | * TBI compatibility needs to be turned on or off. If the link is not |
| 2427 | * at gigabit speed, then TBI compatibility is not needed. If we are |
| 2428 | * at gigabit speed, we turn on TBI compatibility. |
| 2429 | */ |
| 2430 | if(hw->tbi_compatibility_en) { |
| 2431 | uint16_t speed, duplex; |
| 2432 | e1000_get_speed_and_duplex(hw, &speed, &duplex); |
| 2433 | if(speed != SPEED_1000) { |
| 2434 | /* If link speed is not set to gigabit speed, we do not need |
| 2435 | * to enable TBI compatibility. |
| 2436 | */ |
| 2437 | if(hw->tbi_compatibility_on) { |
| 2438 | /* If we previously were in the mode, turn it off. */ |
| 2439 | rctl = E1000_READ_REG(hw, RCTL); |
| 2440 | rctl &= ~E1000_RCTL_SBP; |
| 2441 | E1000_WRITE_REG(hw, RCTL, rctl); |
| 2442 | hw->tbi_compatibility_on = FALSE; |
| 2443 | } |
| 2444 | } else { |
| 2445 | /* If TBI compatibility is was previously off, turn it on. For |
| 2446 | * compatibility with a TBI link partner, we will store bad |
| 2447 | * packets. Some frames have an additional byte on the end and |
| 2448 | * will look like CRC errors to to the hardware. |
| 2449 | */ |
| 2450 | if(!hw->tbi_compatibility_on) { |
| 2451 | hw->tbi_compatibility_on = TRUE; |
| 2452 | rctl = E1000_READ_REG(hw, RCTL); |
| 2453 | rctl |= E1000_RCTL_SBP; |
| 2454 | E1000_WRITE_REG(hw, RCTL, rctl); |
| 2455 | } |
| 2456 | } |
| 2457 | } |
| 2458 | } |
| 2459 | /* If we don't have link (auto-negotiation failed or link partner cannot |
| 2460 | * auto-negotiate), the cable is plugged in (we have signal), and our |
| 2461 | * link partner is not trying to auto-negotiate with us (we are receiving |
| 2462 | * idles or data), we need to force link up. We also need to give |
| 2463 | * auto-negotiation time to complete, in case the cable was just plugged |
| 2464 | * in. The autoneg_failed flag does this. |
| 2465 | */ |
| 2466 | else if((((hw->media_type == e1000_media_type_fiber) && |
| 2467 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
| 2468 | (hw->media_type == e1000_media_type_internal_serdes)) && |
| 2469 | (!(status & E1000_STATUS_LU)) && |
| 2470 | (!(rxcw & E1000_RXCW_C))) { |
| 2471 | if(hw->autoneg_failed == 0) { |
| 2472 | hw->autoneg_failed = 1; |
| 2473 | return 0; |
| 2474 | } |
| 2475 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); |
| 2476 | |
| 2477 | /* Disable auto-negotiation in the TXCW register */ |
| 2478 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
| 2479 | |
| 2480 | /* Force link-up and also force full-duplex. */ |
| 2481 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2482 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 2483 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2484 | |
| 2485 | /* Configure Flow Control after forcing link up. */ |
| 2486 | ret_val = e1000_config_fc_after_link_up(hw); |
| 2487 | if(ret_val) { |
| 2488 | DEBUGOUT("Error configuring flow control\n"); |
| 2489 | return ret_val; |
| 2490 | } |
| 2491 | } |
| 2492 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable |
| 2493 | * auto-negotiation in the TXCW register and disable forced link in the |
| 2494 | * Device Control register in an attempt to auto-negotiate with our link |
| 2495 | * partner. |
| 2496 | */ |
| 2497 | else if(((hw->media_type == e1000_media_type_fiber) || |
| 2498 | (hw->media_type == e1000_media_type_internal_serdes)) && |
| 2499 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
| 2500 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); |
| 2501 | E1000_WRITE_REG(hw, TXCW, hw->txcw); |
| 2502 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 2503 | |
| 2504 | hw->serdes_link_down = FALSE; |
| 2505 | } |
| 2506 | /* If we force link for non-auto-negotiation switch, check link status |
| 2507 | * based on MAC synchronization for internal serdes media type. |
| 2508 | */ |
| 2509 | else if((hw->media_type == e1000_media_type_internal_serdes) && |
| 2510 | !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
| 2511 | /* SYNCH bit and IV bit are sticky. */ |
| 2512 | udelay(10); |
| 2513 | if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { |
| 2514 | if(!(rxcw & E1000_RXCW_IV)) { |
| 2515 | hw->serdes_link_down = FALSE; |
| 2516 | DEBUGOUT("SERDES: Link is up.\n"); |
| 2517 | } |
| 2518 | } else { |
| 2519 | hw->serdes_link_down = TRUE; |
| 2520 | DEBUGOUT("SERDES: Link is down.\n"); |
| 2521 | } |
| 2522 | } |
| 2523 | if((hw->media_type == e1000_media_type_internal_serdes) && |
| 2524 | (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
| 2525 | hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); |
| 2526 | } |
| 2527 | return E1000_SUCCESS; |
| 2528 | } |
| 2529 | |
| 2530 | /****************************************************************************** |
| 2531 | * Detects the current speed and duplex settings of the hardware. |
| 2532 | * |
| 2533 | * hw - Struct containing variables accessed by shared code |
| 2534 | * speed - Speed of the connection |
| 2535 | * duplex - Duplex setting of the connection |
| 2536 | *****************************************************************************/ |
| 2537 | int32_t |
| 2538 | e1000_get_speed_and_duplex(struct e1000_hw *hw, |
| 2539 | uint16_t *speed, |
| 2540 | uint16_t *duplex) |
| 2541 | { |
| 2542 | uint32_t status; |
| 2543 | int32_t ret_val; |
| 2544 | uint16_t phy_data; |
| 2545 | |
| 2546 | DEBUGFUNC("e1000_get_speed_and_duplex"); |
| 2547 | |
| 2548 | if(hw->mac_type >= e1000_82543) { |
| 2549 | status = E1000_READ_REG(hw, STATUS); |
| 2550 | if(status & E1000_STATUS_SPEED_1000) { |
| 2551 | *speed = SPEED_1000; |
| 2552 | DEBUGOUT("1000 Mbs, "); |
| 2553 | } else if(status & E1000_STATUS_SPEED_100) { |
| 2554 | *speed = SPEED_100; |
| 2555 | DEBUGOUT("100 Mbs, "); |
| 2556 | } else { |
| 2557 | *speed = SPEED_10; |
| 2558 | DEBUGOUT("10 Mbs, "); |
| 2559 | } |
| 2560 | |
| 2561 | if(status & E1000_STATUS_FD) { |
| 2562 | *duplex = FULL_DUPLEX; |
| 2563 | DEBUGOUT("Full Duplex\r\n"); |
| 2564 | } else { |
| 2565 | *duplex = HALF_DUPLEX; |
| 2566 | DEBUGOUT(" Half Duplex\r\n"); |
| 2567 | } |
| 2568 | } else { |
| 2569 | DEBUGOUT("1000 Mbs, Full Duplex\r\n"); |
| 2570 | *speed = SPEED_1000; |
| 2571 | *duplex = FULL_DUPLEX; |
| 2572 | } |
| 2573 | |
| 2574 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
| 2575 | * if it is operating at half duplex. Here we set the duplex settings to |
| 2576 | * match the duplex in the link partner's capabilities. |
| 2577 | */ |
| 2578 | if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
| 2579 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
| 2580 | if(ret_val) |
| 2581 | return ret_val; |
| 2582 | |
| 2583 | if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
| 2584 | *duplex = HALF_DUPLEX; |
| 2585 | else { |
| 2586 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
| 2587 | if(ret_val) |
| 2588 | return ret_val; |
| 2589 | if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
| 2590 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
| 2591 | *duplex = HALF_DUPLEX; |
| 2592 | } |
| 2593 | } |
| 2594 | |
| 2595 | return E1000_SUCCESS; |
| 2596 | } |
| 2597 | |
| 2598 | /****************************************************************************** |
| 2599 | * Blocks until autoneg completes or times out (~4.5 seconds) |
| 2600 | * |
| 2601 | * hw - Struct containing variables accessed by shared code |
| 2602 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 2603 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2604 | e1000_wait_autoneg(struct e1000_hw *hw) |
| 2605 | { |
| 2606 | int32_t ret_val; |
| 2607 | uint16_t i; |
| 2608 | uint16_t phy_data; |
| 2609 | |
| 2610 | DEBUGFUNC("e1000_wait_autoneg"); |
| 2611 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
| 2612 | |
| 2613 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
| 2614 | for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
| 2615 | /* Read the MII Status Register and wait for Auto-Neg |
| 2616 | * Complete bit to be set. |
| 2617 | */ |
| 2618 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 2619 | if(ret_val) |
| 2620 | return ret_val; |
| 2621 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 2622 | if(ret_val) |
| 2623 | return ret_val; |
| 2624 | if(phy_data & MII_SR_AUTONEG_COMPLETE) { |
| 2625 | return E1000_SUCCESS; |
| 2626 | } |
| 2627 | msec_delay(100); |
| 2628 | } |
| 2629 | return E1000_SUCCESS; |
| 2630 | } |
| 2631 | |
| 2632 | /****************************************************************************** |
| 2633 | * Raises the Management Data Clock |
| 2634 | * |
| 2635 | * hw - Struct containing variables accessed by shared code |
| 2636 | * ctrl - Device control register's current value |
| 2637 | ******************************************************************************/ |
| 2638 | static void |
| 2639 | e1000_raise_mdi_clk(struct e1000_hw *hw, |
| 2640 | uint32_t *ctrl) |
| 2641 | { |
| 2642 | /* Raise the clock input to the Management Data Clock (by setting the MDC |
| 2643 | * bit), and then delay 10 microseconds. |
| 2644 | */ |
| 2645 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); |
| 2646 | E1000_WRITE_FLUSH(hw); |
| 2647 | udelay(10); |
| 2648 | } |
| 2649 | |
| 2650 | /****************************************************************************** |
| 2651 | * Lowers the Management Data Clock |
| 2652 | * |
| 2653 | * hw - Struct containing variables accessed by shared code |
| 2654 | * ctrl - Device control register's current value |
| 2655 | ******************************************************************************/ |
| 2656 | static void |
| 2657 | e1000_lower_mdi_clk(struct e1000_hw *hw, |
| 2658 | uint32_t *ctrl) |
| 2659 | { |
| 2660 | /* Lower the clock input to the Management Data Clock (by clearing the MDC |
| 2661 | * bit), and then delay 10 microseconds. |
| 2662 | */ |
| 2663 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
| 2664 | E1000_WRITE_FLUSH(hw); |
| 2665 | udelay(10); |
| 2666 | } |
| 2667 | |
| 2668 | /****************************************************************************** |
| 2669 | * Shifts data bits out to the PHY |
| 2670 | * |
| 2671 | * hw - Struct containing variables accessed by shared code |
| 2672 | * data - Data to send out to the PHY |
| 2673 | * count - Number of bits to shift out |
| 2674 | * |
| 2675 | * Bits are shifted out in MSB to LSB order. |
| 2676 | ******************************************************************************/ |
| 2677 | static void |
| 2678 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, |
| 2679 | uint32_t data, |
| 2680 | uint16_t count) |
| 2681 | { |
| 2682 | uint32_t ctrl; |
| 2683 | uint32_t mask; |
| 2684 | |
| 2685 | /* We need to shift "count" number of bits out to the PHY. So, the value |
| 2686 | * in the "data" parameter will be shifted out to the PHY one bit at a |
| 2687 | * time. In order to do this, "data" must be broken down into bits. |
| 2688 | */ |
| 2689 | mask = 0x01; |
| 2690 | mask <<= (count - 1); |
| 2691 | |
| 2692 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2693 | |
| 2694 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
| 2695 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
| 2696 | |
| 2697 | while(mask) { |
| 2698 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
| 2699 | * then raising and lowering the Management Data Clock. A "0" is |
| 2700 | * shifted out to the PHY by setting the MDIO bit to "0" and then |
| 2701 | * raising and lowering the clock. |
| 2702 | */ |
| 2703 | if(data & mask) ctrl |= E1000_CTRL_MDIO; |
| 2704 | else ctrl &= ~E1000_CTRL_MDIO; |
| 2705 | |
| 2706 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2707 | E1000_WRITE_FLUSH(hw); |
| 2708 | |
| 2709 | udelay(10); |
| 2710 | |
| 2711 | e1000_raise_mdi_clk(hw, &ctrl); |
| 2712 | e1000_lower_mdi_clk(hw, &ctrl); |
| 2713 | |
| 2714 | mask = mask >> 1; |
| 2715 | } |
| 2716 | } |
| 2717 | |
| 2718 | /****************************************************************************** |
| 2719 | * Shifts data bits in from the PHY |
| 2720 | * |
| 2721 | * hw - Struct containing variables accessed by shared code |
| 2722 | * |
| 2723 | * Bits are shifted in in MSB to LSB order. |
| 2724 | ******************************************************************************/ |
| 2725 | static uint16_t |
| 2726 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
| 2727 | { |
| 2728 | uint32_t ctrl; |
| 2729 | uint16_t data = 0; |
| 2730 | uint8_t i; |
| 2731 | |
| 2732 | /* In order to read a register from the PHY, we need to shift in a total |
| 2733 | * of 18 bits from the PHY. The first two bit (turnaround) times are used |
| 2734 | * to avoid contention on the MDIO pin when a read operation is performed. |
| 2735 | * These two bits are ignored by us and thrown away. Bits are "shifted in" |
| 2736 | * by raising the input to the Management Data Clock (setting the MDC bit), |
| 2737 | * and then reading the value of the MDIO bit. |
| 2738 | */ |
| 2739 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2740 | |
| 2741 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
| 2742 | ctrl &= ~E1000_CTRL_MDIO_DIR; |
| 2743 | ctrl &= ~E1000_CTRL_MDIO; |
| 2744 | |
| 2745 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2746 | E1000_WRITE_FLUSH(hw); |
| 2747 | |
| 2748 | /* Raise and Lower the clock before reading in the data. This accounts for |
| 2749 | * the turnaround bits. The first clock occurred when we clocked out the |
| 2750 | * last bit of the Register Address. |
| 2751 | */ |
| 2752 | e1000_raise_mdi_clk(hw, &ctrl); |
| 2753 | e1000_lower_mdi_clk(hw, &ctrl); |
| 2754 | |
| 2755 | for(data = 0, i = 0; i < 16; i++) { |
| 2756 | data = data << 1; |
| 2757 | e1000_raise_mdi_clk(hw, &ctrl); |
| 2758 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2759 | /* Check to see if we shifted in a "1". */ |
| 2760 | if(ctrl & E1000_CTRL_MDIO) data |= 1; |
| 2761 | e1000_lower_mdi_clk(hw, &ctrl); |
| 2762 | } |
| 2763 | |
| 2764 | e1000_raise_mdi_clk(hw, &ctrl); |
| 2765 | e1000_lower_mdi_clk(hw, &ctrl); |
| 2766 | |
| 2767 | return data; |
| 2768 | } |
| 2769 | |
| 2770 | /***************************************************************************** |
| 2771 | * Reads the value from a PHY register, if the value is on a specific non zero |
| 2772 | * page, sets the page first. |
| 2773 | * hw - Struct containing variables accessed by shared code |
| 2774 | * reg_addr - address of the PHY register to read |
| 2775 | ******************************************************************************/ |
| 2776 | int32_t |
| 2777 | e1000_read_phy_reg(struct e1000_hw *hw, |
| 2778 | uint32_t reg_addr, |
| 2779 | uint16_t *phy_data) |
| 2780 | { |
| 2781 | uint32_t ret_val; |
| 2782 | |
| 2783 | DEBUGFUNC("e1000_read_phy_reg"); |
| 2784 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2785 | if((hw->phy_type == e1000_phy_igp || |
| 2786 | hw->phy_type == e1000_phy_igp_2) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2787 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
| 2788 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
| 2789 | (uint16_t)reg_addr); |
| 2790 | if(ret_val) { |
| 2791 | return ret_val; |
| 2792 | } |
| 2793 | } |
| 2794 | |
| 2795 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
| 2796 | phy_data); |
| 2797 | |
| 2798 | return ret_val; |
| 2799 | } |
| 2800 | |
| 2801 | int32_t |
| 2802 | e1000_read_phy_reg_ex(struct e1000_hw *hw, |
| 2803 | uint32_t reg_addr, |
| 2804 | uint16_t *phy_data) |
| 2805 | { |
| 2806 | uint32_t i; |
| 2807 | uint32_t mdic = 0; |
| 2808 | const uint32_t phy_addr = 1; |
| 2809 | |
| 2810 | DEBUGFUNC("e1000_read_phy_reg_ex"); |
| 2811 | |
| 2812 | if(reg_addr > MAX_PHY_REG_ADDRESS) { |
| 2813 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 2814 | return -E1000_ERR_PARAM; |
| 2815 | } |
| 2816 | |
| 2817 | if(hw->mac_type > e1000_82543) { |
| 2818 | /* Set up Op-code, Phy Address, and register address in the MDI |
| 2819 | * Control register. The MAC will take care of interfacing with the |
| 2820 | * PHY to retrieve the desired data. |
| 2821 | */ |
| 2822 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
| 2823 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
| 2824 | (E1000_MDIC_OP_READ)); |
| 2825 | |
| 2826 | E1000_WRITE_REG(hw, MDIC, mdic); |
| 2827 | |
| 2828 | /* Poll the ready bit to see if the MDI read completed */ |
| 2829 | for(i = 0; i < 64; i++) { |
| 2830 | udelay(50); |
| 2831 | mdic = E1000_READ_REG(hw, MDIC); |
| 2832 | if(mdic & E1000_MDIC_READY) break; |
| 2833 | } |
| 2834 | if(!(mdic & E1000_MDIC_READY)) { |
| 2835 | DEBUGOUT("MDI Read did not complete\n"); |
| 2836 | return -E1000_ERR_PHY; |
| 2837 | } |
| 2838 | if(mdic & E1000_MDIC_ERROR) { |
| 2839 | DEBUGOUT("MDI Error\n"); |
| 2840 | return -E1000_ERR_PHY; |
| 2841 | } |
| 2842 | *phy_data = (uint16_t) mdic; |
| 2843 | } else { |
| 2844 | /* We must first send a preamble through the MDIO pin to signal the |
| 2845 | * beginning of an MII instruction. This is done by sending 32 |
| 2846 | * consecutive "1" bits. |
| 2847 | */ |
| 2848 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
| 2849 | |
| 2850 | /* Now combine the next few fields that are required for a read |
| 2851 | * operation. We use this method instead of calling the |
| 2852 | * e1000_shift_out_mdi_bits routine five different times. The format of |
| 2853 | * a MII read instruction consists of a shift out of 14 bits and is |
| 2854 | * defined as follows: |
| 2855 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
| 2856 | * followed by a shift in of 18 bits. This first two bits shifted in |
| 2857 | * are TurnAround bits used to avoid contention on the MDIO pin when a |
| 2858 | * READ operation is performed. These two bits are thrown away |
| 2859 | * followed by a shift in of 16 bits which contains the desired data. |
| 2860 | */ |
| 2861 | mdic = ((reg_addr) | (phy_addr << 5) | |
| 2862 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
| 2863 | |
| 2864 | e1000_shift_out_mdi_bits(hw, mdic, 14); |
| 2865 | |
| 2866 | /* Now that we've shifted out the read command to the MII, we need to |
| 2867 | * "shift in" the 16-bit value (18 total bits) of the requested PHY |
| 2868 | * register address. |
| 2869 | */ |
| 2870 | *phy_data = e1000_shift_in_mdi_bits(hw); |
| 2871 | } |
| 2872 | return E1000_SUCCESS; |
| 2873 | } |
| 2874 | |
| 2875 | /****************************************************************************** |
| 2876 | * Writes a value to a PHY register |
| 2877 | * |
| 2878 | * hw - Struct containing variables accessed by shared code |
| 2879 | * reg_addr - address of the PHY register to write |
| 2880 | * data - data to write to the PHY |
| 2881 | ******************************************************************************/ |
| 2882 | int32_t |
| 2883 | e1000_write_phy_reg(struct e1000_hw *hw, |
| 2884 | uint32_t reg_addr, |
| 2885 | uint16_t phy_data) |
| 2886 | { |
| 2887 | uint32_t ret_val; |
| 2888 | |
| 2889 | DEBUGFUNC("e1000_write_phy_reg"); |
| 2890 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2891 | if((hw->phy_type == e1000_phy_igp || |
| 2892 | hw->phy_type == e1000_phy_igp_2) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2893 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
| 2894 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
| 2895 | (uint16_t)reg_addr); |
| 2896 | if(ret_val) { |
| 2897 | return ret_val; |
| 2898 | } |
| 2899 | } |
| 2900 | |
| 2901 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
| 2902 | phy_data); |
| 2903 | |
| 2904 | return ret_val; |
| 2905 | } |
| 2906 | |
| 2907 | int32_t |
| 2908 | e1000_write_phy_reg_ex(struct e1000_hw *hw, |
| 2909 | uint32_t reg_addr, |
| 2910 | uint16_t phy_data) |
| 2911 | { |
| 2912 | uint32_t i; |
| 2913 | uint32_t mdic = 0; |
| 2914 | const uint32_t phy_addr = 1; |
| 2915 | |
| 2916 | DEBUGFUNC("e1000_write_phy_reg_ex"); |
| 2917 | |
| 2918 | if(reg_addr > MAX_PHY_REG_ADDRESS) { |
| 2919 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 2920 | return -E1000_ERR_PARAM; |
| 2921 | } |
| 2922 | |
| 2923 | if(hw->mac_type > e1000_82543) { |
| 2924 | /* Set up Op-code, Phy Address, register address, and data intended |
| 2925 | * for the PHY register in the MDI Control register. The MAC will take |
| 2926 | * care of interfacing with the PHY to send the desired data. |
| 2927 | */ |
| 2928 | mdic = (((uint32_t) phy_data) | |
| 2929 | (reg_addr << E1000_MDIC_REG_SHIFT) | |
| 2930 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
| 2931 | (E1000_MDIC_OP_WRITE)); |
| 2932 | |
| 2933 | E1000_WRITE_REG(hw, MDIC, mdic); |
| 2934 | |
| 2935 | /* Poll the ready bit to see if the MDI read completed */ |
| 2936 | for(i = 0; i < 640; i++) { |
| 2937 | udelay(5); |
| 2938 | mdic = E1000_READ_REG(hw, MDIC); |
| 2939 | if(mdic & E1000_MDIC_READY) break; |
| 2940 | } |
| 2941 | if(!(mdic & E1000_MDIC_READY)) { |
| 2942 | DEBUGOUT("MDI Write did not complete\n"); |
| 2943 | return -E1000_ERR_PHY; |
| 2944 | } |
| 2945 | } else { |
| 2946 | /* We'll need to use the SW defined pins to shift the write command |
| 2947 | * out to the PHY. We first send a preamble to the PHY to signal the |
| 2948 | * beginning of the MII instruction. This is done by sending 32 |
| 2949 | * consecutive "1" bits. |
| 2950 | */ |
| 2951 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
| 2952 | |
| 2953 | /* Now combine the remaining required fields that will indicate a |
| 2954 | * write operation. We use this method instead of calling the |
| 2955 | * e1000_shift_out_mdi_bits routine for each field in the command. The |
| 2956 | * format of a MII write instruction is as follows: |
| 2957 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
| 2958 | */ |
| 2959 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
| 2960 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
| 2961 | mdic <<= 16; |
| 2962 | mdic |= (uint32_t) phy_data; |
| 2963 | |
| 2964 | e1000_shift_out_mdi_bits(hw, mdic, 32); |
| 2965 | } |
| 2966 | |
| 2967 | return E1000_SUCCESS; |
| 2968 | } |
| 2969 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2970 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2971 | /****************************************************************************** |
| 2972 | * Returns the PHY to the power-on reset state |
| 2973 | * |
| 2974 | * hw - Struct containing variables accessed by shared code |
| 2975 | ******************************************************************************/ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2976 | int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2977 | e1000_phy_hw_reset(struct e1000_hw *hw) |
| 2978 | { |
| 2979 | uint32_t ctrl, ctrl_ext; |
| 2980 | uint32_t led_ctrl; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2981 | int32_t ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2982 | |
| 2983 | DEBUGFUNC("e1000_phy_hw_reset"); |
| 2984 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2985 | /* In the case of the phy reset being blocked, it's not an error, we |
| 2986 | * simply return success without performing the reset. */ |
| 2987 | ret_val = e1000_check_phy_reset_block(hw); |
| 2988 | if (ret_val) |
| 2989 | return E1000_SUCCESS; |
| 2990 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2991 | DEBUGOUT("Resetting Phy...\n"); |
| 2992 | |
| 2993 | if(hw->mac_type > e1000_82543) { |
| 2994 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
| 2995 | * bit. Then, take it out of reset. |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 2996 | * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
| 2997 | * and deassert. For e1000_82571 hardware and later, we instead delay |
| 2998 | * for 10ms after the deassertion. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2999 | */ |
| 3000 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3001 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); |
| 3002 | E1000_WRITE_FLUSH(hw); |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 3003 | |
| 3004 | if (hw->mac_type < e1000_82571) |
| 3005 | msec_delay(10); |
Jeff Kirsher | b55ccb3 | 2006-01-12 16:50:30 -0800 | [diff] [blame] | 3006 | else |
| 3007 | udelay(100); |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 3008 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3009 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3010 | E1000_WRITE_FLUSH(hw); |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 3011 | |
| 3012 | if (hw->mac_type >= e1000_82571) |
| 3013 | msec_delay(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3014 | } else { |
| 3015 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
| 3016 | * bit to put the PHY into reset. Then, take it out of reset. |
| 3017 | */ |
| 3018 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 3019 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
| 3020 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
| 3021 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 3022 | E1000_WRITE_FLUSH(hw); |
| 3023 | msec_delay(10); |
| 3024 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
| 3025 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 3026 | E1000_WRITE_FLUSH(hw); |
| 3027 | } |
| 3028 | udelay(150); |
| 3029 | |
| 3030 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
| 3031 | /* Configure activity LED after PHY reset */ |
| 3032 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 3033 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 3034 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 3035 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 3036 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3037 | |
| 3038 | /* Wait for FW to finish PHY configuration. */ |
| 3039 | ret_val = e1000_get_phy_cfg_done(hw); |
| 3040 | |
| 3041 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3042 | } |
| 3043 | |
| 3044 | /****************************************************************************** |
| 3045 | * Resets the PHY |
| 3046 | * |
| 3047 | * hw - Struct containing variables accessed by shared code |
| 3048 | * |
| 3049 | * Sets bit 15 of the MII Control regiser |
| 3050 | ******************************************************************************/ |
| 3051 | int32_t |
| 3052 | e1000_phy_reset(struct e1000_hw *hw) |
| 3053 | { |
| 3054 | int32_t ret_val; |
| 3055 | uint16_t phy_data; |
| 3056 | |
| 3057 | DEBUGFUNC("e1000_phy_reset"); |
| 3058 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3059 | /* In the case of the phy reset being blocked, it's not an error, we |
| 3060 | * simply return success without performing the reset. */ |
| 3061 | ret_val = e1000_check_phy_reset_block(hw); |
| 3062 | if (ret_val) |
| 3063 | return E1000_SUCCESS; |
| 3064 | |
| 3065 | switch (hw->mac_type) { |
| 3066 | case e1000_82541_rev_2: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 3067 | case e1000_82571: |
| 3068 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3069 | ret_val = e1000_phy_hw_reset(hw); |
| 3070 | if(ret_val) |
| 3071 | return ret_val; |
| 3072 | break; |
| 3073 | default: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3074 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
| 3075 | if(ret_val) |
| 3076 | return ret_val; |
| 3077 | |
| 3078 | phy_data |= MII_CR_RESET; |
| 3079 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
| 3080 | if(ret_val) |
| 3081 | return ret_val; |
| 3082 | |
| 3083 | udelay(1); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3084 | break; |
| 3085 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3086 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3087 | if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3088 | e1000_phy_init_script(hw); |
| 3089 | |
| 3090 | return E1000_SUCCESS; |
| 3091 | } |
| 3092 | |
| 3093 | /****************************************************************************** |
| 3094 | * Probes the expected PHY address for known PHY IDs |
| 3095 | * |
| 3096 | * hw - Struct containing variables accessed by shared code |
| 3097 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 3098 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3099 | e1000_detect_gig_phy(struct e1000_hw *hw) |
| 3100 | { |
| 3101 | int32_t phy_init_status, ret_val; |
| 3102 | uint16_t phy_id_high, phy_id_low; |
| 3103 | boolean_t match = FALSE; |
| 3104 | |
| 3105 | DEBUGFUNC("e1000_detect_gig_phy"); |
| 3106 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 3107 | /* The 82571 firmware may still be configuring the PHY. In this |
| 3108 | * case, we cannot access the PHY until the configuration is done. So |
| 3109 | * we explicitly set the PHY values. */ |
| 3110 | if(hw->mac_type == e1000_82571 || |
| 3111 | hw->mac_type == e1000_82572) { |
| 3112 | hw->phy_id = IGP01E1000_I_PHY_ID; |
| 3113 | hw->phy_type = e1000_phy_igp_2; |
| 3114 | return E1000_SUCCESS; |
| 3115 | } |
| 3116 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3117 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
| 3118 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
| 3119 | if(ret_val) |
| 3120 | return ret_val; |
| 3121 | |
| 3122 | hw->phy_id = (uint32_t) (phy_id_high << 16); |
| 3123 | udelay(20); |
| 3124 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
| 3125 | if(ret_val) |
| 3126 | return ret_val; |
| 3127 | |
| 3128 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
| 3129 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
| 3130 | |
| 3131 | switch(hw->mac_type) { |
| 3132 | case e1000_82543: |
| 3133 | if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; |
| 3134 | break; |
| 3135 | case e1000_82544: |
| 3136 | if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; |
| 3137 | break; |
| 3138 | case e1000_82540: |
| 3139 | case e1000_82545: |
| 3140 | case e1000_82545_rev_3: |
| 3141 | case e1000_82546: |
| 3142 | case e1000_82546_rev_3: |
| 3143 | if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; |
| 3144 | break; |
| 3145 | case e1000_82541: |
| 3146 | case e1000_82541_rev_2: |
| 3147 | case e1000_82547: |
| 3148 | case e1000_82547_rev_2: |
| 3149 | if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
| 3150 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3151 | case e1000_82573: |
| 3152 | if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; |
| 3153 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3154 | default: |
| 3155 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); |
| 3156 | return -E1000_ERR_CONFIG; |
| 3157 | } |
| 3158 | phy_init_status = e1000_set_phy_type(hw); |
| 3159 | |
| 3160 | if ((match) && (phy_init_status == E1000_SUCCESS)) { |
| 3161 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); |
| 3162 | return E1000_SUCCESS; |
| 3163 | } |
| 3164 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); |
| 3165 | return -E1000_ERR_PHY; |
| 3166 | } |
| 3167 | |
| 3168 | /****************************************************************************** |
| 3169 | * Resets the PHY's DSP |
| 3170 | * |
| 3171 | * hw - Struct containing variables accessed by shared code |
| 3172 | ******************************************************************************/ |
| 3173 | static int32_t |
| 3174 | e1000_phy_reset_dsp(struct e1000_hw *hw) |
| 3175 | { |
| 3176 | int32_t ret_val; |
| 3177 | DEBUGFUNC("e1000_phy_reset_dsp"); |
| 3178 | |
| 3179 | do { |
| 3180 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
| 3181 | if(ret_val) break; |
| 3182 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
| 3183 | if(ret_val) break; |
| 3184 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
| 3185 | if(ret_val) break; |
| 3186 | ret_val = E1000_SUCCESS; |
| 3187 | } while(0); |
| 3188 | |
| 3189 | return ret_val; |
| 3190 | } |
| 3191 | |
| 3192 | /****************************************************************************** |
| 3193 | * Get PHY information from various PHY registers for igp PHY only. |
| 3194 | * |
| 3195 | * hw - Struct containing variables accessed by shared code |
| 3196 | * phy_info - PHY information structure |
| 3197 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 3198 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3199 | e1000_phy_igp_get_info(struct e1000_hw *hw, |
| 3200 | struct e1000_phy_info *phy_info) |
| 3201 | { |
| 3202 | int32_t ret_val; |
| 3203 | uint16_t phy_data, polarity, min_length, max_length, average; |
| 3204 | |
| 3205 | DEBUGFUNC("e1000_phy_igp_get_info"); |
| 3206 | |
| 3207 | /* The downshift status is checked only once, after link is established, |
| 3208 | * and it stored in the hw->speed_downgraded parameter. */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3209 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3210 | |
| 3211 | /* IGP01E1000 does not need to support it. */ |
| 3212 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
| 3213 | |
| 3214 | /* IGP01E1000 always correct polarity reversal */ |
| 3215 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
| 3216 | |
| 3217 | /* Check polarity status */ |
| 3218 | ret_val = e1000_check_polarity(hw, &polarity); |
| 3219 | if(ret_val) |
| 3220 | return ret_val; |
| 3221 | |
| 3222 | phy_info->cable_polarity = polarity; |
| 3223 | |
| 3224 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
| 3225 | if(ret_val) |
| 3226 | return ret_val; |
| 3227 | |
| 3228 | phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> |
| 3229 | IGP01E1000_PSSR_MDIX_SHIFT; |
| 3230 | |
| 3231 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
| 3232 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
| 3233 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
| 3234 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
| 3235 | if(ret_val) |
| 3236 | return ret_val; |
| 3237 | |
| 3238 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
| 3239 | SR_1000T_LOCAL_RX_STATUS_SHIFT; |
| 3240 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
| 3241 | SR_1000T_REMOTE_RX_STATUS_SHIFT; |
| 3242 | |
| 3243 | /* Get cable length */ |
| 3244 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
| 3245 | if(ret_val) |
| 3246 | return ret_val; |
| 3247 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3248 | /* Translate to old method */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3249 | average = (max_length + min_length) / 2; |
| 3250 | |
| 3251 | if(average <= e1000_igp_cable_length_50) |
| 3252 | phy_info->cable_length = e1000_cable_length_50; |
| 3253 | else if(average <= e1000_igp_cable_length_80) |
| 3254 | phy_info->cable_length = e1000_cable_length_50_80; |
| 3255 | else if(average <= e1000_igp_cable_length_110) |
| 3256 | phy_info->cable_length = e1000_cable_length_80_110; |
| 3257 | else if(average <= e1000_igp_cable_length_140) |
| 3258 | phy_info->cable_length = e1000_cable_length_110_140; |
| 3259 | else |
| 3260 | phy_info->cable_length = e1000_cable_length_140; |
| 3261 | } |
| 3262 | |
| 3263 | return E1000_SUCCESS; |
| 3264 | } |
| 3265 | |
| 3266 | /****************************************************************************** |
| 3267 | * Get PHY information from various PHY registers fot m88 PHY only. |
| 3268 | * |
| 3269 | * hw - Struct containing variables accessed by shared code |
| 3270 | * phy_info - PHY information structure |
| 3271 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 3272 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3273 | e1000_phy_m88_get_info(struct e1000_hw *hw, |
| 3274 | struct e1000_phy_info *phy_info) |
| 3275 | { |
| 3276 | int32_t ret_val; |
| 3277 | uint16_t phy_data, polarity; |
| 3278 | |
| 3279 | DEBUGFUNC("e1000_phy_m88_get_info"); |
| 3280 | |
| 3281 | /* The downshift status is checked only once, after link is established, |
| 3282 | * and it stored in the hw->speed_downgraded parameter. */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3283 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3284 | |
| 3285 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 3286 | if(ret_val) |
| 3287 | return ret_val; |
| 3288 | |
| 3289 | phy_info->extended_10bt_distance = |
| 3290 | (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
| 3291 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; |
| 3292 | phy_info->polarity_correction = |
| 3293 | (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
| 3294 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; |
| 3295 | |
| 3296 | /* Check polarity status */ |
| 3297 | ret_val = e1000_check_polarity(hw, &polarity); |
| 3298 | if(ret_val) |
| 3299 | return ret_val; |
| 3300 | phy_info->cable_polarity = polarity; |
| 3301 | |
| 3302 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
| 3303 | if(ret_val) |
| 3304 | return ret_val; |
| 3305 | |
| 3306 | phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> |
| 3307 | M88E1000_PSSR_MDIX_SHIFT; |
| 3308 | |
| 3309 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
| 3310 | /* Cable Length Estimation and Local/Remote Receiver Information |
| 3311 | * are only valid at 1000 Mbps. |
| 3312 | */ |
| 3313 | phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 3314 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
| 3315 | |
| 3316 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
| 3317 | if(ret_val) |
| 3318 | return ret_val; |
| 3319 | |
| 3320 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
| 3321 | SR_1000T_LOCAL_RX_STATUS_SHIFT; |
| 3322 | |
| 3323 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
| 3324 | SR_1000T_REMOTE_RX_STATUS_SHIFT; |
| 3325 | } |
| 3326 | |
| 3327 | return E1000_SUCCESS; |
| 3328 | } |
| 3329 | |
| 3330 | /****************************************************************************** |
| 3331 | * Get PHY information from various PHY registers |
| 3332 | * |
| 3333 | * hw - Struct containing variables accessed by shared code |
| 3334 | * phy_info - PHY information structure |
| 3335 | ******************************************************************************/ |
| 3336 | int32_t |
| 3337 | e1000_phy_get_info(struct e1000_hw *hw, |
| 3338 | struct e1000_phy_info *phy_info) |
| 3339 | { |
| 3340 | int32_t ret_val; |
| 3341 | uint16_t phy_data; |
| 3342 | |
| 3343 | DEBUGFUNC("e1000_phy_get_info"); |
| 3344 | |
| 3345 | phy_info->cable_length = e1000_cable_length_undefined; |
| 3346 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
| 3347 | phy_info->cable_polarity = e1000_rev_polarity_undefined; |
| 3348 | phy_info->downshift = e1000_downshift_undefined; |
| 3349 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
| 3350 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
| 3351 | phy_info->local_rx = e1000_1000t_rx_status_undefined; |
| 3352 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
| 3353 | |
| 3354 | if(hw->media_type != e1000_media_type_copper) { |
| 3355 | DEBUGOUT("PHY info is only valid for copper media\n"); |
| 3356 | return -E1000_ERR_CONFIG; |
| 3357 | } |
| 3358 | |
| 3359 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 3360 | if(ret_val) |
| 3361 | return ret_val; |
| 3362 | |
| 3363 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 3364 | if(ret_val) |
| 3365 | return ret_val; |
| 3366 | |
| 3367 | if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
| 3368 | DEBUGOUT("PHY info is only valid if link is up\n"); |
| 3369 | return -E1000_ERR_CONFIG; |
| 3370 | } |
| 3371 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3372 | if(hw->phy_type == e1000_phy_igp || |
| 3373 | hw->phy_type == e1000_phy_igp_2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3374 | return e1000_phy_igp_get_info(hw, phy_info); |
| 3375 | else |
| 3376 | return e1000_phy_m88_get_info(hw, phy_info); |
| 3377 | } |
| 3378 | |
| 3379 | int32_t |
| 3380 | e1000_validate_mdi_setting(struct e1000_hw *hw) |
| 3381 | { |
| 3382 | DEBUGFUNC("e1000_validate_mdi_settings"); |
| 3383 | |
| 3384 | if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
| 3385 | DEBUGOUT("Invalid MDI setting detected\n"); |
| 3386 | hw->mdix = 1; |
| 3387 | return -E1000_ERR_CONFIG; |
| 3388 | } |
| 3389 | return E1000_SUCCESS; |
| 3390 | } |
| 3391 | |
| 3392 | |
| 3393 | /****************************************************************************** |
| 3394 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
| 3395 | * is configured. |
| 3396 | * |
| 3397 | * hw - Struct containing variables accessed by shared code |
| 3398 | *****************************************************************************/ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3399 | int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3400 | e1000_init_eeprom_params(struct e1000_hw *hw) |
| 3401 | { |
| 3402 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 3403 | uint32_t eecd = E1000_READ_REG(hw, EECD); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3404 | int32_t ret_val = E1000_SUCCESS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3405 | uint16_t eeprom_size; |
| 3406 | |
| 3407 | DEBUGFUNC("e1000_init_eeprom_params"); |
| 3408 | |
| 3409 | switch (hw->mac_type) { |
| 3410 | case e1000_82542_rev2_0: |
| 3411 | case e1000_82542_rev2_1: |
| 3412 | case e1000_82543: |
| 3413 | case e1000_82544: |
| 3414 | eeprom->type = e1000_eeprom_microwire; |
| 3415 | eeprom->word_size = 64; |
| 3416 | eeprom->opcode_bits = 3; |
| 3417 | eeprom->address_bits = 6; |
| 3418 | eeprom->delay_usec = 50; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3419 | eeprom->use_eerd = FALSE; |
| 3420 | eeprom->use_eewr = FALSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3421 | break; |
| 3422 | case e1000_82540: |
| 3423 | case e1000_82545: |
| 3424 | case e1000_82545_rev_3: |
| 3425 | case e1000_82546: |
| 3426 | case e1000_82546_rev_3: |
| 3427 | eeprom->type = e1000_eeprom_microwire; |
| 3428 | eeprom->opcode_bits = 3; |
| 3429 | eeprom->delay_usec = 50; |
| 3430 | if(eecd & E1000_EECD_SIZE) { |
| 3431 | eeprom->word_size = 256; |
| 3432 | eeprom->address_bits = 8; |
| 3433 | } else { |
| 3434 | eeprom->word_size = 64; |
| 3435 | eeprom->address_bits = 6; |
| 3436 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3437 | eeprom->use_eerd = FALSE; |
| 3438 | eeprom->use_eewr = FALSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3439 | break; |
| 3440 | case e1000_82541: |
| 3441 | case e1000_82541_rev_2: |
| 3442 | case e1000_82547: |
| 3443 | case e1000_82547_rev_2: |
| 3444 | if (eecd & E1000_EECD_TYPE) { |
| 3445 | eeprom->type = e1000_eeprom_spi; |
| 3446 | eeprom->opcode_bits = 8; |
| 3447 | eeprom->delay_usec = 1; |
| 3448 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 3449 | eeprom->page_size = 32; |
| 3450 | eeprom->address_bits = 16; |
| 3451 | } else { |
| 3452 | eeprom->page_size = 8; |
| 3453 | eeprom->address_bits = 8; |
| 3454 | } |
| 3455 | } else { |
| 3456 | eeprom->type = e1000_eeprom_microwire; |
| 3457 | eeprom->opcode_bits = 3; |
| 3458 | eeprom->delay_usec = 50; |
| 3459 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 3460 | eeprom->word_size = 256; |
| 3461 | eeprom->address_bits = 8; |
| 3462 | } else { |
| 3463 | eeprom->word_size = 64; |
| 3464 | eeprom->address_bits = 6; |
| 3465 | } |
| 3466 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3467 | eeprom->use_eerd = FALSE; |
| 3468 | eeprom->use_eewr = FALSE; |
| 3469 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 3470 | case e1000_82571: |
| 3471 | case e1000_82572: |
| 3472 | eeprom->type = e1000_eeprom_spi; |
| 3473 | eeprom->opcode_bits = 8; |
| 3474 | eeprom->delay_usec = 1; |
| 3475 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 3476 | eeprom->page_size = 32; |
| 3477 | eeprom->address_bits = 16; |
| 3478 | } else { |
| 3479 | eeprom->page_size = 8; |
| 3480 | eeprom->address_bits = 8; |
| 3481 | } |
| 3482 | eeprom->use_eerd = FALSE; |
| 3483 | eeprom->use_eewr = FALSE; |
| 3484 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3485 | case e1000_82573: |
| 3486 | eeprom->type = e1000_eeprom_spi; |
| 3487 | eeprom->opcode_bits = 8; |
| 3488 | eeprom->delay_usec = 1; |
| 3489 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 3490 | eeprom->page_size = 32; |
| 3491 | eeprom->address_bits = 16; |
| 3492 | } else { |
| 3493 | eeprom->page_size = 8; |
| 3494 | eeprom->address_bits = 8; |
| 3495 | } |
| 3496 | eeprom->use_eerd = TRUE; |
| 3497 | eeprom->use_eewr = TRUE; |
| 3498 | if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
| 3499 | eeprom->type = e1000_eeprom_flash; |
| 3500 | eeprom->word_size = 2048; |
| 3501 | |
| 3502 | /* Ensure that the Autonomous FLASH update bit is cleared due to |
| 3503 | * Flash update issue on parts which use a FLASH for NVM. */ |
| 3504 | eecd &= ~E1000_EECD_AUPDEN; |
| 3505 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3506 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3507 | break; |
| 3508 | default: |
| 3509 | break; |
| 3510 | } |
| 3511 | |
| 3512 | if (eeprom->type == e1000_eeprom_spi) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3513 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
| 3514 | * 32KB (incremented by powers of 2). |
| 3515 | */ |
| 3516 | if(hw->mac_type <= e1000_82547_rev_2) { |
| 3517 | /* Set to default value for initial eeprom read. */ |
| 3518 | eeprom->word_size = 64; |
| 3519 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
| 3520 | if(ret_val) |
| 3521 | return ret_val; |
| 3522 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
| 3523 | /* 256B eeprom size was not supported in earlier hardware, so we |
| 3524 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
| 3525 | * is never the result used in the shifting logic below. */ |
| 3526 | if(eeprom_size) |
| 3527 | eeprom_size++; |
| 3528 | } else { |
| 3529 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
| 3530 | E1000_EECD_SIZE_EX_SHIFT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3531 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3532 | |
| 3533 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3534 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3535 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3536 | } |
| 3537 | |
| 3538 | /****************************************************************************** |
| 3539 | * Raises the EEPROM's clock input. |
| 3540 | * |
| 3541 | * hw - Struct containing variables accessed by shared code |
| 3542 | * eecd - EECD's current value |
| 3543 | *****************************************************************************/ |
| 3544 | static void |
| 3545 | e1000_raise_ee_clk(struct e1000_hw *hw, |
| 3546 | uint32_t *eecd) |
| 3547 | { |
| 3548 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
| 3549 | * wait <delay> microseconds. |
| 3550 | */ |
| 3551 | *eecd = *eecd | E1000_EECD_SK; |
| 3552 | E1000_WRITE_REG(hw, EECD, *eecd); |
| 3553 | E1000_WRITE_FLUSH(hw); |
| 3554 | udelay(hw->eeprom.delay_usec); |
| 3555 | } |
| 3556 | |
| 3557 | /****************************************************************************** |
| 3558 | * Lowers the EEPROM's clock input. |
| 3559 | * |
| 3560 | * hw - Struct containing variables accessed by shared code |
| 3561 | * eecd - EECD's current value |
| 3562 | *****************************************************************************/ |
| 3563 | static void |
| 3564 | e1000_lower_ee_clk(struct e1000_hw *hw, |
| 3565 | uint32_t *eecd) |
| 3566 | { |
| 3567 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
| 3568 | * wait 50 microseconds. |
| 3569 | */ |
| 3570 | *eecd = *eecd & ~E1000_EECD_SK; |
| 3571 | E1000_WRITE_REG(hw, EECD, *eecd); |
| 3572 | E1000_WRITE_FLUSH(hw); |
| 3573 | udelay(hw->eeprom.delay_usec); |
| 3574 | } |
| 3575 | |
| 3576 | /****************************************************************************** |
| 3577 | * Shift data bits out to the EEPROM. |
| 3578 | * |
| 3579 | * hw - Struct containing variables accessed by shared code |
| 3580 | * data - data to send to the EEPROM |
| 3581 | * count - number of bits to shift out |
| 3582 | *****************************************************************************/ |
| 3583 | static void |
| 3584 | e1000_shift_out_ee_bits(struct e1000_hw *hw, |
| 3585 | uint16_t data, |
| 3586 | uint16_t count) |
| 3587 | { |
| 3588 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 3589 | uint32_t eecd; |
| 3590 | uint32_t mask; |
| 3591 | |
| 3592 | /* We need to shift "count" bits out to the EEPROM. So, value in the |
| 3593 | * "data" parameter will be shifted out to the EEPROM one bit at a time. |
| 3594 | * In order to do this, "data" must be broken down into bits. |
| 3595 | */ |
| 3596 | mask = 0x01 << (count - 1); |
| 3597 | eecd = E1000_READ_REG(hw, EECD); |
| 3598 | if (eeprom->type == e1000_eeprom_microwire) { |
| 3599 | eecd &= ~E1000_EECD_DO; |
| 3600 | } else if (eeprom->type == e1000_eeprom_spi) { |
| 3601 | eecd |= E1000_EECD_DO; |
| 3602 | } |
| 3603 | do { |
| 3604 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
| 3605 | * and then raising and then lowering the clock (the SK bit controls |
| 3606 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
| 3607 | * by setting "DI" to "0" and then raising and then lowering the clock. |
| 3608 | */ |
| 3609 | eecd &= ~E1000_EECD_DI; |
| 3610 | |
| 3611 | if(data & mask) |
| 3612 | eecd |= E1000_EECD_DI; |
| 3613 | |
| 3614 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3615 | E1000_WRITE_FLUSH(hw); |
| 3616 | |
| 3617 | udelay(eeprom->delay_usec); |
| 3618 | |
| 3619 | e1000_raise_ee_clk(hw, &eecd); |
| 3620 | e1000_lower_ee_clk(hw, &eecd); |
| 3621 | |
| 3622 | mask = mask >> 1; |
| 3623 | |
| 3624 | } while(mask); |
| 3625 | |
| 3626 | /* We leave the "DI" bit set to "0" when we leave this routine. */ |
| 3627 | eecd &= ~E1000_EECD_DI; |
| 3628 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3629 | } |
| 3630 | |
| 3631 | /****************************************************************************** |
| 3632 | * Shift data bits in from the EEPROM |
| 3633 | * |
| 3634 | * hw - Struct containing variables accessed by shared code |
| 3635 | *****************************************************************************/ |
| 3636 | static uint16_t |
| 3637 | e1000_shift_in_ee_bits(struct e1000_hw *hw, |
| 3638 | uint16_t count) |
| 3639 | { |
| 3640 | uint32_t eecd; |
| 3641 | uint32_t i; |
| 3642 | uint16_t data; |
| 3643 | |
| 3644 | /* In order to read a register from the EEPROM, we need to shift 'count' |
| 3645 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
| 3646 | * input to the EEPROM (setting the SK bit), and then reading the value of |
| 3647 | * the "DO" bit. During this "shifting in" process the "DI" bit should |
| 3648 | * always be clear. |
| 3649 | */ |
| 3650 | |
| 3651 | eecd = E1000_READ_REG(hw, EECD); |
| 3652 | |
| 3653 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
| 3654 | data = 0; |
| 3655 | |
| 3656 | for(i = 0; i < count; i++) { |
| 3657 | data = data << 1; |
| 3658 | e1000_raise_ee_clk(hw, &eecd); |
| 3659 | |
| 3660 | eecd = E1000_READ_REG(hw, EECD); |
| 3661 | |
| 3662 | eecd &= ~(E1000_EECD_DI); |
| 3663 | if(eecd & E1000_EECD_DO) |
| 3664 | data |= 1; |
| 3665 | |
| 3666 | e1000_lower_ee_clk(hw, &eecd); |
| 3667 | } |
| 3668 | |
| 3669 | return data; |
| 3670 | } |
| 3671 | |
| 3672 | /****************************************************************************** |
| 3673 | * Prepares EEPROM for access |
| 3674 | * |
| 3675 | * hw - Struct containing variables accessed by shared code |
| 3676 | * |
| 3677 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
| 3678 | * function should be called before issuing a command to the EEPROM. |
| 3679 | *****************************************************************************/ |
| 3680 | static int32_t |
| 3681 | e1000_acquire_eeprom(struct e1000_hw *hw) |
| 3682 | { |
| 3683 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 3684 | uint32_t eecd, i=0; |
| 3685 | |
| 3686 | DEBUGFUNC("e1000_acquire_eeprom"); |
| 3687 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3688 | if(e1000_get_hw_eeprom_semaphore(hw)) |
| 3689 | return -E1000_ERR_EEPROM; |
| 3690 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3691 | eecd = E1000_READ_REG(hw, EECD); |
| 3692 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3693 | if (hw->mac_type != e1000_82573) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 3694 | /* Request EEPROM Access */ |
| 3695 | if(hw->mac_type > e1000_82544) { |
| 3696 | eecd |= E1000_EECD_REQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3697 | E1000_WRITE_REG(hw, EECD, eecd); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 3698 | eecd = E1000_READ_REG(hw, EECD); |
| 3699 | while((!(eecd & E1000_EECD_GNT)) && |
| 3700 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
| 3701 | i++; |
| 3702 | udelay(5); |
| 3703 | eecd = E1000_READ_REG(hw, EECD); |
| 3704 | } |
| 3705 | if(!(eecd & E1000_EECD_GNT)) { |
| 3706 | eecd &= ~E1000_EECD_REQ; |
| 3707 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3708 | DEBUGOUT("Could not acquire EEPROM grant\n"); |
| 3709 | e1000_put_hw_eeprom_semaphore(hw); |
| 3710 | return -E1000_ERR_EEPROM; |
| 3711 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3712 | } |
| 3713 | } |
| 3714 | |
| 3715 | /* Setup EEPROM for Read/Write */ |
| 3716 | |
| 3717 | if (eeprom->type == e1000_eeprom_microwire) { |
| 3718 | /* Clear SK and DI */ |
| 3719 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
| 3720 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3721 | |
| 3722 | /* Set CS */ |
| 3723 | eecd |= E1000_EECD_CS; |
| 3724 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3725 | } else if (eeprom->type == e1000_eeprom_spi) { |
| 3726 | /* Clear SK and CS */ |
| 3727 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 3728 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3729 | udelay(1); |
| 3730 | } |
| 3731 | |
| 3732 | return E1000_SUCCESS; |
| 3733 | } |
| 3734 | |
| 3735 | /****************************************************************************** |
| 3736 | * Returns EEPROM to a "standby" state |
| 3737 | * |
| 3738 | * hw - Struct containing variables accessed by shared code |
| 3739 | *****************************************************************************/ |
| 3740 | static void |
| 3741 | e1000_standby_eeprom(struct e1000_hw *hw) |
| 3742 | { |
| 3743 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 3744 | uint32_t eecd; |
| 3745 | |
| 3746 | eecd = E1000_READ_REG(hw, EECD); |
| 3747 | |
| 3748 | if(eeprom->type == e1000_eeprom_microwire) { |
| 3749 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 3750 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3751 | E1000_WRITE_FLUSH(hw); |
| 3752 | udelay(eeprom->delay_usec); |
| 3753 | |
| 3754 | /* Clock high */ |
| 3755 | eecd |= E1000_EECD_SK; |
| 3756 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3757 | E1000_WRITE_FLUSH(hw); |
| 3758 | udelay(eeprom->delay_usec); |
| 3759 | |
| 3760 | /* Select EEPROM */ |
| 3761 | eecd |= E1000_EECD_CS; |
| 3762 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3763 | E1000_WRITE_FLUSH(hw); |
| 3764 | udelay(eeprom->delay_usec); |
| 3765 | |
| 3766 | /* Clock low */ |
| 3767 | eecd &= ~E1000_EECD_SK; |
| 3768 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3769 | E1000_WRITE_FLUSH(hw); |
| 3770 | udelay(eeprom->delay_usec); |
| 3771 | } else if(eeprom->type == e1000_eeprom_spi) { |
| 3772 | /* Toggle CS to flush commands */ |
| 3773 | eecd |= E1000_EECD_CS; |
| 3774 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3775 | E1000_WRITE_FLUSH(hw); |
| 3776 | udelay(eeprom->delay_usec); |
| 3777 | eecd &= ~E1000_EECD_CS; |
| 3778 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3779 | E1000_WRITE_FLUSH(hw); |
| 3780 | udelay(eeprom->delay_usec); |
| 3781 | } |
| 3782 | } |
| 3783 | |
| 3784 | /****************************************************************************** |
| 3785 | * Terminates a command by inverting the EEPROM's chip select pin |
| 3786 | * |
| 3787 | * hw - Struct containing variables accessed by shared code |
| 3788 | *****************************************************************************/ |
| 3789 | static void |
| 3790 | e1000_release_eeprom(struct e1000_hw *hw) |
| 3791 | { |
| 3792 | uint32_t eecd; |
| 3793 | |
| 3794 | DEBUGFUNC("e1000_release_eeprom"); |
| 3795 | |
| 3796 | eecd = E1000_READ_REG(hw, EECD); |
| 3797 | |
| 3798 | if (hw->eeprom.type == e1000_eeprom_spi) { |
| 3799 | eecd |= E1000_EECD_CS; /* Pull CS high */ |
| 3800 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
| 3801 | |
| 3802 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3803 | |
| 3804 | udelay(hw->eeprom.delay_usec); |
| 3805 | } else if(hw->eeprom.type == e1000_eeprom_microwire) { |
| 3806 | /* cleanup eeprom */ |
| 3807 | |
| 3808 | /* CS on Microwire is active-high */ |
| 3809 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
| 3810 | |
| 3811 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3812 | |
| 3813 | /* Rising edge of clock */ |
| 3814 | eecd |= E1000_EECD_SK; |
| 3815 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3816 | E1000_WRITE_FLUSH(hw); |
| 3817 | udelay(hw->eeprom.delay_usec); |
| 3818 | |
| 3819 | /* Falling edge of clock */ |
| 3820 | eecd &= ~E1000_EECD_SK; |
| 3821 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3822 | E1000_WRITE_FLUSH(hw); |
| 3823 | udelay(hw->eeprom.delay_usec); |
| 3824 | } |
| 3825 | |
| 3826 | /* Stop requesting EEPROM access */ |
| 3827 | if(hw->mac_type > e1000_82544) { |
| 3828 | eecd &= ~E1000_EECD_REQ; |
| 3829 | E1000_WRITE_REG(hw, EECD, eecd); |
| 3830 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3831 | |
| 3832 | e1000_put_hw_eeprom_semaphore(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3833 | } |
| 3834 | |
| 3835 | /****************************************************************************** |
| 3836 | * Reads a 16 bit word from the EEPROM. |
| 3837 | * |
| 3838 | * hw - Struct containing variables accessed by shared code |
| 3839 | *****************************************************************************/ |
| 3840 | int32_t |
| 3841 | e1000_spi_eeprom_ready(struct e1000_hw *hw) |
| 3842 | { |
| 3843 | uint16_t retry_count = 0; |
| 3844 | uint8_t spi_stat_reg; |
| 3845 | |
| 3846 | DEBUGFUNC("e1000_spi_eeprom_ready"); |
| 3847 | |
| 3848 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
| 3849 | * EEPROM will signal that the command has been completed by clearing |
| 3850 | * bit 0 of the internal status register. If it's not cleared within |
| 3851 | * 5 milliseconds, then error out. |
| 3852 | */ |
| 3853 | retry_count = 0; |
| 3854 | do { |
| 3855 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
| 3856 | hw->eeprom.opcode_bits); |
| 3857 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); |
| 3858 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
| 3859 | break; |
| 3860 | |
| 3861 | udelay(5); |
| 3862 | retry_count += 5; |
| 3863 | |
| 3864 | e1000_standby_eeprom(hw); |
| 3865 | } while(retry_count < EEPROM_MAX_RETRY_SPI); |
| 3866 | |
| 3867 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
| 3868 | * only 0-5mSec on 5V devices) |
| 3869 | */ |
| 3870 | if(retry_count >= EEPROM_MAX_RETRY_SPI) { |
| 3871 | DEBUGOUT("SPI EEPROM Status error\n"); |
| 3872 | return -E1000_ERR_EEPROM; |
| 3873 | } |
| 3874 | |
| 3875 | return E1000_SUCCESS; |
| 3876 | } |
| 3877 | |
| 3878 | /****************************************************************************** |
| 3879 | * Reads a 16 bit word from the EEPROM. |
| 3880 | * |
| 3881 | * hw - Struct containing variables accessed by shared code |
| 3882 | * offset - offset of word in the EEPROM to read |
| 3883 | * data - word read from the EEPROM |
| 3884 | * words - number of words to read |
| 3885 | *****************************************************************************/ |
| 3886 | int32_t |
| 3887 | e1000_read_eeprom(struct e1000_hw *hw, |
| 3888 | uint16_t offset, |
| 3889 | uint16_t words, |
| 3890 | uint16_t *data) |
| 3891 | { |
| 3892 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 3893 | uint32_t i = 0; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3894 | int32_t ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3895 | |
| 3896 | DEBUGFUNC("e1000_read_eeprom"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3897 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3898 | /* A check for invalid values: offset too large, too many words, and not |
| 3899 | * enough words. |
| 3900 | */ |
| 3901 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
| 3902 | (words == 0)) { |
| 3903 | DEBUGOUT("\"words\" parameter out of bounds\n"); |
| 3904 | return -E1000_ERR_EEPROM; |
| 3905 | } |
| 3906 | |
Jeff Kirsher | 4d35185 | 2006-01-12 16:50:48 -0800 | [diff] [blame] | 3907 | /* FLASH reads without acquiring the semaphore are safe */ |
| 3908 | if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && |
| 3909 | hw->eeprom.use_eerd == FALSE) { |
| 3910 | switch (hw->mac_type) { |
| 3911 | default: |
| 3912 | /* Prepare the EEPROM for reading */ |
| 3913 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
| 3914 | return -E1000_ERR_EEPROM; |
| 3915 | break; |
| 3916 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3917 | } |
| 3918 | |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 3919 | if (eeprom->use_eerd == TRUE) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3920 | ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); |
| 3921 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || |
| 3922 | (hw->mac_type != e1000_82573)) |
| 3923 | e1000_release_eeprom(hw); |
| 3924 | return ret_val; |
| 3925 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3926 | |
| 3927 | if(eeprom->type == e1000_eeprom_spi) { |
| 3928 | uint16_t word_in; |
| 3929 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; |
| 3930 | |
| 3931 | if(e1000_spi_eeprom_ready(hw)) { |
| 3932 | e1000_release_eeprom(hw); |
| 3933 | return -E1000_ERR_EEPROM; |
| 3934 | } |
| 3935 | |
| 3936 | e1000_standby_eeprom(hw); |
| 3937 | |
| 3938 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
| 3939 | if((eeprom->address_bits == 8) && (offset >= 128)) |
| 3940 | read_opcode |= EEPROM_A8_OPCODE_SPI; |
| 3941 | |
| 3942 | /* Send the READ command (opcode + addr) */ |
| 3943 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
| 3944 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); |
| 3945 | |
| 3946 | /* Read the data. The address of the eeprom internally increments with |
| 3947 | * each byte (spi) being read, saving on the overhead of eeprom setup |
| 3948 | * and tear-down. The address counter will roll over if reading beyond |
| 3949 | * the size of the eeprom, thus allowing the entire memory to be read |
| 3950 | * starting from any offset. */ |
| 3951 | for (i = 0; i < words; i++) { |
| 3952 | word_in = e1000_shift_in_ee_bits(hw, 16); |
| 3953 | data[i] = (word_in >> 8) | (word_in << 8); |
| 3954 | } |
| 3955 | } else if(eeprom->type == e1000_eeprom_microwire) { |
| 3956 | for (i = 0; i < words; i++) { |
| 3957 | /* Send the READ command (opcode + addr) */ |
| 3958 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, |
| 3959 | eeprom->opcode_bits); |
| 3960 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), |
| 3961 | eeprom->address_bits); |
| 3962 | |
| 3963 | /* Read the data. For microwire, each word requires the overhead |
| 3964 | * of eeprom setup and tear-down. */ |
| 3965 | data[i] = e1000_shift_in_ee_bits(hw, 16); |
| 3966 | e1000_standby_eeprom(hw); |
| 3967 | } |
| 3968 | } |
| 3969 | |
| 3970 | /* End this read operation */ |
| 3971 | e1000_release_eeprom(hw); |
| 3972 | |
| 3973 | return E1000_SUCCESS; |
| 3974 | } |
| 3975 | |
| 3976 | /****************************************************************************** |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3977 | * Reads a 16 bit word from the EEPROM using the EERD register. |
| 3978 | * |
| 3979 | * hw - Struct containing variables accessed by shared code |
| 3980 | * offset - offset of word in the EEPROM to read |
| 3981 | * data - word read from the EEPROM |
| 3982 | * words - number of words to read |
| 3983 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 3984 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3985 | e1000_read_eeprom_eerd(struct e1000_hw *hw, |
| 3986 | uint16_t offset, |
| 3987 | uint16_t words, |
| 3988 | uint16_t *data) |
| 3989 | { |
| 3990 | uint32_t i, eerd = 0; |
| 3991 | int32_t error = 0; |
| 3992 | |
| 3993 | for (i = 0; i < words; i++) { |
| 3994 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
| 3995 | E1000_EEPROM_RW_REG_START; |
| 3996 | |
| 3997 | E1000_WRITE_REG(hw, EERD, eerd); |
| 3998 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
| 3999 | |
| 4000 | if(error) { |
| 4001 | break; |
| 4002 | } |
| 4003 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
| 4004 | |
| 4005 | } |
| 4006 | |
| 4007 | return error; |
| 4008 | } |
| 4009 | |
| 4010 | /****************************************************************************** |
| 4011 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
| 4012 | * |
| 4013 | * hw - Struct containing variables accessed by shared code |
| 4014 | * offset - offset of word in the EEPROM to read |
| 4015 | * data - word read from the EEPROM |
| 4016 | * words - number of words to read |
| 4017 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4018 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4019 | e1000_write_eeprom_eewr(struct e1000_hw *hw, |
| 4020 | uint16_t offset, |
| 4021 | uint16_t words, |
| 4022 | uint16_t *data) |
| 4023 | { |
| 4024 | uint32_t register_value = 0; |
| 4025 | uint32_t i = 0; |
| 4026 | int32_t error = 0; |
| 4027 | |
| 4028 | for (i = 0; i < words; i++) { |
| 4029 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
| 4030 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | |
| 4031 | E1000_EEPROM_RW_REG_START; |
| 4032 | |
| 4033 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
| 4034 | if(error) { |
| 4035 | break; |
| 4036 | } |
| 4037 | |
| 4038 | E1000_WRITE_REG(hw, EEWR, register_value); |
| 4039 | |
| 4040 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
| 4041 | |
| 4042 | if(error) { |
| 4043 | break; |
| 4044 | } |
| 4045 | } |
| 4046 | |
| 4047 | return error; |
| 4048 | } |
| 4049 | |
| 4050 | /****************************************************************************** |
| 4051 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
| 4052 | * |
| 4053 | * hw - Struct containing variables accessed by shared code |
| 4054 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4055 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4056 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
| 4057 | { |
| 4058 | uint32_t attempts = 100000; |
| 4059 | uint32_t i, reg = 0; |
| 4060 | int32_t done = E1000_ERR_EEPROM; |
| 4061 | |
| 4062 | for(i = 0; i < attempts; i++) { |
| 4063 | if(eerd == E1000_EEPROM_POLL_READ) |
| 4064 | reg = E1000_READ_REG(hw, EERD); |
| 4065 | else |
| 4066 | reg = E1000_READ_REG(hw, EEWR); |
| 4067 | |
| 4068 | if(reg & E1000_EEPROM_RW_REG_DONE) { |
| 4069 | done = E1000_SUCCESS; |
| 4070 | break; |
| 4071 | } |
| 4072 | udelay(5); |
| 4073 | } |
| 4074 | |
| 4075 | return done; |
| 4076 | } |
| 4077 | |
| 4078 | /*************************************************************************** |
| 4079 | * Description: Determines if the onboard NVM is FLASH or EEPROM. |
| 4080 | * |
| 4081 | * hw - Struct containing variables accessed by shared code |
| 4082 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4083 | static boolean_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4084 | e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
| 4085 | { |
| 4086 | uint32_t eecd = 0; |
| 4087 | |
| 4088 | if(hw->mac_type == e1000_82573) { |
| 4089 | eecd = E1000_READ_REG(hw, EECD); |
| 4090 | |
| 4091 | /* Isolate bits 15 & 16 */ |
| 4092 | eecd = ((eecd >> 15) & 0x03); |
| 4093 | |
| 4094 | /* If both bits are set, device is Flash type */ |
| 4095 | if(eecd == 0x03) { |
| 4096 | return FALSE; |
| 4097 | } |
| 4098 | } |
| 4099 | return TRUE; |
| 4100 | } |
| 4101 | |
| 4102 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4103 | * Verifies that the EEPROM has a valid checksum |
| 4104 | * |
| 4105 | * hw - Struct containing variables accessed by shared code |
| 4106 | * |
| 4107 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
| 4108 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
| 4109 | * valid. |
| 4110 | *****************************************************************************/ |
| 4111 | int32_t |
| 4112 | e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
| 4113 | { |
| 4114 | uint16_t checksum = 0; |
| 4115 | uint16_t i, eeprom_data; |
| 4116 | |
| 4117 | DEBUGFUNC("e1000_validate_eeprom_checksum"); |
| 4118 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4119 | if ((hw->mac_type == e1000_82573) && |
| 4120 | (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { |
| 4121 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating |
| 4122 | * 10h-12h. Checksum may need to be fixed. */ |
| 4123 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); |
| 4124 | if ((eeprom_data & 0x10) == 0) { |
| 4125 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum |
| 4126 | * has already been fixed. If the checksum is still wrong and this |
| 4127 | * bit is a 1, we need to return bad checksum. Otherwise, we need |
| 4128 | * to set this bit to a 1 and update the checksum. */ |
| 4129 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); |
| 4130 | if ((eeprom_data & 0x8000) == 0) { |
| 4131 | eeprom_data |= 0x8000; |
| 4132 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); |
| 4133 | e1000_update_eeprom_checksum(hw); |
| 4134 | } |
| 4135 | } |
| 4136 | } |
| 4137 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4138 | for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
| 4139 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
| 4140 | DEBUGOUT("EEPROM Read Error\n"); |
| 4141 | return -E1000_ERR_EEPROM; |
| 4142 | } |
| 4143 | checksum += eeprom_data; |
| 4144 | } |
| 4145 | |
| 4146 | if(checksum == (uint16_t) EEPROM_SUM) |
| 4147 | return E1000_SUCCESS; |
| 4148 | else { |
| 4149 | DEBUGOUT("EEPROM Checksum Invalid\n"); |
| 4150 | return -E1000_ERR_EEPROM; |
| 4151 | } |
| 4152 | } |
| 4153 | |
| 4154 | /****************************************************************************** |
| 4155 | * Calculates the EEPROM checksum and writes it to the EEPROM |
| 4156 | * |
| 4157 | * hw - Struct containing variables accessed by shared code |
| 4158 | * |
| 4159 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
| 4160 | * Writes the difference to word offset 63 of the EEPROM. |
| 4161 | *****************************************************************************/ |
| 4162 | int32_t |
| 4163 | e1000_update_eeprom_checksum(struct e1000_hw *hw) |
| 4164 | { |
| 4165 | uint16_t checksum = 0; |
| 4166 | uint16_t i, eeprom_data; |
| 4167 | |
| 4168 | DEBUGFUNC("e1000_update_eeprom_checksum"); |
| 4169 | |
| 4170 | for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
| 4171 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
| 4172 | DEBUGOUT("EEPROM Read Error\n"); |
| 4173 | return -E1000_ERR_EEPROM; |
| 4174 | } |
| 4175 | checksum += eeprom_data; |
| 4176 | } |
| 4177 | checksum = (uint16_t) EEPROM_SUM - checksum; |
| 4178 | if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
| 4179 | DEBUGOUT("EEPROM Write Error\n"); |
| 4180 | return -E1000_ERR_EEPROM; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4181 | } else if (hw->eeprom.type == e1000_eeprom_flash) { |
| 4182 | e1000_commit_shadow_ram(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4183 | } |
| 4184 | return E1000_SUCCESS; |
| 4185 | } |
| 4186 | |
| 4187 | /****************************************************************************** |
| 4188 | * Parent function for writing words to the different EEPROM types. |
| 4189 | * |
| 4190 | * hw - Struct containing variables accessed by shared code |
| 4191 | * offset - offset within the EEPROM to be written to |
| 4192 | * words - number of words to write |
| 4193 | * data - 16 bit word to be written to the EEPROM |
| 4194 | * |
| 4195 | * If e1000_update_eeprom_checksum is not called after this function, the |
| 4196 | * EEPROM will most likely contain an invalid checksum. |
| 4197 | *****************************************************************************/ |
| 4198 | int32_t |
| 4199 | e1000_write_eeprom(struct e1000_hw *hw, |
| 4200 | uint16_t offset, |
| 4201 | uint16_t words, |
| 4202 | uint16_t *data) |
| 4203 | { |
| 4204 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4205 | int32_t status = 0; |
| 4206 | |
| 4207 | DEBUGFUNC("e1000_write_eeprom"); |
| 4208 | |
| 4209 | /* A check for invalid values: offset too large, too many words, and not |
| 4210 | * enough words. |
| 4211 | */ |
| 4212 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
| 4213 | (words == 0)) { |
| 4214 | DEBUGOUT("\"words\" parameter out of bounds\n"); |
| 4215 | return -E1000_ERR_EEPROM; |
| 4216 | } |
| 4217 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4218 | /* 82573 writes only through eewr */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4219 | if(eeprom->use_eewr == TRUE) |
| 4220 | return e1000_write_eeprom_eewr(hw, offset, words, data); |
| 4221 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4222 | /* Prepare the EEPROM for writing */ |
| 4223 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
| 4224 | return -E1000_ERR_EEPROM; |
| 4225 | |
| 4226 | if(eeprom->type == e1000_eeprom_microwire) { |
| 4227 | status = e1000_write_eeprom_microwire(hw, offset, words, data); |
| 4228 | } else { |
| 4229 | status = e1000_write_eeprom_spi(hw, offset, words, data); |
| 4230 | msec_delay(10); |
| 4231 | } |
| 4232 | |
| 4233 | /* Done with writing */ |
| 4234 | e1000_release_eeprom(hw); |
| 4235 | |
| 4236 | return status; |
| 4237 | } |
| 4238 | |
| 4239 | /****************************************************************************** |
| 4240 | * Writes a 16 bit word to a given offset in an SPI EEPROM. |
| 4241 | * |
| 4242 | * hw - Struct containing variables accessed by shared code |
| 4243 | * offset - offset within the EEPROM to be written to |
| 4244 | * words - number of words to write |
| 4245 | * data - pointer to array of 8 bit words to be written to the EEPROM |
| 4246 | * |
| 4247 | *****************************************************************************/ |
| 4248 | int32_t |
| 4249 | e1000_write_eeprom_spi(struct e1000_hw *hw, |
| 4250 | uint16_t offset, |
| 4251 | uint16_t words, |
| 4252 | uint16_t *data) |
| 4253 | { |
| 4254 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4255 | uint16_t widx = 0; |
| 4256 | |
| 4257 | DEBUGFUNC("e1000_write_eeprom_spi"); |
| 4258 | |
| 4259 | while (widx < words) { |
| 4260 | uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; |
| 4261 | |
| 4262 | if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
| 4263 | |
| 4264 | e1000_standby_eeprom(hw); |
| 4265 | |
| 4266 | /* Send the WRITE ENABLE command (8 bit opcode ) */ |
| 4267 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
| 4268 | eeprom->opcode_bits); |
| 4269 | |
| 4270 | e1000_standby_eeprom(hw); |
| 4271 | |
| 4272 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
| 4273 | if((eeprom->address_bits == 8) && (offset >= 128)) |
| 4274 | write_opcode |= EEPROM_A8_OPCODE_SPI; |
| 4275 | |
| 4276 | /* Send the Write command (8-bit opcode + addr) */ |
| 4277 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
| 4278 | |
| 4279 | e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), |
| 4280 | eeprom->address_bits); |
| 4281 | |
| 4282 | /* Send the data */ |
| 4283 | |
| 4284 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
| 4285 | while (widx < words) { |
| 4286 | uint16_t word_out = data[widx]; |
| 4287 | word_out = (word_out >> 8) | (word_out << 8); |
| 4288 | e1000_shift_out_ee_bits(hw, word_out, 16); |
| 4289 | widx++; |
| 4290 | |
| 4291 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
| 4292 | * operation, while the smaller eeproms are capable of an 8-byte |
| 4293 | * PAGE WRITE operation. Break the inner loop to pass new address |
| 4294 | */ |
| 4295 | if((((offset + widx)*2) % eeprom->page_size) == 0) { |
| 4296 | e1000_standby_eeprom(hw); |
| 4297 | break; |
| 4298 | } |
| 4299 | } |
| 4300 | } |
| 4301 | |
| 4302 | return E1000_SUCCESS; |
| 4303 | } |
| 4304 | |
| 4305 | /****************************************************************************** |
| 4306 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. |
| 4307 | * |
| 4308 | * hw - Struct containing variables accessed by shared code |
| 4309 | * offset - offset within the EEPROM to be written to |
| 4310 | * words - number of words to write |
| 4311 | * data - pointer to array of 16 bit words to be written to the EEPROM |
| 4312 | * |
| 4313 | *****************************************************************************/ |
| 4314 | int32_t |
| 4315 | e1000_write_eeprom_microwire(struct e1000_hw *hw, |
| 4316 | uint16_t offset, |
| 4317 | uint16_t words, |
| 4318 | uint16_t *data) |
| 4319 | { |
| 4320 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4321 | uint32_t eecd; |
| 4322 | uint16_t words_written = 0; |
| 4323 | uint16_t i = 0; |
| 4324 | |
| 4325 | DEBUGFUNC("e1000_write_eeprom_microwire"); |
| 4326 | |
| 4327 | /* Send the write enable command to the EEPROM (3-bit opcode plus |
| 4328 | * 6/8-bit dummy address beginning with 11). It's less work to include |
| 4329 | * the 11 of the dummy address as part of the opcode than it is to shift |
| 4330 | * it over the correct number of bits for the address. This puts the |
| 4331 | * EEPROM into write/erase mode. |
| 4332 | */ |
| 4333 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
| 4334 | (uint16_t)(eeprom->opcode_bits + 2)); |
| 4335 | |
| 4336 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
| 4337 | |
| 4338 | /* Prepare the EEPROM */ |
| 4339 | e1000_standby_eeprom(hw); |
| 4340 | |
| 4341 | while (words_written < words) { |
| 4342 | /* Send the Write command (3-bit opcode + addr) */ |
| 4343 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
| 4344 | eeprom->opcode_bits); |
| 4345 | |
| 4346 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), |
| 4347 | eeprom->address_bits); |
| 4348 | |
| 4349 | /* Send the data */ |
| 4350 | e1000_shift_out_ee_bits(hw, data[words_written], 16); |
| 4351 | |
| 4352 | /* Toggle the CS line. This in effect tells the EEPROM to execute |
| 4353 | * the previous command. |
| 4354 | */ |
| 4355 | e1000_standby_eeprom(hw); |
| 4356 | |
| 4357 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
| 4358 | * signal that the command has been completed by raising the DO signal. |
| 4359 | * If DO does not go high in 10 milliseconds, then error out. |
| 4360 | */ |
| 4361 | for(i = 0; i < 200; i++) { |
| 4362 | eecd = E1000_READ_REG(hw, EECD); |
| 4363 | if(eecd & E1000_EECD_DO) break; |
| 4364 | udelay(50); |
| 4365 | } |
| 4366 | if(i == 200) { |
| 4367 | DEBUGOUT("EEPROM Write did not complete\n"); |
| 4368 | return -E1000_ERR_EEPROM; |
| 4369 | } |
| 4370 | |
| 4371 | /* Recover from write */ |
| 4372 | e1000_standby_eeprom(hw); |
| 4373 | |
| 4374 | words_written++; |
| 4375 | } |
| 4376 | |
| 4377 | /* Send the write disable command to the EEPROM (3-bit opcode plus |
| 4378 | * 6/8-bit dummy address beginning with 10). It's less work to include |
| 4379 | * the 10 of the dummy address as part of the opcode than it is to shift |
| 4380 | * it over the correct number of bits for the address. This takes the |
| 4381 | * EEPROM out of write/erase mode. |
| 4382 | */ |
| 4383 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
| 4384 | (uint16_t)(eeprom->opcode_bits + 2)); |
| 4385 | |
| 4386 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
| 4387 | |
| 4388 | return E1000_SUCCESS; |
| 4389 | } |
| 4390 | |
| 4391 | /****************************************************************************** |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4392 | * Flushes the cached eeprom to NVM. This is done by saving the modified values |
| 4393 | * in the eeprom cache and the non modified values in the currently active bank |
| 4394 | * to the new bank. |
| 4395 | * |
| 4396 | * hw - Struct containing variables accessed by shared code |
| 4397 | * offset - offset of word in the EEPROM to read |
| 4398 | * data - word read from the EEPROM |
| 4399 | * words - number of words to read |
| 4400 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4401 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4402 | e1000_commit_shadow_ram(struct e1000_hw *hw) |
| 4403 | { |
| 4404 | uint32_t attempts = 100000; |
| 4405 | uint32_t eecd = 0; |
| 4406 | uint32_t flop = 0; |
| 4407 | uint32_t i = 0; |
| 4408 | int32_t error = E1000_SUCCESS; |
| 4409 | |
| 4410 | /* The flop register will be used to determine if flash type is STM */ |
| 4411 | flop = E1000_READ_REG(hw, FLOP); |
| 4412 | |
| 4413 | if (hw->mac_type == e1000_82573) { |
| 4414 | for (i=0; i < attempts; i++) { |
| 4415 | eecd = E1000_READ_REG(hw, EECD); |
| 4416 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
| 4417 | break; |
| 4418 | } |
| 4419 | udelay(5); |
| 4420 | } |
| 4421 | |
| 4422 | if (i == attempts) { |
| 4423 | return -E1000_ERR_EEPROM; |
| 4424 | } |
| 4425 | |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 4426 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4427 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
| 4428 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); |
| 4429 | } |
| 4430 | |
| 4431 | /* Perform the flash update */ |
| 4432 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); |
| 4433 | |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 4434 | for (i=0; i < attempts; i++) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4435 | eecd = E1000_READ_REG(hw, EECD); |
| 4436 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
| 4437 | break; |
| 4438 | } |
| 4439 | udelay(5); |
| 4440 | } |
| 4441 | |
| 4442 | if (i == attempts) { |
| 4443 | return -E1000_ERR_EEPROM; |
| 4444 | } |
| 4445 | } |
| 4446 | |
| 4447 | return error; |
| 4448 | } |
| 4449 | |
| 4450 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4451 | * Reads the adapter's part number from the EEPROM |
| 4452 | * |
| 4453 | * hw - Struct containing variables accessed by shared code |
| 4454 | * part_num - Adapter's part number |
| 4455 | *****************************************************************************/ |
| 4456 | int32_t |
| 4457 | e1000_read_part_num(struct e1000_hw *hw, |
| 4458 | uint32_t *part_num) |
| 4459 | { |
| 4460 | uint16_t offset = EEPROM_PBA_BYTE_1; |
| 4461 | uint16_t eeprom_data; |
| 4462 | |
| 4463 | DEBUGFUNC("e1000_read_part_num"); |
| 4464 | |
| 4465 | /* Get word 0 from EEPROM */ |
| 4466 | if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
| 4467 | DEBUGOUT("EEPROM Read Error\n"); |
| 4468 | return -E1000_ERR_EEPROM; |
| 4469 | } |
| 4470 | /* Save word 0 in upper half of part_num */ |
| 4471 | *part_num = (uint32_t) (eeprom_data << 16); |
| 4472 | |
| 4473 | /* Get word 1 from EEPROM */ |
| 4474 | if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { |
| 4475 | DEBUGOUT("EEPROM Read Error\n"); |
| 4476 | return -E1000_ERR_EEPROM; |
| 4477 | } |
| 4478 | /* Save word 1 in lower half of part_num */ |
| 4479 | *part_num |= eeprom_data; |
| 4480 | |
| 4481 | return E1000_SUCCESS; |
| 4482 | } |
| 4483 | |
| 4484 | /****************************************************************************** |
| 4485 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
| 4486 | * second function of dual function devices |
| 4487 | * |
| 4488 | * hw - Struct containing variables accessed by shared code |
| 4489 | *****************************************************************************/ |
| 4490 | int32_t |
| 4491 | e1000_read_mac_addr(struct e1000_hw * hw) |
| 4492 | { |
| 4493 | uint16_t offset; |
| 4494 | uint16_t eeprom_data, i; |
| 4495 | |
| 4496 | DEBUGFUNC("e1000_read_mac_addr"); |
| 4497 | |
| 4498 | for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
| 4499 | offset = i >> 1; |
| 4500 | if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
| 4501 | DEBUGOUT("EEPROM Read Error\n"); |
| 4502 | return -E1000_ERR_EEPROM; |
| 4503 | } |
| 4504 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); |
| 4505 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); |
| 4506 | } |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 4507 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4508 | switch (hw->mac_type) { |
| 4509 | default: |
| 4510 | break; |
| 4511 | case e1000_82546: |
| 4512 | case e1000_82546_rev_3: |
| 4513 | case e1000_82571: |
| 4514 | if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4515 | hw->perm_mac_addr[5] ^= 0x01; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4516 | break; |
| 4517 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4518 | |
| 4519 | for(i = 0; i < NODE_ADDRESS_SIZE; i++) |
| 4520 | hw->mac_addr[i] = hw->perm_mac_addr[i]; |
| 4521 | return E1000_SUCCESS; |
| 4522 | } |
| 4523 | |
| 4524 | /****************************************************************************** |
| 4525 | * Initializes receive address filters. |
| 4526 | * |
| 4527 | * hw - Struct containing variables accessed by shared code |
| 4528 | * |
| 4529 | * Places the MAC address in receive address register 0 and clears the rest |
| 4530 | * of the receive addresss registers. Clears the multicast table. Assumes |
| 4531 | * the receiver is in reset when the routine is called. |
| 4532 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4533 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4534 | e1000_init_rx_addrs(struct e1000_hw *hw) |
| 4535 | { |
| 4536 | uint32_t i; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4537 | uint32_t rar_num; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4538 | |
| 4539 | DEBUGFUNC("e1000_init_rx_addrs"); |
| 4540 | |
| 4541 | /* Setup the receive address. */ |
| 4542 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
| 4543 | |
| 4544 | e1000_rar_set(hw, hw->mac_addr, 0); |
| 4545 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4546 | rar_num = E1000_RAR_ENTRIES; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4547 | |
| 4548 | /* Reserve a spot for the Locally Administered Address to work around |
| 4549 | * an 82571 issue in which a reset on one port will reload the MAC on |
| 4550 | * the other port. */ |
| 4551 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) |
| 4552 | rar_num -= 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4553 | /* Zero out the other 15 receive addresses. */ |
| 4554 | DEBUGOUT("Clearing RAR[1-15]\n"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4555 | for(i = 1; i < rar_num; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4556 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
| 4557 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
| 4558 | } |
| 4559 | } |
| 4560 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4561 | #if 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4562 | /****************************************************************************** |
| 4563 | * Updates the MAC's list of multicast addresses. |
| 4564 | * |
| 4565 | * hw - Struct containing variables accessed by shared code |
| 4566 | * mc_addr_list - the list of new multicast addresses |
| 4567 | * mc_addr_count - number of addresses |
| 4568 | * pad - number of bytes between addresses in the list |
| 4569 | * rar_used_count - offset where to start adding mc addresses into the RAR's |
| 4570 | * |
| 4571 | * The given list replaces any existing list. Clears the last 15 receive |
| 4572 | * address registers and the multicast table. Uses receive address registers |
| 4573 | * for the first 15 multicast addresses, and hashes the rest into the |
| 4574 | * multicast table. |
| 4575 | *****************************************************************************/ |
| 4576 | void |
| 4577 | e1000_mc_addr_list_update(struct e1000_hw *hw, |
| 4578 | uint8_t *mc_addr_list, |
| 4579 | uint32_t mc_addr_count, |
| 4580 | uint32_t pad, |
| 4581 | uint32_t rar_used_count) |
| 4582 | { |
| 4583 | uint32_t hash_value; |
| 4584 | uint32_t i; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4585 | uint32_t num_rar_entry; |
| 4586 | uint32_t num_mta_entry; |
| 4587 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4588 | DEBUGFUNC("e1000_mc_addr_list_update"); |
| 4589 | |
| 4590 | /* Set the new number of MC addresses that we are being requested to use. */ |
| 4591 | hw->num_mc_addrs = mc_addr_count; |
| 4592 | |
| 4593 | /* Clear RAR[1-15] */ |
| 4594 | DEBUGOUT(" Clearing RAR[1-15]\n"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4595 | num_rar_entry = E1000_RAR_ENTRIES; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4596 | /* Reserve a spot for the Locally Administered Address to work around |
| 4597 | * an 82571 issue in which a reset on one port will reload the MAC on |
| 4598 | * the other port. */ |
| 4599 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) |
| 4600 | num_rar_entry -= 1; |
| 4601 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4602 | for(i = rar_used_count; i < num_rar_entry; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4603 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
| 4604 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
| 4605 | } |
| 4606 | |
| 4607 | /* Clear the MTA */ |
| 4608 | DEBUGOUT(" Clearing MTA\n"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4609 | num_mta_entry = E1000_NUM_MTA_REGISTERS; |
| 4610 | for(i = 0; i < num_mta_entry; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4611 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
| 4612 | } |
| 4613 | |
| 4614 | /* Add the new addresses */ |
| 4615 | for(i = 0; i < mc_addr_count; i++) { |
| 4616 | DEBUGOUT(" Adding the multicast addresses:\n"); |
| 4617 | DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, |
| 4618 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], |
| 4619 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], |
| 4620 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], |
| 4621 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], |
| 4622 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], |
| 4623 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); |
| 4624 | |
| 4625 | hash_value = e1000_hash_mc_addr(hw, |
| 4626 | mc_addr_list + |
| 4627 | (i * (ETH_LENGTH_OF_ADDRESS + pad))); |
| 4628 | |
| 4629 | DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); |
| 4630 | |
| 4631 | /* Place this multicast address in the RAR if there is room, * |
| 4632 | * else put it in the MTA |
| 4633 | */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4634 | if (rar_used_count < num_rar_entry) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4635 | e1000_rar_set(hw, |
| 4636 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), |
| 4637 | rar_used_count); |
| 4638 | rar_used_count++; |
| 4639 | } else { |
| 4640 | e1000_mta_set(hw, hash_value); |
| 4641 | } |
| 4642 | } |
| 4643 | DEBUGOUT("MC Update Complete\n"); |
| 4644 | } |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4645 | #endif /* 0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4646 | |
| 4647 | /****************************************************************************** |
| 4648 | * Hashes an address to determine its location in the multicast table |
| 4649 | * |
| 4650 | * hw - Struct containing variables accessed by shared code |
| 4651 | * mc_addr - the multicast address to hash |
| 4652 | *****************************************************************************/ |
| 4653 | uint32_t |
| 4654 | e1000_hash_mc_addr(struct e1000_hw *hw, |
| 4655 | uint8_t *mc_addr) |
| 4656 | { |
| 4657 | uint32_t hash_value = 0; |
| 4658 | |
| 4659 | /* The portion of the address that is used for the hash table is |
| 4660 | * determined by the mc_filter_type setting. |
| 4661 | */ |
| 4662 | switch (hw->mc_filter_type) { |
| 4663 | /* [0] [1] [2] [3] [4] [5] |
| 4664 | * 01 AA 00 12 34 56 |
| 4665 | * LSB MSB |
| 4666 | */ |
| 4667 | case 0: |
| 4668 | /* [47:36] i.e. 0x563 for above example address */ |
| 4669 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
| 4670 | break; |
| 4671 | case 1: |
| 4672 | /* [46:35] i.e. 0xAC6 for above example address */ |
| 4673 | hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); |
| 4674 | break; |
| 4675 | case 2: |
| 4676 | /* [45:34] i.e. 0x5D8 for above example address */ |
| 4677 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
| 4678 | break; |
| 4679 | case 3: |
| 4680 | /* [43:32] i.e. 0x634 for above example address */ |
| 4681 | hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); |
| 4682 | break; |
| 4683 | } |
| 4684 | |
| 4685 | hash_value &= 0xFFF; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4686 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4687 | return hash_value; |
| 4688 | } |
| 4689 | |
| 4690 | /****************************************************************************** |
| 4691 | * Sets the bit in the multicast table corresponding to the hash value. |
| 4692 | * |
| 4693 | * hw - Struct containing variables accessed by shared code |
| 4694 | * hash_value - Multicast address hash value |
| 4695 | *****************************************************************************/ |
| 4696 | void |
| 4697 | e1000_mta_set(struct e1000_hw *hw, |
| 4698 | uint32_t hash_value) |
| 4699 | { |
| 4700 | uint32_t hash_bit, hash_reg; |
| 4701 | uint32_t mta; |
| 4702 | uint32_t temp; |
| 4703 | |
| 4704 | /* The MTA is a register array of 128 32-bit registers. |
| 4705 | * It is treated like an array of 4096 bits. We want to set |
| 4706 | * bit BitArray[hash_value]. So we figure out what register |
| 4707 | * the bit is in, read it, OR in the new bit, then write |
| 4708 | * back the new value. The register is determined by the |
| 4709 | * upper 7 bits of the hash value and the bit within that |
| 4710 | * register are determined by the lower 5 bits of the value. |
| 4711 | */ |
| 4712 | hash_reg = (hash_value >> 5) & 0x7F; |
| 4713 | hash_bit = hash_value & 0x1F; |
| 4714 | |
| 4715 | mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); |
| 4716 | |
| 4717 | mta |= (1 << hash_bit); |
| 4718 | |
| 4719 | /* If we are on an 82544 and we are trying to write an odd offset |
| 4720 | * in the MTA, save off the previous entry before writing and |
| 4721 | * restore the old value after writing. |
| 4722 | */ |
| 4723 | if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { |
| 4724 | temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); |
| 4725 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
| 4726 | E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); |
| 4727 | } else { |
| 4728 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
| 4729 | } |
| 4730 | } |
| 4731 | |
| 4732 | /****************************************************************************** |
| 4733 | * Puts an ethernet address into a receive address register. |
| 4734 | * |
| 4735 | * hw - Struct containing variables accessed by shared code |
| 4736 | * addr - Address to put into receive address register |
| 4737 | * index - Receive address register to write |
| 4738 | *****************************************************************************/ |
| 4739 | void |
| 4740 | e1000_rar_set(struct e1000_hw *hw, |
| 4741 | uint8_t *addr, |
| 4742 | uint32_t index) |
| 4743 | { |
| 4744 | uint32_t rar_low, rar_high; |
| 4745 | |
| 4746 | /* HW expects these in little endian so we reverse the byte order |
| 4747 | * from network order (big endian) to little endian |
| 4748 | */ |
| 4749 | rar_low = ((uint32_t) addr[0] | |
| 4750 | ((uint32_t) addr[1] << 8) | |
| 4751 | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); |
| 4752 | |
| 4753 | rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV); |
| 4754 | |
| 4755 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
| 4756 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
| 4757 | } |
| 4758 | |
| 4759 | /****************************************************************************** |
| 4760 | * Writes a value to the specified offset in the VLAN filter table. |
| 4761 | * |
| 4762 | * hw - Struct containing variables accessed by shared code |
| 4763 | * offset - Offset in VLAN filer table to write |
| 4764 | * value - Value to write into VLAN filter table |
| 4765 | *****************************************************************************/ |
| 4766 | void |
| 4767 | e1000_write_vfta(struct e1000_hw *hw, |
| 4768 | uint32_t offset, |
| 4769 | uint32_t value) |
| 4770 | { |
| 4771 | uint32_t temp; |
| 4772 | |
| 4773 | if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
| 4774 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
| 4775 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
| 4776 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
| 4777 | } else { |
| 4778 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
| 4779 | } |
| 4780 | } |
| 4781 | |
| 4782 | /****************************************************************************** |
| 4783 | * Clears the VLAN filer table |
| 4784 | * |
| 4785 | * hw - Struct containing variables accessed by shared code |
| 4786 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4787 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4788 | e1000_clear_vfta(struct e1000_hw *hw) |
| 4789 | { |
| 4790 | uint32_t offset; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4791 | uint32_t vfta_value = 0; |
| 4792 | uint32_t vfta_offset = 0; |
| 4793 | uint32_t vfta_bit_in_reg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4794 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4795 | if (hw->mac_type == e1000_82573) { |
| 4796 | if (hw->mng_cookie.vlan_id != 0) { |
| 4797 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN |
| 4798 | * ID. The following operations determine which 32b entry |
| 4799 | * (i.e. offset) into the array we want to set the VLAN ID |
| 4800 | * (i.e. bit) of the manageability unit. */ |
| 4801 | vfta_offset = (hw->mng_cookie.vlan_id >> |
| 4802 | E1000_VFTA_ENTRY_SHIFT) & |
| 4803 | E1000_VFTA_ENTRY_MASK; |
| 4804 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
| 4805 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
| 4806 | } |
| 4807 | } |
| 4808 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 4809 | /* If the offset we want to clear is the same offset of the |
| 4810 | * manageability VLAN ID, then clear all bits except that of the |
| 4811 | * manageability unit */ |
| 4812 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
| 4813 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
| 4814 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4815 | } |
| 4816 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4817 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4818 | e1000_id_led_init(struct e1000_hw * hw) |
| 4819 | { |
| 4820 | uint32_t ledctl; |
| 4821 | const uint32_t ledctl_mask = 0x000000FF; |
| 4822 | const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 4823 | const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 4824 | uint16_t eeprom_data, i, temp; |
| 4825 | const uint16_t led_mask = 0x0F; |
| 4826 | |
| 4827 | DEBUGFUNC("e1000_id_led_init"); |
| 4828 | |
| 4829 | if(hw->mac_type < e1000_82540) { |
| 4830 | /* Nothing to do */ |
| 4831 | return E1000_SUCCESS; |
| 4832 | } |
| 4833 | |
| 4834 | ledctl = E1000_READ_REG(hw, LEDCTL); |
| 4835 | hw->ledctl_default = ledctl; |
| 4836 | hw->ledctl_mode1 = hw->ledctl_default; |
| 4837 | hw->ledctl_mode2 = hw->ledctl_default; |
| 4838 | |
| 4839 | if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
| 4840 | DEBUGOUT("EEPROM Read Error\n"); |
| 4841 | return -E1000_ERR_EEPROM; |
| 4842 | } |
| 4843 | if((eeprom_data== ID_LED_RESERVED_0000) || |
| 4844 | (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; |
| 4845 | for(i = 0; i < 4; i++) { |
| 4846 | temp = (eeprom_data >> (i << 2)) & led_mask; |
| 4847 | switch(temp) { |
| 4848 | case ID_LED_ON1_DEF2: |
| 4849 | case ID_LED_ON1_ON2: |
| 4850 | case ID_LED_ON1_OFF2: |
| 4851 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 4852 | hw->ledctl_mode1 |= ledctl_on << (i << 3); |
| 4853 | break; |
| 4854 | case ID_LED_OFF1_DEF2: |
| 4855 | case ID_LED_OFF1_ON2: |
| 4856 | case ID_LED_OFF1_OFF2: |
| 4857 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 4858 | hw->ledctl_mode1 |= ledctl_off << (i << 3); |
| 4859 | break; |
| 4860 | default: |
| 4861 | /* Do nothing */ |
| 4862 | break; |
| 4863 | } |
| 4864 | switch(temp) { |
| 4865 | case ID_LED_DEF1_ON2: |
| 4866 | case ID_LED_ON1_ON2: |
| 4867 | case ID_LED_OFF1_ON2: |
| 4868 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 4869 | hw->ledctl_mode2 |= ledctl_on << (i << 3); |
| 4870 | break; |
| 4871 | case ID_LED_DEF1_OFF2: |
| 4872 | case ID_LED_ON1_OFF2: |
| 4873 | case ID_LED_OFF1_OFF2: |
| 4874 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 4875 | hw->ledctl_mode2 |= ledctl_off << (i << 3); |
| 4876 | break; |
| 4877 | default: |
| 4878 | /* Do nothing */ |
| 4879 | break; |
| 4880 | } |
| 4881 | } |
| 4882 | return E1000_SUCCESS; |
| 4883 | } |
| 4884 | |
| 4885 | /****************************************************************************** |
| 4886 | * Prepares SW controlable LED for use and saves the current state of the LED. |
| 4887 | * |
| 4888 | * hw - Struct containing variables accessed by shared code |
| 4889 | *****************************************************************************/ |
| 4890 | int32_t |
| 4891 | e1000_setup_led(struct e1000_hw *hw) |
| 4892 | { |
| 4893 | uint32_t ledctl; |
| 4894 | int32_t ret_val = E1000_SUCCESS; |
| 4895 | |
| 4896 | DEBUGFUNC("e1000_setup_led"); |
| 4897 | |
| 4898 | switch(hw->mac_type) { |
| 4899 | case e1000_82542_rev2_0: |
| 4900 | case e1000_82542_rev2_1: |
| 4901 | case e1000_82543: |
| 4902 | case e1000_82544: |
| 4903 | /* No setup necessary */ |
| 4904 | break; |
| 4905 | case e1000_82541: |
| 4906 | case e1000_82547: |
| 4907 | case e1000_82541_rev_2: |
| 4908 | case e1000_82547_rev_2: |
| 4909 | /* Turn off PHY Smart Power Down (if enabled) */ |
| 4910 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 4911 | &hw->phy_spd_default); |
| 4912 | if(ret_val) |
| 4913 | return ret_val; |
| 4914 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 4915 | (uint16_t)(hw->phy_spd_default & |
| 4916 | ~IGP01E1000_GMII_SPD)); |
| 4917 | if(ret_val) |
| 4918 | return ret_val; |
| 4919 | /* Fall Through */ |
| 4920 | default: |
| 4921 | if(hw->media_type == e1000_media_type_fiber) { |
| 4922 | ledctl = E1000_READ_REG(hw, LEDCTL); |
| 4923 | /* Save current LEDCTL settings */ |
| 4924 | hw->ledctl_default = ledctl; |
| 4925 | /* Turn off LED0 */ |
| 4926 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
| 4927 | E1000_LEDCTL_LED0_BLINK | |
| 4928 | E1000_LEDCTL_LED0_MODE_MASK); |
| 4929 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
| 4930 | E1000_LEDCTL_LED0_MODE_SHIFT); |
| 4931 | E1000_WRITE_REG(hw, LEDCTL, ledctl); |
| 4932 | } else if(hw->media_type == e1000_media_type_copper) |
| 4933 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
| 4934 | break; |
| 4935 | } |
| 4936 | |
| 4937 | return E1000_SUCCESS; |
| 4938 | } |
| 4939 | |
| 4940 | /****************************************************************************** |
| 4941 | * Restores the saved state of the SW controlable LED. |
| 4942 | * |
| 4943 | * hw - Struct containing variables accessed by shared code |
| 4944 | *****************************************************************************/ |
| 4945 | int32_t |
| 4946 | e1000_cleanup_led(struct e1000_hw *hw) |
| 4947 | { |
| 4948 | int32_t ret_val = E1000_SUCCESS; |
| 4949 | |
| 4950 | DEBUGFUNC("e1000_cleanup_led"); |
| 4951 | |
| 4952 | switch(hw->mac_type) { |
| 4953 | case e1000_82542_rev2_0: |
| 4954 | case e1000_82542_rev2_1: |
| 4955 | case e1000_82543: |
| 4956 | case e1000_82544: |
| 4957 | /* No cleanup necessary */ |
| 4958 | break; |
| 4959 | case e1000_82541: |
| 4960 | case e1000_82547: |
| 4961 | case e1000_82541_rev_2: |
| 4962 | case e1000_82547_rev_2: |
| 4963 | /* Turn on PHY Smart Power Down (if previously enabled) */ |
| 4964 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 4965 | hw->phy_spd_default); |
| 4966 | if(ret_val) |
| 4967 | return ret_val; |
| 4968 | /* Fall Through */ |
| 4969 | default: |
| 4970 | /* Restore LEDCTL settings */ |
| 4971 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); |
| 4972 | break; |
| 4973 | } |
| 4974 | |
| 4975 | return E1000_SUCCESS; |
| 4976 | } |
| 4977 | |
| 4978 | /****************************************************************************** |
| 4979 | * Turns on the software controllable LED |
| 4980 | * |
| 4981 | * hw - Struct containing variables accessed by shared code |
| 4982 | *****************************************************************************/ |
| 4983 | int32_t |
| 4984 | e1000_led_on(struct e1000_hw *hw) |
| 4985 | { |
| 4986 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
| 4987 | |
| 4988 | DEBUGFUNC("e1000_led_on"); |
| 4989 | |
| 4990 | switch(hw->mac_type) { |
| 4991 | case e1000_82542_rev2_0: |
| 4992 | case e1000_82542_rev2_1: |
| 4993 | case e1000_82543: |
| 4994 | /* Set SW Defineable Pin 0 to turn on the LED */ |
| 4995 | ctrl |= E1000_CTRL_SWDPIN0; |
| 4996 | ctrl |= E1000_CTRL_SWDPIO0; |
| 4997 | break; |
| 4998 | case e1000_82544: |
| 4999 | if(hw->media_type == e1000_media_type_fiber) { |
| 5000 | /* Set SW Defineable Pin 0 to turn on the LED */ |
| 5001 | ctrl |= E1000_CTRL_SWDPIN0; |
| 5002 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5003 | } else { |
| 5004 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
| 5005 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 5006 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5007 | } |
| 5008 | break; |
| 5009 | default: |
| 5010 | if(hw->media_type == e1000_media_type_fiber) { |
| 5011 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
| 5012 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 5013 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5014 | } else if(hw->media_type == e1000_media_type_copper) { |
| 5015 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); |
| 5016 | return E1000_SUCCESS; |
| 5017 | } |
| 5018 | break; |
| 5019 | } |
| 5020 | |
| 5021 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 5022 | |
| 5023 | return E1000_SUCCESS; |
| 5024 | } |
| 5025 | |
| 5026 | /****************************************************************************** |
| 5027 | * Turns off the software controllable LED |
| 5028 | * |
| 5029 | * hw - Struct containing variables accessed by shared code |
| 5030 | *****************************************************************************/ |
| 5031 | int32_t |
| 5032 | e1000_led_off(struct e1000_hw *hw) |
| 5033 | { |
| 5034 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
| 5035 | |
| 5036 | DEBUGFUNC("e1000_led_off"); |
| 5037 | |
| 5038 | switch(hw->mac_type) { |
| 5039 | case e1000_82542_rev2_0: |
| 5040 | case e1000_82542_rev2_1: |
| 5041 | case e1000_82543: |
| 5042 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
| 5043 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 5044 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5045 | break; |
| 5046 | case e1000_82544: |
| 5047 | if(hw->media_type == e1000_media_type_fiber) { |
| 5048 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
| 5049 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 5050 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5051 | } else { |
| 5052 | /* Set SW Defineable Pin 0 to turn off the LED */ |
| 5053 | ctrl |= E1000_CTRL_SWDPIN0; |
| 5054 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5055 | } |
| 5056 | break; |
| 5057 | default: |
| 5058 | if(hw->media_type == e1000_media_type_fiber) { |
| 5059 | /* Set SW Defineable Pin 0 to turn off the LED */ |
| 5060 | ctrl |= E1000_CTRL_SWDPIN0; |
| 5061 | ctrl |= E1000_CTRL_SWDPIO0; |
| 5062 | } else if(hw->media_type == e1000_media_type_copper) { |
| 5063 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
| 5064 | return E1000_SUCCESS; |
| 5065 | } |
| 5066 | break; |
| 5067 | } |
| 5068 | |
| 5069 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 5070 | |
| 5071 | return E1000_SUCCESS; |
| 5072 | } |
| 5073 | |
| 5074 | /****************************************************************************** |
| 5075 | * Clears all hardware statistics counters. |
| 5076 | * |
| 5077 | * hw - Struct containing variables accessed by shared code |
| 5078 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5079 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5080 | e1000_clear_hw_cntrs(struct e1000_hw *hw) |
| 5081 | { |
| 5082 | volatile uint32_t temp; |
| 5083 | |
| 5084 | temp = E1000_READ_REG(hw, CRCERRS); |
| 5085 | temp = E1000_READ_REG(hw, SYMERRS); |
| 5086 | temp = E1000_READ_REG(hw, MPC); |
| 5087 | temp = E1000_READ_REG(hw, SCC); |
| 5088 | temp = E1000_READ_REG(hw, ECOL); |
| 5089 | temp = E1000_READ_REG(hw, MCC); |
| 5090 | temp = E1000_READ_REG(hw, LATECOL); |
| 5091 | temp = E1000_READ_REG(hw, COLC); |
| 5092 | temp = E1000_READ_REG(hw, DC); |
| 5093 | temp = E1000_READ_REG(hw, SEC); |
| 5094 | temp = E1000_READ_REG(hw, RLEC); |
| 5095 | temp = E1000_READ_REG(hw, XONRXC); |
| 5096 | temp = E1000_READ_REG(hw, XONTXC); |
| 5097 | temp = E1000_READ_REG(hw, XOFFRXC); |
| 5098 | temp = E1000_READ_REG(hw, XOFFTXC); |
| 5099 | temp = E1000_READ_REG(hw, FCRUC); |
| 5100 | temp = E1000_READ_REG(hw, PRC64); |
| 5101 | temp = E1000_READ_REG(hw, PRC127); |
| 5102 | temp = E1000_READ_REG(hw, PRC255); |
| 5103 | temp = E1000_READ_REG(hw, PRC511); |
| 5104 | temp = E1000_READ_REG(hw, PRC1023); |
| 5105 | temp = E1000_READ_REG(hw, PRC1522); |
| 5106 | temp = E1000_READ_REG(hw, GPRC); |
| 5107 | temp = E1000_READ_REG(hw, BPRC); |
| 5108 | temp = E1000_READ_REG(hw, MPRC); |
| 5109 | temp = E1000_READ_REG(hw, GPTC); |
| 5110 | temp = E1000_READ_REG(hw, GORCL); |
| 5111 | temp = E1000_READ_REG(hw, GORCH); |
| 5112 | temp = E1000_READ_REG(hw, GOTCL); |
| 5113 | temp = E1000_READ_REG(hw, GOTCH); |
| 5114 | temp = E1000_READ_REG(hw, RNBC); |
| 5115 | temp = E1000_READ_REG(hw, RUC); |
| 5116 | temp = E1000_READ_REG(hw, RFC); |
| 5117 | temp = E1000_READ_REG(hw, ROC); |
| 5118 | temp = E1000_READ_REG(hw, RJC); |
| 5119 | temp = E1000_READ_REG(hw, TORL); |
| 5120 | temp = E1000_READ_REG(hw, TORH); |
| 5121 | temp = E1000_READ_REG(hw, TOTL); |
| 5122 | temp = E1000_READ_REG(hw, TOTH); |
| 5123 | temp = E1000_READ_REG(hw, TPR); |
| 5124 | temp = E1000_READ_REG(hw, TPT); |
| 5125 | temp = E1000_READ_REG(hw, PTC64); |
| 5126 | temp = E1000_READ_REG(hw, PTC127); |
| 5127 | temp = E1000_READ_REG(hw, PTC255); |
| 5128 | temp = E1000_READ_REG(hw, PTC511); |
| 5129 | temp = E1000_READ_REG(hw, PTC1023); |
| 5130 | temp = E1000_READ_REG(hw, PTC1522); |
| 5131 | temp = E1000_READ_REG(hw, MPTC); |
| 5132 | temp = E1000_READ_REG(hw, BPTC); |
| 5133 | |
| 5134 | if(hw->mac_type < e1000_82543) return; |
| 5135 | |
| 5136 | temp = E1000_READ_REG(hw, ALGNERRC); |
| 5137 | temp = E1000_READ_REG(hw, RXERRC); |
| 5138 | temp = E1000_READ_REG(hw, TNCRS); |
| 5139 | temp = E1000_READ_REG(hw, CEXTERR); |
| 5140 | temp = E1000_READ_REG(hw, TSCTC); |
| 5141 | temp = E1000_READ_REG(hw, TSCTFC); |
| 5142 | |
| 5143 | if(hw->mac_type <= e1000_82544) return; |
| 5144 | |
| 5145 | temp = E1000_READ_REG(hw, MGTPRC); |
| 5146 | temp = E1000_READ_REG(hw, MGTPDC); |
| 5147 | temp = E1000_READ_REG(hw, MGTPTC); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5148 | |
| 5149 | if(hw->mac_type <= e1000_82547_rev_2) return; |
| 5150 | |
| 5151 | temp = E1000_READ_REG(hw, IAC); |
| 5152 | temp = E1000_READ_REG(hw, ICRXOC); |
| 5153 | temp = E1000_READ_REG(hw, ICRXPTC); |
| 5154 | temp = E1000_READ_REG(hw, ICRXATC); |
| 5155 | temp = E1000_READ_REG(hw, ICTXPTC); |
| 5156 | temp = E1000_READ_REG(hw, ICTXATC); |
| 5157 | temp = E1000_READ_REG(hw, ICTXQEC); |
| 5158 | temp = E1000_READ_REG(hw, ICTXQMTC); |
| 5159 | temp = E1000_READ_REG(hw, ICRXDMTC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5160 | } |
| 5161 | |
| 5162 | /****************************************************************************** |
| 5163 | * Resets Adaptive IFS to its default state. |
| 5164 | * |
| 5165 | * hw - Struct containing variables accessed by shared code |
| 5166 | * |
| 5167 | * Call this after e1000_init_hw. You may override the IFS defaults by setting |
| 5168 | * hw->ifs_params_forced to TRUE. However, you must initialize hw-> |
| 5169 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
| 5170 | * before calling this function. |
| 5171 | *****************************************************************************/ |
| 5172 | void |
| 5173 | e1000_reset_adaptive(struct e1000_hw *hw) |
| 5174 | { |
| 5175 | DEBUGFUNC("e1000_reset_adaptive"); |
| 5176 | |
| 5177 | if(hw->adaptive_ifs) { |
| 5178 | if(!hw->ifs_params_forced) { |
| 5179 | hw->current_ifs_val = 0; |
| 5180 | hw->ifs_min_val = IFS_MIN; |
| 5181 | hw->ifs_max_val = IFS_MAX; |
| 5182 | hw->ifs_step_size = IFS_STEP; |
| 5183 | hw->ifs_ratio = IFS_RATIO; |
| 5184 | } |
| 5185 | hw->in_ifs_mode = FALSE; |
| 5186 | E1000_WRITE_REG(hw, AIT, 0); |
| 5187 | } else { |
| 5188 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
| 5189 | } |
| 5190 | } |
| 5191 | |
| 5192 | /****************************************************************************** |
| 5193 | * Called during the callback/watchdog routine to update IFS value based on |
| 5194 | * the ratio of transmits to collisions. |
| 5195 | * |
| 5196 | * hw - Struct containing variables accessed by shared code |
| 5197 | * tx_packets - Number of transmits since last callback |
| 5198 | * total_collisions - Number of collisions since last callback |
| 5199 | *****************************************************************************/ |
| 5200 | void |
| 5201 | e1000_update_adaptive(struct e1000_hw *hw) |
| 5202 | { |
| 5203 | DEBUGFUNC("e1000_update_adaptive"); |
| 5204 | |
| 5205 | if(hw->adaptive_ifs) { |
| 5206 | if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { |
| 5207 | if(hw->tx_packet_delta > MIN_NUM_XMITS) { |
| 5208 | hw->in_ifs_mode = TRUE; |
| 5209 | if(hw->current_ifs_val < hw->ifs_max_val) { |
| 5210 | if(hw->current_ifs_val == 0) |
| 5211 | hw->current_ifs_val = hw->ifs_min_val; |
| 5212 | else |
| 5213 | hw->current_ifs_val += hw->ifs_step_size; |
| 5214 | E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); |
| 5215 | } |
| 5216 | } |
| 5217 | } else { |
| 5218 | if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
| 5219 | hw->current_ifs_val = 0; |
| 5220 | hw->in_ifs_mode = FALSE; |
| 5221 | E1000_WRITE_REG(hw, AIT, 0); |
| 5222 | } |
| 5223 | } |
| 5224 | } else { |
| 5225 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
| 5226 | } |
| 5227 | } |
| 5228 | |
| 5229 | /****************************************************************************** |
| 5230 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
| 5231 | * |
| 5232 | * hw - Struct containing variables accessed by shared code |
| 5233 | * frame_len - The length of the frame in question |
| 5234 | * mac_addr - The Ethernet destination address of the frame in question |
| 5235 | *****************************************************************************/ |
| 5236 | void |
| 5237 | e1000_tbi_adjust_stats(struct e1000_hw *hw, |
| 5238 | struct e1000_hw_stats *stats, |
| 5239 | uint32_t frame_len, |
| 5240 | uint8_t *mac_addr) |
| 5241 | { |
| 5242 | uint64_t carry_bit; |
| 5243 | |
| 5244 | /* First adjust the frame length. */ |
| 5245 | frame_len--; |
| 5246 | /* We need to adjust the statistics counters, since the hardware |
| 5247 | * counters overcount this packet as a CRC error and undercount |
| 5248 | * the packet as a good packet |
| 5249 | */ |
| 5250 | /* This packet should not be counted as a CRC error. */ |
| 5251 | stats->crcerrs--; |
| 5252 | /* This packet does count as a Good Packet Received. */ |
| 5253 | stats->gprc++; |
| 5254 | |
| 5255 | /* Adjust the Good Octets received counters */ |
| 5256 | carry_bit = 0x80000000 & stats->gorcl; |
| 5257 | stats->gorcl += frame_len; |
| 5258 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
| 5259 | * Received Count) was one before the addition, |
| 5260 | * AND it is zero after, then we lost the carry out, |
| 5261 | * need to add one to Gorch (Good Octets Received Count High). |
| 5262 | * This could be simplified if all environments supported |
| 5263 | * 64-bit integers. |
| 5264 | */ |
| 5265 | if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
| 5266 | stats->gorch++; |
| 5267 | /* Is this a broadcast or multicast? Check broadcast first, |
| 5268 | * since the test for a multicast frame will test positive on |
| 5269 | * a broadcast frame. |
| 5270 | */ |
| 5271 | if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) |
| 5272 | /* Broadcast packet */ |
| 5273 | stats->bprc++; |
| 5274 | else if(*mac_addr & 0x01) |
| 5275 | /* Multicast packet */ |
| 5276 | stats->mprc++; |
| 5277 | |
| 5278 | if(frame_len == hw->max_frame_size) { |
| 5279 | /* In this case, the hardware has overcounted the number of |
| 5280 | * oversize frames. |
| 5281 | */ |
| 5282 | if(stats->roc > 0) |
| 5283 | stats->roc--; |
| 5284 | } |
| 5285 | |
| 5286 | /* Adjust the bin counters when the extra byte put the frame in the |
| 5287 | * wrong bin. Remember that the frame_len was adjusted above. |
| 5288 | */ |
| 5289 | if(frame_len == 64) { |
| 5290 | stats->prc64++; |
| 5291 | stats->prc127--; |
| 5292 | } else if(frame_len == 127) { |
| 5293 | stats->prc127++; |
| 5294 | stats->prc255--; |
| 5295 | } else if(frame_len == 255) { |
| 5296 | stats->prc255++; |
| 5297 | stats->prc511--; |
| 5298 | } else if(frame_len == 511) { |
| 5299 | stats->prc511++; |
| 5300 | stats->prc1023--; |
| 5301 | } else if(frame_len == 1023) { |
| 5302 | stats->prc1023++; |
| 5303 | stats->prc1522--; |
| 5304 | } else if(frame_len == 1522) { |
| 5305 | stats->prc1522++; |
| 5306 | } |
| 5307 | } |
| 5308 | |
| 5309 | /****************************************************************************** |
| 5310 | * Gets the current PCI bus type, speed, and width of the hardware |
| 5311 | * |
| 5312 | * hw - Struct containing variables accessed by shared code |
| 5313 | *****************************************************************************/ |
| 5314 | void |
| 5315 | e1000_get_bus_info(struct e1000_hw *hw) |
| 5316 | { |
| 5317 | uint32_t status; |
| 5318 | |
| 5319 | switch (hw->mac_type) { |
| 5320 | case e1000_82542_rev2_0: |
| 5321 | case e1000_82542_rev2_1: |
| 5322 | hw->bus_type = e1000_bus_type_unknown; |
| 5323 | hw->bus_speed = e1000_bus_speed_unknown; |
| 5324 | hw->bus_width = e1000_bus_width_unknown; |
| 5325 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5326 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5327 | case e1000_82573: |
| 5328 | hw->bus_type = e1000_bus_type_pci_express; |
| 5329 | hw->bus_speed = e1000_bus_speed_2500; |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 5330 | hw->bus_width = e1000_bus_width_pciex_1; |
| 5331 | break; |
| 5332 | case e1000_82571: |
| 5333 | hw->bus_type = e1000_bus_type_pci_express; |
| 5334 | hw->bus_speed = e1000_bus_speed_2500; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5335 | hw->bus_width = e1000_bus_width_pciex_4; |
| 5336 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5337 | default: |
| 5338 | status = E1000_READ_REG(hw, STATUS); |
| 5339 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
| 5340 | e1000_bus_type_pcix : e1000_bus_type_pci; |
| 5341 | |
| 5342 | if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
| 5343 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
| 5344 | e1000_bus_speed_66 : e1000_bus_speed_120; |
| 5345 | } else if(hw->bus_type == e1000_bus_type_pci) { |
| 5346 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
| 5347 | e1000_bus_speed_66 : e1000_bus_speed_33; |
| 5348 | } else { |
| 5349 | switch (status & E1000_STATUS_PCIX_SPEED) { |
| 5350 | case E1000_STATUS_PCIX_SPEED_66: |
| 5351 | hw->bus_speed = e1000_bus_speed_66; |
| 5352 | break; |
| 5353 | case E1000_STATUS_PCIX_SPEED_100: |
| 5354 | hw->bus_speed = e1000_bus_speed_100; |
| 5355 | break; |
| 5356 | case E1000_STATUS_PCIX_SPEED_133: |
| 5357 | hw->bus_speed = e1000_bus_speed_133; |
| 5358 | break; |
| 5359 | default: |
| 5360 | hw->bus_speed = e1000_bus_speed_reserved; |
| 5361 | break; |
| 5362 | } |
| 5363 | } |
| 5364 | hw->bus_width = (status & E1000_STATUS_BUS64) ? |
| 5365 | e1000_bus_width_64 : e1000_bus_width_32; |
| 5366 | break; |
| 5367 | } |
| 5368 | } |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5369 | |
| 5370 | #if 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5371 | /****************************************************************************** |
| 5372 | * Reads a value from one of the devices registers using port I/O (as opposed |
| 5373 | * memory mapped I/O). Only 82544 and newer devices support port I/O. |
| 5374 | * |
| 5375 | * hw - Struct containing variables accessed by shared code |
| 5376 | * offset - offset to read from |
| 5377 | *****************************************************************************/ |
| 5378 | uint32_t |
| 5379 | e1000_read_reg_io(struct e1000_hw *hw, |
| 5380 | uint32_t offset) |
| 5381 | { |
| 5382 | unsigned long io_addr = hw->io_base; |
| 5383 | unsigned long io_data = hw->io_base + 4; |
| 5384 | |
| 5385 | e1000_io_write(hw, io_addr, offset); |
| 5386 | return e1000_io_read(hw, io_data); |
| 5387 | } |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5388 | #endif /* 0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5389 | |
| 5390 | /****************************************************************************** |
| 5391 | * Writes a value to one of the devices registers using port I/O (as opposed to |
| 5392 | * memory mapped I/O). Only 82544 and newer devices support port I/O. |
| 5393 | * |
| 5394 | * hw - Struct containing variables accessed by shared code |
| 5395 | * offset - offset to write to |
| 5396 | * value - value to write |
| 5397 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5398 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5399 | e1000_write_reg_io(struct e1000_hw *hw, |
| 5400 | uint32_t offset, |
| 5401 | uint32_t value) |
| 5402 | { |
| 5403 | unsigned long io_addr = hw->io_base; |
| 5404 | unsigned long io_data = hw->io_base + 4; |
| 5405 | |
| 5406 | e1000_io_write(hw, io_addr, offset); |
| 5407 | e1000_io_write(hw, io_data, value); |
| 5408 | } |
| 5409 | |
| 5410 | |
| 5411 | /****************************************************************************** |
| 5412 | * Estimates the cable length. |
| 5413 | * |
| 5414 | * hw - Struct containing variables accessed by shared code |
| 5415 | * min_length - The estimated minimum length |
| 5416 | * max_length - The estimated maximum length |
| 5417 | * |
| 5418 | * returns: - E1000_ERR_XXX |
| 5419 | * E1000_SUCCESS |
| 5420 | * |
| 5421 | * This function always returns a ranged length (minimum & maximum). |
| 5422 | * So for M88 phy's, this function interprets the one value returned from the |
| 5423 | * register to the minimum and maximum range. |
| 5424 | * For IGP phy's, the function calculates the range by the AGC registers. |
| 5425 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5426 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5427 | e1000_get_cable_length(struct e1000_hw *hw, |
| 5428 | uint16_t *min_length, |
| 5429 | uint16_t *max_length) |
| 5430 | { |
| 5431 | int32_t ret_val; |
| 5432 | uint16_t agc_value = 0; |
| 5433 | uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5434 | uint16_t max_agc = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5435 | uint16_t i, phy_data; |
| 5436 | uint16_t cable_length; |
| 5437 | |
| 5438 | DEBUGFUNC("e1000_get_cable_length"); |
| 5439 | |
| 5440 | *min_length = *max_length = 0; |
| 5441 | |
| 5442 | /* Use old method for Phy older than IGP */ |
| 5443 | if(hw->phy_type == e1000_phy_m88) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5444 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5445 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
| 5446 | &phy_data); |
| 5447 | if(ret_val) |
| 5448 | return ret_val; |
| 5449 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 5450 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
| 5451 | |
| 5452 | /* Convert the enum value to ranged values */ |
| 5453 | switch (cable_length) { |
| 5454 | case e1000_cable_length_50: |
| 5455 | *min_length = 0; |
| 5456 | *max_length = e1000_igp_cable_length_50; |
| 5457 | break; |
| 5458 | case e1000_cable_length_50_80: |
| 5459 | *min_length = e1000_igp_cable_length_50; |
| 5460 | *max_length = e1000_igp_cable_length_80; |
| 5461 | break; |
| 5462 | case e1000_cable_length_80_110: |
| 5463 | *min_length = e1000_igp_cable_length_80; |
| 5464 | *max_length = e1000_igp_cable_length_110; |
| 5465 | break; |
| 5466 | case e1000_cable_length_110_140: |
| 5467 | *min_length = e1000_igp_cable_length_110; |
| 5468 | *max_length = e1000_igp_cable_length_140; |
| 5469 | break; |
| 5470 | case e1000_cable_length_140: |
| 5471 | *min_length = e1000_igp_cable_length_140; |
| 5472 | *max_length = e1000_igp_cable_length_170; |
| 5473 | break; |
| 5474 | default: |
| 5475 | return -E1000_ERR_PHY; |
| 5476 | break; |
| 5477 | } |
| 5478 | } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
| 5479 | uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
| 5480 | {IGP01E1000_PHY_AGC_A, |
| 5481 | IGP01E1000_PHY_AGC_B, |
| 5482 | IGP01E1000_PHY_AGC_C, |
| 5483 | IGP01E1000_PHY_AGC_D}; |
| 5484 | /* Read the AGC registers for all channels */ |
| 5485 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
| 5486 | |
| 5487 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
| 5488 | if(ret_val) |
| 5489 | return ret_val; |
| 5490 | |
| 5491 | cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
| 5492 | |
| 5493 | /* Array bound check. */ |
| 5494 | if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || |
| 5495 | (cur_agc == 0)) |
| 5496 | return -E1000_ERR_PHY; |
| 5497 | |
| 5498 | agc_value += cur_agc; |
| 5499 | |
| 5500 | /* Update minimal AGC value. */ |
| 5501 | if(min_agc > cur_agc) |
| 5502 | min_agc = cur_agc; |
| 5503 | } |
| 5504 | |
| 5505 | /* Remove the minimal AGC result for length < 50m */ |
| 5506 | if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
| 5507 | agc_value -= min_agc; |
| 5508 | |
| 5509 | /* Get the average length of the remaining 3 channels */ |
| 5510 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
| 5511 | } else { |
| 5512 | /* Get the average length of all the 4 channels. */ |
| 5513 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
| 5514 | } |
| 5515 | |
| 5516 | /* Set the range of the calculated length. */ |
| 5517 | *min_length = ((e1000_igp_cable_length_table[agc_value] - |
| 5518 | IGP01E1000_AGC_RANGE) > 0) ? |
| 5519 | (e1000_igp_cable_length_table[agc_value] - |
| 5520 | IGP01E1000_AGC_RANGE) : 0; |
| 5521 | *max_length = e1000_igp_cable_length_table[agc_value] + |
| 5522 | IGP01E1000_AGC_RANGE; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5523 | } else if (hw->phy_type == e1000_phy_igp_2) { |
| 5524 | uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = |
| 5525 | {IGP02E1000_PHY_AGC_A, |
| 5526 | IGP02E1000_PHY_AGC_B, |
| 5527 | IGP02E1000_PHY_AGC_C, |
| 5528 | IGP02E1000_PHY_AGC_D}; |
| 5529 | /* Read the AGC registers for all channels */ |
| 5530 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
| 5531 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
| 5532 | if (ret_val) |
| 5533 | return ret_val; |
| 5534 | |
| 5535 | /* Getting bits 15:9, which represent the combination of course and |
| 5536 | * fine gain values. The result is a number that can be put into |
| 5537 | * the lookup table to obtain the approximate cable length. */ |
| 5538 | cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
| 5539 | IGP02E1000_AGC_LENGTH_MASK; |
| 5540 | |
| 5541 | /* Remove min & max AGC values from calculation. */ |
| 5542 | if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) |
| 5543 | min_agc = cur_agc; |
| 5544 | if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) |
| 5545 | max_agc = cur_agc; |
| 5546 | |
| 5547 | agc_value += e1000_igp_2_cable_length_table[cur_agc]; |
| 5548 | } |
| 5549 | |
| 5550 | agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); |
| 5551 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
| 5552 | |
| 5553 | /* Calculate cable length with the error range of +/- 10 meters. */ |
| 5554 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
| 5555 | (agc_value - IGP02E1000_AGC_RANGE) : 0; |
| 5556 | *max_length = agc_value + IGP02E1000_AGC_RANGE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5557 | } |
| 5558 | |
| 5559 | return E1000_SUCCESS; |
| 5560 | } |
| 5561 | |
| 5562 | /****************************************************************************** |
| 5563 | * Check the cable polarity |
| 5564 | * |
| 5565 | * hw - Struct containing variables accessed by shared code |
| 5566 | * polarity - output parameter : 0 - Polarity is not reversed |
| 5567 | * 1 - Polarity is reversed. |
| 5568 | * |
| 5569 | * returns: - E1000_ERR_XXX |
| 5570 | * E1000_SUCCESS |
| 5571 | * |
| 5572 | * For phy's older then IGP, this function simply reads the polarity bit in the |
| 5573 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
| 5574 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
| 5575 | * return 0. If the link speed is 1000 Mbps the polarity status is in the |
| 5576 | * IGP01E1000_PHY_PCS_INIT_REG. |
| 5577 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5578 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5579 | e1000_check_polarity(struct e1000_hw *hw, |
| 5580 | uint16_t *polarity) |
| 5581 | { |
| 5582 | int32_t ret_val; |
| 5583 | uint16_t phy_data; |
| 5584 | |
| 5585 | DEBUGFUNC("e1000_check_polarity"); |
| 5586 | |
| 5587 | if(hw->phy_type == e1000_phy_m88) { |
| 5588 | /* return the Polarity bit in the Status register. */ |
| 5589 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
| 5590 | &phy_data); |
| 5591 | if(ret_val) |
| 5592 | return ret_val; |
| 5593 | *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> |
| 5594 | M88E1000_PSSR_REV_POLARITY_SHIFT; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5595 | } else if(hw->phy_type == e1000_phy_igp || |
| 5596 | hw->phy_type == e1000_phy_igp_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5597 | /* Read the Status register to check the speed */ |
| 5598 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
| 5599 | &phy_data); |
| 5600 | if(ret_val) |
| 5601 | return ret_val; |
| 5602 | |
| 5603 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
| 5604 | * find the polarity status */ |
| 5605 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
| 5606 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
| 5607 | |
| 5608 | /* Read the GIG initialization PCS register (0x00B4) */ |
| 5609 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
| 5610 | &phy_data); |
| 5611 | if(ret_val) |
| 5612 | return ret_val; |
| 5613 | |
| 5614 | /* Check the polarity bits */ |
| 5615 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; |
| 5616 | } else { |
| 5617 | /* For 10 Mbps, read the polarity bit in the status register. (for |
| 5618 | * 100 Mbps this bit is always 0) */ |
| 5619 | *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; |
| 5620 | } |
| 5621 | } |
| 5622 | return E1000_SUCCESS; |
| 5623 | } |
| 5624 | |
| 5625 | /****************************************************************************** |
| 5626 | * Check if Downshift occured |
| 5627 | * |
| 5628 | * hw - Struct containing variables accessed by shared code |
| 5629 | * downshift - output parameter : 0 - No Downshift ocured. |
| 5630 | * 1 - Downshift ocured. |
| 5631 | * |
| 5632 | * returns: - E1000_ERR_XXX |
| 5633 | * E1000_SUCCESS |
| 5634 | * |
| 5635 | * For phy's older then IGP, this function reads the Downshift bit in the Phy |
| 5636 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
| 5637 | * Link Health register. In IGP this bit is latched high, so the driver must |
| 5638 | * read it immediately after link is established. |
| 5639 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5640 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5641 | e1000_check_downshift(struct e1000_hw *hw) |
| 5642 | { |
| 5643 | int32_t ret_val; |
| 5644 | uint16_t phy_data; |
| 5645 | |
| 5646 | DEBUGFUNC("e1000_check_downshift"); |
| 5647 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5648 | if(hw->phy_type == e1000_phy_igp || |
| 5649 | hw->phy_type == e1000_phy_igp_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5650 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
| 5651 | &phy_data); |
| 5652 | if(ret_val) |
| 5653 | return ret_val; |
| 5654 | |
| 5655 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
| 5656 | } else if(hw->phy_type == e1000_phy_m88) { |
| 5657 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
| 5658 | &phy_data); |
| 5659 | if(ret_val) |
| 5660 | return ret_val; |
| 5661 | |
| 5662 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
| 5663 | M88E1000_PSSR_DOWNSHIFT_SHIFT; |
| 5664 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5665 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5666 | return E1000_SUCCESS; |
| 5667 | } |
| 5668 | |
| 5669 | /***************************************************************************** |
| 5670 | * |
| 5671 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
| 5672 | * gigabit link is achieved to improve link quality. |
| 5673 | * |
| 5674 | * hw: Struct containing variables accessed by shared code |
| 5675 | * |
| 5676 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 5677 | * E1000_SUCCESS at any other case. |
| 5678 | * |
| 5679 | ****************************************************************************/ |
| 5680 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5681 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5682 | e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
| 5683 | boolean_t link_up) |
| 5684 | { |
| 5685 | int32_t ret_val; |
| 5686 | uint16_t phy_data, phy_saved_data, speed, duplex, i; |
| 5687 | uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
| 5688 | {IGP01E1000_PHY_AGC_PARAM_A, |
| 5689 | IGP01E1000_PHY_AGC_PARAM_B, |
| 5690 | IGP01E1000_PHY_AGC_PARAM_C, |
| 5691 | IGP01E1000_PHY_AGC_PARAM_D}; |
| 5692 | uint16_t min_length, max_length; |
| 5693 | |
| 5694 | DEBUGFUNC("e1000_config_dsp_after_link_change"); |
| 5695 | |
| 5696 | if(hw->phy_type != e1000_phy_igp) |
| 5697 | return E1000_SUCCESS; |
| 5698 | |
| 5699 | if(link_up) { |
| 5700 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
| 5701 | if(ret_val) { |
| 5702 | DEBUGOUT("Error getting link speed and duplex\n"); |
| 5703 | return ret_val; |
| 5704 | } |
| 5705 | |
| 5706 | if(speed == SPEED_1000) { |
| 5707 | |
| 5708 | e1000_get_cable_length(hw, &min_length, &max_length); |
| 5709 | |
| 5710 | if((hw->dsp_config_state == e1000_dsp_config_enabled) && |
| 5711 | min_length >= e1000_igp_cable_length_50) { |
| 5712 | |
| 5713 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
| 5714 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
| 5715 | &phy_data); |
| 5716 | if(ret_val) |
| 5717 | return ret_val; |
| 5718 | |
| 5719 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
| 5720 | |
| 5721 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], |
| 5722 | phy_data); |
| 5723 | if(ret_val) |
| 5724 | return ret_val; |
| 5725 | } |
| 5726 | hw->dsp_config_state = e1000_dsp_config_activated; |
| 5727 | } |
| 5728 | |
| 5729 | if((hw->ffe_config_state == e1000_ffe_config_enabled) && |
| 5730 | (min_length < e1000_igp_cable_length_50)) { |
| 5731 | |
| 5732 | uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
| 5733 | uint32_t idle_errs = 0; |
| 5734 | |
| 5735 | /* clear previous idle error counts */ |
| 5736 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
| 5737 | &phy_data); |
| 5738 | if(ret_val) |
| 5739 | return ret_val; |
| 5740 | |
| 5741 | for(i = 0; i < ffe_idle_err_timeout; i++) { |
| 5742 | udelay(1000); |
| 5743 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
| 5744 | &phy_data); |
| 5745 | if(ret_val) |
| 5746 | return ret_val; |
| 5747 | |
| 5748 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); |
| 5749 | if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
| 5750 | hw->ffe_config_state = e1000_ffe_config_active; |
| 5751 | |
| 5752 | ret_val = e1000_write_phy_reg(hw, |
| 5753 | IGP01E1000_PHY_DSP_FFE, |
| 5754 | IGP01E1000_PHY_DSP_FFE_CM_CP); |
| 5755 | if(ret_val) |
| 5756 | return ret_val; |
| 5757 | break; |
| 5758 | } |
| 5759 | |
| 5760 | if(idle_errs) |
| 5761 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
| 5762 | } |
| 5763 | } |
| 5764 | } |
| 5765 | } else { |
| 5766 | if(hw->dsp_config_state == e1000_dsp_config_activated) { |
| 5767 | /* Save off the current value of register 0x2F5B to be restored at |
| 5768 | * the end of the routines. */ |
| 5769 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 5770 | |
| 5771 | if(ret_val) |
| 5772 | return ret_val; |
| 5773 | |
| 5774 | /* Disable the PHY transmitter */ |
| 5775 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 5776 | |
| 5777 | if(ret_val) |
| 5778 | return ret_val; |
| 5779 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5780 | msec_delay_irq(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5781 | |
| 5782 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 5783 | IGP01E1000_IEEE_FORCE_GIGA); |
| 5784 | if(ret_val) |
| 5785 | return ret_val; |
| 5786 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
| 5787 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
| 5788 | if(ret_val) |
| 5789 | return ret_val; |
| 5790 | |
| 5791 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
| 5792 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
| 5793 | |
| 5794 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); |
| 5795 | if(ret_val) |
| 5796 | return ret_val; |
| 5797 | } |
| 5798 | |
| 5799 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 5800 | IGP01E1000_IEEE_RESTART_AUTONEG); |
| 5801 | if(ret_val) |
| 5802 | return ret_val; |
| 5803 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5804 | msec_delay_irq(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5805 | |
| 5806 | /* Now enable the transmitter */ |
| 5807 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 5808 | |
| 5809 | if(ret_val) |
| 5810 | return ret_val; |
| 5811 | |
| 5812 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 5813 | } |
| 5814 | |
| 5815 | if(hw->ffe_config_state == e1000_ffe_config_active) { |
| 5816 | /* Save off the current value of register 0x2F5B to be restored at |
| 5817 | * the end of the routines. */ |
| 5818 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 5819 | |
| 5820 | if(ret_val) |
| 5821 | return ret_val; |
| 5822 | |
| 5823 | /* Disable the PHY transmitter */ |
| 5824 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 5825 | |
| 5826 | if(ret_val) |
| 5827 | return ret_val; |
| 5828 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5829 | msec_delay_irq(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5830 | |
| 5831 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 5832 | IGP01E1000_IEEE_FORCE_GIGA); |
| 5833 | if(ret_val) |
| 5834 | return ret_val; |
| 5835 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
| 5836 | IGP01E1000_PHY_DSP_FFE_DEFAULT); |
| 5837 | if(ret_val) |
| 5838 | return ret_val; |
| 5839 | |
| 5840 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 5841 | IGP01E1000_IEEE_RESTART_AUTONEG); |
| 5842 | if(ret_val) |
| 5843 | return ret_val; |
| 5844 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5845 | msec_delay_irq(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5846 | |
| 5847 | /* Now enable the transmitter */ |
| 5848 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 5849 | |
| 5850 | if(ret_val) |
| 5851 | return ret_val; |
| 5852 | |
| 5853 | hw->ffe_config_state = e1000_ffe_config_enabled; |
| 5854 | } |
| 5855 | } |
| 5856 | return E1000_SUCCESS; |
| 5857 | } |
| 5858 | |
| 5859 | /***************************************************************************** |
| 5860 | * Set PHY to class A mode |
| 5861 | * Assumes the following operations will follow to enable the new class mode. |
| 5862 | * 1. Do a PHY soft reset |
| 5863 | * 2. Restart auto-negotiation or force link. |
| 5864 | * |
| 5865 | * hw - Struct containing variables accessed by shared code |
| 5866 | ****************************************************************************/ |
| 5867 | static int32_t |
| 5868 | e1000_set_phy_mode(struct e1000_hw *hw) |
| 5869 | { |
| 5870 | int32_t ret_val; |
| 5871 | uint16_t eeprom_data; |
| 5872 | |
| 5873 | DEBUGFUNC("e1000_set_phy_mode"); |
| 5874 | |
| 5875 | if((hw->mac_type == e1000_82545_rev_3) && |
| 5876 | (hw->media_type == e1000_media_type_copper)) { |
| 5877 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
| 5878 | if(ret_val) { |
| 5879 | return ret_val; |
| 5880 | } |
| 5881 | |
| 5882 | if((eeprom_data != EEPROM_RESERVED_WORD) && |
| 5883 | (eeprom_data & EEPROM_PHY_CLASS_A)) { |
| 5884 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
| 5885 | if(ret_val) |
| 5886 | return ret_val; |
| 5887 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); |
| 5888 | if(ret_val) |
| 5889 | return ret_val; |
| 5890 | |
| 5891 | hw->phy_reset_disable = FALSE; |
| 5892 | } |
| 5893 | } |
| 5894 | |
| 5895 | return E1000_SUCCESS; |
| 5896 | } |
| 5897 | |
| 5898 | /***************************************************************************** |
| 5899 | * |
| 5900 | * This function sets the lplu state according to the active flag. When |
| 5901 | * activating lplu this function also disables smart speed and vise versa. |
| 5902 | * lplu will not be activated unless the device autonegotiation advertisment |
| 5903 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 5904 | * hw: Struct containing variables accessed by shared code |
| 5905 | * active - true to enable lplu false to disable lplu. |
| 5906 | * |
| 5907 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 5908 | * E1000_SUCCESS at any other case. |
| 5909 | * |
| 5910 | ****************************************************************************/ |
| 5911 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5912 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5913 | e1000_set_d3_lplu_state(struct e1000_hw *hw, |
| 5914 | boolean_t active) |
| 5915 | { |
| 5916 | int32_t ret_val; |
| 5917 | uint16_t phy_data; |
| 5918 | DEBUGFUNC("e1000_set_d3_lplu_state"); |
| 5919 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5920 | if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5921 | return E1000_SUCCESS; |
| 5922 | |
| 5923 | /* During driver activity LPLU should not be used or it will attain link |
| 5924 | * from the lowest speeds starting from 10Mbps. The capability is used for |
| 5925 | * Dx transitions and states */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5926 | if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
| 5927 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5928 | if(ret_val) |
| 5929 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5930 | } else { |
| 5931 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
| 5932 | if(ret_val) |
| 5933 | return ret_val; |
| 5934 | } |
| 5935 | |
| 5936 | if(!active) { |
| 5937 | if(hw->mac_type == e1000_82541_rev_2 || |
| 5938 | hw->mac_type == e1000_82547_rev_2) { |
| 5939 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
| 5940 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
| 5941 | if(ret_val) |
| 5942 | return ret_val; |
| 5943 | } else { |
| 5944 | phy_data &= ~IGP02E1000_PM_D3_LPLU; |
| 5945 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
| 5946 | phy_data); |
| 5947 | if (ret_val) |
| 5948 | return ret_val; |
| 5949 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5950 | |
| 5951 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
| 5952 | * Dx states where the power conservation is most important. During |
| 5953 | * driver activity we should enable SmartSpeed, so performance is |
| 5954 | * maintained. */ |
| 5955 | if (hw->smart_speed == e1000_smart_speed_on) { |
| 5956 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 5957 | &phy_data); |
| 5958 | if(ret_val) |
| 5959 | return ret_val; |
| 5960 | |
| 5961 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 5962 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 5963 | phy_data); |
| 5964 | if(ret_val) |
| 5965 | return ret_val; |
| 5966 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
| 5967 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 5968 | &phy_data); |
| 5969 | if (ret_val) |
| 5970 | return ret_val; |
| 5971 | |
| 5972 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 5973 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 5974 | phy_data); |
| 5975 | if(ret_val) |
| 5976 | return ret_val; |
| 5977 | } |
| 5978 | |
| 5979 | } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
| 5980 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || |
| 5981 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
| 5982 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5983 | if(hw->mac_type == e1000_82541_rev_2 || |
| 5984 | hw->mac_type == e1000_82547_rev_2) { |
| 5985 | phy_data |= IGP01E1000_GMII_FLEX_SPD; |
| 5986 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
| 5987 | if(ret_val) |
| 5988 | return ret_val; |
| 5989 | } else { |
| 5990 | phy_data |= IGP02E1000_PM_D3_LPLU; |
| 5991 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
| 5992 | phy_data); |
| 5993 | if (ret_val) |
| 5994 | return ret_val; |
| 5995 | } |
| 5996 | |
| 5997 | /* When LPLU is enabled we should disable SmartSpeed */ |
| 5998 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5999 | if(ret_val) |
| 6000 | return ret_val; |
| 6001 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6002 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 6003 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 6004 | if(ret_val) |
| 6005 | return ret_val; |
| 6006 | |
| 6007 | } |
| 6008 | return E1000_SUCCESS; |
| 6009 | } |
| 6010 | |
| 6011 | /***************************************************************************** |
| 6012 | * |
| 6013 | * This function sets the lplu d0 state according to the active flag. When |
| 6014 | * activating lplu this function also disables smart speed and vise versa. |
| 6015 | * lplu will not be activated unless the device autonegotiation advertisment |
| 6016 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 6017 | * hw: Struct containing variables accessed by shared code |
| 6018 | * active - true to enable lplu false to disable lplu. |
| 6019 | * |
| 6020 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 6021 | * E1000_SUCCESS at any other case. |
| 6022 | * |
| 6023 | ****************************************************************************/ |
| 6024 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6025 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6026 | e1000_set_d0_lplu_state(struct e1000_hw *hw, |
| 6027 | boolean_t active) |
| 6028 | { |
| 6029 | int32_t ret_val; |
| 6030 | uint16_t phy_data; |
| 6031 | DEBUGFUNC("e1000_set_d0_lplu_state"); |
| 6032 | |
| 6033 | if(hw->mac_type <= e1000_82547_rev_2) |
| 6034 | return E1000_SUCCESS; |
| 6035 | |
| 6036 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
| 6037 | if(ret_val) |
| 6038 | return ret_val; |
| 6039 | |
| 6040 | if (!active) { |
| 6041 | phy_data &= ~IGP02E1000_PM_D0_LPLU; |
| 6042 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 6043 | if (ret_val) |
| 6044 | return ret_val; |
| 6045 | |
| 6046 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
| 6047 | * Dx states where the power conservation is most important. During |
| 6048 | * driver activity we should enable SmartSpeed, so performance is |
| 6049 | * maintained. */ |
| 6050 | if (hw->smart_speed == e1000_smart_speed_on) { |
| 6051 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 6052 | &phy_data); |
| 6053 | if(ret_val) |
| 6054 | return ret_val; |
| 6055 | |
| 6056 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 6057 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 6058 | phy_data); |
| 6059 | if(ret_val) |
| 6060 | return ret_val; |
| 6061 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
| 6062 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 6063 | &phy_data); |
| 6064 | if (ret_val) |
| 6065 | return ret_val; |
| 6066 | |
| 6067 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 6068 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 6069 | phy_data); |
| 6070 | if(ret_val) |
| 6071 | return ret_val; |
| 6072 | } |
| 6073 | |
| 6074 | |
| 6075 | } else { |
| 6076 | |
| 6077 | phy_data |= IGP02E1000_PM_D0_LPLU; |
| 6078 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 6079 | if (ret_val) |
| 6080 | return ret_val; |
| 6081 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6082 | /* When LPLU is enabled we should disable SmartSpeed */ |
| 6083 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
| 6084 | if(ret_val) |
| 6085 | return ret_val; |
| 6086 | |
| 6087 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 6088 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
| 6089 | if(ret_val) |
| 6090 | return ret_val; |
| 6091 | |
| 6092 | } |
| 6093 | return E1000_SUCCESS; |
| 6094 | } |
| 6095 | |
| 6096 | /****************************************************************************** |
| 6097 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
| 6098 | * |
| 6099 | * hw - Struct containing variables accessed by shared code |
| 6100 | *****************************************************************************/ |
| 6101 | static int32_t |
| 6102 | e1000_set_vco_speed(struct e1000_hw *hw) |
| 6103 | { |
| 6104 | int32_t ret_val; |
| 6105 | uint16_t default_page = 0; |
| 6106 | uint16_t phy_data; |
| 6107 | |
| 6108 | DEBUGFUNC("e1000_set_vco_speed"); |
| 6109 | |
| 6110 | switch(hw->mac_type) { |
| 6111 | case e1000_82545_rev_3: |
| 6112 | case e1000_82546_rev_3: |
| 6113 | break; |
| 6114 | default: |
| 6115 | return E1000_SUCCESS; |
| 6116 | } |
| 6117 | |
| 6118 | /* Set PHY register 30, page 5, bit 8 to 0 */ |
| 6119 | |
| 6120 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
| 6121 | if(ret_val) |
| 6122 | return ret_val; |
| 6123 | |
| 6124 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
| 6125 | if(ret_val) |
| 6126 | return ret_val; |
| 6127 | |
| 6128 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
| 6129 | if(ret_val) |
| 6130 | return ret_val; |
| 6131 | |
| 6132 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
| 6133 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
| 6134 | if(ret_val) |
| 6135 | return ret_val; |
| 6136 | |
| 6137 | /* Set PHY register 30, page 4, bit 11 to 1 */ |
| 6138 | |
| 6139 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
| 6140 | if(ret_val) |
| 6141 | return ret_val; |
| 6142 | |
| 6143 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
| 6144 | if(ret_val) |
| 6145 | return ret_val; |
| 6146 | |
| 6147 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
| 6148 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
| 6149 | if(ret_val) |
| 6150 | return ret_val; |
| 6151 | |
| 6152 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
| 6153 | if(ret_val) |
| 6154 | return ret_val; |
| 6155 | |
| 6156 | return E1000_SUCCESS; |
| 6157 | } |
| 6158 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6159 | |
| 6160 | /***************************************************************************** |
| 6161 | * This function reads the cookie from ARC ram. |
| 6162 | * |
| 6163 | * returns: - E1000_SUCCESS . |
| 6164 | ****************************************************************************/ |
| 6165 | int32_t |
| 6166 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) |
| 6167 | { |
| 6168 | uint8_t i; |
| 6169 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
| 6170 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
| 6171 | |
| 6172 | length = (length >> 2); |
| 6173 | offset = (offset >> 2); |
| 6174 | |
| 6175 | for (i = 0; i < length; i++) { |
| 6176 | *((uint32_t *) buffer + i) = |
| 6177 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); |
| 6178 | } |
| 6179 | return E1000_SUCCESS; |
| 6180 | } |
| 6181 | |
| 6182 | |
| 6183 | /***************************************************************************** |
| 6184 | * This function checks whether the HOST IF is enabled for command operaton |
| 6185 | * and also checks whether the previous command is completed. |
| 6186 | * It busy waits in case of previous command is not completed. |
| 6187 | * |
| 6188 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
| 6189 | * timeout |
| 6190 | * - E1000_SUCCESS for success. |
| 6191 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6192 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6193 | e1000_mng_enable_host_if(struct e1000_hw * hw) |
| 6194 | { |
| 6195 | uint32_t hicr; |
| 6196 | uint8_t i; |
| 6197 | |
| 6198 | /* Check that the host interface is enabled. */ |
| 6199 | hicr = E1000_READ_REG(hw, HICR); |
| 6200 | if ((hicr & E1000_HICR_EN) == 0) { |
| 6201 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); |
| 6202 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
| 6203 | } |
| 6204 | /* check the previous command is completed */ |
| 6205 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
| 6206 | hicr = E1000_READ_REG(hw, HICR); |
| 6207 | if (!(hicr & E1000_HICR_C)) |
| 6208 | break; |
| 6209 | msec_delay_irq(1); |
| 6210 | } |
| 6211 | |
| 6212 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
| 6213 | DEBUGOUT("Previous command timeout failed .\n"); |
| 6214 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
| 6215 | } |
| 6216 | return E1000_SUCCESS; |
| 6217 | } |
| 6218 | |
| 6219 | /***************************************************************************** |
| 6220 | * This function writes the buffer content at the offset given on the host if. |
| 6221 | * It also does alignment considerations to do the writes in most efficient way. |
| 6222 | * Also fills up the sum of the buffer in *buffer parameter. |
| 6223 | * |
| 6224 | * returns - E1000_SUCCESS for success. |
| 6225 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6226 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6227 | e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, |
| 6228 | uint16_t length, uint16_t offset, uint8_t *sum) |
| 6229 | { |
| 6230 | uint8_t *tmp; |
| 6231 | uint8_t *bufptr = buffer; |
| 6232 | uint32_t data; |
| 6233 | uint16_t remaining, i, j, prev_bytes; |
| 6234 | |
| 6235 | /* sum = only sum of the data and it is not checksum */ |
| 6236 | |
| 6237 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { |
| 6238 | return -E1000_ERR_PARAM; |
| 6239 | } |
| 6240 | |
| 6241 | tmp = (uint8_t *)&data; |
| 6242 | prev_bytes = offset & 0x3; |
| 6243 | offset &= 0xFFFC; |
| 6244 | offset >>= 2; |
| 6245 | |
| 6246 | if (prev_bytes) { |
| 6247 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); |
| 6248 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { |
| 6249 | *(tmp + j) = *bufptr++; |
| 6250 | *sum += *(tmp + j); |
| 6251 | } |
| 6252 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); |
| 6253 | length -= j - prev_bytes; |
| 6254 | offset++; |
| 6255 | } |
| 6256 | |
| 6257 | remaining = length & 0x3; |
| 6258 | length -= remaining; |
| 6259 | |
| 6260 | /* Calculate length in DWORDs */ |
| 6261 | length >>= 2; |
| 6262 | |
| 6263 | /* The device driver writes the relevant command block into the |
| 6264 | * ram area. */ |
| 6265 | for (i = 0; i < length; i++) { |
| 6266 | for (j = 0; j < sizeof(uint32_t); j++) { |
| 6267 | *(tmp + j) = *bufptr++; |
| 6268 | *sum += *(tmp + j); |
| 6269 | } |
| 6270 | |
| 6271 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
| 6272 | } |
| 6273 | if (remaining) { |
| 6274 | for (j = 0; j < sizeof(uint32_t); j++) { |
| 6275 | if (j < remaining) |
| 6276 | *(tmp + j) = *bufptr++; |
| 6277 | else |
| 6278 | *(tmp + j) = 0; |
| 6279 | |
| 6280 | *sum += *(tmp + j); |
| 6281 | } |
| 6282 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
| 6283 | } |
| 6284 | |
| 6285 | return E1000_SUCCESS; |
| 6286 | } |
| 6287 | |
| 6288 | |
| 6289 | /***************************************************************************** |
| 6290 | * This function writes the command header after does the checksum calculation. |
| 6291 | * |
| 6292 | * returns - E1000_SUCCESS for success. |
| 6293 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6294 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6295 | e1000_mng_write_cmd_header(struct e1000_hw * hw, |
| 6296 | struct e1000_host_mng_command_header * hdr) |
| 6297 | { |
| 6298 | uint16_t i; |
| 6299 | uint8_t sum; |
| 6300 | uint8_t *buffer; |
| 6301 | |
| 6302 | /* Write the whole command header structure which includes sum of |
| 6303 | * the buffer */ |
| 6304 | |
| 6305 | uint16_t length = sizeof(struct e1000_host_mng_command_header); |
| 6306 | |
| 6307 | sum = hdr->checksum; |
| 6308 | hdr->checksum = 0; |
| 6309 | |
| 6310 | buffer = (uint8_t *) hdr; |
| 6311 | i = length; |
| 6312 | while(i--) |
| 6313 | sum += buffer[i]; |
| 6314 | |
| 6315 | hdr->checksum = 0 - sum; |
| 6316 | |
| 6317 | length >>= 2; |
| 6318 | /* The device driver writes the relevant command block into the ram area. */ |
| 6319 | for (i = 0; i < length; i++) |
| 6320 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); |
| 6321 | |
| 6322 | return E1000_SUCCESS; |
| 6323 | } |
| 6324 | |
| 6325 | |
| 6326 | /***************************************************************************** |
| 6327 | * This function indicates to ARC that a new command is pending which completes |
| 6328 | * one write operation by the driver. |
| 6329 | * |
| 6330 | * returns - E1000_SUCCESS for success. |
| 6331 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6332 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6333 | e1000_mng_write_commit( |
| 6334 | struct e1000_hw * hw) |
| 6335 | { |
| 6336 | uint32_t hicr; |
| 6337 | |
| 6338 | hicr = E1000_READ_REG(hw, HICR); |
| 6339 | /* Setting this bit tells the ARC that a new command is pending. */ |
| 6340 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); |
| 6341 | |
| 6342 | return E1000_SUCCESS; |
| 6343 | } |
| 6344 | |
| 6345 | |
| 6346 | /***************************************************************************** |
| 6347 | * This function checks the mode of the firmware. |
| 6348 | * |
| 6349 | * returns - TRUE when the mode is IAMT or FALSE. |
| 6350 | ****************************************************************************/ |
| 6351 | boolean_t |
| 6352 | e1000_check_mng_mode( |
| 6353 | struct e1000_hw *hw) |
| 6354 | { |
| 6355 | uint32_t fwsm; |
| 6356 | |
| 6357 | fwsm = E1000_READ_REG(hw, FWSM); |
| 6358 | |
| 6359 | if((fwsm & E1000_FWSM_MODE_MASK) == |
| 6360 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
| 6361 | return TRUE; |
| 6362 | |
| 6363 | return FALSE; |
| 6364 | } |
| 6365 | |
| 6366 | |
| 6367 | /***************************************************************************** |
| 6368 | * This function writes the dhcp info . |
| 6369 | ****************************************************************************/ |
| 6370 | int32_t |
| 6371 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, |
| 6372 | uint16_t length) |
| 6373 | { |
| 6374 | int32_t ret_val; |
| 6375 | struct e1000_host_mng_command_header hdr; |
| 6376 | |
| 6377 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
| 6378 | hdr.command_length = length; |
| 6379 | hdr.reserved1 = 0; |
| 6380 | hdr.reserved2 = 0; |
| 6381 | hdr.checksum = 0; |
| 6382 | |
| 6383 | ret_val = e1000_mng_enable_host_if(hw); |
| 6384 | if (ret_val == E1000_SUCCESS) { |
| 6385 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), |
| 6386 | &(hdr.checksum)); |
| 6387 | if (ret_val == E1000_SUCCESS) { |
| 6388 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); |
| 6389 | if (ret_val == E1000_SUCCESS) |
| 6390 | ret_val = e1000_mng_write_commit(hw); |
| 6391 | } |
| 6392 | } |
| 6393 | return ret_val; |
| 6394 | } |
| 6395 | |
| 6396 | |
| 6397 | /***************************************************************************** |
| 6398 | * This function calculates the checksum. |
| 6399 | * |
| 6400 | * returns - checksum of buffer contents. |
| 6401 | ****************************************************************************/ |
| 6402 | uint8_t |
| 6403 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) |
| 6404 | { |
| 6405 | uint8_t sum = 0; |
| 6406 | uint32_t i; |
| 6407 | |
| 6408 | if (!buffer) |
| 6409 | return 0; |
| 6410 | |
| 6411 | for (i=0; i < length; i++) |
| 6412 | sum += buffer[i]; |
| 6413 | |
| 6414 | return (uint8_t) (0 - sum); |
| 6415 | } |
| 6416 | |
| 6417 | /***************************************************************************** |
| 6418 | * This function checks whether tx pkt filtering needs to be enabled or not. |
| 6419 | * |
| 6420 | * returns - TRUE for packet filtering or FALSE. |
| 6421 | ****************************************************************************/ |
| 6422 | boolean_t |
| 6423 | e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) |
| 6424 | { |
| 6425 | /* called in init as well as watchdog timer functions */ |
| 6426 | |
| 6427 | int32_t ret_val, checksum; |
| 6428 | boolean_t tx_filter = FALSE; |
| 6429 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); |
| 6430 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); |
| 6431 | |
| 6432 | if (e1000_check_mng_mode(hw)) { |
| 6433 | ret_val = e1000_mng_enable_host_if(hw); |
| 6434 | if (ret_val == E1000_SUCCESS) { |
| 6435 | ret_val = e1000_host_if_read_cookie(hw, buffer); |
| 6436 | if (ret_val == E1000_SUCCESS) { |
| 6437 | checksum = hdr->checksum; |
| 6438 | hdr->checksum = 0; |
| 6439 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && |
| 6440 | checksum == e1000_calculate_mng_checksum((char *)buffer, |
| 6441 | E1000_MNG_DHCP_COOKIE_LENGTH)) { |
| 6442 | if (hdr->status & |
| 6443 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) |
| 6444 | tx_filter = TRUE; |
| 6445 | } else |
| 6446 | tx_filter = TRUE; |
| 6447 | } else |
| 6448 | tx_filter = TRUE; |
| 6449 | } |
| 6450 | } |
| 6451 | |
| 6452 | hw->tx_pkt_filtering = tx_filter; |
| 6453 | return tx_filter; |
| 6454 | } |
| 6455 | |
| 6456 | /****************************************************************************** |
| 6457 | * Verifies the hardware needs to allow ARPs to be processed by the host |
| 6458 | * |
| 6459 | * hw - Struct containing variables accessed by shared code |
| 6460 | * |
| 6461 | * returns: - TRUE/FALSE |
| 6462 | * |
| 6463 | *****************************************************************************/ |
| 6464 | uint32_t |
| 6465 | e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
| 6466 | { |
| 6467 | uint32_t manc; |
| 6468 | uint32_t fwsm, factps; |
| 6469 | |
| 6470 | if (hw->asf_firmware_present) { |
| 6471 | manc = E1000_READ_REG(hw, MANC); |
| 6472 | |
| 6473 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
| 6474 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
| 6475 | return FALSE; |
| 6476 | if (e1000_arc_subsystem_valid(hw) == TRUE) { |
| 6477 | fwsm = E1000_READ_REG(hw, FWSM); |
| 6478 | factps = E1000_READ_REG(hw, FACTPS); |
| 6479 | |
| 6480 | if (((fwsm & E1000_FWSM_MODE_MASK) == |
| 6481 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && |
| 6482 | (factps & E1000_FACTPS_MNGCG)) |
| 6483 | return TRUE; |
| 6484 | } else |
| 6485 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
| 6486 | return TRUE; |
| 6487 | } |
| 6488 | return FALSE; |
| 6489 | } |
| 6490 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6491 | static int32_t |
| 6492 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
| 6493 | { |
| 6494 | int32_t ret_val; |
| 6495 | uint16_t mii_status_reg; |
| 6496 | uint16_t i; |
| 6497 | |
| 6498 | /* Polarity reversal workaround for forced 10F/10H links. */ |
| 6499 | |
| 6500 | /* Disable the transmitter on the PHY */ |
| 6501 | |
| 6502 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
| 6503 | if(ret_val) |
| 6504 | return ret_val; |
| 6505 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
| 6506 | if(ret_val) |
| 6507 | return ret_val; |
| 6508 | |
| 6509 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
| 6510 | if(ret_val) |
| 6511 | return ret_val; |
| 6512 | |
| 6513 | /* This loop will early-out if the NO link condition has been met. */ |
| 6514 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
| 6515 | /* Read the MII Status Register and wait for Link Status bit |
| 6516 | * to be clear. |
| 6517 | */ |
| 6518 | |
| 6519 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 6520 | if(ret_val) |
| 6521 | return ret_val; |
| 6522 | |
| 6523 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 6524 | if(ret_val) |
| 6525 | return ret_val; |
| 6526 | |
| 6527 | if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
| 6528 | msec_delay_irq(100); |
| 6529 | } |
| 6530 | |
| 6531 | /* Recommended delay time after link has been lost */ |
| 6532 | msec_delay_irq(1000); |
| 6533 | |
| 6534 | /* Now we will re-enable th transmitter on the PHY */ |
| 6535 | |
| 6536 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
| 6537 | if(ret_val) |
| 6538 | return ret_val; |
| 6539 | msec_delay_irq(50); |
| 6540 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
| 6541 | if(ret_val) |
| 6542 | return ret_val; |
| 6543 | msec_delay_irq(50); |
| 6544 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
| 6545 | if(ret_val) |
| 6546 | return ret_val; |
| 6547 | msec_delay_irq(50); |
| 6548 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
| 6549 | if(ret_val) |
| 6550 | return ret_val; |
| 6551 | |
| 6552 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
| 6553 | if(ret_val) |
| 6554 | return ret_val; |
| 6555 | |
| 6556 | /* This loop will early-out if the link condition has been met. */ |
| 6557 | for(i = PHY_FORCE_TIME; i > 0; i--) { |
| 6558 | /* Read the MII Status Register and wait for Link Status bit |
| 6559 | * to be set. |
| 6560 | */ |
| 6561 | |
| 6562 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 6563 | if(ret_val) |
| 6564 | return ret_val; |
| 6565 | |
| 6566 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
| 6567 | if(ret_val) |
| 6568 | return ret_val; |
| 6569 | |
| 6570 | if(mii_status_reg & MII_SR_LINK_STATUS) break; |
| 6571 | msec_delay_irq(100); |
| 6572 | } |
| 6573 | return E1000_SUCCESS; |
| 6574 | } |
| 6575 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6576 | /*************************************************************************** |
| 6577 | * |
| 6578 | * Disables PCI-Express master access. |
| 6579 | * |
| 6580 | * hw: Struct containing variables accessed by shared code |
| 6581 | * |
| 6582 | * returns: - none. |
| 6583 | * |
| 6584 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6585 | static void |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6586 | e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
| 6587 | { |
| 6588 | uint32_t ctrl; |
| 6589 | |
| 6590 | DEBUGFUNC("e1000_set_pci_express_master_disable"); |
| 6591 | |
| 6592 | if (hw->bus_type != e1000_bus_type_pci_express) |
| 6593 | return; |
| 6594 | |
| 6595 | ctrl = E1000_READ_REG(hw, CTRL); |
| 6596 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 6597 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 6598 | } |
| 6599 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6600 | #if 0 |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6601 | /*************************************************************************** |
| 6602 | * |
| 6603 | * Enables PCI-Express master access. |
| 6604 | * |
| 6605 | * hw: Struct containing variables accessed by shared code |
| 6606 | * |
| 6607 | * returns: - none. |
| 6608 | * |
| 6609 | ***************************************************************************/ |
| 6610 | void |
| 6611 | e1000_enable_pciex_master(struct e1000_hw *hw) |
| 6612 | { |
| 6613 | uint32_t ctrl; |
| 6614 | |
| 6615 | DEBUGFUNC("e1000_enable_pciex_master"); |
| 6616 | |
| 6617 | if (hw->bus_type != e1000_bus_type_pci_express) |
| 6618 | return; |
| 6619 | |
| 6620 | ctrl = E1000_READ_REG(hw, CTRL); |
| 6621 | ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; |
| 6622 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 6623 | } |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6624 | #endif /* 0 */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6625 | |
| 6626 | /******************************************************************************* |
| 6627 | * |
| 6628 | * Disables PCI-Express master access and verifies there are no pending requests |
| 6629 | * |
| 6630 | * hw: Struct containing variables accessed by shared code |
| 6631 | * |
| 6632 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't |
| 6633 | * caused the master requests to be disabled. |
| 6634 | * E1000_SUCCESS master requests disabled. |
| 6635 | * |
| 6636 | ******************************************************************************/ |
| 6637 | int32_t |
| 6638 | e1000_disable_pciex_master(struct e1000_hw *hw) |
| 6639 | { |
| 6640 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ |
| 6641 | |
| 6642 | DEBUGFUNC("e1000_disable_pciex_master"); |
| 6643 | |
| 6644 | if (hw->bus_type != e1000_bus_type_pci_express) |
| 6645 | return E1000_SUCCESS; |
| 6646 | |
| 6647 | e1000_set_pci_express_master_disable(hw); |
| 6648 | |
| 6649 | while(timeout) { |
| 6650 | if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
| 6651 | break; |
| 6652 | else |
| 6653 | udelay(100); |
| 6654 | timeout--; |
| 6655 | } |
| 6656 | |
| 6657 | if(!timeout) { |
| 6658 | DEBUGOUT("Master requests are pending.\n"); |
| 6659 | return -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 6660 | } |
| 6661 | |
| 6662 | return E1000_SUCCESS; |
| 6663 | } |
| 6664 | |
| 6665 | /******************************************************************************* |
| 6666 | * |
| 6667 | * Check for EEPROM Auto Read bit done. |
| 6668 | * |
| 6669 | * hw: Struct containing variables accessed by shared code |
| 6670 | * |
| 6671 | * returns: - E1000_ERR_RESET if fail to reset MAC |
| 6672 | * E1000_SUCCESS at any other case. |
| 6673 | * |
| 6674 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6675 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6676 | e1000_get_auto_rd_done(struct e1000_hw *hw) |
| 6677 | { |
| 6678 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; |
| 6679 | |
| 6680 | DEBUGFUNC("e1000_get_auto_rd_done"); |
| 6681 | |
| 6682 | switch (hw->mac_type) { |
| 6683 | default: |
| 6684 | msec_delay(5); |
| 6685 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6686 | case e1000_82571: |
| 6687 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6688 | case e1000_82573: |
| 6689 | while(timeout) { |
| 6690 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; |
| 6691 | else msec_delay(1); |
| 6692 | timeout--; |
| 6693 | } |
| 6694 | |
| 6695 | if(!timeout) { |
| 6696 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
| 6697 | return -E1000_ERR_RESET; |
| 6698 | } |
| 6699 | break; |
| 6700 | } |
| 6701 | |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 6702 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
| 6703 | * Need to wait for PHY configuration completion before accessing NVM |
| 6704 | * and PHY. */ |
| 6705 | if (hw->mac_type == e1000_82573) |
| 6706 | msec_delay(25); |
| 6707 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6708 | return E1000_SUCCESS; |
| 6709 | } |
| 6710 | |
| 6711 | /*************************************************************************** |
| 6712 | * Checks if the PHY configuration is done |
| 6713 | * |
| 6714 | * hw: Struct containing variables accessed by shared code |
| 6715 | * |
| 6716 | * returns: - E1000_ERR_RESET if fail to reset MAC |
| 6717 | * E1000_SUCCESS at any other case. |
| 6718 | * |
| 6719 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6720 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6721 | e1000_get_phy_cfg_done(struct e1000_hw *hw) |
| 6722 | { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6723 | int32_t timeout = PHY_CFG_TIMEOUT; |
| 6724 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; |
| 6725 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6726 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
| 6727 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6728 | switch (hw->mac_type) { |
| 6729 | default: |
| 6730 | msec_delay(10); |
| 6731 | break; |
| 6732 | case e1000_82571: |
| 6733 | case e1000_82572: |
| 6734 | while (timeout) { |
| 6735 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
| 6736 | break; |
| 6737 | else |
| 6738 | msec_delay(1); |
| 6739 | timeout--; |
| 6740 | } |
| 6741 | |
| 6742 | if (!timeout) { |
| 6743 | DEBUGOUT("MNG configuration cycle has not completed.\n"); |
| 6744 | return -E1000_ERR_RESET; |
| 6745 | } |
| 6746 | break; |
| 6747 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6748 | |
Jeff Kirsher | 7892f59 | 2006-01-12 16:50:32 -0800 | [diff] [blame] | 6749 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
| 6750 | * Need to wait for PHY configuration completion before accessing NVM |
| 6751 | * and PHY. */ |
| 6752 | if (hw->mac_type == e1000_82573) |
| 6753 | msec_delay(25); |
| 6754 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6755 | return E1000_SUCCESS; |
| 6756 | } |
| 6757 | |
| 6758 | /*************************************************************************** |
| 6759 | * |
| 6760 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting |
| 6761 | * adapter or Eeprom access. |
| 6762 | * |
| 6763 | * hw: Struct containing variables accessed by shared code |
| 6764 | * |
| 6765 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. |
| 6766 | * E1000_SUCCESS at any other case. |
| 6767 | * |
| 6768 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6769 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6770 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
| 6771 | { |
| 6772 | int32_t timeout; |
| 6773 | uint32_t swsm; |
| 6774 | |
| 6775 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); |
| 6776 | |
| 6777 | if(!hw->eeprom_semaphore_present) |
| 6778 | return E1000_SUCCESS; |
| 6779 | |
| 6780 | |
| 6781 | /* Get the FW semaphore. */ |
| 6782 | timeout = hw->eeprom.word_size + 1; |
| 6783 | while(timeout) { |
| 6784 | swsm = E1000_READ_REG(hw, SWSM); |
| 6785 | swsm |= E1000_SWSM_SWESMBI; |
| 6786 | E1000_WRITE_REG(hw, SWSM, swsm); |
| 6787 | /* if we managed to set the bit we got the semaphore. */ |
| 6788 | swsm = E1000_READ_REG(hw, SWSM); |
| 6789 | if(swsm & E1000_SWSM_SWESMBI) |
| 6790 | break; |
| 6791 | |
| 6792 | udelay(50); |
| 6793 | timeout--; |
| 6794 | } |
| 6795 | |
| 6796 | if(!timeout) { |
| 6797 | /* Release semaphores */ |
| 6798 | e1000_put_hw_eeprom_semaphore(hw); |
| 6799 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); |
| 6800 | return -E1000_ERR_EEPROM; |
| 6801 | } |
| 6802 | |
| 6803 | return E1000_SUCCESS; |
| 6804 | } |
| 6805 | |
| 6806 | /*************************************************************************** |
| 6807 | * This function clears HW semaphore bits. |
| 6808 | * |
| 6809 | * hw: Struct containing variables accessed by shared code |
| 6810 | * |
| 6811 | * returns: - None. |
| 6812 | * |
| 6813 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6814 | static void |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6815 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
| 6816 | { |
| 6817 | uint32_t swsm; |
| 6818 | |
| 6819 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); |
| 6820 | |
| 6821 | if(!hw->eeprom_semaphore_present) |
| 6822 | return; |
| 6823 | |
| 6824 | swsm = E1000_READ_REG(hw, SWSM); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6825 | swsm &= ~(E1000_SWSM_SWESMBI); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6826 | E1000_WRITE_REG(hw, SWSM, swsm); |
| 6827 | } |
| 6828 | |
| 6829 | /****************************************************************************** |
| 6830 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. |
| 6831 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to |
| 6832 | * the caller to figure out how to deal with it. |
| 6833 | * |
| 6834 | * hw - Struct containing variables accessed by shared code |
| 6835 | * |
| 6836 | * returns: - E1000_BLK_PHY_RESET |
| 6837 | * E1000_SUCCESS |
| 6838 | * |
| 6839 | *****************************************************************************/ |
| 6840 | int32_t |
| 6841 | e1000_check_phy_reset_block(struct e1000_hw *hw) |
| 6842 | { |
| 6843 | uint32_t manc = 0; |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 6844 | |
| 6845 | if (hw->mac_type > e1000_82547_rev_2) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6846 | manc = E1000_READ_REG(hw, MANC); |
| 6847 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
| 6848 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
| 6849 | } |
| 6850 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6851 | static uint8_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6852 | e1000_arc_subsystem_valid(struct e1000_hw *hw) |
| 6853 | { |
| 6854 | uint32_t fwsm; |
| 6855 | |
| 6856 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC |
| 6857 | * may not be provided a DMA clock when no manageability features are |
| 6858 | * enabled. We do not want to perform any reads/writes to these registers |
| 6859 | * if this is the case. We read FWSM to determine the manageability mode. |
| 6860 | */ |
| 6861 | switch (hw->mac_type) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6862 | case e1000_82571: |
| 6863 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6864 | case e1000_82573: |
| 6865 | fwsm = E1000_READ_REG(hw, FWSM); |
| 6866 | if((fwsm & E1000_FWSM_MODE_MASK) != 0) |
| 6867 | return TRUE; |
| 6868 | break; |
| 6869 | default: |
| 6870 | break; |
| 6871 | } |
| 6872 | return FALSE; |
| 6873 | } |
| 6874 | |
| 6875 | |
| 6876 | |