Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * include/linux/amba/pl022.h |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 ST-Ericsson AB |
| 5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
| 6 | * |
| 7 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 8 | * |
| 9 | * Initial version inspired by: |
| 10 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
| 11 | * Initial adoption to PL022 by: |
| 12 | * Sachin Verma <sachin.verma@st.com> |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | */ |
| 24 | |
| 25 | #ifndef _SSP_PL022_H |
| 26 | #define _SSP_PL022_H |
| 27 | |
Viresh Kumar | 327ef2e | 2012-03-23 13:05:48 +0530 | [diff] [blame] | 28 | #include <linux/types.h> |
| 29 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 30 | /** |
| 31 | * whether SSP is in loopback mode or not |
| 32 | */ |
| 33 | enum ssp_loopback { |
| 34 | LOOPBACK_DISABLED, |
| 35 | LOOPBACK_ENABLED |
| 36 | }; |
| 37 | |
| 38 | /** |
| 39 | * enum ssp_interface - interfaces allowed for this SSP Controller |
| 40 | * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface |
| 41 | * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial |
| 42 | * interface |
| 43 | * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire |
| 44 | * interface |
| 45 | * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810 |
| 46 | * &STn8815 only) |
| 47 | */ |
| 48 | enum ssp_interface { |
| 49 | SSP_INTERFACE_MOTOROLA_SPI, |
| 50 | SSP_INTERFACE_TI_SYNC_SERIAL, |
| 51 | SSP_INTERFACE_NATIONAL_MICROWIRE, |
| 52 | SSP_INTERFACE_UNIDIRECTIONAL |
| 53 | }; |
| 54 | |
| 55 | /** |
| 56 | * enum ssp_hierarchy - whether SSP is configured as Master or Slave |
| 57 | */ |
| 58 | enum ssp_hierarchy { |
| 59 | SSP_MASTER, |
| 60 | SSP_SLAVE |
| 61 | }; |
| 62 | |
| 63 | /** |
| 64 | * enum ssp_clock_params - clock parameters, to set SSP clock at a |
| 65 | * desired freq |
| 66 | */ |
| 67 | struct ssp_clock_params { |
| 68 | u8 cpsdvsr; /* value from 2 to 254 (even only!) */ |
| 69 | u8 scr; /* value from 0 to 255 */ |
| 70 | }; |
| 71 | |
| 72 | /** |
| 73 | * enum ssp_rx_endian - endianess of Rx FIFO Data |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 74 | * this feature is only available in ST versionf of PL022 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 75 | */ |
| 76 | enum ssp_rx_endian { |
| 77 | SSP_RX_MSB, |
| 78 | SSP_RX_LSB |
| 79 | }; |
| 80 | |
| 81 | /** |
| 82 | * enum ssp_tx_endian - endianess of Tx FIFO Data |
| 83 | */ |
| 84 | enum ssp_tx_endian { |
| 85 | SSP_TX_MSB, |
| 86 | SSP_TX_LSB |
| 87 | }; |
| 88 | |
| 89 | /** |
| 90 | * enum ssp_data_size - number of bits in one data element |
| 91 | */ |
| 92 | enum ssp_data_size { |
| 93 | SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6, |
| 94 | SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9, |
| 95 | SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12, |
| 96 | SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15, |
| 97 | SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18, |
| 98 | SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21, |
| 99 | SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24, |
| 100 | SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27, |
| 101 | SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30, |
| 102 | SSP_DATA_BITS_31, SSP_DATA_BITS_32 |
| 103 | }; |
| 104 | |
| 105 | /** |
| 106 | * enum ssp_mode - SSP mode of operation (Communication modes) |
| 107 | */ |
| 108 | enum ssp_mode { |
| 109 | INTERRUPT_TRANSFER, |
| 110 | POLLING_TRANSFER, |
| 111 | DMA_TRANSFER |
| 112 | }; |
| 113 | |
| 114 | /** |
| 115 | * enum ssp_rx_level_trig - receive FIFO watermark level which triggers |
| 116 | * IT: Interrupt fires when _N_ or more elements in RX FIFO. |
| 117 | */ |
| 118 | enum ssp_rx_level_trig { |
| 119 | SSP_RX_1_OR_MORE_ELEM, |
| 120 | SSP_RX_4_OR_MORE_ELEM, |
| 121 | SSP_RX_8_OR_MORE_ELEM, |
| 122 | SSP_RX_16_OR_MORE_ELEM, |
| 123 | SSP_RX_32_OR_MORE_ELEM |
| 124 | }; |
| 125 | |
| 126 | /** |
| 127 | * Transmit FIFO watermark level which triggers (IT Interrupt fires |
| 128 | * when _N_ or more empty locations in TX FIFO) |
| 129 | */ |
| 130 | enum ssp_tx_level_trig { |
| 131 | SSP_TX_1_OR_MORE_EMPTY_LOC, |
| 132 | SSP_TX_4_OR_MORE_EMPTY_LOC, |
| 133 | SSP_TX_8_OR_MORE_EMPTY_LOC, |
| 134 | SSP_TX_16_OR_MORE_EMPTY_LOC, |
| 135 | SSP_TX_32_OR_MORE_EMPTY_LOC |
| 136 | }; |
| 137 | |
| 138 | /** |
| 139 | * enum SPI Clock Phase - clock phase (Motorola SPI interface only) |
Linus Walleij | ee2b805 | 2009-08-15 15:12:05 +0100 | [diff] [blame] | 140 | * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity) |
| 141 | * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 142 | */ |
| 143 | enum ssp_spi_clk_phase { |
Linus Walleij | ee2b805 | 2009-08-15 15:12:05 +0100 | [diff] [blame] | 144 | SSP_CLK_FIRST_EDGE, |
| 145 | SSP_CLK_SECOND_EDGE |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | /** |
| 149 | * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only) |
| 150 | * @SSP_CLK_POL_IDLE_LOW: Low inactive level |
| 151 | * @SSP_CLK_POL_IDLE_HIGH: High inactive level |
| 152 | */ |
| 153 | enum ssp_spi_clk_pol { |
| 154 | SSP_CLK_POL_IDLE_LOW, |
| 155 | SSP_CLK_POL_IDLE_HIGH |
| 156 | }; |
| 157 | |
| 158 | /** |
| 159 | * Microwire Conrol Lengths Command size in microwire format |
| 160 | */ |
| 161 | enum ssp_microwire_ctrl_len { |
| 162 | SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6, |
| 163 | SSP_BITS_7, SSP_BITS_8, SSP_BITS_9, |
| 164 | SSP_BITS_10, SSP_BITS_11, SSP_BITS_12, |
| 165 | SSP_BITS_13, SSP_BITS_14, SSP_BITS_15, |
| 166 | SSP_BITS_16, SSP_BITS_17, SSP_BITS_18, |
| 167 | SSP_BITS_19, SSP_BITS_20, SSP_BITS_21, |
| 168 | SSP_BITS_22, SSP_BITS_23, SSP_BITS_24, |
| 169 | SSP_BITS_25, SSP_BITS_26, SSP_BITS_27, |
| 170 | SSP_BITS_28, SSP_BITS_29, SSP_BITS_30, |
| 171 | SSP_BITS_31, SSP_BITS_32 |
| 172 | }; |
| 173 | |
| 174 | /** |
| 175 | * enum Microwire Wait State |
| 176 | * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit |
| 177 | * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit |
| 178 | */ |
| 179 | enum ssp_microwire_wait_state { |
| 180 | SSP_MWIRE_WAIT_ZERO, |
| 181 | SSP_MWIRE_WAIT_ONE |
| 182 | }; |
| 183 | |
| 184 | /** |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 185 | * enum ssp_duplex - whether Full/Half Duplex on microwire, only |
| 186 | * available in the ST Micro variant. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 187 | * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional, |
| 188 | * SSPRXD not used |
| 189 | * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is |
| 190 | * an input. |
| 191 | */ |
| 192 | enum ssp_duplex { |
| 193 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
| 194 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX |
| 195 | }; |
| 196 | |
| 197 | /** |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 198 | * enum ssp_clkdelay - an optional clock delay on the feedback clock |
| 199 | * only available in the ST Micro PL023 variant. |
| 200 | * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the |
| 201 | * slave is sampled directly |
| 202 | * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with |
| 203 | * a delay of T-dt |
| 204 | * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt |
| 205 | * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt |
| 206 | * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt |
| 207 | * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt |
| 208 | * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt |
| 209 | * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt |
| 210 | */ |
| 211 | enum ssp_clkdelay { |
| 212 | SSP_FEEDBACK_CLK_DELAY_NONE, |
| 213 | SSP_FEEDBACK_CLK_DELAY_1T, |
| 214 | SSP_FEEDBACK_CLK_DELAY_2T, |
| 215 | SSP_FEEDBACK_CLK_DELAY_3T, |
| 216 | SSP_FEEDBACK_CLK_DELAY_4T, |
| 217 | SSP_FEEDBACK_CLK_DELAY_5T, |
| 218 | SSP_FEEDBACK_CLK_DELAY_6T, |
| 219 | SSP_FEEDBACK_CLK_DELAY_7T |
| 220 | }; |
| 221 | |
| 222 | /** |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 223 | * CHIP select/deselect commands |
| 224 | */ |
| 225 | enum ssp_chip_select { |
| 226 | SSP_CHIP_SELECT, |
| 227 | SSP_CHIP_DESELECT |
| 228 | }; |
| 229 | |
| 230 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 231 | struct dma_chan; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 232 | /** |
| 233 | * struct pl022_ssp_master - device.platform_data for SPI controller devices. |
| 234 | * @num_chipselect: chipselects are used to distinguish individual |
| 235 | * SPI slaves, and are numbered from zero to num_chipselects - 1. |
| 236 | * each slave has a chipselect signal, but it's common that not |
| 237 | * every chipselect is connected to a slave. |
| 238 | * @enable_dma: if true enables DMA driven transfers. |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 239 | * @dma_rx_param: parameter to locate an RX DMA channel. |
| 240 | * @dma_tx_param: parameter to locate a TX DMA channel. |
Chris Blair | 53e4ace | 2011-11-08 08:54:46 +0000 | [diff] [blame] | 241 | * @autosuspend_delay: delay in ms following transfer completion before the |
| 242 | * runtime power management system suspends the device. A setting of 0 |
| 243 | * indicates no delay and the device will be suspended immediately. |
Chris Blair | 14af60b | 2012-02-02 13:59:34 +0100 | [diff] [blame] | 244 | * @rt: indicates the controller should run the message pump with realtime |
| 245 | * priority to minimise the transfer latency on the bus. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 246 | */ |
| 247 | struct pl022_ssp_controller { |
| 248 | u16 bus_id; |
| 249 | u8 num_chipselect; |
| 250 | u8 enable_dma:1; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 251 | bool (*dma_filter)(struct dma_chan *chan, void *filter_param); |
| 252 | void *dma_rx_param; |
| 253 | void *dma_tx_param; |
Chris Blair | 53e4ace | 2011-11-08 08:54:46 +0000 | [diff] [blame] | 254 | int autosuspend_delay; |
Chris Blair | 14af60b | 2012-02-02 13:59:34 +0100 | [diff] [blame] | 255 | bool rt; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 256 | }; |
| 257 | |
| 258 | /** |
| 259 | * struct ssp_config_chip - spi_board_info.controller_data for SPI |
| 260 | * slave devices, copied to spi_device.controller_data. |
| 261 | * |
| 262 | * @lbm: used for test purpose to internally connect RX and TX |
| 263 | * @iface: Interface type(Motorola, TI, Microwire, Universal) |
| 264 | * @hierarchy: sets whether interface is master or slave |
| 265 | * @slave_tx_disable: SSPTXD is disconnected (in slave mode only) |
| 266 | * @clk_freq: Tune freq parameters of SSP(when in master mode) |
| 267 | * @endian_rx: Endianess of Data in Rx FIFO |
| 268 | * @endian_tx: Endianess of Data in Tx FIFO |
| 269 | * @data_size: Width of data element(4 to 32 bits) |
| 270 | * @com_mode: communication mode: polling, Interrupt or DMA |
| 271 | * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode) |
| 272 | * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode) |
| 273 | * @clk_phase: Motorola SPI interface Clock phase |
| 274 | * @clk_pol: Motorola SPI interface Clock polarity |
| 275 | * @ctrl_len: Microwire interface: Control length |
| 276 | * @wait_state: Microwire interface: Wait state |
| 277 | * @duplex: Microwire interface: Full/Half duplex |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 278 | * @clkdelay: on the PL023 variant, the delay in feeback clock cycles |
| 279 | * before sampling the incoming line |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 280 | * @cs_control: function pointer to board-specific function to |
| 281 | * assert/deassert I/O port to control HW generation of devices chip-select. |
| 282 | * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph) |
| 283 | * @dma_config: DMA configuration for SSP controller and peripheral |
| 284 | */ |
| 285 | struct pl022_config_chip { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 286 | enum ssp_interface iface; |
| 287 | enum ssp_hierarchy hierarchy; |
| 288 | bool slave_tx_disable; |
| 289 | struct ssp_clock_params clk_freq; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 290 | enum ssp_mode com_mode; |
| 291 | enum ssp_rx_level_trig rx_lev_trig; |
| 292 | enum ssp_tx_level_trig tx_lev_trig; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 293 | enum ssp_microwire_ctrl_len ctrl_len; |
| 294 | enum ssp_microwire_wait_state wait_state; |
| 295 | enum ssp_duplex duplex; |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 296 | enum ssp_clkdelay clkdelay; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 297 | void (*cs_control) (u32 control); |
| 298 | }; |
| 299 | |
| 300 | #endif /* _SSP_PL022_H */ |