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Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001/*
2 * include/linux/mfd/asic3.h
3 *
4 * Compaq ASIC3 headers.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
Samuel Ortiz3b26bf12008-06-20 11:09:51 +020011 * Copyright 2007-2008 OpenedHand Ltd.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080012 */
13
14#ifndef __ASIC3_H__
15#define __ASIC3_H__
16
17#include <linux/types.h>
18
Paul Parsons7d9e7e92011-05-13 18:52:56 +000019struct led_classdev;
20struct asic3_led {
21 const char *name;
22 const char *default_trigger;
23 struct led_classdev *cdev;
24};
25
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080026struct asic3_platform_data {
Samuel Ortiz3b26bf12008-06-20 11:09:51 +020027 u16 *gpio_config;
28 unsigned int gpio_config_num;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080029
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080030 unsigned int irq_base;
31
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020032 unsigned int gpio_base;
Paul Parsons7d9e7e92011-05-13 18:52:56 +000033
34 struct asic3_led *leds;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080035};
36
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080037#define ASIC3_NUM_GPIO_BANKS 4
38#define ASIC3_GPIOS_PER_BANK 16
39#define ASIC3_NUM_GPIOS 64
40#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
41
Philipp Zabel01906d62009-06-05 18:31:03 +020042#define ASIC3_IRQ_LED0 64
43#define ASIC3_IRQ_LED1 65
44#define ASIC3_IRQ_LED2 66
45#define ASIC3_IRQ_SPI 67
46#define ASIC3_IRQ_SMBUS 68
47#define ASIC3_IRQ_OWM 69
48
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020049#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
50
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080051#define ASIC3_GPIO_BANK_A 0
52#define ASIC3_GPIO_BANK_B 1
53#define ASIC3_GPIO_BANK_C 2
54#define ASIC3_GPIO_BANK_D 3
55
56#define ASIC3_GPIO(bank, gpio) \
57 ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
58#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
59/* All offsets below are specified with this address bus shift */
60#define ASIC3_DEFAULT_ADDR_SHIFT 2
61
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020062#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080063#define ASIC3_GPIO_OFFSET(base, reg) \
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020064 (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080065
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020066#define ASIC3_GPIO_A_BASE 0x0000
67#define ASIC3_GPIO_B_BASE 0x0100
68#define ASIC3_GPIO_C_BASE 0x0200
69#define ASIC3_GPIO_D_BASE 0x0300
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080070
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020071#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
72#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
73 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
74#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020075#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
76#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020077
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020078#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
79#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
80#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
81#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
82#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
83#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
84#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
85#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
86#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
87#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
88#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
89#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080090 * R/W bit 1: autosleep
91 * 0: disable gposlpout in normal mode,
92 * enable gposlpout in sleep mode.
93 */
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020094#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080095
Samuel Ortiz3b26bf12008-06-20 11:09:51 +020096/*
97 * ASIC3 GPIO config
98 *
99 * Bits 0..6 gpio number
100 * Bits 7..13 Alternate function
101 * Bit 14 Direction
102 * Bit 15 Initial value
103 *
104 */
105#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
106#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
107#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
108#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
109#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
110 | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
111 | (((init) & 0x1) << 15))
112#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
113 ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
114#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
115 ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
116
Philipp Zabel4a67b522008-07-03 12:27:32 +0200117/*
118 * Alternate functions
119 */
120#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
121#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
122#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
Paul Parsons7d9e7e92011-05-13 18:52:56 +0000123#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0)
124#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0)
125#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0)
Philipp Zabel4a67b522008-07-03 12:27:32 +0200126#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
127#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
128#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
129#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
130#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
131#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
132#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
133#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
134#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
135#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
136#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
137#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
138#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
139#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
140#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
141#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
142#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
143#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
144
145
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800146#define ASIC3_SPI_Base 0x0400
147#define ASIC3_SPI_Control 0x0000
148#define ASIC3_SPI_TxData 0x0004
149#define ASIC3_SPI_RxData 0x0008
150#define ASIC3_SPI_Int 0x000c
151#define ASIC3_SPI_Status 0x0010
152
153#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
154
155#define ASIC3_PWM_0_Base 0x0500
156#define ASIC3_PWM_1_Base 0x0600
157#define ASIC3_PWM_TimeBase 0x0000
158#define ASIC3_PWM_PeriodTime 0x0004
159#define ASIC3_PWM_DutyTime 0x0008
160
161#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
162#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
163
Paul Parsons7d9e7e92011-05-13 18:52:56 +0000164#define ASIC3_NUM_LEDS 3
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800165#define ASIC3_LED_0_Base 0x0700
166#define ASIC3_LED_1_Base 0x0800
167#define ASIC3_LED_2_Base 0x0900
168#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
169#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
170#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
171#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
172
173/* LED TimeBase bits - match ASIC2 */
174#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
175 /* Note: max = 5 on hx4700 */
176 /* 0: maximum time base */
177 /* 1: maximum time base / 2 */
178 /* n: maximum time base / 2^n */
179
180#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
181#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
182#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
183
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200184#define ASIC3_CLOCK_BASE 0x0A00
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800185#define ASIC3_CLOCK_CDEX 0x00
186#define ASIC3_CLOCK_SEL 0x04
187
188#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
189#define CLOCK_CDEX_SOURCE0 (1 << 0)
190#define CLOCK_CDEX_SOURCE1 (1 << 1)
191#define CLOCK_CDEX_SPI (1 << 2)
192#define CLOCK_CDEX_OWM (1 << 3)
193#define CLOCK_CDEX_PWM0 (1 << 4)
194#define CLOCK_CDEX_PWM1 (1 << 5)
195#define CLOCK_CDEX_LED0 (1 << 6)
196#define CLOCK_CDEX_LED1 (1 << 7)
197#define CLOCK_CDEX_LED2 (1 << 8)
198
199/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
200#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
201#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
202#define CLOCK_CDEX_SMBUS (1 << 11)
203#define CLOCK_CDEX_CONTROL_CX (1 << 12)
204
205#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
206#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
207
208#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
209#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
210
211/* R/W: INT clock source control (32.768 kHz) */
212#define CLOCK_SEL_CX (1 << 2)
213
214
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200215#define ASIC3_INTR_BASE 0x0B00
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800216
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200217#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
218#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
219#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
220#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800221
222#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
223#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
224#define ASIC3_INTMASK_MASK0 (1 << 2)
225#define ASIC3_INTMASK_MASK1 (1 << 3)
226#define ASIC3_INTMASK_MASK2 (1 << 4)
227#define ASIC3_INTMASK_MASK3 (1 << 5)
228#define ASIC3_INTMASK_MASK4 (1 << 6)
229#define ASIC3_INTMASK_MASK5 (1 << 7)
230
231#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
232#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
233#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
234#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
235#define ASIC3_INTR_LED0 (1 << 4)
236#define ASIC3_INTR_LED1 (1 << 5)
237#define ASIC3_INTR_LED2 (1 << 6)
238#define ASIC3_INTR_SPI (1 << 7)
239#define ASIC3_INTR_SMBUS (1 << 8)
240#define ASIC3_INTR_OWM (1 << 9)
241
242#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
243#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
244
245
246/* Basic control of the SD ASIC */
Philipp Zabel6483c1b2009-06-05 18:31:01 +0200247#define ASIC3_SDHWCTRL_BASE 0x0E00
248#define ASIC3_SDHWCTRL_SDCONF 0x00
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800249
250#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
251#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
252#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
253#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
254
255/* SD card write protection: 0=high */
256#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
257#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
258
259/* SD card power supply ctrl 1=enable */
260#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
261
Philipp Zabel6483c1b2009-06-05 18:31:01 +0200262#define ASIC3_EXTCF_BASE 0x1100
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800263
Philipp Zabel6483c1b2009-06-05 18:31:01 +0200264#define ASIC3_EXTCF_SELECT 0x00
265#define ASIC3_EXTCF_RESET 0x04
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800266
267#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
268#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
269#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
270#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
271#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
272#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
273#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
274#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
275#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
276#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
277#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
278#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
279#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
280#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
281
282/*********************************************
Philipp Zabel279cac42008-07-10 02:16:27 +0200283 * The Onewire interface (DS1WM) is handled
284 * by the ds1wm driver.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800285 *
286 *********************************************/
287
Philipp Zabel279cac42008-07-10 02:16:27 +0200288#define ASIC3_OWM_BASE 0xC00
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800289
290/*****************************************************************************
291 * The SD configuration registers are at a completely different location
292 * in memory. They are divided into three sets of registers:
293 *
294 * SD_CONFIG Core configuration register
295 * SD_CTRL Control registers for SD operations
296 * SDIO_CTRL Control registers for SDIO operations
297 *
298 *****************************************************************************/
Philipp Zabel1b890402009-06-05 18:31:05 +0200299#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
Paul Parsons74e32d12011-05-15 14:13:11 +0000300#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */
Philipp Zabel1b890402009-06-05 18:31:05 +0200301#define ASIC3_SD_CTRL_BASE 0x1000
302#define ASIC3_SDIO_CTRL_BASE 0x1200
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800303
Philipp Zabel99cdb0c2008-07-10 02:17:02 +0200304#define ASIC3_MAP_SIZE_32BIT 0x2000
305#define ASIC3_MAP_SIZE_16BIT 0x1000
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800306
Paul Parsons7d9e7e92011-05-13 18:52:56 +0000307/* Functions needed by leds-asic3 */
308
309struct asic3;
310extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
311extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
312
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800313#endif /* __ASIC3_H__ */