blob: ebf51ad1b71478f08532edcdda8b3acf9d711bb7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
Chris Wright6faf17f2009-08-28 13:00:06 -070028#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Yinghai Lu568ddef2010-01-22 01:02:21 -080030struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
Ram Paic8adf9a2011-02-14 17:43:20 -080036 resource_size_t add_size;
Yinghai Lu568ddef2010-01-22 01:02:21 -080037 unsigned long flags;
38};
39
Ram Pai094732a2011-02-14 17:43:18 -080040#define free_list(type, head) do { \
41 struct type *list, *tmp; \
42 for (list = (head)->next; list;) { \
43 tmp = list; \
44 list = list->next; \
45 kfree(tmp); \
46 } \
47 (head)->next = NULL; \
48} while (0)
49
Ram Paic8adf9a2011-02-14 17:43:20 -080050/**
51 * add_to_list() - add a new resource tracker to the list
52 * @head: Head of the list
53 * @dev: device corresponding to which the resource
54 * belongs
55 * @res: The resource to be tracked
56 * @add_size: additional size to be optionally added
57 * to the resource
58 */
59static void add_to_list(struct resource_list_x *head,
60 struct pci_dev *dev, struct resource *res,
61 resource_size_t add_size)
Yinghai Lu568ddef2010-01-22 01:02:21 -080062{
63 struct resource_list_x *list = head;
64 struct resource_list_x *ln = list->next;
65 struct resource_list_x *tmp;
66
67 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
68 if (!tmp) {
Ram Paic8adf9a2011-02-14 17:43:20 -080069 pr_warning("add_to_list: kmalloc() failed!\n");
Yinghai Lu568ddef2010-01-22 01:02:21 -080070 return;
71 }
72
73 tmp->next = ln;
74 tmp->res = res;
75 tmp->dev = dev;
76 tmp->start = res->start;
77 tmp->end = res->end;
78 tmp->flags = res->flags;
Ram Paic8adf9a2011-02-14 17:43:20 -080079 tmp->add_size = add_size;
Yinghai Lu568ddef2010-01-22 01:02:21 -080080 list->next = tmp;
81}
82
Ram Paic8adf9a2011-02-14 17:43:20 -080083static void add_to_failed_list(struct resource_list_x *head,
84 struct pci_dev *dev, struct resource *res)
85{
86 add_to_list(head, dev, res, 0);
87}
88
Yinghai Lu6841ec62010-01-22 01:02:25 -080089static void __dev_sort_resources(struct pci_dev *dev,
90 struct resource_list *head)
Linus Torvalds1da177e2005-04-16 15:20:36 -070091{
Yinghai Lu6841ec62010-01-22 01:02:25 -080092 u16 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
Yinghai Lu6841ec62010-01-22 01:02:25 -080094 /* Don't touch classless devices or host bridges or ioapics. */
95 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
96 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -070097
Yinghai Lu6841ec62010-01-22 01:02:25 -080098 /* Don't touch ioapic devices already enabled by firmware */
99 if (class == PCI_CLASS_SYSTEM_PIC) {
100 u16 command;
101 pci_read_config_word(dev, PCI_COMMAND, &command);
102 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
103 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 }
105
Yinghai Lu6841ec62010-01-22 01:02:25 -0800106 pdev_sort_resources(dev, head);
107}
108
Ram Paifc075e12011-02-14 17:43:19 -0800109static inline void reset_resource(struct resource *res)
110{
111 res->start = 0;
112 res->end = 0;
113 res->flags = 0;
114}
115
Ram Paic8adf9a2011-02-14 17:43:20 -0800116/**
117 * adjust_resources_sorted() - satisfy any additional resource requests
118 *
119 * @add_head : head of the list tracking requests requiring additional
120 * resources
121 * @head : head of the list tracking requests with allocated
122 * resources
123 *
124 * Walk through each element of the add_head and try to procure
125 * additional resources for the element, provided the element
126 * is in the head list.
127 */
128static void adjust_resources_sorted(struct resource_list_x *add_head,
129 struct resource_list *head)
130{
131 struct resource *res;
132 struct resource_list_x *list, *tmp, *prev;
133 struct resource_list *hlist;
134 resource_size_t add_size;
135 int idx;
136
137 prev = add_head;
138 for (list = add_head->next; list;) {
139 res = list->res;
140 /* skip resource that has been reset */
141 if (!res->flags)
142 goto out;
143
144 /* skip this resource if not found in head list */
145 for (hlist = head->next; hlist && hlist->res != res;
146 hlist = hlist->next);
147 if (!hlist) { /* just skip */
148 prev = list;
149 list = list->next;
150 continue;
151 }
152
153 idx = res - &list->dev->resource[0];
154 add_size=list->add_size;
155 if (!resource_size(res) && add_size) {
156 res->end = res->start + add_size - 1;
157 if(pci_assign_resource(list->dev, idx))
158 reset_resource(res);
159 } else if (add_size) {
160 adjust_resource(res, res->start,
161 resource_size(res) + add_size);
162 }
163out:
164 tmp = list;
165 prev->next = list = list->next;
166 kfree(tmp);
167 }
168}
169
170/**
171 * assign_requested_resources_sorted() - satisfy resource requests
172 *
173 * @head : head of the list tracking requests for resources
174 * @failed_list : head of the list tracking requests that could
175 * not be allocated
176 *
177 * Satisfy resource requests of each element in the list. Add
178 * requests that could not satisfied to the failed_list.
179 */
180static void assign_requested_resources_sorted(struct resource_list *head,
Yinghai Lu6841ec62010-01-22 01:02:25 -0800181 struct resource_list_x *fail_head)
182{
183 struct resource *res;
Ram Paic8adf9a2011-02-14 17:43:20 -0800184 struct resource_list *list;
Yinghai Lu6841ec62010-01-22 01:02:25 -0800185 int idx;
186
Ram Paic8adf9a2011-02-14 17:43:20 -0800187 for (list = head->next; list; list = list->next) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 res = list->res;
189 idx = res - &list->dev->resource[0];
Ram Paic8adf9a2011-02-14 17:43:20 -0800190 if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
Yinghai Lu9a928662010-02-28 15:49:39 -0800191 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
192 /*
193 * if the failed res is for ROM BAR, and it will
194 * be enabled later, don't add it to the list
195 */
196 if (!((idx == PCI_ROM_RESOURCE) &&
197 (!(res->flags & IORESOURCE_ROM_ENABLE))))
198 add_to_failed_list(fail_head, list->dev, res);
199 }
Ram Paifc075e12011-02-14 17:43:19 -0800200 reset_resource(res);
Rajesh Shah542df5d2005-04-28 00:25:50 -0700201 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 }
203}
204
Ram Paic8adf9a2011-02-14 17:43:20 -0800205static void __assign_resources_sorted(struct resource_list *head,
206 struct resource_list_x *add_head,
207 struct resource_list_x *fail_head)
208{
209 /* Satisfy the must-have resource requests */
210 assign_requested_resources_sorted(head, fail_head);
211
212 /* Try to satisfy any additional nice-to-have resource
213 requests */
214 if (add_head)
215 adjust_resources_sorted(add_head, head);
216 free_list(resource_list, head);
217}
218
Yinghai Lu6841ec62010-01-22 01:02:25 -0800219static void pdev_assign_resources_sorted(struct pci_dev *dev,
220 struct resource_list_x *fail_head)
221{
222 struct resource_list head;
223
224 head.next = NULL;
225 __dev_sort_resources(dev, &head);
Ram Paic8adf9a2011-02-14 17:43:20 -0800226 __assign_resources_sorted(&head, NULL, fail_head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800227
228}
229
230static void pbus_assign_resources_sorted(const struct pci_bus *bus,
Ram Paic8adf9a2011-02-14 17:43:20 -0800231 struct resource_list_x *add_head,
Yinghai Lu6841ec62010-01-22 01:02:25 -0800232 struct resource_list_x *fail_head)
233{
234 struct pci_dev *dev;
235 struct resource_list head;
236
237 head.next = NULL;
238 list_for_each_entry(dev, &bus->devices, bus_list)
239 __dev_sort_resources(dev, &head);
240
Ram Paic8adf9a2011-02-14 17:43:20 -0800241 __assign_resources_sorted(&head, add_head, fail_head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800242}
243
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700244void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245{
246 struct pci_dev *bridge = bus->self;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600247 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 struct pci_bus_region region;
249
Bjorn Helgaas865df572009-11-04 10:32:57 -0700250 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
251 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600253 res = bus->resource[0];
254 pcibios_resource_to_bus(bridge, &region, res);
255 if (res->flags & IORESOURCE_IO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 /*
257 * The IO resource is allocated a range twice as large as it
258 * would normally need. This allows us to set both IO regs.
259 */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600260 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
262 region.start);
263 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
264 region.end);
265 }
266
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600267 res = bus->resource[1];
268 pcibios_resource_to_bus(bridge, &region, res);
269 if (res->flags & IORESOURCE_IO) {
270 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
272 region.start);
273 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
274 region.end);
275 }
276
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600277 res = bus->resource[2];
278 pcibios_resource_to_bus(bridge, &region, res);
279 if (res->flags & IORESOURCE_MEM) {
280 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
282 region.start);
283 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
284 region.end);
285 }
286
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600287 res = bus->resource[3];
288 pcibios_resource_to_bus(bridge, &region, res);
289 if (res->flags & IORESOURCE_MEM) {
290 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
292 region.start);
293 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
294 region.end);
295 }
296}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700297EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298
299/* Initialize bridges with base/limit values we have collected.
300 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
301 requires that if there is no I/O ports or memory behind the
302 bridge, corresponding range must be turned off by writing base
303 value greater than limit to the bridge's base/limit registers.
304
305 Note: care must be taken when updating I/O base/limit registers
306 of bridges which support 32-bit I/O. This update requires two
307 config space writes, so it's quite possible that an I/O window of
308 the bridge will have some undesirable address (e.g. 0) after the
309 first write. Ditto 64-bit prefetchable MMIO. */
Yinghai Lu7cc59972009-12-22 15:02:21 -0800310static void pci_setup_bridge_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311{
312 struct pci_dev *bridge = bus->self;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600313 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 struct pci_bus_region region;
Yinghai Lu7cc59972009-12-22 15:02:21 -0800315 u32 l, io_upper16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316
317 /* Set up the top and bottom of the PCI I/O segment for this bus. */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600318 res = bus->resource[0];
319 pcibios_resource_to_bus(bridge, &region, res);
320 if (res->flags & IORESOURCE_IO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
322 l &= 0xffff0000;
323 l |= (region.start >> 8) & 0x00f0;
324 l |= region.end & 0xf000;
325 /* Set up upper 16 bits of I/O base/limit. */
326 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600327 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800328 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 /* Clear upper 16 bits of I/O base/limit. */
330 io_upper16 = 0;
331 l = 0x00f0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600332 dev_info(&bridge->dev, " bridge window [io disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 }
334 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
335 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
336 /* Update lower 16 bits of I/O base/limit. */
337 pci_write_config_dword(bridge, PCI_IO_BASE, l);
338 /* Update upper 16 bits of I/O base/limit. */
339 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800340}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341
Yinghai Lu7cc59972009-12-22 15:02:21 -0800342static void pci_setup_bridge_mmio(struct pci_bus *bus)
343{
344 struct pci_dev *bridge = bus->self;
345 struct resource *res;
346 struct pci_bus_region region;
347 u32 l;
348
349 /* Set up the top and bottom of the PCI Memory segment for this bus. */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600350 res = bus->resource[1];
351 pcibios_resource_to_bus(bridge, &region, res);
352 if (res->flags & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 l = (region.start >> 16) & 0xfff0;
354 l |= region.end & 0xfff00000;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600355 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800356 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 l = 0x0000fff0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600358 dev_info(&bridge->dev, " bridge window [mem disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 }
360 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800361}
362
363static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
364{
365 struct pci_dev *bridge = bus->self;
366 struct resource *res;
367 struct pci_bus_region region;
368 u32 l, bu, lu;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
370 /* Clear out the upper 32 bits of PREF limit.
371 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
372 disables PREF range, which is ok. */
373 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
374
375 /* Set up PREF base/limit. */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100376 bu = lu = 0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600377 res = bus->resource[2];
378 pcibios_resource_to_bus(bridge, &region, res);
379 if (res->flags & IORESOURCE_PREFETCH) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 l = (region.start >> 16) & 0xfff0;
381 l |= region.end & 0xfff00000;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600382 if (res->flags & IORESOURCE_MEM_64) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700383 bu = upper_32_bits(region.start);
384 lu = upper_32_bits(region.end);
Yinghai Lu1f82de12009-04-23 20:48:32 -0700385 }
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600386 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800387 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 l = 0x0000fff0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600389 dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390 }
391 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
392
Alex Williamson59353ea2009-11-30 14:51:44 -0700393 /* Set the upper 32 bits of PREF base & limit. */
394 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
395 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800396}
397
398static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
399{
400 struct pci_dev *bridge = bus->self;
401
Yinghai Lu7cc59972009-12-22 15:02:21 -0800402 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
403 bus->secondary, bus->subordinate);
404
405 if (type & IORESOURCE_IO)
406 pci_setup_bridge_io(bus);
407
408 if (type & IORESOURCE_MEM)
409 pci_setup_bridge_mmio(bus);
410
411 if (type & IORESOURCE_PREFETCH)
412 pci_setup_bridge_mmio_pref(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
414 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
415}
416
Yinghai Lu7cc59972009-12-22 15:02:21 -0800417static void pci_setup_bridge(struct pci_bus *bus)
418{
419 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
420 IORESOURCE_PREFETCH;
421
422 __pci_setup_bridge(bus, type);
423}
424
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425/* Check whether the bridge supports optional I/O and
426 prefetchable memory ranges. If not, the respective
427 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800428static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429{
430 u16 io;
431 u32 pmem;
432 struct pci_dev *bridge = bus->self;
433 struct resource *b_res;
434
435 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
436 b_res[1].flags |= IORESOURCE_MEM;
437
438 pci_read_config_word(bridge, PCI_IO_BASE, &io);
439 if (!io) {
440 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
441 pci_read_config_word(bridge, PCI_IO_BASE, &io);
442 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
443 }
444 if (io)
445 b_res[0].flags |= IORESOURCE_IO;
446 /* DECchip 21050 pass 2 errata: the bridge may miss an address
447 disconnect boundary by one PCI data phase.
448 Workaround: do not use prefetching on this device. */
449 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
450 return;
451 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
452 if (!pmem) {
453 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
454 0xfff0fff0);
455 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
456 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
457 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700458 if (pmem) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
Yinghai Lu99586102010-01-22 01:02:28 -0800460 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
461 PCI_PREF_RANGE_TYPE_64) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700462 b_res[2].flags |= IORESOURCE_MEM_64;
Yinghai Lu99586102010-01-22 01:02:28 -0800463 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
464 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700465 }
466
467 /* double check if bridge does support 64 bit pref */
468 if (b_res[2].flags & IORESOURCE_MEM_64) {
469 u32 mem_base_hi, tmp;
470 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
471 &mem_base_hi);
472 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
473 0xffffffff);
474 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
475 if (!tmp)
476 b_res[2].flags &= ~IORESOURCE_MEM_64;
477 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
478 mem_base_hi);
479 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480}
481
482/* Helper function for sizing routines: find first available
483 bus resource of a given type. Note: we intentionally skip
484 the bus resources which have already been assigned (that is,
485 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800486static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487{
488 int i;
489 struct resource *r;
490 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
491 IORESOURCE_PREFETCH;
492
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700493 pci_bus_for_each_resource(bus, r, i) {
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400494 if (r == &ioport_resource || r == &iomem_resource)
495 continue;
Jesse Barnes55a10982009-10-27 09:39:18 -0700496 if (r && (r->flags & type_mask) == type && !r->parent)
497 return r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498 }
499 return NULL;
500}
501
Ram Pai13583b12011-02-14 17:43:17 -0800502static resource_size_t calculate_iosize(resource_size_t size,
503 resource_size_t min_size,
504 resource_size_t size1,
505 resource_size_t old_size,
506 resource_size_t align)
507{
508 if (size < min_size)
509 size = min_size;
510 if (old_size == 1 )
511 old_size = 0;
512 /* To be fixed in 2.5: we should have sort of HAVE_ISA
513 flag in the struct pci_bus. */
514#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
515 size = (size & 0xff) + ((size & ~0xffUL) << 2);
516#endif
517 size = ALIGN(size + size1, align);
518 if (size < old_size)
519 size = old_size;
520 return size;
521}
522
523static resource_size_t calculate_memsize(resource_size_t size,
524 resource_size_t min_size,
525 resource_size_t size1,
526 resource_size_t old_size,
527 resource_size_t align)
528{
529 if (size < min_size)
530 size = min_size;
531 if (old_size == 1 )
532 old_size = 0;
533 if (size < old_size)
534 size = old_size;
535 size = ALIGN(size + size1, align);
536 return size;
537}
538
Ram Paic8adf9a2011-02-14 17:43:20 -0800539/**
540 * pbus_size_io() - size the io window of a given bus
541 *
542 * @bus : the bus
543 * @min_size : the minimum io window that must to be allocated
544 * @add_size : additional optional io window
545 * @add_head : track the additional io window on this list
546 *
547 * Sizing the IO windows of the PCI-PCI bridge is trivial,
548 * since these windows have 4K granularity and the IO ranges
549 * of non-bridge PCI devices are limited to 256 bytes.
550 * We must be careful with the ISA aliasing though.
551 */
552static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
553 resource_size_t add_size, struct resource_list_x *add_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554{
555 struct pci_dev *dev;
556 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
Ram Paic8adf9a2011-02-14 17:43:20 -0800557 unsigned long size = 0, size0 = 0, size1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558
559 if (!b_res)
560 return;
561
562 list_for_each_entry(dev, &bus->devices, bus_list) {
563 int i;
564
565 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
566 struct resource *r = &dev->resource[i];
567 unsigned long r_size;
568
569 if (r->parent || !(r->flags & IORESOURCE_IO))
570 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800571 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572
573 if (r_size < 0x400)
574 /* Might be re-aligned for ISA */
575 size += r_size;
576 else
577 size1 += r_size;
578 }
579 }
Ram Paic8adf9a2011-02-14 17:43:20 -0800580 size0 = calculate_iosize(size, min_size, size1,
Ram Pai13583b12011-02-14 17:43:17 -0800581 resource_size(b_res), 4096);
Ram Paic8adf9a2011-02-14 17:43:20 -0800582 size1 = !add_size? size0:
583 calculate_iosize(size, min_size+add_size, size1,
584 resource_size(b_res), 4096);
585 if (!size0 && !size1) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700586 if (b_res->start || b_res->end)
587 dev_info(&bus->self->dev, "disabling bridge window "
588 "%pR to [bus %02x-%02x] (unused)\n", b_res,
589 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 b_res->flags = 0;
591 return;
592 }
593 /* Alignment of the IO window is always 4K */
594 b_res->start = 4096;
Ram Paic8adf9a2011-02-14 17:43:20 -0800595 b_res->end = b_res->start + size0 - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400596 b_res->flags |= IORESOURCE_STARTALIGN;
Ram Paic8adf9a2011-02-14 17:43:20 -0800597 if (size1 > size0 && add_head)
598 add_to_list(add_head, bus->self, b_res, size1-size0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599}
600
Ram Paic8adf9a2011-02-14 17:43:20 -0800601/**
602 * pbus_size_mem() - size the memory window of a given bus
603 *
604 * @bus : the bus
605 * @min_size : the minimum memory window that must to be allocated
606 * @add_size : additional optional memory window
607 * @add_head : track the additional memory window on this list
608 *
609 * Calculate the size of the bus and minimal alignment which
610 * guarantees that all child resources fit in this size.
611 */
Eric W. Biederman28760482009-09-09 14:09:24 -0700612static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
Ram Paic8adf9a2011-02-14 17:43:20 -0800613 unsigned long type, resource_size_t min_size,
614 resource_size_t add_size,
615 struct resource_list_x *add_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616{
617 struct pci_dev *dev;
Ram Paic8adf9a2011-02-14 17:43:20 -0800618 resource_size_t min_align, align, size, size0, size1;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100619 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 int order, max_order;
621 struct resource *b_res = find_free_bus_resource(bus, type);
Yinghai Lu1f82de12009-04-23 20:48:32 -0700622 unsigned int mem64_mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623
624 if (!b_res)
625 return 0;
626
627 memset(aligns, 0, sizeof(aligns));
628 max_order = 0;
629 size = 0;
630
Yinghai Lu1f82de12009-04-23 20:48:32 -0700631 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
632 b_res->flags &= ~IORESOURCE_MEM_64;
633
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 list_for_each_entry(dev, &bus->devices, bus_list) {
635 int i;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700636
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
638 struct resource *r = &dev->resource[i];
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100639 resource_size_t r_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640
641 if (r->parent || (r->flags & mask) != type)
642 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800643 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 /* For bridges size != alignment */
Chris Wright6faf17f2009-08-28 13:00:06 -0700645 align = pci_resource_alignment(dev, r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 order = __ffs(align) - 20;
647 if (order > 11) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700648 dev_warn(&dev->dev, "disabling BAR %d: %pR "
649 "(bad alignment %#llx)\n", i, r,
650 (unsigned long long) align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 r->flags = 0;
652 continue;
653 }
654 size += r_size;
655 if (order < 0)
656 order = 0;
657 /* Exclude ranges with size > align from
658 calculation of the alignment. */
659 if (r_size == align)
660 aligns[order] += align;
661 if (order > max_order)
662 max_order = order;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700663 mem64_mask &= r->flags & IORESOURCE_MEM_64;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 }
665 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 align = 0;
667 min_align = 0;
668 for (order = 0; order <= max_order; order++) {
Jeremy Fitzhardinge8308c542008-09-11 01:31:50 -0700669 resource_size_t align1 = 1;
670
671 align1 <<= (order + 20);
672
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 if (!align)
674 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700675 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 min_align = align1 >> 1;
677 align += aligns[order];
678 }
Linus Torvaldsb42282e2011-04-11 10:53:11 -0700679 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
Ram Paic8adf9a2011-02-14 17:43:20 -0800680 size1 = !add_size ? size :
681 calculate_memsize(size, min_size+add_size, 0,
Linus Torvaldsb42282e2011-04-11 10:53:11 -0700682 resource_size(b_res), min_align);
Ram Paic8adf9a2011-02-14 17:43:20 -0800683 if (!size0 && !size1) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700684 if (b_res->start || b_res->end)
685 dev_info(&bus->self->dev, "disabling bridge window "
686 "%pR to [bus %02x-%02x] (unused)\n", b_res,
687 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 b_res->flags = 0;
689 return 1;
690 }
691 b_res->start = min_align;
Ram Paic8adf9a2011-02-14 17:43:20 -0800692 b_res->end = size0 + min_align - 1;
693 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
694 if (size1 > size0 && add_head)
695 add_to_list(add_head, bus->self, b_res, size1-size0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 return 1;
697}
698
Adrian Bunk5468ae62008-04-18 13:53:56 -0700699static void pci_bus_size_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700{
701 struct pci_dev *bridge = bus->self;
702 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
703 u16 ctrl;
704
705 /*
706 * Reserve some resources for CardBus. We reserve
707 * a fixed amount of bus space for CardBus bridges.
708 */
Linus Torvalds934b7022008-04-22 18:16:30 -0700709 b_res[0].start = 0;
710 b_res[0].end = pci_cardbus_io_size - 1;
711 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712
Linus Torvalds934b7022008-04-22 18:16:30 -0700713 b_res[1].start = 0;
714 b_res[1].end = pci_cardbus_io_size - 1;
715 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
717 /*
718 * Check whether prefetchable memory is supported
719 * by this bridge.
720 */
721 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
722 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
723 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
724 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
725 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
726 }
727
728 /*
729 * If we have prefetchable memory support, allocate
730 * two regions. Otherwise, allocate one region of
731 * twice the size.
732 */
733 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Linus Torvalds934b7022008-04-22 18:16:30 -0700734 b_res[2].start = 0;
735 b_res[2].end = pci_cardbus_mem_size - 1;
736 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737
Linus Torvalds934b7022008-04-22 18:16:30 -0700738 b_res[3].start = 0;
739 b_res[3].end = pci_cardbus_mem_size - 1;
740 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 } else {
Linus Torvalds934b7022008-04-22 18:16:30 -0700742 b_res[3].start = 0;
743 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
744 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 }
746}
747
Ram Paic8adf9a2011-02-14 17:43:20 -0800748void __ref __pci_bus_size_bridges(struct pci_bus *bus,
749 struct resource_list_x *add_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750{
751 struct pci_dev *dev;
752 unsigned long mask, prefmask;
Ram Paic8adf9a2011-02-14 17:43:20 -0800753 resource_size_t additional_mem_size = 0, additional_io_size = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754
755 list_for_each_entry(dev, &bus->devices, bus_list) {
756 struct pci_bus *b = dev->subordinate;
757 if (!b)
758 continue;
759
760 switch (dev->class >> 8) {
761 case PCI_CLASS_BRIDGE_CARDBUS:
762 pci_bus_size_cardbus(b);
763 break;
764
765 case PCI_CLASS_BRIDGE_PCI:
766 default:
Ram Paic8adf9a2011-02-14 17:43:20 -0800767 __pci_bus_size_bridges(b, add_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 break;
769 }
770 }
771
772 /* The root bus? */
773 if (!bus->self)
774 return;
775
776 switch (bus->self->class >> 8) {
777 case PCI_CLASS_BRIDGE_CARDBUS:
778 /* don't size cardbuses yet. */
779 break;
780
781 case PCI_CLASS_BRIDGE_PCI:
782 pci_bridge_check_ranges(bus);
Eric W. Biederman28760482009-09-09 14:09:24 -0700783 if (bus->self->is_hotplug_bridge) {
Ram Paic8adf9a2011-02-14 17:43:20 -0800784 additional_io_size = pci_hotplug_io_size;
785 additional_mem_size = pci_hotplug_mem_size;
Eric W. Biederman28760482009-09-09 14:09:24 -0700786 }
Ram Paic8adf9a2011-02-14 17:43:20 -0800787 /*
788 * Follow thru
789 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 default:
Ram Paic8adf9a2011-02-14 17:43:20 -0800791 pbus_size_io(bus, 0, additional_io_size, add_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 /* If the bridge supports prefetchable range, size it
793 separately. If it doesn't, or its prefetchable window
794 has already been allocated by arch code, try
795 non-prefetchable range for both types of PCI memory
796 resources. */
797 mask = IORESOURCE_MEM;
798 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
Ram Paic8adf9a2011-02-14 17:43:20 -0800799 if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 mask = prefmask; /* Success, size non-prefetch only. */
Eric W. Biederman28760482009-09-09 14:09:24 -0700801 else
Ram Paic8adf9a2011-02-14 17:43:20 -0800802 additional_mem_size += additional_mem_size;
803 pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 break;
805 }
806}
Ram Paic8adf9a2011-02-14 17:43:20 -0800807
808void __ref pci_bus_size_bridges(struct pci_bus *bus)
809{
810 __pci_bus_size_bridges(bus, NULL);
811}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812EXPORT_SYMBOL(pci_bus_size_bridges);
813
Yinghai Lu568ddef2010-01-22 01:02:21 -0800814static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
Ram Paic8adf9a2011-02-14 17:43:20 -0800815 struct resource_list_x *add_head,
Yinghai Lu568ddef2010-01-22 01:02:21 -0800816 struct resource_list_x *fail_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817{
818 struct pci_bus *b;
819 struct pci_dev *dev;
820
Ram Paic8adf9a2011-02-14 17:43:20 -0800821 pbus_assign_resources_sorted(bus, add_head, fail_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823 list_for_each_entry(dev, &bus->devices, bus_list) {
824 b = dev->subordinate;
825 if (!b)
826 continue;
827
Ram Paic8adf9a2011-02-14 17:43:20 -0800828 __pci_bus_assign_resources(b, add_head, fail_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829
830 switch (dev->class >> 8) {
831 case PCI_CLASS_BRIDGE_PCI:
Yinghai Lu6841ec62010-01-22 01:02:25 -0800832 if (!pci_is_enabled(dev))
833 pci_setup_bridge(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 break;
835
836 case PCI_CLASS_BRIDGE_CARDBUS:
837 pci_setup_cardbus(b);
838 break;
839
840 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600841 dev_info(&dev->dev, "not setting up bridge for bus "
842 "%04x:%02x\n", pci_domain_nr(b), b->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 break;
844 }
845 }
846}
Yinghai Lu568ddef2010-01-22 01:02:21 -0800847
848void __ref pci_bus_assign_resources(const struct pci_bus *bus)
849{
Ram Paic8adf9a2011-02-14 17:43:20 -0800850 __pci_bus_assign_resources(bus, NULL, NULL);
Yinghai Lu568ddef2010-01-22 01:02:21 -0800851}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852EXPORT_SYMBOL(pci_bus_assign_resources);
853
Yinghai Lu6841ec62010-01-22 01:02:25 -0800854static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
855 struct resource_list_x *fail_head)
856{
857 struct pci_bus *b;
858
859 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
860
861 b = bridge->subordinate;
862 if (!b)
863 return;
864
Ram Paic8adf9a2011-02-14 17:43:20 -0800865 __pci_bus_assign_resources(b, NULL, fail_head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800866
867 switch (bridge->class >> 8) {
868 case PCI_CLASS_BRIDGE_PCI:
869 pci_setup_bridge(b);
870 break;
871
872 case PCI_CLASS_BRIDGE_CARDBUS:
873 pci_setup_cardbus(b);
874 break;
875
876 default:
877 dev_info(&bridge->dev, "not setting up bridge for bus "
878 "%04x:%02x\n", pci_domain_nr(b), b->number);
879 break;
880 }
881}
Yinghai Lu5009b462010-01-22 01:02:20 -0800882static void pci_bridge_release_resources(struct pci_bus *bus,
883 unsigned long type)
884{
885 int idx;
886 bool changed = false;
887 struct pci_dev *dev;
888 struct resource *r;
889 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
890 IORESOURCE_PREFETCH;
891
892 dev = bus->self;
893 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
894 idx++) {
895 r = &dev->resource[idx];
896 if ((r->flags & type_mask) != type)
897 continue;
898 if (!r->parent)
899 continue;
900 /*
901 * if there are children under that, we should release them
902 * all
903 */
904 release_child_resources(r);
905 if (!release_resource(r)) {
906 dev_printk(KERN_DEBUG, &dev->dev,
907 "resource %d %pR released\n", idx, r);
908 /* keep the old size */
909 r->end = resource_size(r) - 1;
910 r->start = 0;
911 r->flags = 0;
912 changed = true;
913 }
914 }
915
916 if (changed) {
917 /* avoiding touch the one without PREF */
918 if (type & IORESOURCE_PREFETCH)
919 type = IORESOURCE_PREFETCH;
920 __pci_setup_bridge(bus, type);
921 }
922}
923
924enum release_type {
925 leaf_only,
926 whole_subtree,
927};
928/*
929 * try to release pci bridge resources that is from leaf bridge,
930 * so we can allocate big new one later
931 */
932static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
933 unsigned long type,
934 enum release_type rel_type)
935{
936 struct pci_dev *dev;
937 bool is_leaf_bridge = true;
938
939 list_for_each_entry(dev, &bus->devices, bus_list) {
940 struct pci_bus *b = dev->subordinate;
941 if (!b)
942 continue;
943
944 is_leaf_bridge = false;
945
946 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
947 continue;
948
949 if (rel_type == whole_subtree)
950 pci_bus_release_bridge_resources(b, type,
951 whole_subtree);
952 }
953
954 if (pci_is_root_bus(bus))
955 return;
956
957 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
958 return;
959
960 if ((rel_type == whole_subtree) || is_leaf_bridge)
961 pci_bridge_release_resources(bus, type);
962}
963
Yinghai Lu76fbc262008-06-23 20:33:06 +0200964static void pci_bus_dump_res(struct pci_bus *bus)
965{
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700966 struct resource *res;
967 int i;
Yinghai Lu76fbc262008-06-23 20:33:06 +0200968
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700969 pci_bus_for_each_resource(bus, res, i) {
Yinghai Lu7c9342b2009-12-22 15:02:24 -0800970 if (!res || !res->end || !res->flags)
Yinghai Lu76fbc262008-06-23 20:33:06 +0200971 continue;
972
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600973 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
Yinghai Lu76fbc262008-06-23 20:33:06 +0200974 }
975}
976
977static void pci_bus_dump_resources(struct pci_bus *bus)
978{
979 struct pci_bus *b;
980 struct pci_dev *dev;
981
982
983 pci_bus_dump_res(bus);
984
985 list_for_each_entry(dev, &bus->devices, bus_list) {
986 b = dev->subordinate;
987 if (!b)
988 continue;
989
990 pci_bus_dump_resources(b);
991 }
992}
993
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994void __init
995pci_assign_unassigned_resources(void)
996{
997 struct pci_bus *bus;
Ram Paic8adf9a2011-02-14 17:43:20 -0800998 struct resource_list_x add_list; /* list of resources that
999 want additional resources */
1000 add_list.next = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001 /* Depth first, calculate sizes and alignments of all
1002 subordinate buses. */
1003 list_for_each_entry(bus, &pci_root_buses, node) {
Ram Paic8adf9a2011-02-14 17:43:20 -08001004 __pci_bus_size_bridges(bus, &add_list);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 }
Ram Paic8adf9a2011-02-14 17:43:20 -08001006
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007 /* Depth last, allocate resources and update the hardware. */
1008 list_for_each_entry(bus, &pci_root_buses, node) {
Ram Paic8adf9a2011-02-14 17:43:20 -08001009 __pci_bus_assign_resources(bus, &add_list, NULL);
Yinghai Lu977d17b2010-01-22 01:02:24 -08001010 pci_enable_bridges(bus);
Linus Torvalds769d9962010-05-12 18:39:45 -07001011 }
Ram Paic8adf9a2011-02-14 17:43:20 -08001012 BUG_ON(add_list.next);
Yinghai Lu76fbc262008-06-23 20:33:06 +02001013
1014 /* dump the resource on buses */
1015 list_for_each_entry(bus, &pci_root_buses, node) {
1016 pci_bus_dump_resources(bus);
1017 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018}
Yinghai Lu6841ec62010-01-22 01:02:25 -08001019
1020void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1021{
1022 struct pci_bus *parent = bridge->subordinate;
Yinghai Lu32180e42010-01-22 01:02:27 -08001023 int tried_times = 0;
1024 struct resource_list_x head, *list;
Yinghai Lu6841ec62010-01-22 01:02:25 -08001025 int retval;
Yinghai Lu32180e42010-01-22 01:02:27 -08001026 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1027 IORESOURCE_PREFETCH;
Yinghai Lu6841ec62010-01-22 01:02:25 -08001028
Yinghai Lu32180e42010-01-22 01:02:27 -08001029 head.next = NULL;
1030
1031again:
Yinghai Lu6841ec62010-01-22 01:02:25 -08001032 pci_bus_size_bridges(parent);
Yinghai Lu32180e42010-01-22 01:02:27 -08001033 __pci_bridge_assign_resources(bridge, &head);
Yinghai Lu32180e42010-01-22 01:02:27 -08001034
1035 tried_times++;
1036
1037 if (!head.next)
Yinghai Lu3f579c32010-05-21 14:35:06 -07001038 goto enable_all;
Yinghai Lu32180e42010-01-22 01:02:27 -08001039
1040 if (tried_times >= 2) {
1041 /* still fail, don't need to try more */
Ram Pai094732a2011-02-14 17:43:18 -08001042 free_list(resource_list_x, &head);
Yinghai Lu3f579c32010-05-21 14:35:06 -07001043 goto enable_all;
Yinghai Lu32180e42010-01-22 01:02:27 -08001044 }
1045
1046 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1047 tried_times + 1);
1048
1049 /*
1050 * Try to release leaf bridge's resources that doesn't fit resource of
1051 * child device under that bridge
1052 */
1053 for (list = head.next; list;) {
1054 struct pci_bus *bus = list->dev->bus;
1055 unsigned long flags = list->flags;
1056
1057 pci_bus_release_bridge_resources(bus, flags & type_mask,
1058 whole_subtree);
1059 list = list->next;
1060 }
1061 /* restore size and flags */
1062 for (list = head.next; list;) {
1063 struct resource *res = list->res;
1064
1065 res->start = list->start;
1066 res->end = list->end;
1067 res->flags = list->flags;
1068 if (list->dev->subordinate)
1069 res->flags = 0;
1070
1071 list = list->next;
1072 }
Ram Pai094732a2011-02-14 17:43:18 -08001073 free_list(resource_list_x, &head);
Yinghai Lu32180e42010-01-22 01:02:27 -08001074
1075 goto again;
Yinghai Lu3f579c32010-05-21 14:35:06 -07001076
1077enable_all:
1078 retval = pci_reenable_device(bridge);
1079 pci_set_master(bridge);
1080 pci_enable_bridges(parent);
Yinghai Lu6841ec62010-01-22 01:02:25 -08001081}
1082EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);