blob: 7a84f04e8439c1ea2f68acce4520f0d4665490f7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Jesse Barnes585fb112008-07-29 11:54:06 -070033#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_bios.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070035#include <linux/io-mapping.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070036
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/* General customization:
38 */
39
40#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42#define DRIVER_NAME "i915"
43#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070044#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
Jesse Barnes317c35d2008-08-25 15:11:06 -070046enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49};
50
Keith Packard52440212008-11-18 09:30:25 -080051#define I915_NUM_PIPE 2
52
Linus Torvalds1da177e2005-04-16 15:20:36 -070053/* Interface history:
54 *
55 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110056 * 1.2: Add Power Management
57 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110058 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100059 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100060 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 */
63#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100064#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070065#define DRIVER_PATCHLEVEL 0
66
Eric Anholt673a3942008-07-30 12:06:12 -070067#define WATCH_COHERENCY 0
68#define WATCH_BUF 0
69#define WATCH_EXEC 0
70#define WATCH_LRU 0
71#define WATCH_RELOC 0
72#define WATCH_INACTIVE 0
73#define WATCH_PWRITE 0
74
Dave Airlie71acb5e2008-12-30 20:31:46 +100075#define I915_GEM_PHYS_CURSOR_0 1
76#define I915_GEM_PHYS_CURSOR_1 2
77#define I915_GEM_PHYS_OVERLAY_REGS 3
78#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
79
80struct drm_i915_gem_phys_object {
81 int id;
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
85};
86
Linus Torvalds1da177e2005-04-16 15:20:36 -070087typedef struct _drm_i915_ring_buffer {
88 int tail_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 unsigned long Size;
90 u8 *virtual_start;
91 int head;
92 int tail;
93 int space;
94 drm_local_map_t map;
Eric Anholt673a3942008-07-30 12:06:12 -070095 struct drm_gem_object *ring_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096} drm_i915_ring_buffer_t;
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104};
105
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100111struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 int enabled;
117};
118
Dave Airlie7c1c2872008-11-28 14:22:24 +1000119struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
122};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800123#define I915_FENCE_REG_NONE -1
124
125struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
127};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000128
yakui_zhao9b9d1722009-05-31 17:17:17 +0800129struct sdvo_device_mapping {
130 u8 dvo_port;
131 u8 slave_addr;
132 u8 dvo_wiring;
133 u8 initialized;
134};
135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136typedef struct drm_i915_private {
Eric Anholt673a3942008-07-30 12:06:12 -0700137 struct drm_device *dev;
138
Dave Airlieac5c4e72008-12-19 15:38:34 +1000139 int has_gem;
140
Eric Anholt3043c602008-10-02 12:24:47 -0700141 void __iomem *regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 drm_i915_ring_buffer_t ring;
144
Dave Airlie9c8da5e2005-07-10 15:38:56 +1000145 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 dma_addr_t dma_status_page;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700148 uint32_t counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000149 unsigned int status_gfx_addr;
150 drm_local_map_t hws_map;
Eric Anholt673a3942008-07-30 12:06:12 -0700151 struct drm_gem_object *hws_obj;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152
Jesse Barnesd7658982009-06-05 14:41:29 +0000153 struct resource mch_res;
154
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000155 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 int back_offset;
157 int front_offset;
158 int current_page;
159 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160
161 wait_queue_head_t irq_queue;
162 atomic_t irq_received;
Eric Anholted4cb412008-07-29 12:10:39 -0700163 /** Protects user_irq_refcount and irq_mask_reg */
164 spinlock_t user_irq_lock;
165 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
166 int user_irq_refcount;
167 /** Cached value of IMR to avoid reads in updating the bitfield */
168 u32 irq_mask_reg;
Keith Packard7c463582008-11-04 02:03:27 -0800169 u32 pipestat[2];
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800170 /** splitted irq regs for graphics and display engine on IGDNG,
171 irq_mask_reg is still used for display irq. */
172 u32 gt_irq_mask_reg;
173 u32 gt_irq_enable_reg;
174 u32 de_irq_enable_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175
Jesse Barnes5ca58282009-03-31 14:11:15 -0700176 u32 hotplug_supported_mask;
177 struct work_struct hotplug_work;
178
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 int tex_lru_log_granularity;
180 int allow_batchbuffer;
181 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100182 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000183 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000184
Jesse Barnes79e53942008-11-07 14:24:08 -0800185 bool cursor_needs_physical;
186
187 struct drm_mm vram;
188
189 int irq_enabled;
190
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100191 struct intel_opregion opregion;
192
Jesse Barnes79e53942008-11-07 14:24:08 -0800193 /* LVDS info */
194 int backlight_duty_cycle; /* restore backlight to this value */
195 bool panel_wants_dither;
196 struct drm_display_mode *panel_fixed_mode;
Ma Ling88631702009-05-13 11:19:55 +0800197 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
198 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
Jesse Barnes79e53942008-11-07 14:24:08 -0800199
200 /* Feature bits from the VBIOS */
Hannes Eder95281e32008-12-18 15:09:00 +0100201 unsigned int int_tv_support:1;
202 unsigned int lvds_dither:1;
203 unsigned int lvds_vbt:1;
204 unsigned int int_crt_support:1;
Kristian Høgsberg43565a02009-02-13 20:56:52 -0500205 unsigned int lvds_use_ssc:1;
206 int lvds_ssc_freq;
Jesse Barnes79e53942008-11-07 14:24:08 -0800207
Jesse Barnesde151cf2008-11-12 10:03:55 -0800208 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
209 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
210 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
211
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000212 /* Register state */
213 u8 saveLBB;
214 u32 saveDSPACNTR;
215 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000216 u32 saveDSPARB;
Keith Packard881ee982008-11-02 23:08:44 -0800217 u32 saveRENDERSTANDBY;
Peng Li461cba22008-11-18 12:39:02 +0800218 u32 saveHWS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000219 u32 savePIPEACONF;
220 u32 savePIPEBCONF;
221 u32 savePIPEASRC;
222 u32 savePIPEBSRC;
223 u32 saveFPA0;
224 u32 saveFPA1;
225 u32 saveDPLL_A;
226 u32 saveDPLL_A_MD;
227 u32 saveHTOTAL_A;
228 u32 saveHBLANK_A;
229 u32 saveHSYNC_A;
230 u32 saveVTOTAL_A;
231 u32 saveVBLANK_A;
232 u32 saveVSYNC_A;
233 u32 saveBCLRPAT_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000234 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000235 u32 saveDSPASTRIDE;
236 u32 saveDSPASIZE;
237 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700238 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000239 u32 saveDSPASURF;
240 u32 saveDSPATILEOFF;
241 u32 savePFIT_PGM_RATIOS;
242 u32 saveBLC_PWM_CTL;
243 u32 saveBLC_PWM_CTL2;
244 u32 saveFPB0;
245 u32 saveFPB1;
246 u32 saveDPLL_B;
247 u32 saveDPLL_B_MD;
248 u32 saveHTOTAL_B;
249 u32 saveHBLANK_B;
250 u32 saveHSYNC_B;
251 u32 saveVTOTAL_B;
252 u32 saveVBLANK_B;
253 u32 saveVSYNC_B;
254 u32 saveBCLRPAT_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000255 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000256 u32 saveDSPBSTRIDE;
257 u32 saveDSPBSIZE;
258 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700259 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000260 u32 saveDSPBSURF;
261 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700262 u32 saveVGA0;
263 u32 saveVGA1;
264 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000265 u32 saveVGACNTRL;
266 u32 saveADPA;
267 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700268 u32 savePP_ON_DELAYS;
269 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000270 u32 saveDVOA;
271 u32 saveDVOB;
272 u32 saveDVOC;
273 u32 savePP_ON;
274 u32 savePP_OFF;
275 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700276 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000277 u32 savePFIT_CONTROL;
278 u32 save_palette_a[256];
279 u32 save_palette_b[256];
280 u32 saveFBC_CFB_BASE;
281 u32 saveFBC_LL_BASE;
282 u32 saveFBC_CONTROL;
283 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000284 u32 saveIER;
285 u32 saveIIR;
286 u32 saveIMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800287 u32 saveCACHE_MODE_0;
Keith Packarde948e992008-05-07 12:27:53 +1000288 u32 saveD_STATE;
Jesse Barnes585fb112008-07-29 11:54:06 -0700289 u32 saveCG_2D_DIS;
Keith Packard1f84e552008-02-16 19:19:29 -0800290 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000291 u32 saveSWF0[16];
292 u32 saveSWF1[16];
293 u32 saveSWF2[3];
294 u8 saveMSR;
295 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800296 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000297 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000298 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000299 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000300 u8 saveCR[37];
Keith Packard79f11c12009-04-30 14:43:44 -0700301 uint64_t saveFENCE[16];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000302 u32 saveCURACNTR;
303 u32 saveCURAPOS;
304 u32 saveCURABASE;
305 u32 saveCURBCNTR;
306 u32 saveCURBPOS;
307 u32 saveCURBBASE;
308 u32 saveCURSIZE;
Eric Anholt673a3942008-07-30 12:06:12 -0700309
310 struct {
311 struct drm_mm gtt_space;
312
Keith Packard0839ccb2008-10-30 19:38:48 -0700313 struct io_mapping *gtt_mapping;
Eric Anholtab657db12009-01-23 12:57:47 -0800314 int gtt_mtrr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700315
Eric Anholt673a3942008-07-30 12:06:12 -0700316 /**
317 * List of objects currently involved in rendering from the
318 * ringbuffer.
319 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800320 * Includes buffers having the contents of their GPU caches
321 * flushed, not necessarily primitives. last_rendering_seqno
322 * represents when the rendering involved will be completed.
323 *
Eric Anholt673a3942008-07-30 12:06:12 -0700324 * A reference is held on the buffer while on this list.
325 */
Carl Worth5e118f42009-03-20 11:54:25 -0700326 spinlock_t active_list_lock;
Eric Anholt673a3942008-07-30 12:06:12 -0700327 struct list_head active_list;
328
329 /**
330 * List of objects which are not in the ringbuffer but which
331 * still have a write_domain which needs to be flushed before
332 * unbinding.
333 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800334 * last_rendering_seqno is 0 while an object is in this list.
335 *
Eric Anholt673a3942008-07-30 12:06:12 -0700336 * A reference is held on the buffer while on this list.
337 */
338 struct list_head flushing_list;
339
340 /**
341 * LRU list of objects which are not in the ringbuffer and
342 * are ready to unbind, but are still in the GTT.
343 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800344 * last_rendering_seqno is 0 while an object is in this list.
345 *
Eric Anholt673a3942008-07-30 12:06:12 -0700346 * A reference is not held on the buffer while on this list,
347 * as merely being GTT-bound shouldn't prevent its being
348 * freed, and we'll pull it off the list in the free path.
349 */
350 struct list_head inactive_list;
351
352 /**
353 * List of breadcrumbs associated with GPU requests currently
354 * outstanding.
355 */
356 struct list_head request_list;
357
358 /**
359 * We leave the user IRQ off as much as possible,
360 * but this means that requests will finish and never
361 * be retired once the system goes idle. Set a timer to
362 * fire periodically while the ring is running. When it
363 * fires, go retire requests.
364 */
365 struct delayed_work retire_work;
366
367 uint32_t next_gem_seqno;
368
369 /**
370 * Waiting sequence number, if any
371 */
372 uint32_t waiting_gem_seqno;
373
374 /**
375 * Last seq seen at irq time
376 */
377 uint32_t irq_gem_seqno;
378
379 /**
380 * Flag if the X Server, and thus DRM, is not currently in
381 * control of the device.
382 *
383 * This is set between LeaveVT and EnterVT. It needs to be
384 * replaced with a semaphore. It also needs to be
385 * transitioned away from for kernel modesetting.
386 */
387 int suspended;
388
389 /**
390 * Flag if the hardware appears to be wedged.
391 *
392 * This is set when attempts to idle the device timeout.
393 * It prevents command submission from occuring and makes
394 * every pending request fail
395 */
396 int wedged;
397
398 /** Bit 6 swizzling required for X tiling */
399 uint32_t bit_6_swizzle_x;
400 /** Bit 6 swizzling required for Y tiling */
401 uint32_t bit_6_swizzle_y;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000402
403 /* storage for physical objects */
404 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
Eric Anholt673a3942008-07-30 12:06:12 -0700405 } mm;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800406 struct sdvo_device_mapping sdvo_mappings[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407} drm_i915_private_t;
408
Eric Anholt673a3942008-07-30 12:06:12 -0700409/** driver private structure attached to each drm_gem_object */
410struct drm_i915_gem_object {
411 struct drm_gem_object *obj;
412
413 /** Current space allocated to this object in the GTT, if any. */
414 struct drm_mm_node *gtt_space;
415
416 /** This object's place on the active/flushing/inactive lists */
417 struct list_head list;
418
419 /**
420 * This is set if the object is on the active or flushing lists
421 * (has pending rendering), and is not set if it's on inactive (ready
422 * to be unbound).
423 */
424 int active;
425
426 /**
427 * This is set if the object has been written to since last bound
428 * to the GTT
429 */
430 int dirty;
431
432 /** AGP memory structure for our GTT binding. */
433 DRM_AGP_MEM *agp_mem;
434
Eric Anholt856fa192009-03-19 14:10:50 -0700435 struct page **pages;
436 int pages_refcount;
Eric Anholt673a3942008-07-30 12:06:12 -0700437
438 /**
439 * Current offset of the object in GTT space.
440 *
441 * This is the same as gtt_space->start
442 */
443 uint32_t gtt_offset;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800444 /**
445 * Required alignment for the object
446 */
447 uint32_t gtt_alignment;
448 /**
449 * Fake offset for use by mmap(2)
450 */
451 uint64_t mmap_offset;
452
453 /**
454 * Fence register bits (if any) for this object. Will be set
455 * as needed when mapped into the GTT.
456 * Protected by dev->struct_mutex.
457 */
458 int fence_reg;
Eric Anholt673a3942008-07-30 12:06:12 -0700459
460 /** Boolean whether this object has a valid gtt offset. */
461 int gtt_bound;
462
463 /** How many users have pinned this object in GTT space */
464 int pin_count;
465
466 /** Breadcrumb of last rendering to the buffer. */
467 uint32_t last_rendering_seqno;
468
469 /** Current tiling mode for the object. */
470 uint32_t tiling_mode;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800471 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -0700472
Eric Anholt280b7132009-03-12 16:56:27 -0700473 /** Record of address bit 17 of each page at last unbind. */
474 long *bit_17;
475
Keith Packardba1eb1d2008-10-14 19:55:10 -0700476 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
477 uint32_t agp_type;
478
Eric Anholt673a3942008-07-30 12:06:12 -0700479 /**
Eric Anholte47c68e2008-11-14 13:35:19 -0800480 * If present, while GEM_DOMAIN_CPU is in the read domain this array
481 * flags which individual pages are valid.
Eric Anholt673a3942008-07-30 12:06:12 -0700482 */
483 uint8_t *page_cpu_valid;
Jesse Barnes79e53942008-11-07 14:24:08 -0800484
485 /** User space pin count and filp owning the pin */
486 uint32_t user_pin_count;
487 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000488
489 /** for phy allocated objects */
490 struct drm_i915_gem_phys_object *phys_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -0500491
492 /**
493 * Used for checking the object doesn't appear more than once
494 * in an execbuffer object list.
495 */
496 int in_execbuffer;
Eric Anholt673a3942008-07-30 12:06:12 -0700497};
498
499/**
500 * Request queue structure.
501 *
502 * The request queue allows us to note sequence numbers that have been emitted
503 * and may be associated with active buffers to be retired.
504 *
505 * By keeping this list, we can avoid having to do questionable
506 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
507 * an emission time with seqnos for tracking how far ahead of the GPU we are.
508 */
509struct drm_i915_gem_request {
510 /** GEM sequence number associated with this request. */
511 uint32_t seqno;
512
513 /** Time at which this request was emitted, in jiffies. */
514 unsigned long emitted_jiffies;
515
Eric Anholtb9624422009-06-03 07:27:35 +0000516 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -0700517 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +0000518
519 /** file_priv list entry for this request */
520 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700521};
522
523struct drm_i915_file_private {
524 struct {
Eric Anholtb9624422009-06-03 07:27:35 +0000525 struct list_head request_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700526 } mm;
527};
528
Jesse Barnes79e53942008-11-07 14:24:08 -0800529enum intel_chip_family {
530 CHIP_I8XX = 0x01,
531 CHIP_I9XX = 0x02,
532 CHIP_I915 = 0x04,
533 CHIP_I965 = 0x08,
534};
535
Eric Anholtc153f452007-09-03 12:06:45 +1000536extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000537extern int i915_max_ioctl;
Jesse Barnes79e53942008-11-07 14:24:08 -0800538extern unsigned int i915_fbpercrtc;
Dave Airlieb3a83632005-09-30 18:37:36 +1000539
Dave Airlie7c1c2872008-11-28 14:22:24 +1000540extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
541extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
542
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000544extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100545extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000546extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -0700547extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000548extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000549extern void i915_driver_preclose(struct drm_device *dev,
550 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700551extern void i915_driver_postclose(struct drm_device *dev,
552 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000553extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100554extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
555 unsigned long arg);
Eric Anholt673a3942008-07-30 12:06:12 -0700556extern int i915_emit_box(struct drm_device *dev,
Eric Anholt201361a2009-03-11 12:30:04 -0700557 struct drm_clip_rect *boxes,
Eric Anholt673a3942008-07-30 12:06:12 -0700558 int i, int DR1, int DR4);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000559
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560/* i915_irq.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000561extern int i915_irq_emit(struct drm_device *dev, void *data,
562 struct drm_file *file_priv);
563extern int i915_irq_wait(struct drm_device *dev, void *data,
564 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700565void i915_user_irq_get(struct drm_device *dev);
566void i915_user_irq_put(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800567extern void i915_enable_interrupt (struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568
569extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000570extern void i915_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700571extern int i915_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000572extern void i915_driver_irq_uninstall(struct drm_device * dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000573extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
574 struct drm_file *file_priv);
575extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
576 struct drm_file *file_priv);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700577extern int i915_enable_vblank(struct drm_device *dev, int crtc);
578extern void i915_disable_vblank(struct drm_device *dev, int crtc);
579extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800580extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
Eric Anholtc153f452007-09-03 12:06:45 +1000581extern int i915_vblank_swap(struct drm_device *dev, void *data,
582 struct drm_file *file_priv);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100583extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
Keith Packard7c463582008-11-04 02:03:27 -0800585void
586i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
587
588void
589i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
590
591
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592/* i915_mem.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000593extern int i915_mem_alloc(struct drm_device *dev, void *data,
594 struct drm_file *file_priv);
595extern int i915_mem_free(struct drm_device *dev, void *data,
596 struct drm_file *file_priv);
597extern int i915_mem_init_heap(struct drm_device *dev, void *data,
598 struct drm_file *file_priv);
599extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
600 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000602extern void i915_mem_release(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000603 struct drm_file *file_priv, struct mem_block *heap);
Eric Anholt673a3942008-07-30 12:06:12 -0700604/* i915_gem.c */
605int i915_gem_init_ioctl(struct drm_device *dev, void *data,
606 struct drm_file *file_priv);
607int i915_gem_create_ioctl(struct drm_device *dev, void *data,
608 struct drm_file *file_priv);
609int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
610 struct drm_file *file_priv);
611int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
612 struct drm_file *file_priv);
613int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
614 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800615int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
616 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700617int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
618 struct drm_file *file_priv);
619int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
620 struct drm_file *file_priv);
621int i915_gem_execbuffer(struct drm_device *dev, void *data,
622 struct drm_file *file_priv);
623int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
624 struct drm_file *file_priv);
625int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
626 struct drm_file *file_priv);
627int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
628 struct drm_file *file_priv);
629int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
630 struct drm_file *file_priv);
631int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
632 struct drm_file *file_priv);
633int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
634 struct drm_file *file_priv);
635int i915_gem_set_tiling(struct drm_device *dev, void *data,
636 struct drm_file *file_priv);
637int i915_gem_get_tiling(struct drm_device *dev, void *data,
638 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -0700639int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
640 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700641void i915_gem_load(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -0700642int i915_gem_init_object(struct drm_gem_object *obj);
643void i915_gem_free_object(struct drm_gem_object *obj);
644int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
645void i915_gem_object_unpin(struct drm_gem_object *obj);
Jesse Barnes0f973f22009-01-26 17:10:45 -0800646int i915_gem_object_unbind(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700647void i915_gem_lastclose(struct drm_device *dev);
648uint32_t i915_get_gem_seqno(struct drm_device *dev);
Chris Wilson8c4b8c32009-06-17 22:08:52 +0100649int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
Chris Wilson52dc7d32009-06-06 09:46:01 +0100650int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700651void i915_gem_retire_requests(struct drm_device *dev);
652void i915_gem_retire_work_handler(struct work_struct *work);
653void i915_gem_clflush_object(struct drm_gem_object *obj);
Jesse Barnes79e53942008-11-07 14:24:08 -0800654int i915_gem_object_set_domain(struct drm_gem_object *obj,
655 uint32_t read_domains,
656 uint32_t write_domain);
657int i915_gem_init_ringbuffer(struct drm_device *dev);
658void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
659int i915_gem_do_init(struct drm_device *dev, unsigned long start,
660 unsigned long end);
Jesse Barnes5669fca2009-02-17 15:13:31 -0800661int i915_gem_idle(struct drm_device *dev);
Jesse Barnesde151cf2008-11-12 10:03:55 -0800662int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Jesse Barnes79e53942008-11-07 14:24:08 -0800663int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
664 int write);
Dave Airlie71acb5e2008-12-30 20:31:46 +1000665int i915_gem_attach_phys_object(struct drm_device *dev,
666 struct drm_gem_object *obj, int id);
667void i915_gem_detach_phys_object(struct drm_device *dev,
668 struct drm_gem_object *obj);
669void i915_gem_free_all_phys_object(struct drm_device *dev);
Ben Gamari6911a9b2009-04-02 11:24:54 -0700670int i915_gem_object_get_pages(struct drm_gem_object *obj);
671void i915_gem_object_put_pages(struct drm_gem_object *obj);
Eric Anholt1fd1c622009-06-03 07:26:58 +0000672void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700673
674/* i915_gem_tiling.c */
675void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -0700676void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
677void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700678
679/* i915_gem_debug.c */
680void i915_gem_dump_object(struct drm_gem_object *obj, int len,
681 const char *where, uint32_t mark);
682#if WATCH_INACTIVE
683void i915_verify_inactive(struct drm_device *dev, char *file, int line);
684#else
685#define i915_verify_inactive(dev, file, line)
686#endif
687void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
688void i915_gem_dump_object(struct drm_gem_object *obj, int len,
689 const char *where, uint32_t mark);
690void i915_dump_lru(struct drm_device *dev, const char *where);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691
Ben Gamari20172632009-02-17 20:08:50 -0500692/* i915_debugfs.c */
693int i915_gem_debugfs_init(struct drm_minor *minor);
694void i915_gem_debugfs_cleanup(struct drm_minor *minor);
695
Jesse Barnes317c35d2008-08-25 15:11:06 -0700696/* i915_suspend.c */
697extern int i915_save_state(struct drm_device *dev);
698extern int i915_restore_state(struct drm_device *dev);
699
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700700/* i915_suspend.c */
701extern int i915_save_state(struct drm_device *dev);
702extern int i915_restore_state(struct drm_device *dev);
703
Len Brown65e082c2008-10-24 17:18:10 -0400704#ifdef CONFIG_ACPI
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100705/* i915_opregion.c */
Matthew Garrett74a365b2009-03-19 21:35:39 +0000706extern int intel_opregion_init(struct drm_device *dev, int resume);
Matthew Garrett3b1c1c12009-04-01 19:52:29 +0100707extern void intel_opregion_free(struct drm_device *dev, int suspend);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100708extern void opregion_asle_intr(struct drm_device *dev);
709extern void opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -0400710#else
Len Brown03ae61d2009-03-28 01:41:14 -0400711static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
Matthew Garrett3b1c1c12009-04-01 19:52:29 +0100712static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
Len Brown65e082c2008-10-24 17:18:10 -0400713static inline void opregion_asle_intr(struct drm_device *dev) { return; }
714static inline void opregion_enable_asle(struct drm_device *dev) { return; }
715#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100716
Jesse Barnes79e53942008-11-07 14:24:08 -0800717/* modesetting */
718extern void intel_modeset_init(struct drm_device *dev);
719extern void intel_modeset_cleanup(struct drm_device *dev);
720
Eric Anholt546b0972008-09-01 16:45:29 -0700721/**
722 * Lock test for when it's just for synchronization of ring access.
723 *
724 * In that case, we don't need to do it when GEM is initialized as nobody else
725 * has access to the ring.
726 */
727#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
728 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
729 LOCK_TEST_WITH_RETURN(dev, file_priv); \
730} while (0)
731
Eric Anholt3043c602008-10-02 12:24:47 -0700732#define I915_READ(reg) readl(dev_priv->regs + (reg))
733#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
734#define I915_READ16(reg) readw(dev_priv->regs + (reg))
735#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
736#define I915_READ8(reg) readb(dev_priv->regs + (reg))
737#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
Jesse Barnesde151cf2008-11-12 10:03:55 -0800738#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
Keith Packard049ef7e2009-04-30 14:43:43 -0700739#define I915_READ64(reg) readq(dev_priv->regs + (reg))
Eric Anholt7d573822009-01-02 13:33:00 -0800740#define POSTING_READ(reg) (void)I915_READ(reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741
742#define I915_VERBOSE 0
743
744#define RING_LOCALS unsigned int outring, ringmask, outcount; \
745 volatile char *virt;
746
747#define BEGIN_LP_RING(n) do { \
748 if (I915_VERBOSE) \
Márton Németh3e684ea2008-01-24 15:58:57 +1000749 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
750 if (dev_priv->ring.space < (n)*4) \
Harvey Harrisonbf9d8922008-04-30 00:55:10 -0700751 i915_wait_ring(dev, (n)*4, __func__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 outcount = 0; \
753 outring = dev_priv->ring.tail; \
754 ringmask = dev_priv->ring.tail_mask; \
755 virt = dev_priv->ring.virtual_start; \
756} while (0)
757
758#define OUT_RING(n) do { \
759 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000760 *(volatile unsigned int *)(virt + outring) = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 outcount++; \
762 outring += 4; \
763 outring &= ringmask; \
764} while (0)
765
766#define ADVANCE_LP_RING() do { \
767 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
768 dev_priv->ring.tail = outring; \
769 dev_priv->ring.space -= outcount * 4; \
Jesse Barnes585fb112008-07-29 11:54:06 -0700770 I915_WRITE(PRB0_TAIL, outring); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771} while(0)
772
Jesse Barnes585fb112008-07-29 11:54:06 -0700773/**
774 * Reads a dword out of the status page, which is written to from the command
775 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
776 * MI_STORE_DATA_IMM.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000777 *
Jesse Barnes585fb112008-07-29 11:54:06 -0700778 * The following dwords have a reserved meaning:
Keith Packard0cdad7e2008-10-14 17:19:38 -0700779 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
780 * 0x04: ring 0 head pointer
781 * 0x05: ring 1 head pointer (915-class)
782 * 0x06: ring 2 head pointer (915-class)
783 * 0x10-0x1b: Context status DWords (GM45)
784 * 0x1f: Last written status offset. (GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -0700785 *
Keith Packard0cdad7e2008-10-14 17:19:38 -0700786 * The area from dword 0x20 to 0x3ff is available for driver usage.
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000787 */
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000788#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
Keith Packard0baf8232008-11-08 11:44:14 +1000789#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
Keith Packard0cdad7e2008-10-14 17:19:38 -0700790#define I915_GEM_HWS_INDEX 0x20
Keith Packard0baf8232008-11-08 11:44:14 +1000791#define I915_BREADCRUMB_INDEX 0x21
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000792
Jesse Barnes585fb112008-07-29 11:54:06 -0700793extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000794
795#define IS_I830(dev) ((dev)->pci_device == 0x3577)
796#define IS_845G(dev) ((dev)->pci_device == 0x2562)
797#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
798#define IS_I855(dev) ((dev)->pci_device == 0x3582)
799#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
800
Carlos Martín4d1f7882008-01-23 16:41:17 +1000801#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000802#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
803#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
Jesse Barnes3bf48462008-04-06 11:55:04 -0700804#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
805 (dev)->pci_device == 0x27AE)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000806#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
807 (dev)->pci_device == 0x2982 || \
808 (dev)->pci_device == 0x2992 || \
809 (dev)->pci_device == 0x29A2 || \
810 (dev)->pci_device == 0x2A02 || \
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000811 (dev)->pci_device == 0x2A12 || \
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000812 (dev)->pci_device == 0x2A42 || \
813 (dev)->pci_device == 0x2E02 || \
814 (dev)->pci_device == 0x2E12 || \
Zhenyu Wang72021782008-11-17 13:58:11 +0800815 (dev)->pci_device == 0x2E22 || \
Zhenyu Wang280da222009-06-05 15:38:37 +0800816 (dev)->pci_device == 0x2E32 || \
817 (dev)->pci_device == 0x0042 || \
818 (dev)->pci_device == 0x0046)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000819
Ma Lingc9ed4482009-05-13 15:08:27 +0800820#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
821 (dev)->pci_device == 0x2A12)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000822
Jesse Barnesb9bfdfe2008-08-25 15:16:19 -0700823#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +1000824
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000825#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
826 (dev)->pci_device == 0x2E12 || \
Eric Anholt60fd99e2008-12-03 22:50:02 -0800827 (dev)->pci_device == 0x2E22 || \
Zhenyu Wang72021782008-11-17 13:58:11 +0800828 (dev)->pci_device == 0x2E32 || \
Eric Anholt60fd99e2008-12-03 22:50:02 -0800829 IS_GM45(dev))
Zhenyu Wangd3adbc02008-06-20 12:12:56 +1000830
Shaohua Li21778322009-02-23 15:19:16 +0800831#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
832#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
833#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
834
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000835#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
836 (dev)->pci_device == 0x29B2 || \
Shaohua Li21778322009-02-23 15:19:16 +0800837 (dev)->pci_device == 0x29D2 || \
838 (IS_IGD(dev)))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000839
Zhenyu Wang280da222009-06-05 15:38:37 +0800840#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
841#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
842#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
843
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000844#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
Zhenyu Wang280da222009-06-05 15:38:37 +0800845 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
846 IS_IGDNG(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000847
848#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
Shaohua Li21778322009-02-23 15:19:16 +0800849 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
Zhenyu Wang280da222009-06-05 15:38:37 +0800850 IS_IGD(dev) || IS_IGDNG_M(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000851
Zhenyu Wang280da222009-06-05 15:38:37 +0800852#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
853 IS_IGDNG(dev))
Jesse Barnes0f973f22009-01-26 17:10:45 -0800854/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
855 * rows, which changed the alignment requirements and fence programming.
856 */
857#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
858 IS_I915GM(dev)))
Zhenyu Wang280da222009-06-05 15:38:37 +0800859#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
Jesse Barnes5ca58282009-03-31 14:11:15 -0700860#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
Zhenyu Wangb39d50e2008-02-19 20:59:09 +1000861
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000862#define PRIMARY_RINGBUFFER_SIZE (128*1024)
Dave Airlie0d6aa602006-01-02 20:14:23 +1100863
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864#endif