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Grant Likelyc6d4d652006-11-27 14:16:29 -07001/*
2 * Lite5200 board Device Tree Source
3 *
Grant Likely05cbbc62007-02-12 13:36:54 -07004 * Copyright 2006-2007 Secret Lab Technologies Ltd.
Grant Likelyc6d4d652006-11-27 14:16:29 -07005 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
Grant Likelya2884f32008-04-29 07:19:07 -060013/dts-v1/;
14
Grant Likelyc6d4d652006-11-27 14:16:29 -070015/ {
Grant Likely05cbbc62007-02-12 13:36:54 -070016 model = "fsl,lite5200";
Marian Balakowicz5b5820d2007-11-15 22:40:21 +110017 compatible = "fsl,lite5200";
Grant Likelyc6d4d652006-11-27 14:16:29 -070018 #address-cells = <1>;
19 #size-cells = <1>;
Grant Likelyb8842452009-02-03 12:30:26 -070020 interrupt-parent = <&mpc5200_pic>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070021
22 cpus {
Grant Likelyc6d4d652006-11-27 14:16:29 -070023 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
Grant Likelya2884f32008-04-29 07:19:07 -060029 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
Grant Likelyc6d4d652006-11-27 14:16:29 -070033 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
Grant Likelyc6d4d652006-11-27 14:16:29 -070036 };
37 };
38
39 memory {
40 device_type = "memory";
Grant Likelya2884f32008-04-29 07:19:07 -060041 reg = <0x00000000 0x04000000>; // 64MB
Grant Likelyc6d4d652006-11-27 14:16:29 -070042 };
43
44 soc5200@f0000000 {
Paul Gortmaker58a5be32008-01-26 07:33:20 +110045 #address-cells = <1>;
46 #size-cells = <1>;
Grant Likely24ce6bc2008-01-24 22:25:31 -070047 compatible = "fsl,mpc5200-immr";
Grant Likelya2884f32008-04-29 07:19:07 -060048 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070050 bus-frequency = <0>; // from bootloader
Grant Likely05cbbc62007-02-12 13:36:54 -070051 system-frequency = <0>; // from bootloader
Grant Likelyc6d4d652006-11-27 14:16:29 -070052
53 cdm@200 {
Grant Likely24ce6bc2008-01-24 22:25:31 -070054 compatible = "fsl,mpc5200-cdm";
Grant Likelya2884f32008-04-29 07:19:07 -060055 reg = <0x200 0x38>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070056 };
57
Grant Likely24ce6bc2008-01-24 22:25:31 -070058 mpc5200_pic: interrupt-controller@500 {
Grant Likelyc6d4d652006-11-27 14:16:29 -070059 // 5200 interrupts are encoded into two levels;
Grant Likelyc6d4d652006-11-27 14:16:29 -070060 interrupt-controller;
61 #interrupt-cells = <3>;
Grant Likely24ce6bc2008-01-24 22:25:31 -070062 compatible = "fsl,mpc5200-pic";
Grant Likelya2884f32008-04-29 07:19:07 -060063 reg = <0x500 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070064 };
65
Grant Likely24ce6bc2008-01-24 22:25:31 -070066 timer@600 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +100067 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -060068 reg = <0x600 0x10>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070069 interrupts = <1 9 0>;
Marian Balakowiczd24bc312007-10-19 04:44:24 +100070 fsl,has-wdt;
Grant Likelyc6d4d652006-11-27 14:16:29 -070071 };
72
Grant Likely24ce6bc2008-01-24 22:25:31 -070073 timer@610 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +100074 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -060075 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070077 };
78
Grant Likely24ce6bc2008-01-24 22:25:31 -070079 timer@620 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +100080 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -060081 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070083 };
84
Grant Likely24ce6bc2008-01-24 22:25:31 -070085 timer@630 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +100086 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -060087 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070089 };
90
Grant Likely24ce6bc2008-01-24 22:25:31 -070091 timer@640 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +100092 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -060093 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -070095 };
96
Grant Likely24ce6bc2008-01-24 22:25:31 -070097 timer@650 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +100098 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -060099 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700101 };
102
Grant Likely24ce6bc2008-01-24 22:25:31 -0700103 timer@660 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000104 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700107 };
108
Grant Likely24ce6bc2008-01-24 22:25:31 -0700109 timer@670 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000110 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700113 };
114
115 rtc@800 { // Real time clock
Grant Likely24ce6bc2008-01-24 22:25:31 -0700116 compatible = "fsl,mpc5200-rtc";
Grant Likelya2884f32008-04-29 07:19:07 -0600117 reg = <0x800 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700118 interrupts = <1 5 0 1 6 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700119 };
120
Grant Likely24ce6bc2008-01-24 22:25:31 -0700121 can@900 {
122 compatible = "fsl,mpc5200-mscan";
Grant Likelya2884f32008-04-29 07:19:07 -0600123 interrupts = <2 17 0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600124 reg = <0x900 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700125 };
126
Grant Likely24ce6bc2008-01-24 22:25:31 -0700127 can@980 {
128 compatible = "fsl,mpc5200-mscan";
Grant Likelya2884f32008-04-29 07:19:07 -0600129 interrupts = <2 18 0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600130 reg = <0x980 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700131 };
132
133 gpio@b00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700134 compatible = "fsl,mpc5200-gpio";
Grant Likelya2884f32008-04-29 07:19:07 -0600135 reg = <0xb00 0x40>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700136 interrupts = <1 7 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700137 };
138
Grant Likely24ce6bc2008-01-24 22:25:31 -0700139 gpio@c00 {
140 compatible = "fsl,mpc5200-gpio-wkup";
Grant Likelya2884f32008-04-29 07:19:07 -0600141 reg = <0xc00 0x40>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700142 interrupts = <1 8 0 0 3 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700143 };
144
Grant Likelyc6d4d652006-11-27 14:16:29 -0700145 spi@f00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700146 compatible = "fsl,mpc5200-spi";
Grant Likelya2884f32008-04-29 07:19:07 -0600147 reg = <0xf00 0x20>;
148 interrupts = <2 13 0 2 14 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700149 };
150
151 usb@1000 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700152 compatible = "fsl,mpc5200-ohci","ohci-be";
Grant Likelya2884f32008-04-29 07:19:07 -0600153 reg = <0x1000 0xff>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700154 interrupts = <2 6 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700155 };
156
Grant Likely24ce6bc2008-01-24 22:25:31 -0700157 dma-controller@1200 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700158 compatible = "fsl,mpc5200-bestcomm";
Grant Likelya2884f32008-04-29 07:19:07 -0600159 reg = <0x1200 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
161 3 4 0 3 5 0 3 6 0 3 7 0
Grant Likelya2884f32008-04-29 07:19:07 -0600162 3 8 0 3 9 0 3 10 0 3 11 0
163 3 12 0 3 13 0 3 14 0 3 15 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700164 };
165
166 xlb@1f00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700167 compatible = "fsl,mpc5200-xlb";
Grant Likelya2884f32008-04-29 07:19:07 -0600168 reg = <0x1f00 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700169 };
170
171 serial@2000 { // PSC1
Grant Likely24ce6bc2008-01-24 22:25:31 -0700172 compatible = "fsl,mpc5200-psc-uart";
Grant Likely05cbbc62007-02-12 13:36:54 -0700173 cell-index = <0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600174 reg = <0x2000 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700175 interrupts = <2 1 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700176 };
177
Grant Likely05cbbc62007-02-12 13:36:54 -0700178 // PSC2 in ac97 mode example
179 //ac97@2200 { // PSC2
Grant Likely24ce6bc2008-01-24 22:25:31 -0700180 // compatible = "fsl,mpc5200-psc-ac97";
Grant Likely05cbbc62007-02-12 13:36:54 -0700181 // cell-index = <1>;
Grant Likelya2884f32008-04-29 07:19:07 -0600182 // reg = <0x2200 0x100>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700183 // interrupts = <2 2 0>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700184 //};
Grant Likelyc6d4d652006-11-27 14:16:29 -0700185
186 // PSC3 in CODEC mode example
Grant Likely05cbbc62007-02-12 13:36:54 -0700187 //i2s@2400 { // PSC3
Grant Likely24ce6bc2008-01-24 22:25:31 -0700188 // compatible = "fsl,mpc5200-psc-i2s";
Grant Likely05cbbc62007-02-12 13:36:54 -0700189 // cell-index = <2>;
Grant Likelya2884f32008-04-29 07:19:07 -0600190 // reg = <0x2400 0x100>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700191 // interrupts = <2 3 0>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700192 //};
Grant Likelyc6d4d652006-11-27 14:16:29 -0700193
Grant Likely05cbbc62007-02-12 13:36:54 -0700194 // PSC4 in uart mode example
Grant Likelyc6d4d652006-11-27 14:16:29 -0700195 //serial@2600 { // PSC4
Grant Likely24ce6bc2008-01-24 22:25:31 -0700196 // compatible = "fsl,mpc5200-psc-uart";
Grant Likely05cbbc62007-02-12 13:36:54 -0700197 // cell-index = <3>;
Grant Likelya2884f32008-04-29 07:19:07 -0600198 // reg = <0x2600 0x100>;
199 // interrupts = <2 11 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700200 //};
201
Grant Likely05cbbc62007-02-12 13:36:54 -0700202 // PSC5 in uart mode example
Grant Likelyc6d4d652006-11-27 14:16:29 -0700203 //serial@2800 { // PSC5
Grant Likely24ce6bc2008-01-24 22:25:31 -0700204 // compatible = "fsl,mpc5200-psc-uart";
Grant Likely05cbbc62007-02-12 13:36:54 -0700205 // cell-index = <4>;
Grant Likelya2884f32008-04-29 07:19:07 -0600206 // reg = <0x2800 0x100>;
207 // interrupts = <2 12 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700208 //};
209
Grant Likely05cbbc62007-02-12 13:36:54 -0700210 // PSC6 in spi mode example
211 //spi@2c00 { // PSC6
Grant Likely24ce6bc2008-01-24 22:25:31 -0700212 // compatible = "fsl,mpc5200-psc-spi";
Grant Likely05cbbc62007-02-12 13:36:54 -0700213 // cell-index = <5>;
Grant Likelya2884f32008-04-29 07:19:07 -0600214 // reg = <0x2c00 0x100>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700215 // interrupts = <2 4 0>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700216 //};
Grant Likelyc6d4d652006-11-27 14:16:29 -0700217
218 ethernet@3000 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700219 compatible = "fsl,mpc5200-fec";
Grant Likelya2884f32008-04-29 07:19:07 -0600220 reg = <0x3000 0x400>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700221 local-mac-address = [ 00 00 00 00 00 00 ];
Grant Likelyc6d4d652006-11-27 14:16:29 -0700222 interrupts = <2 5 0>;
René Bürgel8d813942008-04-03 19:58:37 +1100223 phy-handle = <&phy0>;
224 };
225
226 mdio@3000 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,mpc5200-mdio";
Grant Likelya2884f32008-04-29 07:19:07 -0600230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
René Bürgel8d813942008-04-03 19:58:37 +1100231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
René Bürgel8d813942008-04-03 19:58:37 +1100232
Grant Likelya2884f32008-04-29 07:19:07 -0600233 phy0: ethernet-phy@1 {
René Bürgel8d813942008-04-03 19:58:37 +1100234 reg = <1>;
235 };
Grant Likelyc6d4d652006-11-27 14:16:29 -0700236 };
237
238 ata@3a00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700239 compatible = "fsl,mpc5200-ata";
Grant Likelya2884f32008-04-29 07:19:07 -0600240 reg = <0x3a00 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700241 interrupts = <2 7 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700242 };
243
244 i2c@3d00 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600245 #address-cells = <1>;
246 #size-cells = <0>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
Grant Likelya2884f32008-04-29 07:19:07 -0600248 reg = <0x3d00 0x40>;
249 interrupts = <2 15 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700250 };
251
252 i2c@3d40 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600253 #address-cells = <1>;
254 #size-cells = <0>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700255 compatible = "fsl,mpc5200-i2c","fsl-i2c";
Grant Likelya2884f32008-04-29 07:19:07 -0600256 reg = <0x3d40 0x40>;
257 interrupts = <2 16 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700258 };
259 sram@8000 {
Grant Likelyb8842452009-02-03 12:30:26 -0700260 compatible = "fsl,mpc5200-sram";
Grant Likelya2884f32008-04-29 07:19:07 -0600261 reg = <0x8000 0x4000>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700262 };
263 };
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500264
265 pci@f0000d00 {
266 #interrupt-cells = <1>;
267 #size-cells = <2>;
268 #address-cells = <3>;
269 device_type = "pci";
Grant Likely24ce6bc2008-01-24 22:25:31 -0700270 compatible = "fsl,mpc5200-pci";
Grant Likelya2884f32008-04-29 07:19:07 -0600271 reg = <0xf0000d00 0x100>;
272 interrupt-map-mask = <0xf800 0 0 7>;
273 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
274 0xc000 0 0 2 &mpc5200_pic 0 0 3
275 0xc000 0 0 3 &mpc5200_pic 0 0 3
276 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500277 clock-frequency = <0>; // From boot loader
Grant Likelya2884f32008-04-29 07:19:07 -0600278 interrupts = <2 8 0 2 9 0 2 10 0>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500279 bus-range = <0 0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600280 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
281 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
282 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
Kumar Gala1b3c5cd2007-09-12 18:23:46 -0500283 };
Grant Likelyc6d4d652006-11-27 14:16:29 -0700284};