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gerrit-public.fairphone.software / kernel / msm / 57c938ef4fe2a14f68e8a8f09800217c0cf0cdf0 / . / arch / arm / boot / dts / msm8610.dtsi
blob: 91dfdbefe72209e0ff5499cba5d0c2ab238c6513 [file] [log] [blame]
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Olav Haugan54166782013-01-28 16:59:51 -0800[diff] [blame]14/include/ "msm-iommu-v0.dtsi"
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]15/include/ "msm8610-ion.dtsi"
Lokesh Batra8d55eec2013-02-26 11:31:21 -0800[diff] [blame]16/include/ "msm8610-gpu.dtsi"
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]17/include/ "msm-gdsc.dtsi"
Aparna Dasd16555b2013-03-06 15:46:38 -0800[diff] [blame]18/include/ "msm8610-coresight.dtsi"
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]19/include/ "msm8610-pm.dtsi"
Jeff Hugo53dcf0f2013-03-20 12:37:50 -0600[diff] [blame]20/include/ "msm8610-smp2p.dtsi"
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]21
22/ {
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]23 model = "Qualcomm MSM 8610";
24 compatible = "qcom,msm8610";
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]25 interrupt-parent = <&intc>;
26
27 intc: interrupt-controller@f9000000 {
28 compatible = "qcom,msm-qgic2";
29 interrupt-controller;
30 #interrupt-cells = <3>;
31 reg = <0xf9000000 0x1000>,
32 <0xf9002000 0x1000>;
33 };
34
35 msmgpio: gpio@fd510000 {
36 compatible = "qcom,msm-gpio";
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -0800[diff] [blame]40 gpio-controller;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]41 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -0800[diff] [blame]42 ngpio = <102>;
Rohit Vaswanid2001522012-12-05 19:23:44 -0800[diff] [blame]43 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -0800[diff] [blame]44 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]45 };
46
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]47 aliases {
48 spi0 = &spi_0;
49 };
50
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]51 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -0800[diff] [blame]52 compatible = "arm,armv7-timer";
Syed Rameez Mustafafd9ac032012-10-10 17:52:07 -0700[diff] [blame]53 interrupts = <1 2 0 1 3 0>;
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]54 clock-frequency = <19200000>;
55 };
56
Arun Menon2a7e3772013-01-17 12:06:59 -0800[diff] [blame]57 qcom,msm-adsp-loader {
58 compatible = "qcom,adsp-loader";
59 qcom,adsp-state = <0>;
60 };
61
Abhimanyu Kapur032b1f42013-01-18 00:10:50 -0800[diff] [blame]62 qcom,msm-imem@fe805000 {
63 compatible = "qcom,msm-imem";
64 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
65 };
66
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]67 serial@f991f000 {
68 compatible = "qcom,msm-lsuart-v14";
69 reg = <0xf991f000 0x1000>;
70 interrupts = <0 109 0>;
71 status = "disabled";
72 };
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]73
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]74 qcom,vidc@fdc00000 {
75 compatible = "qcom,msm-vidc";
Sachin Shah4e1c8fe2013-03-20 15:10:05 -0700[diff] [blame]76 qcom,vidc-ns-map = <0x40000000 0x40000000>;
77 qcom,iommu-groups = <&q6_domain_ns>;
78 qcom,iommu-group-buffer-types = <0xfff>;
79 qcom,buffer-type-tz-usage-map = <0x1 0x1>,
80 <0x1fe 0x2>;
81 qcom,hfi = "q6";
Deva Ramasubramanian74b1dda2013-03-27 13:16:17 -0700[diff] [blame]82 qcom,max-hw-load = <97200>; /* FWVGA @ 30 * 2 */
Arun Menon8e25dd42013-01-11 14:11:54 -0800[diff] [blame]83 };
84
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]85 usb@f9a55000 {
86 compatible = "qcom,hsusb-otg";
87 reg = <0xf9a55000 0x400>;
Mayank Rana33d26662013-01-17 10:22:25 +0530[diff] [blame]88 interrupts = <0 134 0>, <0 140 0>;
89 interrupt-names = "core_irq", "async_irq";
Mayank Rana76c6ce22012-11-07 17:07:58 +0530[diff] [blame]90 HSUSB_VDDCX-supply = <&pm8110_s1>;
91 HSUSB_1p8-supply = <&pm8110_l10>;
92 HSUSB_3p3-supply = <&pm8110_l20>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]93
94 qcom,hsusb-otg-phy-type = <2>;
95 qcom,hsusb-otg-mode = <1>;
96 qcom,hsusb-otg-otg-control = <1>;
97 qcom,hsusb-otg-disable-reset;
98 };
99
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]100 android_usb@fe8050c8 {
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]101 compatible = "qcom,android-usb";
Mayank Ranacc0c5452013-01-29 16:41:53 +0530[diff] [blame]102 reg = <0xfe8050c8 0xc8>;
Mayank Rana55db0cb2012-10-15 16:50:06 +0530[diff] [blame]103 };
104
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]105 sdcc1: qcom,sdcc@f9824000 {
106 cell-index = <1>; /* SDC1 eMMC slot */
107 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]108 reg = <0xf9824000 0x800>,
109 <0xf9824800 0x100>,
110 <0xf9804000 0x7000>;
111 reg-names = "core_mem", "dml_mem", "bam_mem";
112 interrupts = <0 123 0>, <0 137 0>;
113 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]114
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]115 vdd-supply = <&pm8110_l17>;
116 qcom,vdd-always-on;
117 qcom,vdd-lpm-sup;
118 qcom,vdd-voltage-level = <2900000 2900000>;
119 qcom,vdd-current-level = <9000 400000>;
120
121 vdd-io-supply = <&pm8110_l6>;
122 qcom,vdd-io-always-on;
123 qcom,vdd-io-lpm-sup;
124 qcom,vdd-io-voltage-level = <1800000 1800000>;
125 qcom,vdd-io-current-level = <9000 60000>;
126
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]127 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
128 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
129 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
130 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]131
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]132 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]133 qcom,sup-voltages = <2900 2900>;
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]134 qcom,bus-width = <8>;
135 qcom,nonremovable;
136 qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]137 };
138
139 sdcc2: qcom,sdcc@f98a4000 {
140 cell-index = <2>; /* SDC2 SD card slot */
141 compatible = "qcom,msm-sdcc";
Oluwafemi Adeyemi4641e7f2012-11-28 16:12:56 -0800[diff] [blame]142 reg = <0xf98a4000 0x800>,
143 <0xf98a4800 0x100>,
144 <0xf9884000 0x7000>;
145 reg-names = "core_mem", "dml_mem", "bam_mem";
146 interrupts = <0 125 0>, <0 220 0>;
147 interrupt-names = "core_irq", "bam_irq";
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]148
Oluwafemi Adeyemid0035622012-11-02 12:07:06 -0700[diff] [blame]149 vdd-supply = <&pm8110_l18>;
150 qcom,vdd-voltage-level = <2950000 2950000>;
151 qcom,vdd-current-level = <9000 400000>;
152
153 vdd-io-supply = <&pm8110_l21>;
154 qcom,vdd-io-voltage-level = <1800000 2950000>;
155 qcom,vdd-io-current-level = <9000 50000>;
156
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]157 qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
158 qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
159 qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
160 qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]161
Oluwafemi Adeyemi6cdfdb82012-11-02 13:36:29 -0700[diff] [blame]162 qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
163 qcom,sup-voltages = <2950 2950>;
164 qcom,bus-width = <4>;
165 qcom,xpc;
166 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
167 qcom,current-limit = <800>;
Oluwafemi Adeyemi58289bf2012-10-16 17:24:33 -0700[diff] [blame]168 };
169
Yan He6c7304c2012-11-09 22:07:08 -0800[diff] [blame]170 qcom,sps {
171 compatible = "qcom,msm_sps";
172 qcom,device-type = <3>;
173 };
174
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]175 qcom,smem@d600000 {
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]176 compatible = "qcom,smem";
Jeff Hugo6a289a32012-11-29 16:16:47 -0700[diff] [blame]177 reg = <0xd600000 0x200000>,
Stepan Moskovchenkod6ee8262013-02-06 11:26:05 -0800[diff] [blame]178 <0xf9011000 0x1000>,
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]179 <0xfc428000 0x4000>;
180 reg-names = "smem", "irq-reg-base", "aux-mem1";
181
182 qcom,smd-modem {
183 compatible = "qcom,smd";
184 qcom,smd-edge = <0>;
185 qcom,smd-irq-offset = <0x8>;
186 qcom,smd-irq-bitmask = <0x1000>;
187 qcom,pil-string = "modem";
188 interrupts = <0 25 1>;
189 };
190
191 qcom,smsm-modem {
192 compatible = "qcom,smsm";
193 qcom,smsm-edge = <0>;
194 qcom,smsm-irq-offset = <0x8>;
195 qcom,smsm-irq-bitmask = <0x2000>;
196 interrupts = <0 26 1>;
197 };
198
199 qcom,smd-adsp {
200 compatible = "qcom,smd";
201 qcom,smd-edge = <1>;
202 qcom,smd-irq-offset = <0x8>;
203 qcom,smd-irq-bitmask = <0x100>;
204 qcom,pil-string = "adsp";
205 interrupts = <0 156 1>;
206 };
207
208 qcom,smsm-adsp {
209 compatible = "qcom,smsm";
210 qcom,smsm-edge = <1>;
211 qcom,smsm-irq-offset = <0x8>;
212 qcom,smsm-irq-bitmask = <0x200>;
213 interrupts = <0 157 1>;
214 };
215
216 qcom,smd-wcnss {
217 compatible = "qcom,smd";
218 qcom,smd-edge = <6>;
219 qcom,smd-irq-offset = <0x8>;
220 qcom,smd-irq-bitmask = <0x20000>;
221 qcom,pil-string = "wcnss";
222 interrupts = <0 142 1>;
223 };
224
225 qcom,smsm-wcnss {
226 compatible = "qcom,smsm";
227 qcom,smsm-edge = <6>;
228 qcom,smsm-irq-offset = <0x8>;
229 qcom,smsm-irq-bitmask = <0x80000>;
230 interrupts = <0 144 1>;
231 };
232
233 qcom,smd-rpm {
234 compatible = "qcom,smd";
235 qcom,smd-edge = <15>;
236 qcom,smd-irq-offset = <0x8>;
237 qcom,smd-irq-bitmask = <0x1>;
238 interrupts = <0 168 1>;
239 qcom,irq-no-suspend;
240 };
David Ng5a3cb232012-12-03 16:42:53 -0800[diff] [blame]241 };
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]242
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]243 rpm_bus: qcom,rpm-smd {
244 compatible = "qcom,rpm-smd";
245 rpm-channel-name = "rpm_requests";
246 rpm-channel-type = <15>; /* SMD_APPS_RPM */
Priyanka Mathur6e993c92013-03-20 11:17:27 -0700[diff] [blame]247 rpm-standalone;
Praveen Chidambarama1f98282012-11-29 09:56:57 -0700[diff] [blame]248 };
249
Olav Haugan8340d932013-01-25 12:03:11 -0800[diff] [blame]250 qcom,msm-mem-hole {
251 compatible = "qcom,msm-mem-hole";
252 qcom,memblock-remove = <0x07C00000 0x6000000>; /* Address and Size of Hole */
253 };
254
Hanumant Singh4e334c82012-11-14 10:16:39 -0800[diff] [blame]255 qcom,wdt@f9017000 {
256 compatible = "qcom,msm-watchdog";
257 reg = <0xf9017000 0x1000>;
258 interrupts = <0 3 0>, <0 4 0>;
259 qcom,bark-time = <11000>;
260 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800[diff] [blame]261 qcom,ipi-ping;
Jeff Hugo818d0f72012-11-05 14:19:28 -0700[diff] [blame]262 };
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]263
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]264 qcom,acpuclk@f9011050 {
265 compatible = "qcom,acpuclk-a7";
266 reg = <0xf9011050 0x8>;
267 reg-names = "rcg_base";
Patrick Dalyf9451d22013-03-20 14:20:12 -0700[diff] [blame]268 a7_cpu-supply = <&apc_vreg_corner>;
Vikram Mulukutlaa3cebff2013-01-28 13:54:54 -0800[diff] [blame]269 a7_mem-supply = <&pm8110_l3>;
270 };
271
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]272 spmi_bus: qcom,spmi@fc4c0000 {
273 cell-index = <0>;
274 compatible = "qcom,spmi-pmic-arb";
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]275 reg-names = "core", "intr", "cnfg";
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]276 reg = <0xfc4cf000 0x1000>,
Kenneth Heitke366b8a42012-12-18 13:51:37 -0700[diff] [blame]277 <0Xfc4cb000 0x1000>,
278 <0Xfc4ca000 0x1000>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]279 /* 190,ee0_krait_hlos_spmi_periph_irq */
280 /* 187,channel_0_krait_hlos_trans_done_irq */
281 interrupts = <0 190 0>, <0 187 0>;
282 qcom,not-wakeup;
283 qcom,pmic-arb-ee = <0>;
284 qcom,pmic-arb-channel = <0>;
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]285 };
286
Gilad Avidovf84f2792013-01-31 13:26:39 -0700[diff] [blame]287 i2c@f9925000 { /* BLSP-1 QUP-3 */
288 cell-index = <0>;
289 compatible = "qcom,i2c-qup";
290 #address-cells = <1>;
291 #size-cells = <0>;
292 reg-names = "qup_phys_addr";
293 reg = <0xf9925000 0x1000>;
294 interrupt-names = "qup_err_intr";
295 interrupts = <0 97 0>;
296 qcom,i2c-bus-freq = <100000>;
297 };
298
Gilad Avidovf58f1832013-01-09 17:31:28 -0700[diff] [blame]299
300 spi_0: spi@f9923000 { /* BLSP1 QUP1 */
301 compatible = "qcom,spi-qup-v2";
302 #address-cells = <1>;
303 #size-cells = <0>;
304 reg-names = "spi_physical", "spi_bam_physical";
305 reg = <0xf9923000 0x1000>,
306 <0xf9904000 0xF000>;
307 interrupt-names = "spi_irq", "spi_bam_irq";
308 interrupts = <0 95 0>, <0 238 0>;
309 spi-max-frequency = <19200000>;
310
311 gpios = <&msmgpio 3 0>, /* CLK */
312 <&msmgpio 1 0>, /* MISO */
313 <&msmgpio 0 0>; /* MOSI */
314 cs-gpios = <&msmgpio 2 0>;
315
316 qcom,infinite-mode = <0>;
317 qcom,use-bam;
318 qcom,ver-reg-exists;
319 qcom,bam-consumer-pipe-index = <12>;
320 qcom,bam-producer-pipe-index = <13>;
321 };
322
Vikram Mulukutla1ac32fd2013-01-28 10:03:58 -0800[diff] [blame]323 qcom,pronto@fb21b000 {
324 compatible = "qcom,pil-pronto";
325 reg = <0xfb21b000 0x3000>,
326 <0xfc401700 0x4>,
327 <0xfd485300 0xc>;
328 reg-names = "pmu_base", "clk_base", "halt_base";
329 interrupts = <0 149 1>;
330 vdd_pronto_pll-supply = <&pm8110_l10>;
331
332 qcom,firmware-name = "wcnss";
333 };
334
Fred Oh92b18a02013-01-22 13:29:41 -0800[diff] [blame]335 sound {
336 compatible = "qcom,msm8x10-audio-codec";
337 qcom,model = "msm8x10-snd-card";
338 };
339
340 qcom,msm-pcm {
341 compatible = "qcom,msm-pcm-dsp";
342 };
343
344 qcom,msm-pcm-routing {
345 compatible = "qcom,msm-pcm-routing";
346 };
347
348 qcom,msm-pcm-lpa {
349 compatible = "qcom,msm-pcm-lpa";
350 };
351
352 qcom,msm-compr-dsp {
353 compatible = "qcom,msm-compr-dsp";
354 };
355
356 qcom,msm-voip-dsp {
357 compatible = "qcom,msm-voip-dsp";
358 };
359
360 qcom,msm-pcm-voice {
361 compatible = "qcom,msm-pcm-voice";
362 };
363
364 qcom,msm-stub-codec {
365 compatible = "qcom,msm-stub-codec";
366 };
367
368 qcom,msm-dai-fe {
369 compatible = "qcom,msm-dai-fe";
370 };
371
372 qcom,msm-pcm-afe {
373 compatible = "qcom,msm-pcm-afe";
374 };
375
376 qcom,msm-dai-mi2s {
377 compatible = "qcom,msm-dai-mi2s";
378 qcom,msm-dai-q6-mi2s-prim {
379 compatible = "qcom,msm-dai-q6-mi2s";
380 qcom,msm-dai-q6-mi2s-dev-id = <0>;
381 qcom,msm-mi2s-rx-lines = <1>;
382 qcom,msm-mi2s-tx-lines = <0>;
383 };
384
385 qcom,msm-dai-q6-mi2s-sec {
386 compatible = "qcom,msm-dai-q6-mi2s";
387 qcom,msm-dai-q6-mi2s-dev-id = <1>;
388 qcom,msm-mi2s-rx-lines = <0>;
389 qcom,msm-mi2s-tx-lines = <3>;
390 };
391 };
392
393 qcom,msm-dai-q6 {
394 compatible = "qcom,msm-dai-q6";
395 qcom,msm-dai-q6-bt-sco-rx {
396 compatible = "qcom,msm-dai-q6-dev";
397 qcom,msm-dai-q6-dev-id = <12288>;
398 };
399
400 qcom,msm-dai-q6-bt-sco-tx {
401 compatible = "qcom,msm-dai-q6-dev";
402 qcom,msm-dai-q6-dev-id = <12289>;
403 };
404
405 qcom,msm-dai-q6-int-fm-rx {
406 compatible = "qcom,msm-dai-q6-dev";
407 qcom,msm-dai-q6-dev-id = <12292>;
408 };
409
410 qcom,msm-dai-q6-int-fm-tx {
411 compatible = "qcom,msm-dai-q6-dev";
412 qcom,msm-dai-q6-dev-id = <12293>;
413 };
414
415 qcom,msm-dai-q6-be-afe-pcm-rx {
416 compatible = "qcom,msm-dai-q6-dev";
417 qcom,msm-dai-q6-dev-id = <224>;
418 };
419
420 qcom,msm-dai-q6-be-afe-pcm-tx {
421 compatible = "qcom,msm-dai-q6-dev";
422 qcom,msm-dai-q6-dev-id = <225>;
423 };
424
425 qcom,msm-dai-q6-afe-proxy-rx {
426 compatible = "qcom,msm-dai-q6-dev";
427 qcom,msm-dai-q6-dev-id = <241>;
428 };
429
430 qcom,msm-dai-q6-afe-proxy-tx {
431 compatible = "qcom,msm-dai-q6-dev";
432 qcom,msm-dai-q6-dev-id = <240>;
433 };
434 };
435
436 qcom,msm-pcm-hostless {
437 compatible = "qcom,msm-pcm-hostless";
438 };
439
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]440 qcom,mss@fc880000 {
441 compatible = "qcom,pil-q6v5-mss";
442 reg = <0xfc880000 0x100>,
443 <0xfd485000 0x400>,
444 <0xfc820000 0x020>,
445 <0xfc401680 0x004>,
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]446 <0xfd485194 0x4>;
447 reg-names = "qdsp6_base", "halt_base", "rmb_base",
Matt Wagantall724b2bb2013-03-18 14:54:06 -0700[diff] [blame]448 "restart_reg", "cxrail_bhs_reg";
Vikram Mulukutla186edd62013-02-22 14:10:40 -0800[diff] [blame]449
450 interrupts = <0 24 1>;
451 vdd_mss-supply = <&pm8110_s1>;
452 vdd_cx-supply = <&pm8110_s1_corner>;
453 vdd_mx-supply = <&pm8110_l3>;
454 vdd_pll-supply = <&pm8110_l10>;
455 qcom,vdd_pll = <1800000>;
456 qcom,is-loadable;
457 qcom,firmware-name = "mba";
458 qcom,pil-self-auth;
459 };
460
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]461 qcom,lpass@fe200000 {
462 compatible = "qcom,pil-q6v5-lpass";
463 reg = <0xfe200000 0x00100>,
Matt Wagantall015b50af2013-03-05 18:51:16 -0800[diff] [blame]464 <0xfd485100 0x00010>,
465 <0xfc4016c0 0x00004>;
466 reg-names = "qdsp6_base", "halt_base", "restart_reg";
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]467 interrupts = <0 162 1>;
Matt Wagantall6c515982013-01-29 14:58:43 -0800[diff] [blame]468 vdd_cx-supply = <&pm8110_s1_corner>;
Vikram Mulukutla36d2dc42012-11-16 15:36:00 -0800[diff] [blame]469 qcom,firmware-name = "adsp";
470 };
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]471
472 tsens: tsens@fc4a8000 {
473 compatible = "qcom,msm-tsens";
474 reg = <0xfc4a8000 0x2000>,
475 <0xfc4b8000 0x1000>;
476 reg-names = "tsens_physical", "tsens_eeprom_physical";
477 interrupts = <0 184 0>;
478 qcom,sensors = <2>;
479 qcom,slope = <2901 2846>;
Siddartha Mohanadossb2f48982013-03-28 13:51:38 -0700[diff] [blame]480 qcom,calib-mode = "fuse_map3";
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]481 qcom,calibration-less-mode;
Siddartha Mohanadoss0ca83312013-03-14 11:43:18 -0700[diff] [blame]482 qcom,tsens-local-init;
Siddartha Mohanadossf7d2f4d2013-03-11 22:10:15 -0700[diff] [blame]483 };
484
Syed Rameez Mustafad3935822012-10-09 11:23:20 -0700[diff] [blame]485};
David Collinsc6b34832012-10-24 12:57:57 -0700[diff] [blame]486
Matt Wagantall1bf56932012-11-29 15:03:29 -0800[diff] [blame]487&gdsc_vfe {
488 status = "ok";
489};
490
491&gdsc_oxili_cx {
492 status = "ok";
493};
494
Olav Haugan9c255522012-11-16 16:43:17 -0800[diff] [blame]495&lpass_iommu {
496 status = "ok";
497};
498
499&copss_iommu {
500 status = "ok";
501};
502
503&mdpe_iommu {
504 status = "ok";
505};
506
507&mdps_iommu {
508 status = "ok";
509};
510
511&gfx_iommu {
512 status = "ok";
513};
514
515&vfe_iommu {
516 status = "ok";
517};
518
Syed Rameez Mustafa3971c142013-01-09 19:04:53 -0800[diff] [blame]519/include/ "msm8610-iommu-domains.dtsi"
Olav Haugan4bc4b692012-12-10 18:29:35 -0800[diff] [blame]520
Kenneth Heitkedb6e1b12012-11-20 15:24:42 -0700[diff] [blame]521/include/ "msm-pm8110.dtsi"
Xiaozhe Shi1581a7b2013-02-21 15:17:57 -0800[diff] [blame]522/include/ "msm8610-regulator.dtsi"
Siddartha Mohanadoss0f664a82013-03-11 22:52:01 -0700[diff] [blame]523
524&pm8110_vadc {
525 chan@0 {
526 label = "usb_in";
527 reg = <0>;
528 qcom,decimation = <0>;
529 qcom,pre-div-channel-scaling = <4>;
530 qcom,calibration-type = "absolute";
531 qcom,scale-function = <0>;
532 qcom,hw-settle-time = <0>;
533 qcom,fast-avg-setup = <0>;
534 };
535
536 chan@2 {
537 label = "vchg_sns";
538 reg = <2>;
539 qcom,decimation = <0>;
540 qcom,pre-div-channel-scaling = <3>;
541 qcom,calibration-type = "absolute";
542 qcom,scale-function = <0>;
543 qcom,hw-settle-time = <0>;
544 qcom,fast-avg-setup = <0>;
545 };
546
547 chan@5 {
548 label = "vcoin";
549 reg = <5>;
550 qcom,decimation = <0>;
551 qcom,pre-div-channel-scaling = <1>;
552 qcom,calibration-type = "absolute";
553 qcom,scale-function = <0>;
554 qcom,hw-settle-time = <0>;
555 qcom,fast-avg-setup = <0>;
556 };
557
558 chan@6 {
559 label = "vbat_sns";
560 reg = <6>;
561 qcom,decimation = <0>;
562 qcom,pre-div-channel-scaling = <1>;
563 qcom,calibration-type = "absolute";
564 qcom,scale-function = <0>;
565 qcom,hw-settle-time = <0>;
566 qcom,fast-avg-setup = <0>;
567 };
568
569 chan@7 {
570 label = "vph_pwr";
571 reg = <7>;
572 qcom,decimation = <0>;
573 qcom,pre-div-channel-scaling = <1>;
574 qcom,calibration-type = "absolute";
575 qcom,scale-function = <0>;
576 qcom,hw-settle-time = <0>;
577 qcom,fast-avg-setup = <0>;
578 };
579
580 chan@30 {
581 label = "batt_therm";
582 reg = <0x30>;
583 qcom,decimation = <0>;
584 qcom,pre-div-channel-scaling = <0>;
585 qcom,calibration-type = "ratiometric";
586 qcom,scale-function = <1>;
587 qcom,hw-settle-time = <2>;
588 qcom,fast-avg-setup = <0>;
589 };
590
591 chan@31 {
592 label = "batt_id";
593 reg = <0x31>;
594 qcom,decimation = <0>;
595 qcom,pre-div-channel-scaling = <0>;
596 qcom,calibration-type = "ratiometric";
597 qcom,scale-function = <0>;
598 qcom,hw-settle-time = <2>;
599 qcom,fast-avg-setup = <0>;
600 };
601
602 chan@b2 {
603 label = "xo_therm_pu2";
604 reg = <0xb2>;
605 qcom,decimation = <0>;
606 qcom,pre-div-channel-scaling = <0>;
607 qcom,calibration-type = "ratiometric";
608 qcom,scale-function = <4>;
609 qcom,hw-settle-time = <2>;
610 qcom,fast-avg-setup = <0>;
611 };
612};
613
614