blob: 23112ef68f675d43565bc04688e0127eadb18db1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Support for IDE interfaces on PowerMacs.
Bartlomiej Zolnierkiewicz58f189f2008-02-01 23:09:33 +01003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +02008 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/types.h>
26#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
Andrew Morton9e5755b2007-03-03 17:48:54 +010051#include "../ide-timing.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78#endif
79
80} pmac_ide_hwif_t;
81
Jon Loeligeraacaf9b2005-09-17 10:36:54 -050082static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
Linus Torvalds1da177e2005-04-16 15:20:36 -070083static int pmac_ide_count;
84
85enum {
86 controller_ohare, /* OHare based */
87 controller_heathrow, /* Heathrow/Paddington */
88 controller_kl_ata3, /* KeyLargo ATA-3 */
89 controller_kl_ata4, /* KeyLargo ATA-4 */
90 controller_un_ata6, /* UniNorth2 ATA-6 */
91 controller_k2_ata6, /* K2 ATA-6 */
92 controller_sh_ata6, /* Shasta ATA-6 */
93};
94
95static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103};
104
105/*
106 * Extra registers, both 32-bit little-endian
107 */
108#define IDE_TIMING_CONFIG 0x200
109#define IDE_INTERRUPT 0x300
110
111/* Kauai (U2) ATA has different register setup */
112#define IDE_KAUAI_PIO_CONFIG 0x200
113#define IDE_KAUAI_ULTRA_CONFIG 0x210
114#define IDE_KAUAI_POLL_CONFIG 0x220
115
116/*
117 * Timing configuration register definitions
118 */
119
120/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
125
126/* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
129 */
130#define TR_133_PIOREG_PIO_MASK 0xff000fff
131#define TR_133_PIOREG_MDMA_MASK 0x00fff800
132#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133#define TR_133_UDMAREG_UDMA_EN 0x00000001
134
135/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
141 *
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
144 *
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
150 */
151#define TR_100_PIOREG_PIO_MASK 0xff000fff
152#define TR_100_PIOREG_MDMA_MASK 0x00fff000
153#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154#define TR_100_UDMAREG_UDMA_EN 0x00000001
155
156
157/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
160 *
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
169 * min value of 45ns.
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
171 * reads.
172 */
173#define TR_66_UDMA_MASK 0xfff00000
174#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176#define TR_66_UDMA_ADDRSETUP_SHIFT 29
177#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178#define TR_66_UDMA_RDY2PAUS_SHIFT 25
179#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180#define TR_66_UDMA_WRDATASETUP_SHIFT 21
181#define TR_66_MDMA_MASK 0x000ffc00
182#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183#define TR_66_MDMA_RECOVERY_SHIFT 15
184#define TR_66_MDMA_ACCESS_MASK 0x00007c00
185#define TR_66_MDMA_ACCESS_SHIFT 10
186#define TR_66_PIO_MASK 0x000003ff
187#define TR_66_PIO_RECOVERY_MASK 0x000003e0
188#define TR_66_PIO_RECOVERY_SHIFT 5
189#define TR_66_PIO_ACCESS_MASK 0x0000001f
190#define TR_66_PIO_ACCESS_SHIFT 0
191
192/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
194 *
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
202 */
203#define TR_33_MDMA_MASK 0x003ff800
204#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205#define TR_33_MDMA_RECOVERY_SHIFT 16
206#define TR_33_MDMA_ACCESS_MASK 0x0000f800
207#define TR_33_MDMA_ACCESS_SHIFT 11
208#define TR_33_MDMA_HALFTICK 0x00200000
209#define TR_33_PIO_MASK 0x000007ff
210#define TR_33_PIO_E 0x00000400
211#define TR_33_PIO_RECOVERY_MASK 0x000003e0
212#define TR_33_PIO_RECOVERY_SHIFT 5
213#define TR_33_PIO_ACCESS_MASK 0x0000001f
214#define TR_33_PIO_ACCESS_SHIFT 0
215
216/*
217 * Interrupt register definitions
218 */
219#define IDE_INTR_DMA 0x80000000
220#define IDE_INTR_DEVICE 0x40000000
221
222/*
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
224 */
225#define KAUAI_FCR_UATA_MAGIC 0x00000004
226#define KAUAI_FCR_UATA_RESET_N 0x00000002
227#define KAUAI_FCR_UATA_ENABLE 0x00000001
228
229#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
230
231/* Rounded Multiword DMA timings
232 *
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
236 */
237struct mdma_timings_t {
238 int accessTime;
239 int recoveryTime;
240 int cycleTime;
241};
242
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500243struct mdma_timings_t mdma_timings_33[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244{
245 { 240, 240, 480 },
246 { 180, 180, 360 },
247 { 135, 135, 270 },
248 { 120, 120, 240 },
249 { 105, 105, 210 },
250 { 90, 90, 180 },
251 { 75, 75, 150 },
252 { 75, 45, 120 },
253 { 0, 0, 0 }
254};
255
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500256struct mdma_timings_t mdma_timings_33k[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257{
258 { 240, 240, 480 },
259 { 180, 180, 360 },
260 { 150, 150, 300 },
261 { 120, 120, 240 },
262 { 90, 120, 210 },
263 { 90, 90, 180 },
264 { 90, 60, 150 },
265 { 90, 30, 120 },
266 { 0, 0, 0 }
267};
268
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500269struct mdma_timings_t mdma_timings_66[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270{
271 { 240, 240, 480 },
272 { 180, 180, 360 },
273 { 135, 135, 270 },
274 { 120, 120, 240 },
275 { 105, 105, 210 },
276 { 90, 90, 180 },
277 { 90, 75, 165 },
278 { 75, 45, 120 },
279 { 0, 0, 0 }
280};
281
282/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
283struct {
284 int addrSetup; /* ??? */
285 int rdy2pause;
286 int wrDataSetup;
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500287} kl66_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288{
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
294};
295
296/* UniNorth 2 ATA/100 timings */
297struct kauai_timing {
298 int cycle_time;
299 u32 timing_reg;
300};
301
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500302static struct kauai_timing kauai_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303{
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200314 { 120 , 0x04000148 },
315 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316};
317
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500318static struct kauai_timing kauai_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319{
320 { 1260 , 0x00fff000 },
321 { 480 , 0x00618000 },
322 { 360 , 0x00492000 },
323 { 270 , 0x0038e000 },
324 { 240 , 0x0030c000 },
325 { 210 , 0x002cb000 },
326 { 180 , 0x00249000 },
327 { 150 , 0x00209000 },
328 { 120 , 0x00148000 },
329 { 0 , 0 },
330};
331
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500332static struct kauai_timing kauai_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333{
334 { 120 , 0x000070c0 },
335 { 90 , 0x00005d80 },
336 { 60 , 0x00004a60 },
337 { 45 , 0x00003a50 },
338 { 30 , 0x00002a30 },
339 { 20 , 0x00002921 },
340 { 0 , 0 },
341};
342
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500343static struct kauai_timing shasta_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344{
345 { 930 , 0x08000fff },
346 { 600 , 0x0A000c97 },
347 { 383 , 0x07000712 },
348 { 360 , 0x040003cd },
349 { 330 , 0x040003cd },
350 { 300 , 0x040003cd },
351 { 270 , 0x040003cd },
352 { 240 , 0x040003cd },
353 { 239 , 0x040003cd },
354 { 180 , 0x0400028b },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200355 { 120 , 0x0400010a },
356 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357};
358
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500359static struct kauai_timing shasta_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360{
361 { 1260 , 0x00fff000 },
362 { 480 , 0x00820800 },
363 { 360 , 0x00820800 },
364 { 270 , 0x00820800 },
365 { 240 , 0x00820800 },
366 { 210 , 0x00820800 },
367 { 180 , 0x00820800 },
368 { 150 , 0x0028b000 },
369 { 120 , 0x001ca000 },
370 { 0 , 0 },
371};
372
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500373static struct kauai_timing shasta_udma133_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374{
375 { 120 , 0x00035901, },
376 { 90 , 0x000348b1, },
377 { 60 , 0x00033881, },
378 { 45 , 0x00033861, },
379 { 30 , 0x00033841, },
380 { 20 , 0x00033031, },
381 { 15 , 0x00033021, },
382 { 0 , 0 },
383};
384
385
386static inline u32
387kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
388{
389 int i;
390
391 for (i=0; table[i].cycle_time; i++)
392 if (cycle_time > table[i+1].cycle_time)
393 return table[i].timing_reg;
Bartlomiej Zolnierkiewicz90a87ea2007-10-13 17:47:48 +0200394 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 return 0;
396}
397
398/* allow up to 256 DBDMA commands per xfer */
399#define MAX_DCMDS 256
400
401/*
402 * Wait 1s for disk to answer on IDE bus after a hard reset
403 * of the device (via GPIO/FCR).
404 *
405 * Some devices seem to "pollute" the bus even after dropping
406 * the BSY bit (typically some combo drives slave on the UDMA
407 * bus) after a hard reset. Since we hard reset all drives on
408 * KeyLargo ATA66, we have to keep that delay around. I may end
409 * up not hard resetting anymore on these and keep the delay only
410 * for older interfaces instead (we have to reset when coming
411 * from MacOS...) --BenH.
412 */
413#define IDE_WAKEUP_DELAY (1*HZ)
414
415static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
416static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417static void pmac_ide_selectproc(ide_drive_t *drive);
418static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
419
420#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
421
422/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 * N.B. this can't be an initfunc, because the media-bay task can
424 * call ide_[un]register at any time.
425 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500426void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427pmac_ide_init_hwif_ports(hw_regs_t *hw,
428 unsigned long data_port, unsigned long ctrl_port,
429 int *irq)
430{
431 int i, ix;
432
433 if (data_port == 0)
434 return;
435
436 for (ix = 0; ix < MAX_HWIFS; ++ix)
437 if (data_port == pmac_ide[ix].regbase)
438 break;
439
Bartlomiej Zolnierkiewiczd26805f2008-01-25 22:17:07 +0100440 if (ix >= MAX_HWIFS)
441 return; /* not an IDE PMAC interface */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442
443 for (i = 0; i < 8; ++i)
444 hw->io_ports[i] = data_port + i * 0x10;
445 hw->io_ports[8] = data_port + 0x160;
446
447 if (irq != NULL)
448 *irq = pmac_ide[ix].irq;
Benjamin Herrenschmidt22192cc2006-05-20 14:59:53 -0700449
450 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451}
452
453#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
454
455/*
456 * Apply the timings of the proper unit (master/slave) to the shared
457 * timing register when selecting that unit. This version is for
458 * ASICs with a single timing register
459 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500460static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461pmac_ide_selectproc(ide_drive_t *drive)
462{
463 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
464
465 if (pmif == NULL)
466 return;
467
468 if (drive->select.b.unit & 0x01)
469 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
470 else
471 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
472 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
473}
474
475/*
476 * Apply the timings of the proper unit (master/slave) to the shared
477 * timing register when selecting that unit. This version is for
478 * ASICs with a dual timing register (Kauai)
479 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500480static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481pmac_ide_kauai_selectproc(ide_drive_t *drive)
482{
483 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
484
485 if (pmif == NULL)
486 return;
487
488 if (drive->select.b.unit & 0x01) {
489 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
490 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
491 } else {
492 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
493 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
494 }
495 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
496}
497
498/*
499 * Force an update of controller timing values for a given drive
500 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500501static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502pmac_ide_do_update_timings(ide_drive_t *drive)
503{
504 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
505
506 if (pmif == NULL)
507 return;
508
509 if (pmif->kind == controller_sh_ata6 ||
510 pmif->kind == controller_un_ata6 ||
511 pmif->kind == controller_k2_ata6)
512 pmac_ide_kauai_selectproc(drive);
513 else
514 pmac_ide_selectproc(drive);
515}
516
517static void
518pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
519{
520 u32 tmp;
521
522 writeb(value, (void __iomem *) port);
523 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
524}
525
526/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
528 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500529static void
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200530pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531{
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200532 u32 *timings, t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 unsigned accessTicks, recTicks;
534 unsigned accessTime, recTime;
535 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200536 unsigned int cycle_time;
537
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 if (pmif == NULL)
539 return;
540
541 /* which drive is it ? */
542 timings = &pmif->timings[drive->select.b.unit & 0x01];
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200543 t = *timings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200545 cycle_time = ide_pio_cycle_time(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546
547 switch (pmif->kind) {
548 case controller_sh_ata6: {
549 /* 133Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200550 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200551 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552 break;
553 }
554 case controller_un_ata6:
555 case controller_k2_ata6: {
556 /* 100Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200557 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200558 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 break;
560 }
561 case controller_kl_ata4:
562 /* 66Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200563 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 - ide_pio_timings[pio].setup_time;
565 recTime = max(recTime, 150U);
566 accessTime = ide_pio_timings[pio].active_time;
567 accessTime = max(accessTime, 150U);
568 accessTicks = SYSCLK_TICKS_66(accessTime);
569 accessTicks = min(accessTicks, 0x1fU);
570 recTicks = SYSCLK_TICKS_66(recTime);
571 recTicks = min(recTicks, 0x1fU);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200572 t = (t & ~TR_66_PIO_MASK) |
573 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
574 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575 break;
576 default: {
577 /* 33Mhz cell */
578 int ebit = 0;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200579 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580 - ide_pio_timings[pio].setup_time;
581 recTime = max(recTime, 150U);
582 accessTime = ide_pio_timings[pio].active_time;
583 accessTime = max(accessTime, 150U);
584 accessTicks = SYSCLK_TICKS(accessTime);
585 accessTicks = min(accessTicks, 0x1fU);
586 accessTicks = max(accessTicks, 4U);
587 recTicks = SYSCLK_TICKS(recTime);
588 recTicks = min(recTicks, 0x1fU);
589 recTicks = max(recTicks, 5U) - 4;
590 if (recTicks > 9) {
591 recTicks--; /* guess, but it's only for PIO0, so... */
592 ebit = 1;
593 }
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200594 t = (t & ~TR_33_PIO_MASK) |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
596 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
597 if (ebit)
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200598 t |= TR_33_PIO_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 break;
600 }
601 }
602
603#ifdef IDE_PMAC_DEBUG
604 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
605 drive->name, pio, *timings);
606#endif
607
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200608 *timings = t;
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200609 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610}
611
612#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
613
614/*
615 * Calculate KeyLargo ATA/66 UDMA timings
616 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500617static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618set_timings_udma_ata4(u32 *timings, u8 speed)
619{
620 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
621
622 if (speed > XFER_UDMA_4)
623 return 1;
624
625 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
626 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
627 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
628
629 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
630 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
631 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
632 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
633 TR_66_UDMA_EN;
634#ifdef IDE_PMAC_DEBUG
635 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
636 speed & 0xf, *timings);
637#endif
638
639 return 0;
640}
641
642/*
643 * Calculate Kauai ATA/100 UDMA timings
644 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500645static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
647{
648 struct ide_timing *t = ide_timing_find_mode(speed);
649 u32 tr;
650
651 if (speed > XFER_UDMA_5 || t == NULL)
652 return 1;
653 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
655 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
656
657 return 0;
658}
659
660/*
661 * Calculate Shasta ATA/133 UDMA timings
662 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500663static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
665{
666 struct ide_timing *t = ide_timing_find_mode(speed);
667 u32 tr;
668
669 if (speed > XFER_UDMA_6 || t == NULL)
670 return 1;
671 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
673 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
674
675 return 0;
676}
677
678/*
679 * Calculate MDMA timings for all cells
680 */
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200681static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200683 u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684{
685 int cycleTime, accessTime = 0, recTime = 0;
686 unsigned accessTicks, recTicks;
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200687 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 struct mdma_timings_t* tm = NULL;
689 int i;
690
691 /* Get default cycle time for mode */
692 switch(speed & 0xf) {
693 case 0: cycleTime = 480; break;
694 case 1: cycleTime = 150; break;
695 case 2: cycleTime = 120; break;
696 default:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200697 BUG();
698 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 }
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200700
701 /* Check if drive provides explicit DMA cycle time */
702 if ((id->field_valid & 2) && id->eide_dma_time)
703 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
704
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 /* OHare limits according to some old Apple sources */
706 if ((intf_type == controller_ohare) && (cycleTime < 150))
707 cycleTime = 150;
708 /* Get the proper timing array for this controller */
709 switch(intf_type) {
710 case controller_sh_ata6:
711 case controller_un_ata6:
712 case controller_k2_ata6:
713 break;
714 case controller_kl_ata4:
715 tm = mdma_timings_66;
716 break;
717 case controller_kl_ata3:
718 tm = mdma_timings_33k;
719 break;
720 default:
721 tm = mdma_timings_33;
722 break;
723 }
724 if (tm != NULL) {
725 /* Lookup matching access & recovery times */
726 i = -1;
727 for (;;) {
728 if (tm[i+1].cycleTime < cycleTime)
729 break;
730 i++;
731 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 cycleTime = tm[i].cycleTime;
733 accessTime = tm[i].accessTime;
734 recTime = tm[i].recoveryTime;
735
736#ifdef IDE_PMAC_DEBUG
737 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
738 drive->name, cycleTime, accessTime, recTime);
739#endif
740 }
741 switch(intf_type) {
742 case controller_sh_ata6: {
743 /* 133Mhz cell */
744 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
746 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
747 }
748 case controller_un_ata6:
749 case controller_k2_ata6: {
750 /* 100Mhz cell */
751 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
753 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
754 }
755 break;
756 case controller_kl_ata4:
757 /* 66Mhz cell */
758 accessTicks = SYSCLK_TICKS_66(accessTime);
759 accessTicks = min(accessTicks, 0x1fU);
760 accessTicks = max(accessTicks, 0x1U);
761 recTicks = SYSCLK_TICKS_66(recTime);
762 recTicks = min(recTicks, 0x1fU);
763 recTicks = max(recTicks, 0x3U);
764 /* Clear out mdma bits and disable udma */
765 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
766 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
767 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
768 break;
769 case controller_kl_ata3:
770 /* 33Mhz cell on KeyLargo */
771 accessTicks = SYSCLK_TICKS(accessTime);
772 accessTicks = max(accessTicks, 1U);
773 accessTicks = min(accessTicks, 0x1fU);
774 accessTime = accessTicks * IDE_SYSCLK_NS;
775 recTicks = SYSCLK_TICKS(recTime);
776 recTicks = max(recTicks, 1U);
777 recTicks = min(recTicks, 0x1fU);
778 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
779 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
780 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
781 break;
782 default: {
783 /* 33Mhz cell on others */
784 int halfTick = 0;
785 int origAccessTime = accessTime;
786 int origRecTime = recTime;
787
788 accessTicks = SYSCLK_TICKS(accessTime);
789 accessTicks = max(accessTicks, 1U);
790 accessTicks = min(accessTicks, 0x1fU);
791 accessTime = accessTicks * IDE_SYSCLK_NS;
792 recTicks = SYSCLK_TICKS(recTime);
793 recTicks = max(recTicks, 2U) - 1;
794 recTicks = min(recTicks, 0x1fU);
795 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
796 if ((accessTicks > 1) &&
797 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
798 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
799 halfTick = 1;
800 accessTicks--;
801 }
802 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
803 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
804 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
805 if (halfTick)
806 *timings |= TR_33_MDMA_HALFTICK;
807 }
808 }
809#ifdef IDE_PMAC_DEBUG
810 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
811 drive->name, speed & 0xf, *timings);
812#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813}
814#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
815
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200816static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817{
818 int unit = (drive->select.b.unit & 0x01);
819 int ret = 0;
820 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200821 u32 *timings, *timings2, tl[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823 timings = &pmif->timings[unit];
824 timings2 = &pmif->timings[unit+2];
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200825
826 /* Copy timings to local image */
827 tl[0] = *timings;
828 tl[1] = *timings2;
829
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +0100831 if (speed >= XFER_UDMA_0) {
832 if (pmif->kind == controller_kl_ata4)
833 ret = set_timings_udma_ata4(&tl[0], speed);
834 else if (pmif->kind == controller_un_ata6
835 || pmif->kind == controller_k2_ata6)
836 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
837 else if (pmif->kind == controller_sh_ata6)
838 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
839 else
840 ret = -1;
841 } else
842 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844 if (ret)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200845 return;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200846
847 /* Apply timings to controller */
848 *timings = tl[0];
849 *timings2 = tl[1];
850
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852}
853
854/*
855 * Blast some well known "safe" values to the timing registers at init or
856 * wakeup from sleep time, before we do real calculation
857 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500858static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859sanitize_timings(pmac_ide_hwif_t *pmif)
860{
861 unsigned int value, value2 = 0;
862
863 switch(pmif->kind) {
864 case controller_sh_ata6:
865 value = 0x0a820c97;
866 value2 = 0x00033031;
867 break;
868 case controller_un_ata6:
869 case controller_k2_ata6:
870 value = 0x08618a92;
871 value2 = 0x00002921;
872 break;
873 case controller_kl_ata4:
874 value = 0x0008438c;
875 break;
876 case controller_kl_ata3:
877 value = 0x00084526;
878 break;
879 case controller_heathrow:
880 case controller_ohare:
881 default:
882 value = 0x00074526;
883 break;
884 }
885 pmif->timings[0] = pmif->timings[1] = value;
886 pmif->timings[2] = pmif->timings[3] = value2;
887}
888
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500889unsigned long
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890pmac_ide_get_base(int index)
891{
892 return pmac_ide[index].regbase;
893}
894
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500895int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896pmac_ide_check_base(unsigned long base)
897{
898 int ix;
899
900 for (ix = 0; ix < MAX_HWIFS; ++ix)
901 if (base == pmac_ide[ix].regbase)
902 return ix;
903 return -1;
904}
905
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500906int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907pmac_ide_get_irq(unsigned long base)
908{
909 int ix;
910
911 for (ix = 0; ix < MAX_HWIFS; ++ix)
912 if (base == pmac_ide[ix].regbase)
913 return pmac_ide[ix].irq;
914 return 0;
915}
916
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500917static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918
919dev_t __init
920pmac_find_ide_boot(char *bootdevice, int n)
921{
922 int i;
923
924 /*
925 * Look through the list of IDE interfaces for this one.
926 */
927 for (i = 0; i < pmac_ide_count; ++i) {
928 char *name;
929 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
930 continue;
931 name = pmac_ide[i].node->full_name;
932 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
933 /* XXX should cope with the 2nd drive as well... */
934 return MKDEV(ide_majors[i], 0);
935 }
936 }
937
938 return 0;
939}
940
941/* Suspend call back, should be called after the child devices
942 * have actually been suspended
943 */
944static int
945pmac_ide_do_suspend(ide_hwif_t *hwif)
946{
947 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
948
949 /* We clear the timings */
950 pmif->timings[0] = 0;
951 pmif->timings[1] = 0;
952
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700953 disable_irq(pmif->irq);
954
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 /* The media bay will handle itself just fine */
956 if (pmif->mediabay)
957 return 0;
958
959 /* Kauai has bus control FCRs directly here */
960 if (pmif->kauai_fcr) {
961 u32 fcr = readl(pmif->kauai_fcr);
962 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
963 writel(fcr, pmif->kauai_fcr);
964 }
965
966 /* Disable the bus on older machines and the cell on kauai */
967 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
968 0);
969
970 return 0;
971}
972
973/* Resume call back, should be called before the child devices
974 * are resumed
975 */
976static int
977pmac_ide_do_resume(ide_hwif_t *hwif)
978{
979 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
980
981 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
982 if (!pmif->mediabay) {
983 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
984 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
985 msleep(10);
986 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987
988 /* Kauai has it different */
989 if (pmif->kauai_fcr) {
990 u32 fcr = readl(pmif->kauai_fcr);
991 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
992 writel(fcr, pmif->kauai_fcr);
993 }
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700994
995 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996 }
997
998 /* Sanitize drive timings */
999 sanitize_timings(pmif);
1000
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -07001001 enable_irq(pmif->irq);
1002
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 return 0;
1004}
1005
1006/*
1007 * Setup, register & probe an IDE channel driven by this driver, this is
1008 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1009 * that ends up beeing free of any device is not kept around by this driver
1010 * (it is kept in 2.4). This introduce an interface numbering change on some
1011 * rare machines unfortunately, but it's better this way.
1012 */
Adrian Bunk468e4682008-02-01 23:09:16 +01001013static int __devinit
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001014pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015{
1016 struct device_node *np = pmif->node;
Jeremy Kerr018a3d12006-07-12 15:40:29 +10001017 const int *bidp;
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001018 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019
1020 pmif->cable_80 = 0;
1021 pmif->broken_dma = pmif->broken_dma_warn = 0;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001022 if (of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001023 pmif->kind = controller_sh_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001024 else if (of_device_is_compatible(np, "kauai-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 pmif->kind = controller_un_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001026 else if (of_device_is_compatible(np, "K2-UATA"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 pmif->kind = controller_k2_ata6;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001028 else if (of_device_is_compatible(np, "keylargo-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 if (strcmp(np->name, "ata-4") == 0)
1030 pmif->kind = controller_kl_ata4;
1031 else
1032 pmif->kind = controller_kl_ata3;
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001033 } else if (of_device_is_compatible(np, "heathrow-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 pmif->kind = controller_heathrow;
1035 else {
1036 pmif->kind = controller_ohare;
1037 pmif->broken_dma = 1;
1038 }
1039
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001040 bidp = of_get_property(np, "AAPL,bus-id", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 pmif->aapl_bus_id = bidp ? *bidp : 0;
1042
1043 /* Get cable type from device-tree */
1044 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1045 || pmif->kind == controller_k2_ata6
1046 || pmif->kind == controller_sh_ata6) {
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001047 const char* cable = of_get_property(np, "cable-type", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 if (cable && !strncmp(cable, "80-", 3))
1049 pmif->cable_80 = 1;
1050 }
1051 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1052 * they have a 80 conductor cable, this seem to be always the case unless
1053 * the user mucked around
1054 */
Stephen Rothwell55b61fe2007-05-03 17:26:52 +10001055 if (of_device_is_compatible(np, "K2-UATA") ||
1056 of_device_is_compatible(np, "shasta-ata"))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 pmif->cable_80 = 1;
1058
1059 /* On Kauai-type controllers, we make sure the FCR is correct */
1060 if (pmif->kauai_fcr)
1061 writel(KAUAI_FCR_UATA_MAGIC |
1062 KAUAI_FCR_UATA_RESET_N |
1063 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1064
1065 pmif->mediabay = 0;
1066
1067 /* Make sure we have sane timings */
1068 sanitize_timings(pmif);
1069
1070#ifndef CONFIG_PPC64
1071 /* XXX FIXME: Media bay stuff need re-organizing */
1072 if (np->parent && np->parent->name
1073 && strcasecmp(np->parent->name, "media-bay") == 0) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001074#ifdef CONFIG_PMAC_MEDIABAY
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001076#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 pmif->mediabay = 1;
1078 if (!bidp)
1079 pmif->aapl_bus_id = 1;
1080 } else if (pmif->kind == controller_ohare) {
1081 /* The code below is having trouble on some ohare machines
1082 * (timing related ?). Until I can put my hand on one of these
1083 * units, I keep the old way
1084 */
1085 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1086 } else
1087#endif
1088 {
1089 /* This is necessary to enable IDE when net-booting */
1090 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1091 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1092 msleep(10);
1093 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1094 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1095 }
1096
1097 /* Setup MMIO ops */
1098 default_hwif_mmiops(hwif);
1099 hwif->OUTBSYNC = pmac_outbsync;
1100
1101 /* Tell common code _not_ to mess with resources */
Bartlomiej Zolnierkiewicz2ad1e552007-02-17 02:40:25 +01001102 hwif->mmio = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 hwif->hwif_data = pmif;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001104 hw->chipset = ide_pmac;
1105 ide_init_port_hw(hwif, hw);
1106 hwif->noprobe = pmif->mediabay;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 hwif->hold = pmif->mediabay;
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +02001108 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 hwif->drives[0].unmask = 1;
1110 hwif->drives[1].unmask = 1;
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +02001111 hwif->drives[0].autotune = IDE_TUNE_AUTO;
1112 hwif->drives[1].autotune = IDE_TUNE_AUTO;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001113 hwif->host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
Bartlomiej Zolnierkiewicz03644cd2007-11-13 22:09:15 +01001114 IDE_HFLAG_PIO_NO_DOWNGRADE |
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001115 IDE_HFLAG_POST_SET_MODE;
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001116 hwif->pio_mask = ATA_PIO4;
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +02001117 hwif->set_pio_mode = pmac_ide_set_pio_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 if (pmif->kind == controller_un_ata6
1119 || pmif->kind == controller_k2_ata6
1120 || pmif->kind == controller_sh_ata6)
1121 hwif->selectproc = pmac_ide_kauai_selectproc;
1122 else
1123 hwif->selectproc = pmac_ide_selectproc;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001124 hwif->set_dma_mode = pmac_ide_set_dma_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1127 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1128 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1129
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001130#ifdef CONFIG_PMAC_MEDIABAY
Linus Torvalds1da177e2005-04-16 15:20:36 -07001131 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1132 hwif->noprobe = 0;
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001133#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1136 /* has a DBDMA controller channel */
1137 if (pmif->dma_regs)
1138 pmac_ide_setup_dma(pmif, hwif);
1139#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1140
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001141 idx[0] = hwif->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001143 ide_device_add(idx);
Bartlomiej Zolnierkiewicz5cbf79c2007-05-10 00:01:11 +02001144
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145 return 0;
1146}
1147
1148/*
1149 * Attach to a macio probed interface
1150 */
1151static int __devinit
Jeff Mahoney5e655772005-07-06 15:44:41 -04001152pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153{
1154 void __iomem *base;
1155 unsigned long regbase;
1156 int irq;
1157 ide_hwif_t *hwif;
1158 pmac_ide_hwif_t *pmif;
1159 int i, rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001160 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161
1162 i = 0;
1163 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1164 || pmac_ide[i].node != NULL))
1165 ++i;
1166 if (i >= MAX_HWIFS) {
1167 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1168 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1169 return -ENODEV;
1170 }
1171
1172 pmif = &pmac_ide[i];
1173 hwif = &ide_hwifs[i];
1174
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +11001175 if (macio_resource_count(mdev) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 printk(KERN_WARNING "ide%d: no address for %s\n",
1177 i, mdev->ofdev.node->full_name);
1178 return -ENXIO;
1179 }
1180
1181 /* Request memory resource for IO ports */
1182 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1183 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1184 return -EBUSY;
1185 }
1186
1187 /* XXX This is bogus. Should be fixed in the registry by checking
1188 * the kind of host interrupt controller, a bit like gatwick
1189 * fixes in irq.c. That works well enough for the single case
1190 * where that happens though...
1191 */
1192 if (macio_irq_count(mdev) == 0) {
1193 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1194 i, mdev->ofdev.node->full_name);
Benjamin Herrenschmidt69917c22006-09-22 12:56:30 +10001195 irq = irq_create_mapping(NULL, 13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 } else
1197 irq = macio_irq(mdev, 0);
1198
1199 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1200 regbase = (unsigned long) base;
1201
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001202 hwif->dev = &mdev->bus->pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203
1204 pmif->mdev = mdev;
1205 pmif->node = mdev->ofdev.node;
1206 pmif->regbase = regbase;
1207 pmif->irq = irq;
1208 pmif->kauai_fcr = NULL;
1209#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1210 if (macio_resource_count(mdev) >= 2) {
1211 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1212 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1213 else
1214 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1215 } else
1216 pmif->dma_regs = NULL;
1217#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1218 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1219
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001220 memset(&hw, 0, sizeof(hw));
1221 pmac_ide_init_hwif_ports(&hw, pmif->regbase, 0, NULL);
1222 hw.irq = irq;
1223 hw.dev = &mdev->ofdev.dev;
1224
1225 rc = pmac_ide_setup_device(pmif, hwif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 if (rc != 0) {
1227 /* The inteface is released to the common IDE layer */
1228 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1229 iounmap(base);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001230 if (pmif->dma_regs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231 iounmap(pmif->dma_regs);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001232 macio_release_resource(mdev, 1);
1233 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234 memset(pmif, 0, sizeof(*pmif));
1235 macio_release_resource(mdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 }
1237
1238 return rc;
1239}
1240
1241static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001242pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243{
1244 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1245 int rc = 0;
1246
David Brownell8b4b8a22006-08-14 23:11:03 -07001247 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1248 && mesg.event == PM_EVENT_SUSPEND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 rc = pmac_ide_do_suspend(hwif);
1250 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001251 mdev->ofdev.dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 }
1253
1254 return rc;
1255}
1256
1257static int
1258pmac_ide_macio_resume(struct macio_dev *mdev)
1259{
1260 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1261 int rc = 0;
1262
Pavel Machekca078ba2005-09-03 15:56:57 -07001263 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264 rc = pmac_ide_do_resume(hwif);
1265 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001266 mdev->ofdev.dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267 }
1268
1269 return rc;
1270}
1271
1272/*
1273 * Attach to a PCI probed interface
1274 */
1275static int __devinit
1276pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1277{
1278 ide_hwif_t *hwif;
1279 struct device_node *np;
1280 pmac_ide_hwif_t *pmif;
1281 void __iomem *base;
1282 unsigned long rbase, rlen;
1283 int i, rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001284 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285
1286 np = pci_device_to_OF_node(pdev);
1287 if (np == NULL) {
1288 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1289 return -ENODEV;
1290 }
1291 i = 0;
1292 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1293 || pmac_ide[i].node != NULL))
1294 ++i;
1295 if (i >= MAX_HWIFS) {
1296 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1297 printk(KERN_ERR " %s\n", np->full_name);
1298 return -ENODEV;
1299 }
1300
1301 pmif = &pmac_ide[i];
1302 hwif = &ide_hwifs[i];
1303
1304 if (pci_enable_device(pdev)) {
1305 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1306 i, np->full_name);
1307 return -ENXIO;
1308 }
1309 pci_set_master(pdev);
1310
1311 if (pci_request_regions(pdev, "Kauai ATA")) {
1312 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1313 i, np->full_name);
1314 return -ENXIO;
1315 }
1316
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001317 hwif->dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318 pmif->mdev = NULL;
1319 pmif->node = np;
1320
1321 rbase = pci_resource_start(pdev, 0);
1322 rlen = pci_resource_len(pdev, 0);
1323
1324 base = ioremap(rbase, rlen);
1325 pmif->regbase = (unsigned long) base + 0x2000;
1326#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1327 pmif->dma_regs = base + 0x1000;
1328#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1329 pmif->kauai_fcr = base;
1330 pmif->irq = pdev->irq;
1331
1332 pci_set_drvdata(pdev, hwif);
1333
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001334 memset(&hw, 0, sizeof(hw));
1335 pmac_ide_init_hwif_ports(&hw, pmif->regbase, 0, NULL);
1336 hw.irq = pdev->irq;
1337 hw.dev = &pdev->dev;
1338
1339 rc = pmac_ide_setup_device(pmif, hwif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340 if (rc != 0) {
1341 /* The inteface is released to the common IDE layer */
1342 pci_set_drvdata(pdev, NULL);
1343 iounmap(base);
1344 memset(pmif, 0, sizeof(*pmif));
1345 pci_release_regions(pdev);
1346 }
1347
1348 return rc;
1349}
1350
1351static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001352pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353{
1354 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1355 int rc = 0;
1356
David Brownell8b4b8a22006-08-14 23:11:03 -07001357 if (mesg.event != pdev->dev.power.power_state.event
1358 && mesg.event == PM_EVENT_SUSPEND) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 rc = pmac_ide_do_suspend(hwif);
1360 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001361 pdev->dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 }
1363
1364 return rc;
1365}
1366
1367static int
1368pmac_ide_pci_resume(struct pci_dev *pdev)
1369{
1370 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1371 int rc = 0;
1372
Pavel Machekca078ba2005-09-03 15:56:57 -07001373 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 rc = pmac_ide_do_resume(hwif);
1375 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001376 pdev->dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377 }
1378
1379 return rc;
1380}
1381
Jeff Mahoney5e655772005-07-06 15:44:41 -04001382static struct of_device_id pmac_ide_macio_match[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383{
1384 {
1385 .name = "IDE",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001386 },
1387 {
1388 .name = "ATA",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389 },
1390 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001391 .type = "ide",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001392 },
1393 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394 .type = "ata",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395 },
1396 {},
1397};
1398
1399static struct macio_driver pmac_ide_macio_driver =
1400{
1401 .name = "ide-pmac",
1402 .match_table = pmac_ide_macio_match,
1403 .probe = pmac_ide_macio_attach,
1404 .suspend = pmac_ide_macio_suspend,
1405 .resume = pmac_ide_macio_resume,
1406};
1407
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001408static const struct pci_device_id pmac_ide_pci_match[] = {
1409 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1410 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1411 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1412 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1413 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
Benjamin Herrenschmidt71e4eda2007-10-06 18:52:27 +10001414 {},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415};
1416
1417static struct pci_driver pmac_ide_pci_driver = {
1418 .name = "ide-pmac",
1419 .id_table = pmac_ide_pci_match,
1420 .probe = pmac_ide_pci_attach,
1421 .suspend = pmac_ide_pci_suspend,
1422 .resume = pmac_ide_pci_resume,
1423};
1424MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1425
Andrew Morton9e5755b2007-03-03 17:48:54 +01001426int __init pmac_ide_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427{
Andrew Morton9e5755b2007-03-03 17:48:54 +01001428 int error;
1429
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001430 if (!machine_is(powermac))
Andrew Morton9e5755b2007-03-03 17:48:54 +01001431 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432
1433#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
Andrew Morton9e5755b2007-03-03 17:48:54 +01001434 error = pci_register_driver(&pmac_ide_pci_driver);
1435 if (error)
1436 goto out;
1437 error = macio_register_driver(&pmac_ide_macio_driver);
1438 if (error) {
1439 pci_unregister_driver(&pmac_ide_pci_driver);
1440 goto out;
1441 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001442#else
Andrew Morton9e5755b2007-03-03 17:48:54 +01001443 error = macio_register_driver(&pmac_ide_macio_driver);
1444 if (error)
1445 goto out;
1446 error = pci_register_driver(&pmac_ide_pci_driver);
1447 if (error) {
1448 macio_unregister_driver(&pmac_ide_macio_driver);
1449 goto out;
1450 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001451#endif
Andrew Morton9e5755b2007-03-03 17:48:54 +01001452out:
1453 return error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454}
1455
1456#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1457
1458/*
1459 * pmac_ide_build_dmatable builds the DBDMA command list
1460 * for a transfer and sets the DBDMA channel to point to it.
1461 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001462static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1464{
1465 struct dbdma_cmd *table;
1466 int i, count = 0;
1467 ide_hwif_t *hwif = HWIF(drive);
1468 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1469 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1470 struct scatterlist *sg;
1471 int wr = (rq_data_dir(rq) == WRITE);
1472
1473 /* DMA table is already aligned */
1474 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1475
1476 /* Make sure DMA controller is stopped (necessary ?) */
1477 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1478 while (readl(&dma->status) & RUN)
1479 udelay(1);
1480
1481 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1482
1483 if (!i)
1484 return 0;
1485
1486 /* Build DBDMA commands list */
1487 sg = hwif->sg_table;
1488 while (i && sg_dma_len(sg)) {
1489 u32 cur_addr;
1490 u32 cur_len;
1491
1492 cur_addr = sg_dma_address(sg);
1493 cur_len = sg_dma_len(sg);
1494
1495 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1496 if (pmif->broken_dma_warn == 0) {
Joe Perchesaca38a52007-11-27 21:35:55 +01001497 printk(KERN_WARNING "%s: DMA on non aligned address, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 "switching to PIO on Ohare chipset\n", drive->name);
1499 pmif->broken_dma_warn = 1;
1500 }
1501 goto use_pio_instead;
1502 }
1503 while (cur_len) {
1504 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1505
1506 if (count++ >= MAX_DCMDS) {
1507 printk(KERN_WARNING "%s: DMA table too small\n",
1508 drive->name);
1509 goto use_pio_instead;
1510 }
1511 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1512 st_le16(&table->req_count, tc);
1513 st_le32(&table->phy_addr, cur_addr);
1514 table->cmd_dep = 0;
1515 table->xfer_status = 0;
1516 table->res_count = 0;
1517 cur_addr += tc;
1518 cur_len -= tc;
1519 ++table;
1520 }
Jens Axboe55c16a72007-07-25 08:13:56 +02001521 sg = sg_next(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 i--;
1523 }
1524
1525 /* convert the last command to an input/output last command */
1526 if (count) {
1527 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1528 /* add the stop command to the end of the list */
1529 memset(table, 0, sizeof(struct dbdma_cmd));
1530 st_le16(&table->command, DBDMA_STOP);
1531 mb();
1532 writel(hwif->dmatable_dma, &dma->cmdptr);
1533 return 1;
1534 }
1535
1536 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001537
1538use_pio_instead:
1539 ide_destroy_dmatable(drive);
1540
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 return 0; /* revert to PIO for this request */
1542}
1543
1544/* Teardown mappings after DMA has completed. */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001545static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001546pmac_ide_destroy_dmatable (ide_drive_t *drive)
1547{
1548 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001550 if (hwif->sg_nents) {
1551 ide_destroy_dmatable(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552 hwif->sg_nents = 0;
1553 }
1554}
1555
1556/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1558 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1559 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001560static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561pmac_ide_dma_setup(ide_drive_t *drive)
1562{
1563 ide_hwif_t *hwif = HWIF(drive);
1564 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1565 struct request *rq = HWGROUP(drive)->rq;
1566 u8 unit = (drive->select.b.unit & 0x01);
1567 u8 ata4;
1568
1569 if (pmif == NULL)
1570 return 1;
1571 ata4 = (pmif->kind == controller_kl_ata4);
1572
1573 if (!pmac_ide_build_dmatable(drive, rq)) {
1574 ide_map_sg(drive, rq);
1575 return 1;
1576 }
1577
1578 /* Apple adds 60ns to wrDataSetup on reads */
1579 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1580 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1581 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1582 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1583 }
1584
1585 drive->waiting_for_dma = 1;
1586
1587 return 0;
1588}
1589
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001590static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1592{
1593 /* issue cmd to drive */
1594 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1595}
1596
1597/*
1598 * Kick the DMA controller into life after the DMA command has been issued
1599 * to the drive.
1600 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001601static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602pmac_ide_dma_start(ide_drive_t *drive)
1603{
1604 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1605 volatile struct dbdma_regs __iomem *dma;
1606
1607 dma = pmif->dma_regs;
1608
1609 writel((RUN << 16) | RUN, &dma->control);
1610 /* Make sure it gets to the controller right now */
1611 (void)readl(&dma->control);
1612}
1613
1614/*
1615 * After a DMA transfer, make sure the controller is stopped
1616 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001617static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618pmac_ide_dma_end (ide_drive_t *drive)
1619{
1620 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1621 volatile struct dbdma_regs __iomem *dma;
1622 u32 dstat;
1623
1624 if (pmif == NULL)
1625 return 0;
1626 dma = pmif->dma_regs;
1627
1628 drive->waiting_for_dma = 0;
1629 dstat = readl(&dma->status);
1630 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1631 pmac_ide_destroy_dmatable(drive);
1632 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1633 * in theory, but with ATAPI decices doing buffer underruns, that would
1634 * cause us to disable DMA, which isn't what we want
1635 */
1636 return (dstat & (RUN|DEAD)) != RUN;
1637}
1638
1639/*
1640 * Check out that the interrupt we got was for us. We can't always know this
1641 * for sure with those Apple interfaces (well, we could on the recent ones but
1642 * that's not implemented yet), on the other hand, we don't have shared interrupts
1643 * so it's not really a problem
1644 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001645static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646pmac_ide_dma_test_irq (ide_drive_t *drive)
1647{
1648 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1649 volatile struct dbdma_regs __iomem *dma;
1650 unsigned long status, timeout;
1651
1652 if (pmif == NULL)
1653 return 0;
1654 dma = pmif->dma_regs;
1655
1656 /* We have to things to deal with here:
1657 *
1658 * - The dbdma won't stop if the command was started
1659 * but completed with an error without transferring all
1660 * datas. This happens when bad blocks are met during
1661 * a multi-block transfer.
1662 *
1663 * - The dbdma fifo hasn't yet finished flushing to
1664 * to system memory when the disk interrupt occurs.
1665 *
1666 */
1667
1668 /* If ACTIVE is cleared, the STOP command have passed and
1669 * transfer is complete.
1670 */
1671 status = readl(&dma->status);
1672 if (!(status & ACTIVE))
1673 return 1;
1674 if (!drive->waiting_for_dma)
1675 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1676 called while not waiting\n", HWIF(drive)->index);
1677
1678 /* If dbdma didn't execute the STOP command yet, the
1679 * active bit is still set. We consider that we aren't
1680 * sharing interrupts (which is hopefully the case with
1681 * those controllers) and so we just try to flush the
1682 * channel for pending data in the fifo
1683 */
1684 udelay(1);
1685 writel((FLUSH << 16) | FLUSH, &dma->control);
1686 timeout = 0;
1687 for (;;) {
1688 udelay(1);
1689 status = readl(&dma->status);
1690 if ((status & FLUSH) == 0)
1691 break;
1692 if (++timeout > 100) {
1693 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1694 timeout flushing channel\n", HWIF(drive)->index);
1695 break;
1696 }
1697 }
1698 return 1;
1699}
1700
Bartlomiej Zolnierkiewicz15ce9262008-01-26 20:13:03 +01001701static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001702{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703}
1704
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001705static void
1706pmac_ide_dma_lost_irq (ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707{
1708 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1709 volatile struct dbdma_regs __iomem *dma;
1710 unsigned long status;
1711
1712 if (pmif == NULL)
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001713 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714 dma = pmif->dma_regs;
1715
1716 status = readl(&dma->status);
1717 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718}
1719
1720/*
1721 * Allocate the data structures needed for using DMA with an interface
1722 * and fill the proper list of functions pointers
1723 */
Adrian Bunk468e4682008-02-01 23:09:16 +01001724static void __devinit
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1726{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001727 struct pci_dev *dev = to_pci_dev(hwif->dev);
1728
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729 /* We won't need pci_dev if we switch to generic consistent
1730 * DMA routines ...
1731 */
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001732 if (dev == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733 return;
1734 /*
1735 * Allocate space for the DBDMA commands.
1736 * The +2 is +1 for the stop command and +1 to allow for
1737 * aligning the start address to a multiple of 16 bytes.
1738 */
1739 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001740 dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1742 &hwif->dmatable_dma);
1743 if (pmif->dma_table_cpu == NULL) {
1744 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1745 hwif->name);
1746 return;
1747 }
1748
Bartlomiej Zolnierkiewicz4f52a322008-01-26 20:13:08 +01001749 hwif->sg_max_nents = MAX_DCMDS;
1750
Bartlomiej Zolnierkiewicz15ce9262008-01-26 20:13:03 +01001751 hwif->dma_host_set = &pmac_ide_dma_host_set;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001752 hwif->dma_setup = &pmac_ide_dma_setup;
1753 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
1754 hwif->dma_start = &pmac_ide_dma_start;
1755 hwif->ide_dma_end = &pmac_ide_dma_end;
1756 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +02001757 hwif->dma_timeout = &ide_dma_timeout;
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001758 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001759
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760 switch(pmif->kind) {
1761 case controller_sh_ata6:
1762 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
1763 hwif->mwdma_mask = 0x07;
1764 hwif->swdma_mask = 0x00;
1765 break;
1766 case controller_un_ata6:
1767 case controller_k2_ata6:
1768 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
1769 hwif->mwdma_mask = 0x07;
1770 hwif->swdma_mask = 0x00;
1771 break;
1772 case controller_kl_ata4:
1773 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
1774 hwif->mwdma_mask = 0x07;
1775 hwif->swdma_mask = 0x00;
1776 break;
1777 default:
1778 hwif->ultra_mask = 0x00;
1779 hwif->mwdma_mask = 0x07;
1780 hwif->swdma_mask = 0x00;
1781 break;
Bartlomiej Zolnierkiewicz254bb552007-10-13 17:47:50 +02001782 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783}
1784
1785#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Bartlomiej Zolnierkiewiczade2daf2008-01-26 20:13:07 +01001786
1787module_init(pmac_ide_probe);