Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel I/OAT DMA Linux driver |
| 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | * |
| 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * This driver supports an Intel I/OAT DMA engine (versions >= 2), which |
| 25 | * does asynchronous data movement and checksumming operations. |
| 26 | */ |
| 27 | |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame^] | 30 | #include <linux/slab.h> |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 31 | #include <linux/pci.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/dmaengine.h> |
| 34 | #include <linux/delay.h> |
| 35 | #include <linux/dma-mapping.h> |
| 36 | #include <linux/workqueue.h> |
| 37 | #include <linux/i7300_idle.h> |
| 38 | #include "dma.h" |
| 39 | #include "dma_v2.h" |
| 40 | #include "registers.h" |
| 41 | #include "hw.h" |
| 42 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 43 | int ioat_ring_alloc_order = 8; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 44 | module_param(ioat_ring_alloc_order, int, 0644); |
| 45 | MODULE_PARM_DESC(ioat_ring_alloc_order, |
Dan Williams | 376ec37 | 2009-09-16 15:16:50 -0700 | [diff] [blame] | 46 | "ioat2+: allocate 2^n descriptors per channel" |
| 47 | " (default: 8 max: 16)"); |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 48 | static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER; |
| 49 | module_param(ioat_ring_max_alloc_order, int, 0644); |
| 50 | MODULE_PARM_DESC(ioat_ring_max_alloc_order, |
Dan Williams | 376ec37 | 2009-09-16 15:16:50 -0700 | [diff] [blame] | 51 | "ioat2+: upper limit for ring size (default: 16)"); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 52 | |
Dan Williams | b094ad3 | 2009-09-08 17:42:57 -0700 | [diff] [blame] | 53 | void __ioat2_issue_pending(struct ioat2_dma_chan *ioat) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 54 | { |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 55 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 56 | |
Dan Williams | 376ec37 | 2009-09-16 15:16:50 -0700 | [diff] [blame] | 57 | ioat->dmacount += ioat2_ring_pending(ioat); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 58 | ioat->issued = ioat->head; |
| 59 | /* make descriptor updates globally visible before notifying channel */ |
| 60 | wmb(); |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 61 | writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); |
| 62 | dev_dbg(to_dev(chan), |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 63 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", |
| 64 | __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 65 | } |
| 66 | |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 67 | void ioat2_issue_pending(struct dma_chan *c) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 68 | { |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 69 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 70 | |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 71 | if (ioat2_ring_pending(ioat)) { |
| 72 | spin_lock_bh(&ioat->ring_lock); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 73 | __ioat2_issue_pending(ioat); |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 74 | spin_unlock_bh(&ioat->ring_lock); |
| 75 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | /** |
| 79 | * ioat2_update_pending - log pending descriptors |
| 80 | * @ioat: ioat2+ channel |
| 81 | * |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 82 | * Check if the number of unsubmitted descriptors has exceeded the |
| 83 | * watermark. Called with ring_lock held |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 84 | */ |
| 85 | static void ioat2_update_pending(struct ioat2_dma_chan *ioat) |
| 86 | { |
Dan Williams | 281befa | 2010-03-03 11:47:43 -0700 | [diff] [blame] | 87 | if (ioat2_ring_pending(ioat) > ioat_pending_level) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 88 | __ioat2_issue_pending(ioat); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat) |
| 92 | { |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 93 | struct ioat_ring_ent *desc; |
| 94 | struct ioat_dma_descriptor *hw; |
| 95 | int idx; |
| 96 | |
| 97 | if (ioat2_ring_space(ioat) < 1) { |
| 98 | dev_err(to_dev(&ioat->base), |
| 99 | "Unable to start null desc - ring full\n"); |
| 100 | return; |
| 101 | } |
| 102 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 103 | dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n", |
| 104 | __func__, ioat->head, ioat->tail, ioat->issued); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 105 | idx = ioat2_desc_alloc(ioat, 1); |
| 106 | desc = ioat2_get_ring_ent(ioat, idx); |
| 107 | |
| 108 | hw = desc->hw; |
| 109 | hw->ctl = 0; |
| 110 | hw->ctl_f.null = 1; |
| 111 | hw->ctl_f.int_en = 1; |
| 112 | hw->ctl_f.compl_write = 1; |
| 113 | /* set size to non-zero value (channel returns error when size is 0) */ |
| 114 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 115 | hw->src_addr = 0; |
| 116 | hw->dst_addr = 0; |
| 117 | async_tx_ack(&desc->txd); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 118 | ioat2_set_chainaddr(ioat, desc->txd.phys); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 119 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 120 | __ioat2_issue_pending(ioat); |
| 121 | } |
| 122 | |
| 123 | static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat) |
| 124 | { |
| 125 | spin_lock_bh(&ioat->ring_lock); |
| 126 | __ioat2_start_null_desc(ioat); |
| 127 | spin_unlock_bh(&ioat->ring_lock); |
| 128 | } |
| 129 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 130 | static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 131 | { |
| 132 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 133 | struct dma_async_tx_descriptor *tx; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 134 | struct ioat_ring_ent *desc; |
| 135 | bool seen_current = false; |
| 136 | u16 active; |
| 137 | int i; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 138 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 139 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", |
| 140 | __func__, ioat->head, ioat->tail, ioat->issued); |
| 141 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 142 | active = ioat2_ring_active(ioat); |
| 143 | for (i = 0; i < active && !seen_current; i++) { |
| 144 | prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); |
| 145 | desc = ioat2_get_ring_ent(ioat, ioat->tail + i); |
| 146 | tx = &desc->txd; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 147 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 148 | if (tx->cookie) { |
| 149 | ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); |
| 150 | chan->completed_cookie = tx->cookie; |
| 151 | tx->cookie = 0; |
| 152 | if (tx->callback) { |
| 153 | tx->callback(tx->callback_param); |
| 154 | tx->callback = NULL; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | if (tx->phys == phys_complete) |
| 159 | seen_current = true; |
| 160 | } |
| 161 | ioat->tail += i; |
Dan Williams | aa75db0 | 2010-03-03 21:21:10 -0700 | [diff] [blame] | 162 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 163 | |
| 164 | chan->last_completion = phys_complete; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 165 | if (ioat->head == ioat->tail) { |
| 166 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
| 167 | __func__); |
| 168 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 169 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 170 | } |
| 171 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 172 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 173 | /** |
| 174 | * ioat2_cleanup - clean finished descriptors (advance tail pointer) |
| 175 | * @chan: ioat channel to be cleaned up |
| 176 | */ |
| 177 | static void ioat2_cleanup(struct ioat2_dma_chan *ioat) |
| 178 | { |
| 179 | struct ioat_chan_common *chan = &ioat->base; |
| 180 | unsigned long phys_complete; |
| 181 | |
| 182 | prefetch(chan->completion); |
| 183 | |
| 184 | if (!spin_trylock_bh(&chan->cleanup_lock)) |
| 185 | return; |
| 186 | |
| 187 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { |
| 188 | spin_unlock_bh(&chan->cleanup_lock); |
| 189 | return; |
| 190 | } |
| 191 | |
| 192 | if (!spin_trylock_bh(&ioat->ring_lock)) { |
| 193 | spin_unlock_bh(&chan->cleanup_lock); |
| 194 | return; |
| 195 | } |
| 196 | |
| 197 | __cleanup(ioat, phys_complete); |
| 198 | |
| 199 | spin_unlock_bh(&ioat->ring_lock); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 200 | spin_unlock_bh(&chan->cleanup_lock); |
| 201 | } |
| 202 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 203 | void ioat2_cleanup_event(unsigned long data) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 204 | { |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 205 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 206 | |
| 207 | ioat2_cleanup(ioat); |
Dan Williams | f6ab95b | 2009-09-08 12:01:21 -0700 | [diff] [blame] | 208 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 209 | } |
| 210 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 211 | void __ioat2_restart_chan(struct ioat2_dma_chan *ioat) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 212 | { |
| 213 | struct ioat_chan_common *chan = &ioat->base; |
| 214 | |
| 215 | /* set the tail to be re-issued */ |
| 216 | ioat->issued = ioat->tail; |
| 217 | ioat->dmacount = 0; |
| 218 | set_bit(IOAT_COMPLETION_PENDING, &chan->state); |
| 219 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 220 | |
| 221 | dev_dbg(to_dev(chan), |
| 222 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", |
| 223 | __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount); |
| 224 | |
| 225 | if (ioat2_ring_pending(ioat)) { |
| 226 | struct ioat_ring_ent *desc; |
| 227 | |
| 228 | desc = ioat2_get_ring_ent(ioat, ioat->tail); |
| 229 | ioat2_set_chainaddr(ioat, desc->txd.phys); |
| 230 | __ioat2_issue_pending(ioat); |
| 231 | } else |
| 232 | __ioat2_start_null_desc(ioat); |
| 233 | } |
| 234 | |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 235 | int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 236 | { |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 237 | unsigned long end = jiffies + tmo; |
| 238 | int err = 0; |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 239 | u32 status; |
| 240 | |
| 241 | status = ioat_chansts(chan); |
| 242 | if (is_ioat_active(status) || is_ioat_idle(status)) |
| 243 | ioat_suspend(chan); |
| 244 | while (is_ioat_active(status) || is_ioat_idle(status)) { |
Dan Williams | 7e55a70 | 2010-01-13 13:33:12 -0700 | [diff] [blame] | 245 | if (tmo && time_after(jiffies, end)) { |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 246 | err = -ETIMEDOUT; |
| 247 | break; |
| 248 | } |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 249 | status = ioat_chansts(chan); |
| 250 | cpu_relax(); |
| 251 | } |
| 252 | |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 253 | return err; |
| 254 | } |
| 255 | |
| 256 | int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo) |
| 257 | { |
| 258 | unsigned long end = jiffies + tmo; |
| 259 | int err = 0; |
| 260 | |
| 261 | ioat_reset(chan); |
| 262 | while (ioat_reset_pending(chan)) { |
| 263 | if (end && time_after(jiffies, end)) { |
| 264 | err = -ETIMEDOUT; |
| 265 | break; |
| 266 | } |
| 267 | cpu_relax(); |
| 268 | } |
| 269 | |
| 270 | return err; |
| 271 | } |
| 272 | |
| 273 | static void ioat2_restart_channel(struct ioat2_dma_chan *ioat) |
| 274 | { |
| 275 | struct ioat_chan_common *chan = &ioat->base; |
| 276 | unsigned long phys_complete; |
| 277 | |
| 278 | ioat2_quiesce(chan, 0); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 279 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
| 280 | __cleanup(ioat, phys_complete); |
| 281 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 282 | __ioat2_restart_chan(ioat); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 283 | } |
| 284 | |
Dan Williams | e323271 | 2009-09-08 17:43:02 -0700 | [diff] [blame] | 285 | void ioat2_timer_event(unsigned long data) |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 286 | { |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 287 | struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 288 | struct ioat_chan_common *chan = &ioat->base; |
| 289 | |
| 290 | spin_lock_bh(&chan->cleanup_lock); |
| 291 | if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { |
| 292 | unsigned long phys_complete; |
| 293 | u64 status; |
| 294 | |
| 295 | spin_lock_bh(&ioat->ring_lock); |
| 296 | status = ioat_chansts(chan); |
| 297 | |
| 298 | /* when halted due to errors check for channel |
| 299 | * programming errors before advancing the completion state |
| 300 | */ |
| 301 | if (is_ioat_halted(status)) { |
| 302 | u32 chanerr; |
| 303 | |
| 304 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
Dan Williams | b57014d | 2009-11-19 17:10:07 -0700 | [diff] [blame] | 305 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", |
| 306 | __func__, chanerr); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 307 | BUG_ON(is_ioat_bug(chanerr)); |
| 308 | } |
| 309 | |
| 310 | /* if we haven't made progress and we have already |
| 311 | * acknowledged a pending completion once, then be more |
| 312 | * forceful with a restart |
| 313 | */ |
| 314 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
| 315 | __cleanup(ioat, phys_complete); |
| 316 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) |
| 317 | ioat2_restart_channel(ioat); |
| 318 | else { |
| 319 | set_bit(IOAT_COMPLETION_ACK, &chan->state); |
| 320 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 321 | } |
| 322 | spin_unlock_bh(&ioat->ring_lock); |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 323 | } else { |
| 324 | u16 active; |
| 325 | |
| 326 | /* if the ring is idle, empty, and oversized try to step |
| 327 | * down the size |
| 328 | */ |
| 329 | spin_lock_bh(&ioat->ring_lock); |
| 330 | active = ioat2_ring_active(ioat); |
| 331 | if (active == 0 && ioat->alloc_order > ioat_get_alloc_order()) |
| 332 | reshape_ring(ioat, ioat->alloc_order-1); |
| 333 | spin_unlock_bh(&ioat->ring_lock); |
| 334 | |
| 335 | /* keep shrinking until we get back to our minimum |
| 336 | * default size |
| 337 | */ |
| 338 | if (ioat->alloc_order > ioat_get_alloc_order()) |
| 339 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 340 | } |
| 341 | spin_unlock_bh(&chan->cleanup_lock); |
| 342 | } |
| 343 | |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 344 | static int ioat2_reset_hw(struct ioat_chan_common *chan) |
| 345 | { |
| 346 | /* throw away whatever the channel was doing and get it initialized */ |
| 347 | u32 chanerr; |
| 348 | |
| 349 | ioat2_quiesce(chan, msecs_to_jiffies(100)); |
| 350 | |
| 351 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
| 352 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); |
| 353 | |
| 354 | return ioat2_reset_sync(chan, msecs_to_jiffies(200)); |
| 355 | } |
| 356 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 357 | /** |
| 358 | * ioat2_enumerate_channels - find and initialize the device's channels |
| 359 | * @device: the device to be enumerated |
| 360 | */ |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 361 | int ioat2_enumerate_channels(struct ioatdma_device *device) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 362 | { |
| 363 | struct ioat2_dma_chan *ioat; |
| 364 | struct device *dev = &device->pdev->dev; |
| 365 | struct dma_device *dma = &device->common; |
| 366 | u8 xfercap_log; |
| 367 | int i; |
| 368 | |
| 369 | INIT_LIST_HEAD(&dma->channels); |
| 370 | dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); |
Dan Williams | bb32078 | 2009-09-08 12:01:14 -0700 | [diff] [blame] | 371 | dma->chancnt &= 0x1f; /* bits [4:0] valid */ |
| 372 | if (dma->chancnt > ARRAY_SIZE(device->idx)) { |
| 373 | dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", |
| 374 | dma->chancnt, ARRAY_SIZE(device->idx)); |
| 375 | dma->chancnt = ARRAY_SIZE(device->idx); |
| 376 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 377 | xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
Dan Williams | bb32078 | 2009-09-08 12:01:14 -0700 | [diff] [blame] | 378 | xfercap_log &= 0x1f; /* bits [4:0] valid */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 379 | if (xfercap_log == 0) |
| 380 | return 0; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 381 | dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 382 | |
| 383 | /* FIXME which i/oat version is i7300? */ |
| 384 | #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL |
| 385 | if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) |
| 386 | dma->chancnt--; |
| 387 | #endif |
| 388 | for (i = 0; i < dma->chancnt; i++) { |
| 389 | ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); |
| 390 | if (!ioat) |
| 391 | break; |
| 392 | |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 393 | ioat_init_channel(device, &ioat->base, i); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 394 | ioat->xfercap_log = xfercap_log; |
| 395 | spin_lock_init(&ioat->ring_lock); |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 396 | if (device->reset_hw(&ioat->base)) { |
| 397 | i = 0; |
| 398 | break; |
| 399 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 400 | } |
| 401 | dma->chancnt = i; |
| 402 | return i; |
| 403 | } |
| 404 | |
| 405 | static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx) |
| 406 | { |
| 407 | struct dma_chan *c = tx->chan; |
| 408 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 409 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 410 | dma_cookie_t cookie = c->cookie; |
| 411 | |
| 412 | cookie++; |
| 413 | if (cookie < 0) |
| 414 | cookie = 1; |
| 415 | tx->cookie = cookie; |
| 416 | c->cookie = cookie; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 417 | dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); |
| 418 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 419 | if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state)) |
| 420 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 421 | ioat2_update_pending(ioat); |
| 422 | spin_unlock_bh(&ioat->ring_lock); |
| 423 | |
| 424 | return cookie; |
| 425 | } |
| 426 | |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 427 | static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 428 | { |
| 429 | struct ioat_dma_descriptor *hw; |
| 430 | struct ioat_ring_ent *desc; |
| 431 | struct ioatdma_device *dma; |
| 432 | dma_addr_t phys; |
| 433 | |
| 434 | dma = to_ioatdma_device(chan->device); |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 435 | hw = pci_pool_alloc(dma->dma_pool, flags, &phys); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 436 | if (!hw) |
| 437 | return NULL; |
| 438 | memset(hw, 0, sizeof(*hw)); |
| 439 | |
Dan Williams | 162b96e | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 440 | desc = kmem_cache_alloc(ioat2_cache, flags); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 441 | if (!desc) { |
| 442 | pci_pool_free(dma->dma_pool, hw, phys); |
| 443 | return NULL; |
| 444 | } |
Dan Williams | 162b96e | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 445 | memset(desc, 0, sizeof(*desc)); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 446 | |
| 447 | dma_async_tx_descriptor_init(&desc->txd, chan); |
| 448 | desc->txd.tx_submit = ioat2_tx_submit_unlock; |
| 449 | desc->hw = hw; |
| 450 | desc->txd.phys = phys; |
| 451 | return desc; |
| 452 | } |
| 453 | |
| 454 | static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan) |
| 455 | { |
| 456 | struct ioatdma_device *dma; |
| 457 | |
| 458 | dma = to_ioatdma_device(chan->device); |
| 459 | pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys); |
Dan Williams | 162b96e | 2009-09-08 17:53:04 -0700 | [diff] [blame] | 460 | kmem_cache_free(ioat2_cache, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 461 | } |
| 462 | |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 463 | static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags) |
| 464 | { |
| 465 | struct ioat_ring_ent **ring; |
| 466 | int descs = 1 << order; |
| 467 | int i; |
| 468 | |
| 469 | if (order > ioat_get_max_alloc_order()) |
| 470 | return NULL; |
| 471 | |
| 472 | /* allocate the array to hold the software ring */ |
| 473 | ring = kcalloc(descs, sizeof(*ring), flags); |
| 474 | if (!ring) |
| 475 | return NULL; |
| 476 | for (i = 0; i < descs; i++) { |
| 477 | ring[i] = ioat2_alloc_ring_ent(c, flags); |
| 478 | if (!ring[i]) { |
| 479 | while (i--) |
| 480 | ioat2_free_ring_ent(ring[i], c); |
| 481 | kfree(ring); |
| 482 | return NULL; |
| 483 | } |
| 484 | set_desc_id(ring[i], i); |
| 485 | } |
| 486 | |
| 487 | /* link descs */ |
| 488 | for (i = 0; i < descs-1; i++) { |
| 489 | struct ioat_ring_ent *next = ring[i+1]; |
| 490 | struct ioat_dma_descriptor *hw = ring[i]->hw; |
| 491 | |
| 492 | hw->next = next->txd.phys; |
| 493 | } |
| 494 | ring[i]->hw->next = ring[0]->txd.phys; |
| 495 | |
| 496 | return ring; |
| 497 | } |
| 498 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 499 | /* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring |
| 500 | * @chan: channel to be initialized |
| 501 | */ |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 502 | int ioat2_alloc_chan_resources(struct dma_chan *c) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 503 | { |
| 504 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 505 | struct ioat_chan_common *chan = &ioat->base; |
| 506 | struct ioat_ring_ent **ring; |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 507 | int order; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 508 | |
| 509 | /* have we already been set up? */ |
| 510 | if (ioat->ring) |
| 511 | return 1 << ioat->alloc_order; |
| 512 | |
| 513 | /* Setup register to interrupt and write completion status on error */ |
Dan Williams | f6ab95b | 2009-09-08 12:01:21 -0700 | [diff] [blame] | 514 | writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 515 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 516 | /* allocate a completion writeback area */ |
| 517 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 518 | chan->completion = pci_pool_alloc(chan->device->completion_pool, |
| 519 | GFP_KERNEL, &chan->completion_dma); |
| 520 | if (!chan->completion) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 521 | return -ENOMEM; |
| 522 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 523 | memset(chan->completion, 0, sizeof(*chan->completion)); |
| 524 | writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 525 | chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 526 | writel(((u64) chan->completion_dma) >> 32, |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 527 | chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
| 528 | |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 529 | order = ioat_get_alloc_order(); |
| 530 | ring = ioat2_alloc_ring(c, order, GFP_KERNEL); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 531 | if (!ring) |
| 532 | return -ENOMEM; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 533 | |
| 534 | spin_lock_bh(&ioat->ring_lock); |
| 535 | ioat->ring = ring; |
| 536 | ioat->head = 0; |
| 537 | ioat->issued = 0; |
| 538 | ioat->tail = 0; |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 539 | ioat->alloc_order = order; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 540 | spin_unlock_bh(&ioat->ring_lock); |
| 541 | |
| 542 | tasklet_enable(&chan->cleanup_task); |
| 543 | ioat2_start_null_desc(ioat); |
| 544 | |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 545 | return 1 << ioat->alloc_order; |
| 546 | } |
| 547 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 548 | bool reshape_ring(struct ioat2_dma_chan *ioat, int order) |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 549 | { |
| 550 | /* reshape differs from normal ring allocation in that we want |
| 551 | * to allocate a new software ring while only |
| 552 | * extending/truncating the hardware ring |
| 553 | */ |
| 554 | struct ioat_chan_common *chan = &ioat->base; |
| 555 | struct dma_chan *c = &chan->common; |
| 556 | const u16 curr_size = ioat2_ring_mask(ioat) + 1; |
| 557 | const u16 active = ioat2_ring_active(ioat); |
| 558 | const u16 new_size = 1 << order; |
| 559 | struct ioat_ring_ent **ring; |
| 560 | u16 i; |
| 561 | |
| 562 | if (order > ioat_get_max_alloc_order()) |
| 563 | return false; |
| 564 | |
| 565 | /* double check that we have at least 1 free descriptor */ |
| 566 | if (active == curr_size) |
| 567 | return false; |
| 568 | |
| 569 | /* when shrinking, verify that we can hold the current active |
| 570 | * set in the new ring |
| 571 | */ |
| 572 | if (active >= new_size) |
| 573 | return false; |
| 574 | |
| 575 | /* allocate the array to hold the software ring */ |
| 576 | ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT); |
| 577 | if (!ring) |
| 578 | return false; |
| 579 | |
| 580 | /* allocate/trim descriptors as needed */ |
| 581 | if (new_size > curr_size) { |
| 582 | /* copy current descriptors to the new ring */ |
| 583 | for (i = 0; i < curr_size; i++) { |
| 584 | u16 curr_idx = (ioat->tail+i) & (curr_size-1); |
| 585 | u16 new_idx = (ioat->tail+i) & (new_size-1); |
| 586 | |
| 587 | ring[new_idx] = ioat->ring[curr_idx]; |
| 588 | set_desc_id(ring[new_idx], new_idx); |
| 589 | } |
| 590 | |
| 591 | /* add new descriptors to the ring */ |
| 592 | for (i = curr_size; i < new_size; i++) { |
| 593 | u16 new_idx = (ioat->tail+i) & (new_size-1); |
| 594 | |
| 595 | ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT); |
| 596 | if (!ring[new_idx]) { |
| 597 | while (i--) { |
| 598 | u16 new_idx = (ioat->tail+i) & (new_size-1); |
| 599 | |
| 600 | ioat2_free_ring_ent(ring[new_idx], c); |
| 601 | } |
| 602 | kfree(ring); |
| 603 | return false; |
| 604 | } |
| 605 | set_desc_id(ring[new_idx], new_idx); |
| 606 | } |
| 607 | |
| 608 | /* hw link new descriptors */ |
| 609 | for (i = curr_size-1; i < new_size; i++) { |
| 610 | u16 new_idx = (ioat->tail+i) & (new_size-1); |
| 611 | struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)]; |
| 612 | struct ioat_dma_descriptor *hw = ring[new_idx]->hw; |
| 613 | |
| 614 | hw->next = next->txd.phys; |
| 615 | } |
| 616 | } else { |
| 617 | struct ioat_dma_descriptor *hw; |
| 618 | struct ioat_ring_ent *next; |
| 619 | |
| 620 | /* copy current descriptors to the new ring, dropping the |
| 621 | * removed descriptors |
| 622 | */ |
| 623 | for (i = 0; i < new_size; i++) { |
| 624 | u16 curr_idx = (ioat->tail+i) & (curr_size-1); |
| 625 | u16 new_idx = (ioat->tail+i) & (new_size-1); |
| 626 | |
| 627 | ring[new_idx] = ioat->ring[curr_idx]; |
| 628 | set_desc_id(ring[new_idx], new_idx); |
| 629 | } |
| 630 | |
| 631 | /* free deleted descriptors */ |
| 632 | for (i = new_size; i < curr_size; i++) { |
| 633 | struct ioat_ring_ent *ent; |
| 634 | |
| 635 | ent = ioat2_get_ring_ent(ioat, ioat->tail+i); |
| 636 | ioat2_free_ring_ent(ent, c); |
| 637 | } |
| 638 | |
| 639 | /* fix up hardware ring */ |
| 640 | hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw; |
| 641 | next = ring[(ioat->tail+new_size) & (new_size-1)]; |
| 642 | hw->next = next->txd.phys; |
| 643 | } |
| 644 | |
| 645 | dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", |
| 646 | __func__, new_size); |
| 647 | |
| 648 | kfree(ioat->ring); |
| 649 | ioat->ring = ring; |
| 650 | ioat->alloc_order = order; |
| 651 | |
| 652 | return true; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 653 | } |
| 654 | |
| 655 | /** |
| 656 | * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops |
| 657 | * @idx: gets starting descriptor index on successful allocation |
| 658 | * @ioat: ioat2,3 channel (ring) to operate on |
| 659 | * @num_descs: allocation length |
| 660 | */ |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 661 | int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 662 | { |
| 663 | struct ioat_chan_common *chan = &ioat->base; |
| 664 | |
| 665 | spin_lock_bh(&ioat->ring_lock); |
Dan Williams | a309218 | 2009-09-08 12:02:01 -0700 | [diff] [blame] | 666 | /* never allow the last descriptor to be consumed, we need at |
| 667 | * least one free at all times to allow for on-the-fly ring |
| 668 | * resizing. |
| 669 | */ |
| 670 | while (unlikely(ioat2_ring_space(ioat) <= num_descs)) { |
| 671 | if (reshape_ring(ioat, ioat->alloc_order + 1) && |
| 672 | ioat2_ring_space(ioat) > num_descs) |
| 673 | break; |
| 674 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 675 | if (printk_ratelimit()) |
| 676 | dev_dbg(to_dev(chan), |
| 677 | "%s: ring full! num_descs: %d (%x:%x:%x)\n", |
| 678 | __func__, num_descs, ioat->head, ioat->tail, |
| 679 | ioat->issued); |
| 680 | spin_unlock_bh(&ioat->ring_lock); |
| 681 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 682 | /* progress reclaim in the allocation failure case we |
| 683 | * may be called under bh_disabled so we need to trigger |
| 684 | * the timer event directly |
| 685 | */ |
| 686 | spin_lock_bh(&chan->cleanup_lock); |
| 687 | if (jiffies > chan->timer.expires && |
| 688 | timer_pending(&chan->timer)) { |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 689 | struct ioatdma_device *device = chan->device; |
| 690 | |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 691 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); |
| 692 | spin_unlock_bh(&chan->cleanup_lock); |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 693 | device->timer_fn((unsigned long) &chan->common); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 694 | } else |
| 695 | spin_unlock_bh(&chan->cleanup_lock); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 696 | return -ENOMEM; |
| 697 | } |
| 698 | |
| 699 | dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n", |
| 700 | __func__, num_descs, ioat->head, ioat->tail, ioat->issued); |
| 701 | |
| 702 | *idx = ioat2_desc_alloc(ioat, num_descs); |
| 703 | return 0; /* with ioat->ring_lock held */ |
| 704 | } |
| 705 | |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 706 | struct dma_async_tx_descriptor * |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 707 | ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, |
| 708 | dma_addr_t dma_src, size_t len, unsigned long flags) |
| 709 | { |
| 710 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 711 | struct ioat_dma_descriptor *hw; |
| 712 | struct ioat_ring_ent *desc; |
| 713 | dma_addr_t dst = dma_dest; |
| 714 | dma_addr_t src = dma_src; |
| 715 | size_t total_len = len; |
| 716 | int num_descs; |
| 717 | u16 idx; |
| 718 | int i; |
| 719 | |
| 720 | num_descs = ioat2_xferlen_to_descs(ioat, len); |
| 721 | if (likely(num_descs) && |
| 722 | ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0) |
| 723 | /* pass */; |
| 724 | else |
| 725 | return NULL; |
Andrew Morton | f477f5b | 2009-09-21 09:17:58 -0700 | [diff] [blame] | 726 | i = 0; |
| 727 | do { |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 728 | size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log); |
| 729 | |
| 730 | desc = ioat2_get_ring_ent(ioat, idx + i); |
| 731 | hw = desc->hw; |
| 732 | |
| 733 | hw->size = copy; |
| 734 | hw->ctl = 0; |
| 735 | hw->src_addr = src; |
| 736 | hw->dst_addr = dst; |
| 737 | |
| 738 | len -= copy; |
| 739 | dst += copy; |
| 740 | src += copy; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 741 | dump_desc_dbg(ioat, desc); |
Andrew Morton | f477f5b | 2009-09-21 09:17:58 -0700 | [diff] [blame] | 742 | } while (++i < num_descs); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 743 | |
| 744 | desc->txd.flags = flags; |
| 745 | desc->len = total_len; |
| 746 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
Dan Williams | 128f2d5 | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 747 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 748 | hw->ctl_f.compl_write = 1; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 749 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 750 | /* we leave the channel locked to ensure in order submission */ |
| 751 | |
| 752 | return &desc->txd; |
| 753 | } |
| 754 | |
| 755 | /** |
| 756 | * ioat2_free_chan_resources - release all the descriptors |
| 757 | * @chan: the channel to be cleaned |
| 758 | */ |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 759 | void ioat2_free_chan_resources(struct dma_chan *c) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 760 | { |
| 761 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 762 | struct ioat_chan_common *chan = &ioat->base; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 763 | struct ioatdma_device *device = chan->device; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 764 | struct ioat_ring_ent *desc; |
| 765 | const u16 total_descs = 1 << ioat->alloc_order; |
| 766 | int descs; |
| 767 | int i; |
| 768 | |
| 769 | /* Before freeing channel resources first check |
| 770 | * if they have been previously allocated for this channel. |
| 771 | */ |
| 772 | if (!ioat->ring) |
| 773 | return; |
| 774 | |
| 775 | tasklet_disable(&chan->cleanup_task); |
Dan Williams | 09c8a5b | 2009-09-08 12:01:49 -0700 | [diff] [blame] | 776 | del_timer_sync(&chan->timer); |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 777 | device->cleanup_fn((unsigned long) c); |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 778 | device->reset_hw(chan); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 779 | |
| 780 | spin_lock_bh(&ioat->ring_lock); |
| 781 | descs = ioat2_ring_space(ioat); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 782 | dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 783 | for (i = 0; i < descs; i++) { |
| 784 | desc = ioat2_get_ring_ent(ioat, ioat->head + i); |
| 785 | ioat2_free_ring_ent(desc, c); |
| 786 | } |
| 787 | |
| 788 | if (descs < total_descs) |
| 789 | dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", |
| 790 | total_descs - descs); |
| 791 | |
| 792 | for (i = 0; i < total_descs - descs; i++) { |
| 793 | desc = ioat2_get_ring_ent(ioat, ioat->tail + i); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 794 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 795 | ioat2_free_ring_ent(desc, c); |
| 796 | } |
| 797 | |
| 798 | kfree(ioat->ring); |
| 799 | ioat->ring = NULL; |
| 800 | ioat->alloc_order = 0; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 801 | pci_pool_free(device->completion_pool, chan->completion, |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 802 | chan->completion_dma); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 803 | spin_unlock_bh(&ioat->ring_lock); |
| 804 | |
| 805 | chan->last_completion = 0; |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame] | 806 | chan->completion_dma = 0; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 807 | ioat->dmacount = 0; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 808 | } |
| 809 | |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 810 | static ssize_t ring_size_show(struct dma_chan *c, char *page) |
| 811 | { |
| 812 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 813 | |
| 814 | return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1); |
| 815 | } |
| 816 | static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); |
| 817 | |
| 818 | static ssize_t ring_active_show(struct dma_chan *c, char *page) |
| 819 | { |
| 820 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); |
| 821 | |
| 822 | /* ...taken outside the lock, no need to be precise */ |
| 823 | return sprintf(page, "%d\n", ioat2_ring_active(ioat)); |
| 824 | } |
| 825 | static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); |
| 826 | |
| 827 | static struct attribute *ioat2_attrs[] = { |
| 828 | &ring_size_attr.attr, |
| 829 | &ring_active_attr.attr, |
| 830 | &ioat_cap_attr.attr, |
| 831 | &ioat_version_attr.attr, |
| 832 | NULL, |
| 833 | }; |
| 834 | |
| 835 | struct kobj_type ioat2_ktype = { |
| 836 | .sysfs_ops = &ioat_sysfs_ops, |
| 837 | .default_attrs = ioat2_attrs, |
| 838 | }; |
| 839 | |
Dan Williams | 345d852 | 2009-09-08 12:01:30 -0700 | [diff] [blame] | 840 | int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 841 | { |
| 842 | struct pci_dev *pdev = device->pdev; |
| 843 | struct dma_device *dma; |
| 844 | struct dma_chan *c; |
| 845 | struct ioat_chan_common *chan; |
| 846 | int err; |
| 847 | |
| 848 | device->enumerate_channels = ioat2_enumerate_channels; |
Dan Williams | a6d52d7 | 2009-12-19 15:36:02 -0700 | [diff] [blame] | 849 | device->reset_hw = ioat2_reset_hw; |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 850 | device->cleanup_fn = ioat2_cleanup_event; |
Dan Williams | bf40a68 | 2009-09-08 17:42:55 -0700 | [diff] [blame] | 851 | device->timer_fn = ioat2_timer_event; |
Dan Williams | 9de6fc7 | 2009-09-08 17:42:58 -0700 | [diff] [blame] | 852 | device->self_test = ioat_dma_self_test; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 853 | dma = &device->common; |
| 854 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; |
| 855 | dma->device_issue_pending = ioat2_issue_pending; |
| 856 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; |
| 857 | dma->device_free_chan_resources = ioat2_free_chan_resources; |
Dan Williams | aa4d72a | 2010-03-03 21:21:13 -0700 | [diff] [blame] | 858 | dma->device_is_tx_complete = ioat_is_dma_complete; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 859 | |
| 860 | err = ioat_probe(device); |
| 861 | if (err) |
| 862 | return err; |
| 863 | ioat_set_tcp_copy_break(2048); |
| 864 | |
| 865 | list_for_each_entry(c, &dma->channels, device_node) { |
| 866 | chan = to_chan_common(c); |
| 867 | writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU, |
| 868 | chan->reg_base + IOAT_DCACTRL_OFFSET); |
| 869 | } |
| 870 | |
| 871 | err = ioat_register(device); |
| 872 | if (err) |
| 873 | return err; |
Dan Williams | 5669e31 | 2009-09-08 17:42:56 -0700 | [diff] [blame] | 874 | |
| 875 | ioat_kobject_add(device, &ioat2_ktype); |
| 876 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 877 | if (dca) |
| 878 | device->dca = ioat2_dca_init(pdev, device->reg_base); |
| 879 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 880 | return err; |
| 881 | } |