Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver |
| 3 | * |
| 4 | * Copyright (C) 2005 SAN People |
| 5 | * Copyright (C) 2008 Atmel |
| 6 | * |
| 7 | * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> |
| 8 | * ATMEL CORP. |
| 9 | * |
| 10 | * Based on at91-ssc.c by |
| 11 | * Frank Mandarino <fmandarino@endrelia.com> |
| 12 | * Based on pxa2xx Platform drivers by |
| 13 | * Liam Girdwood <liam.girdwood@wolfsonmicro.com> |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License as published by |
| 17 | * the Free Software Foundation; either version 2 of the License, or |
| 18 | * (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 28 | */ |
| 29 | |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/device.h> |
| 34 | #include <linux/delay.h> |
| 35 | #include <linux/clk.h> |
| 36 | #include <linux/atmel_pdc.h> |
| 37 | |
| 38 | #include <linux/atmel-ssc.h> |
| 39 | #include <sound/core.h> |
| 40 | #include <sound/pcm.h> |
| 41 | #include <sound/pcm_params.h> |
| 42 | #include <sound/initval.h> |
| 43 | #include <sound/soc.h> |
| 44 | |
| 45 | #include <mach/hardware.h> |
| 46 | |
| 47 | #include "atmel-pcm.h" |
| 48 | #include "atmel_ssc_dai.h" |
| 49 | |
| 50 | |
| 51 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) |
| 52 | #define NUM_SSC_DEVICES 1 |
| 53 | #else |
| 54 | #define NUM_SSC_DEVICES 3 |
| 55 | #endif |
| 56 | |
| 57 | /* |
| 58 | * SSC PDC registers required by the PCM DMA engine. |
| 59 | */ |
| 60 | static struct atmel_pdc_regs pdc_tx_reg = { |
| 61 | .xpr = ATMEL_PDC_TPR, |
| 62 | .xcr = ATMEL_PDC_TCR, |
| 63 | .xnpr = ATMEL_PDC_TNPR, |
| 64 | .xncr = ATMEL_PDC_TNCR, |
| 65 | }; |
| 66 | |
| 67 | static struct atmel_pdc_regs pdc_rx_reg = { |
| 68 | .xpr = ATMEL_PDC_RPR, |
| 69 | .xcr = ATMEL_PDC_RCR, |
| 70 | .xnpr = ATMEL_PDC_RNPR, |
| 71 | .xncr = ATMEL_PDC_RNCR, |
| 72 | }; |
| 73 | |
| 74 | /* |
| 75 | * SSC & PDC status bits for transmit and receive. |
| 76 | */ |
| 77 | static struct atmel_ssc_mask ssc_tx_mask = { |
| 78 | .ssc_enable = SSC_BIT(CR_TXEN), |
| 79 | .ssc_disable = SSC_BIT(CR_TXDIS), |
| 80 | .ssc_endx = SSC_BIT(SR_ENDTX), |
| 81 | .ssc_endbuf = SSC_BIT(SR_TXBUFE), |
| 82 | .pdc_enable = ATMEL_PDC_TXTEN, |
| 83 | .pdc_disable = ATMEL_PDC_TXTDIS, |
| 84 | }; |
| 85 | |
| 86 | static struct atmel_ssc_mask ssc_rx_mask = { |
| 87 | .ssc_enable = SSC_BIT(CR_RXEN), |
| 88 | .ssc_disable = SSC_BIT(CR_RXDIS), |
| 89 | .ssc_endx = SSC_BIT(SR_ENDRX), |
| 90 | .ssc_endbuf = SSC_BIT(SR_RXBUFF), |
| 91 | .pdc_enable = ATMEL_PDC_RXTEN, |
| 92 | .pdc_disable = ATMEL_PDC_RXTDIS, |
| 93 | }; |
| 94 | |
| 95 | |
| 96 | /* |
| 97 | * DMA parameters. |
| 98 | */ |
| 99 | static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { |
| 100 | {{ |
| 101 | .name = "SSC0 PCM out", |
| 102 | .pdc = &pdc_tx_reg, |
| 103 | .mask = &ssc_tx_mask, |
| 104 | }, |
| 105 | { |
| 106 | .name = "SSC0 PCM in", |
| 107 | .pdc = &pdc_rx_reg, |
| 108 | .mask = &ssc_rx_mask, |
| 109 | } }, |
| 110 | #if NUM_SSC_DEVICES == 3 |
| 111 | {{ |
| 112 | .name = "SSC1 PCM out", |
| 113 | .pdc = &pdc_tx_reg, |
| 114 | .mask = &ssc_tx_mask, |
| 115 | }, |
| 116 | { |
| 117 | .name = "SSC1 PCM in", |
| 118 | .pdc = &pdc_rx_reg, |
| 119 | .mask = &ssc_rx_mask, |
| 120 | } }, |
| 121 | {{ |
| 122 | .name = "SSC2 PCM out", |
| 123 | .pdc = &pdc_tx_reg, |
| 124 | .mask = &ssc_tx_mask, |
| 125 | }, |
| 126 | { |
| 127 | .name = "SSC2 PCM in", |
| 128 | .pdc = &pdc_rx_reg, |
| 129 | .mask = &ssc_rx_mask, |
| 130 | } }, |
| 131 | #endif |
| 132 | }; |
| 133 | |
| 134 | |
| 135 | static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { |
| 136 | { |
| 137 | .name = "ssc0", |
| 138 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), |
| 139 | .dir_mask = SSC_DIR_MASK_UNUSED, |
| 140 | .initialized = 0, |
| 141 | }, |
| 142 | #if NUM_SSC_DEVICES == 3 |
| 143 | { |
| 144 | .name = "ssc1", |
| 145 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), |
| 146 | .dir_mask = SSC_DIR_MASK_UNUSED, |
| 147 | .initialized = 0, |
| 148 | }, |
| 149 | { |
| 150 | .name = "ssc2", |
| 151 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), |
| 152 | .dir_mask = SSC_DIR_MASK_UNUSED, |
| 153 | .initialized = 0, |
| 154 | }, |
| 155 | #endif |
| 156 | }; |
| 157 | |
| 158 | |
| 159 | /* |
| 160 | * SSC interrupt handler. Passes PDC interrupts to the DMA |
| 161 | * interrupt handler in the PCM driver. |
| 162 | */ |
| 163 | static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) |
| 164 | { |
| 165 | struct atmel_ssc_info *ssc_p = dev_id; |
| 166 | struct atmel_pcm_dma_params *dma_params; |
| 167 | u32 ssc_sr; |
| 168 | u32 ssc_substream_mask; |
| 169 | int i; |
| 170 | |
| 171 | ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) |
| 172 | & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); |
| 173 | |
| 174 | /* |
| 175 | * Loop through the substreams attached to this SSC. If |
| 176 | * a DMA-related interrupt occurred on that substream, call |
| 177 | * the DMA interrupt handler function, if one has been |
| 178 | * registered in the dma_params structure by the PCM driver. |
| 179 | */ |
| 180 | for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { |
| 181 | dma_params = ssc_p->dma_params[i]; |
| 182 | |
| 183 | if ((dma_params != NULL) && |
| 184 | (dma_params->dma_intr_handler != NULL)) { |
| 185 | ssc_substream_mask = (dma_params->mask->ssc_endx | |
| 186 | dma_params->mask->ssc_endbuf); |
| 187 | if (ssc_sr & ssc_substream_mask) { |
| 188 | dma_params->dma_intr_handler(ssc_sr, |
| 189 | dma_params-> |
| 190 | substream); |
| 191 | } |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | return IRQ_HANDLED; |
| 196 | } |
| 197 | |
| 198 | |
| 199 | /*-------------------------------------------------------------------------*\ |
| 200 | * DAI functions |
| 201 | \*-------------------------------------------------------------------------*/ |
| 202 | /* |
| 203 | * Startup. Only that one substream allowed in each direction. |
| 204 | */ |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 205 | static int atmel_ssc_startup(struct snd_pcm_substream *substream, |
| 206 | struct snd_soc_dai *dai) |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 207 | { |
| 208 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); |
| 209 | struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id]; |
| 210 | int dir_mask; |
| 211 | |
| 212 | pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n", |
| 213 | ssc_readl(ssc_p->ssc->regs, SR)); |
| 214 | |
| 215 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 216 | dir_mask = SSC_DIR_MASK_PLAYBACK; |
| 217 | else |
| 218 | dir_mask = SSC_DIR_MASK_CAPTURE; |
| 219 | |
| 220 | spin_lock_irq(&ssc_p->lock); |
| 221 | if (ssc_p->dir_mask & dir_mask) { |
| 222 | spin_unlock_irq(&ssc_p->lock); |
| 223 | return -EBUSY; |
| 224 | } |
| 225 | ssc_p->dir_mask |= dir_mask; |
| 226 | spin_unlock_irq(&ssc_p->lock); |
| 227 | |
| 228 | return 0; |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * Shutdown. Clear DMA parameters and shutdown the SSC if there |
| 233 | * are no other substreams open. |
| 234 | */ |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 235 | static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, |
| 236 | struct snd_soc_dai *dai) |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 237 | { |
| 238 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); |
| 239 | struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id]; |
| 240 | struct atmel_pcm_dma_params *dma_params; |
| 241 | int dir, dir_mask; |
| 242 | |
| 243 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 244 | dir = 0; |
| 245 | else |
| 246 | dir = 1; |
| 247 | |
| 248 | dma_params = ssc_p->dma_params[dir]; |
| 249 | |
| 250 | if (dma_params != NULL) { |
| 251 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); |
| 252 | pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n", |
| 253 | (dir ? "receive" : "transmit"), |
| 254 | ssc_readl(ssc_p->ssc->regs, SR)); |
| 255 | |
| 256 | dma_params->ssc = NULL; |
| 257 | dma_params->substream = NULL; |
| 258 | ssc_p->dma_params[dir] = NULL; |
| 259 | } |
| 260 | |
| 261 | dir_mask = 1 << dir; |
| 262 | |
| 263 | spin_lock_irq(&ssc_p->lock); |
| 264 | ssc_p->dir_mask &= ~dir_mask; |
| 265 | if (!ssc_p->dir_mask) { |
| 266 | if (ssc_p->initialized) { |
| 267 | /* Shutdown the SSC clock. */ |
| 268 | pr_debug("atmel_ssc_dau: Stopping clock\n"); |
| 269 | clk_disable(ssc_p->ssc->clk); |
| 270 | |
| 271 | free_irq(ssc_p->ssc->irq, ssc_p); |
| 272 | ssc_p->initialized = 0; |
| 273 | } |
| 274 | |
| 275 | /* Reset the SSC */ |
| 276 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); |
| 277 | /* Clear the SSC dividers */ |
| 278 | ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; |
| 279 | } |
| 280 | spin_unlock_irq(&ssc_p->lock); |
| 281 | } |
| 282 | |
| 283 | |
| 284 | /* |
| 285 | * Record the DAI format for use in hw_params(). |
| 286 | */ |
| 287 | static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
| 288 | unsigned int fmt) |
| 289 | { |
| 290 | struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; |
| 291 | |
| 292 | ssc_p->daifmt = fmt; |
| 293 | return 0; |
| 294 | } |
| 295 | |
| 296 | /* |
| 297 | * Record SSC clock dividers for use in hw_params(). |
| 298 | */ |
| 299 | static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, |
| 300 | int div_id, int div) |
| 301 | { |
| 302 | struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; |
| 303 | |
| 304 | switch (div_id) { |
| 305 | case ATMEL_SSC_CMR_DIV: |
| 306 | /* |
| 307 | * The same master clock divider is used for both |
| 308 | * transmit and receive, so if a value has already |
| 309 | * been set, it must match this value. |
| 310 | */ |
| 311 | if (ssc_p->cmr_div == 0) |
| 312 | ssc_p->cmr_div = div; |
| 313 | else |
| 314 | if (div != ssc_p->cmr_div) |
| 315 | return -EBUSY; |
| 316 | break; |
| 317 | |
| 318 | case ATMEL_SSC_TCMR_PERIOD: |
| 319 | ssc_p->tcmr_period = div; |
| 320 | break; |
| 321 | |
| 322 | case ATMEL_SSC_RCMR_PERIOD: |
| 323 | ssc_p->rcmr_period = div; |
| 324 | break; |
| 325 | |
| 326 | default: |
| 327 | return -EINVAL; |
| 328 | } |
| 329 | |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | /* |
| 334 | * Configure the SSC. |
| 335 | */ |
| 336 | static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 337 | struct snd_pcm_hw_params *params, |
| 338 | struct snd_soc_dai *dai) |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 339 | { |
| 340 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); |
| 341 | int id = rtd->dai->cpu_dai->id; |
| 342 | struct atmel_ssc_info *ssc_p = &ssc_info[id]; |
| 343 | struct atmel_pcm_dma_params *dma_params; |
| 344 | int dir, channels, bits; |
| 345 | u32 tfmr, rfmr, tcmr, rcmr; |
| 346 | int start_event; |
| 347 | int ret; |
| 348 | |
| 349 | /* |
| 350 | * Currently, there is only one set of dma params for |
| 351 | * each direction. If more are added, this code will |
| 352 | * have to be changed to select the proper set. |
| 353 | */ |
| 354 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 355 | dir = 0; |
| 356 | else |
| 357 | dir = 1; |
| 358 | |
| 359 | dma_params = &ssc_dma_params[id][dir]; |
| 360 | dma_params->ssc = ssc_p->ssc; |
| 361 | dma_params->substream = substream; |
| 362 | |
| 363 | ssc_p->dma_params[dir] = dma_params; |
| 364 | |
| 365 | /* |
| 366 | * The cpu_dai->dma_data field is only used to communicate the |
| 367 | * appropriate DMA parameters to the pcm driver hw_params() |
| 368 | * function. It should not be used for other purposes |
| 369 | * as it is common to all substreams. |
| 370 | */ |
| 371 | rtd->dai->cpu_dai->dma_data = dma_params; |
| 372 | |
| 373 | channels = params_channels(params); |
| 374 | |
| 375 | /* |
| 376 | * Determine sample size in bits and the PDC increment. |
| 377 | */ |
| 378 | switch (params_format(params)) { |
| 379 | case SNDRV_PCM_FORMAT_S8: |
| 380 | bits = 8; |
| 381 | dma_params->pdc_xfer_size = 1; |
| 382 | break; |
| 383 | case SNDRV_PCM_FORMAT_S16_LE: |
| 384 | bits = 16; |
| 385 | dma_params->pdc_xfer_size = 2; |
| 386 | break; |
| 387 | case SNDRV_PCM_FORMAT_S24_LE: |
| 388 | bits = 24; |
| 389 | dma_params->pdc_xfer_size = 4; |
| 390 | break; |
| 391 | case SNDRV_PCM_FORMAT_S32_LE: |
| 392 | bits = 32; |
| 393 | dma_params->pdc_xfer_size = 4; |
| 394 | break; |
| 395 | default: |
| 396 | printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); |
| 397 | return -EINVAL; |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * The SSC only supports up to 16-bit samples in I2S format, due |
| 402 | * to the size of the Frame Mode Register FSLEN field. |
| 403 | */ |
| 404 | if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S |
| 405 | && bits > 16) { |
| 406 | printk(KERN_WARNING |
| 407 | "atmel_ssc_dai: sample size %d" |
| 408 | "is too large for I2S\n", bits); |
| 409 | return -EINVAL; |
| 410 | } |
| 411 | |
| 412 | /* |
| 413 | * Compute SSC register settings. |
| 414 | */ |
| 415 | switch (ssc_p->daifmt |
| 416 | & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { |
| 417 | |
| 418 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: |
| 419 | /* |
| 420 | * I2S format, SSC provides BCLK and LRC clocks. |
| 421 | * |
| 422 | * The SSC transmit and receive clocks are generated |
| 423 | * from the MCK divider, and the BCLK signal |
| 424 | * is output on the SSC TK line. |
| 425 | */ |
| 426 | rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) |
| 427 | | SSC_BF(RCMR_STTDLY, START_DELAY) |
| 428 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) |
| 429 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
| 430 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
| 431 | | SSC_BF(RCMR_CKS, SSC_CKS_DIV); |
| 432 | |
| 433 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
| 434 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) |
| 435 | | SSC_BF(RFMR_FSLEN, (bits - 1)) |
| 436 | | SSC_BF(RFMR_DATNB, (channels - 1)) |
| 437 | | SSC_BIT(RFMR_MSBF) |
| 438 | | SSC_BF(RFMR_LOOP, 0) |
| 439 | | SSC_BF(RFMR_DATLEN, (bits - 1)); |
| 440 | |
| 441 | tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) |
| 442 | | SSC_BF(TCMR_STTDLY, START_DELAY) |
| 443 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) |
| 444 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
| 445 | | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) |
| 446 | | SSC_BF(TCMR_CKS, SSC_CKS_DIV); |
| 447 | |
| 448 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
| 449 | | SSC_BF(TFMR_FSDEN, 0) |
| 450 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) |
| 451 | | SSC_BF(TFMR_FSLEN, (bits - 1)) |
| 452 | | SSC_BF(TFMR_DATNB, (channels - 1)) |
| 453 | | SSC_BIT(TFMR_MSBF) |
| 454 | | SSC_BF(TFMR_DATDEF, 0) |
| 455 | | SSC_BF(TFMR_DATLEN, (bits - 1)); |
| 456 | break; |
| 457 | |
| 458 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: |
| 459 | /* |
| 460 | * I2S format, CODEC supplies BCLK and LRC clocks. |
| 461 | * |
| 462 | * The SSC transmit clock is obtained from the BCLK signal on |
| 463 | * on the TK line, and the SSC receive clock is |
| 464 | * generated from the transmit clock. |
| 465 | * |
| 466 | * For single channel data, one sample is transferred |
| 467 | * on the falling edge of the LRC clock. |
| 468 | * For two channel data, one sample is |
| 469 | * transferred on both edges of the LRC clock. |
| 470 | */ |
| 471 | start_event = ((channels == 1) |
| 472 | ? SSC_START_FALLING_RF |
| 473 | : SSC_START_EDGE_RF); |
| 474 | |
| 475 | rcmr = SSC_BF(RCMR_PERIOD, 0) |
| 476 | | SSC_BF(RCMR_STTDLY, START_DELAY) |
| 477 | | SSC_BF(RCMR_START, start_event) |
| 478 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
| 479 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
| 480 | | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK); |
| 481 | |
| 482 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
| 483 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) |
| 484 | | SSC_BF(RFMR_FSLEN, 0) |
| 485 | | SSC_BF(RFMR_DATNB, 0) |
| 486 | | SSC_BIT(RFMR_MSBF) |
| 487 | | SSC_BF(RFMR_LOOP, 0) |
| 488 | | SSC_BF(RFMR_DATLEN, (bits - 1)); |
| 489 | |
| 490 | tcmr = SSC_BF(TCMR_PERIOD, 0) |
| 491 | | SSC_BF(TCMR_STTDLY, START_DELAY) |
| 492 | | SSC_BF(TCMR_START, start_event) |
| 493 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
| 494 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) |
| 495 | | SSC_BF(TCMR_CKS, SSC_CKS_PIN); |
| 496 | |
| 497 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
| 498 | | SSC_BF(TFMR_FSDEN, 0) |
| 499 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) |
| 500 | | SSC_BF(TFMR_FSLEN, 0) |
| 501 | | SSC_BF(TFMR_DATNB, 0) |
| 502 | | SSC_BIT(TFMR_MSBF) |
| 503 | | SSC_BF(TFMR_DATDEF, 0) |
| 504 | | SSC_BF(TFMR_DATLEN, (bits - 1)); |
| 505 | break; |
| 506 | |
| 507 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: |
| 508 | /* |
| 509 | * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. |
| 510 | * |
| 511 | * The SSC transmit and receive clocks are generated from the |
| 512 | * MCK divider, and the BCLK signal is output |
| 513 | * on the SSC TK line. |
| 514 | */ |
| 515 | rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) |
| 516 | | SSC_BF(RCMR_STTDLY, 1) |
| 517 | | SSC_BF(RCMR_START, SSC_START_RISING_RF) |
| 518 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
| 519 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
| 520 | | SSC_BF(RCMR_CKS, SSC_CKS_DIV); |
| 521 | |
| 522 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
| 523 | | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) |
| 524 | | SSC_BF(RFMR_FSLEN, 0) |
| 525 | | SSC_BF(RFMR_DATNB, (channels - 1)) |
| 526 | | SSC_BIT(RFMR_MSBF) |
| 527 | | SSC_BF(RFMR_LOOP, 0) |
| 528 | | SSC_BF(RFMR_DATLEN, (bits - 1)); |
| 529 | |
| 530 | tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) |
| 531 | | SSC_BF(TCMR_STTDLY, 1) |
| 532 | | SSC_BF(TCMR_START, SSC_START_RISING_RF) |
| 533 | | SSC_BF(TCMR_CKI, SSC_CKI_RISING) |
| 534 | | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) |
| 535 | | SSC_BF(TCMR_CKS, SSC_CKS_DIV); |
| 536 | |
| 537 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) |
| 538 | | SSC_BF(TFMR_FSDEN, 0) |
| 539 | | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) |
| 540 | | SSC_BF(TFMR_FSLEN, 0) |
| 541 | | SSC_BF(TFMR_DATNB, (channels - 1)) |
| 542 | | SSC_BIT(TFMR_MSBF) |
| 543 | | SSC_BF(TFMR_DATDEF, 0) |
| 544 | | SSC_BF(TFMR_DATLEN, (bits - 1)); |
| 545 | break; |
| 546 | |
| 547 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: |
| 548 | default: |
| 549 | printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", |
| 550 | ssc_p->daifmt); |
| 551 | return -EINVAL; |
| 552 | break; |
| 553 | } |
| 554 | pr_debug("atmel_ssc_hw_params: " |
| 555 | "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", |
| 556 | rcmr, rfmr, tcmr, tfmr); |
| 557 | |
| 558 | if (!ssc_p->initialized) { |
| 559 | |
| 560 | /* Enable PMC peripheral clock for this SSC */ |
| 561 | pr_debug("atmel_ssc_dai: Starting clock\n"); |
| 562 | clk_enable(ssc_p->ssc->clk); |
| 563 | |
| 564 | /* Reset the SSC and its PDC registers */ |
| 565 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); |
| 566 | |
| 567 | ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); |
| 568 | ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); |
| 569 | ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); |
| 570 | ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); |
| 571 | |
| 572 | ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); |
| 573 | ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); |
| 574 | ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); |
| 575 | ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); |
| 576 | |
| 577 | ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, |
| 578 | ssc_p->name, ssc_p); |
| 579 | if (ret < 0) { |
| 580 | printk(KERN_WARNING |
| 581 | "atmel_ssc_dai: request_irq failure\n"); |
| 582 | pr_debug("Atmel_ssc_dai: Stoping clock\n"); |
| 583 | clk_disable(ssc_p->ssc->clk); |
| 584 | return ret; |
| 585 | } |
| 586 | |
| 587 | ssc_p->initialized = 1; |
| 588 | } |
| 589 | |
| 590 | /* set SSC clock mode register */ |
| 591 | ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); |
| 592 | |
| 593 | /* set receive clock mode and format */ |
| 594 | ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); |
| 595 | ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); |
| 596 | |
| 597 | /* set transmit clock mode and format */ |
| 598 | ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); |
| 599 | ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); |
| 600 | |
| 601 | pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); |
| 602 | return 0; |
| 603 | } |
| 604 | |
| 605 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 606 | static int atmel_ssc_prepare(struct snd_pcm_substream *substream, |
| 607 | struct snd_soc_dai *dai) |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 608 | { |
| 609 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); |
| 610 | struct atmel_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id]; |
| 611 | struct atmel_pcm_dma_params *dma_params; |
| 612 | int dir; |
| 613 | |
| 614 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 615 | dir = 0; |
| 616 | else |
| 617 | dir = 1; |
| 618 | |
| 619 | dma_params = ssc_p->dma_params[dir]; |
| 620 | |
| 621 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); |
| 622 | |
| 623 | pr_debug("%s enabled SSC_SR=0x%08x\n", |
| 624 | dir ? "receive" : "transmit", |
| 625 | ssc_readl(ssc_p->ssc->regs, SR)); |
| 626 | return 0; |
| 627 | } |
| 628 | |
| 629 | |
| 630 | #ifdef CONFIG_PM |
Mark Brown | dc7d7b8 | 2008-12-03 18:21:52 +0000 | [diff] [blame] | 631 | static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 632 | { |
| 633 | struct atmel_ssc_info *ssc_p; |
| 634 | |
| 635 | if (!cpu_dai->active) |
| 636 | return 0; |
| 637 | |
| 638 | ssc_p = &ssc_info[cpu_dai->id]; |
| 639 | |
| 640 | /* Save the status register before disabling transmit and receive */ |
| 641 | ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); |
| 642 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); |
| 643 | |
| 644 | /* Save the current interrupt mask, then disable unmasked interrupts */ |
| 645 | ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); |
| 646 | ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); |
| 647 | |
| 648 | ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); |
| 649 | ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); |
| 650 | ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); |
| 651 | ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); |
| 652 | ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); |
| 653 | |
| 654 | return 0; |
| 655 | } |
| 656 | |
| 657 | |
| 658 | |
Mark Brown | dc7d7b8 | 2008-12-03 18:21:52 +0000 | [diff] [blame] | 659 | static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 660 | { |
| 661 | struct atmel_ssc_info *ssc_p; |
| 662 | u32 cr; |
| 663 | |
| 664 | if (!cpu_dai->active) |
| 665 | return 0; |
| 666 | |
| 667 | ssc_p = &ssc_info[cpu_dai->id]; |
| 668 | |
| 669 | /* restore SSC register settings */ |
| 670 | ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); |
| 671 | ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); |
| 672 | ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); |
| 673 | ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); |
| 674 | ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); |
| 675 | |
| 676 | /* re-enable interrupts */ |
| 677 | ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); |
| 678 | |
| 679 | /* Re-enable recieve and transmit as appropriate */ |
| 680 | cr = 0; |
| 681 | cr |= |
| 682 | (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; |
| 683 | cr |= |
| 684 | (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; |
| 685 | ssc_writel(ssc_p->ssc->regs, CR, cr); |
| 686 | |
| 687 | return 0; |
| 688 | } |
| 689 | #else /* CONFIG_PM */ |
| 690 | # define atmel_ssc_suspend NULL |
| 691 | # define atmel_ssc_resume NULL |
| 692 | #endif /* CONFIG_PM */ |
| 693 | |
| 694 | |
| 695 | #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000) |
| 696 | |
| 697 | #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ |
| 698 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 699 | |
| 700 | struct snd_soc_dai atmel_ssc_dai[NUM_SSC_DEVICES] = { |
| 701 | { .name = "atmel-ssc0", |
| 702 | .id = 0, |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 703 | .suspend = atmel_ssc_suspend, |
| 704 | .resume = atmel_ssc_resume, |
| 705 | .playback = { |
| 706 | .channels_min = 1, |
| 707 | .channels_max = 2, |
| 708 | .rates = ATMEL_SSC_RATES, |
| 709 | .formats = ATMEL_SSC_FORMATS,}, |
| 710 | .capture = { |
| 711 | .channels_min = 1, |
| 712 | .channels_max = 2, |
| 713 | .rates = ATMEL_SSC_RATES, |
| 714 | .formats = ATMEL_SSC_FORMATS,}, |
| 715 | .ops = { |
| 716 | .startup = atmel_ssc_startup, |
| 717 | .shutdown = atmel_ssc_shutdown, |
| 718 | .prepare = atmel_ssc_prepare, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 719 | .hw_params = atmel_ssc_hw_params, |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 720 | .set_fmt = atmel_ssc_set_dai_fmt, |
| 721 | .set_clkdiv = atmel_ssc_set_dai_clkdiv,}, |
| 722 | .private_data = &ssc_info[0], |
| 723 | }, |
| 724 | #if NUM_SSC_DEVICES == 3 |
| 725 | { .name = "atmel-ssc1", |
| 726 | .id = 1, |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 727 | .suspend = atmel_ssc_suspend, |
| 728 | .resume = atmel_ssc_resume, |
| 729 | .playback = { |
| 730 | .channels_min = 1, |
| 731 | .channels_max = 2, |
| 732 | .rates = ATMEL_SSC_RATES, |
| 733 | .formats = ATMEL_SSC_FORMATS,}, |
| 734 | .capture = { |
| 735 | .channels_min = 1, |
| 736 | .channels_max = 2, |
| 737 | .rates = ATMEL_SSC_RATES, |
| 738 | .formats = ATMEL_SSC_FORMATS,}, |
| 739 | .ops = { |
| 740 | .startup = atmel_ssc_startup, |
| 741 | .shutdown = atmel_ssc_shutdown, |
| 742 | .prepare = atmel_ssc_prepare, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 743 | .hw_params = atmel_ssc_hw_params, |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 744 | .set_fmt = atmel_ssc_set_dai_fmt, |
| 745 | .set_clkdiv = atmel_ssc_set_dai_clkdiv,}, |
| 746 | .private_data = &ssc_info[1], |
| 747 | }, |
| 748 | { .name = "atmel-ssc2", |
| 749 | .id = 2, |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 750 | .suspend = atmel_ssc_suspend, |
| 751 | .resume = atmel_ssc_resume, |
| 752 | .playback = { |
| 753 | .channels_min = 1, |
| 754 | .channels_max = 2, |
| 755 | .rates = ATMEL_SSC_RATES, |
| 756 | .formats = ATMEL_SSC_FORMATS,}, |
| 757 | .capture = { |
| 758 | .channels_min = 1, |
| 759 | .channels_max = 2, |
| 760 | .rates = ATMEL_SSC_RATES, |
| 761 | .formats = ATMEL_SSC_FORMATS,}, |
| 762 | .ops = { |
| 763 | .startup = atmel_ssc_startup, |
| 764 | .shutdown = atmel_ssc_shutdown, |
| 765 | .prepare = atmel_ssc_prepare, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 766 | .hw_params = atmel_ssc_hw_params, |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 767 | .set_fmt = atmel_ssc_set_dai_fmt, |
| 768 | .set_clkdiv = atmel_ssc_set_dai_clkdiv,}, |
| 769 | .private_data = &ssc_info[2], |
| 770 | }, |
| 771 | #endif |
| 772 | }; |
| 773 | EXPORT_SYMBOL_GPL(atmel_ssc_dai); |
| 774 | |
Takashi Iwai | c9b3a40 | 2008-12-10 07:47:22 +0100 | [diff] [blame] | 775 | static int __init atmel_ssc_modinit(void) |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 776 | { |
| 777 | return snd_soc_register_dais(atmel_ssc_dai, ARRAY_SIZE(atmel_ssc_dai)); |
| 778 | } |
Mark Brown | 471716f | 2008-12-09 14:47:07 +0000 | [diff] [blame] | 779 | module_init(atmel_ssc_modinit); |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 780 | |
Mark Brown | 471716f | 2008-12-09 14:47:07 +0000 | [diff] [blame] | 781 | static void __exit atmel_ssc_modexit(void) |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 782 | { |
| 783 | snd_soc_unregister_dais(atmel_ssc_dai, ARRAY_SIZE(atmel_ssc_dai)); |
| 784 | } |
Mark Brown | 471716f | 2008-12-09 14:47:07 +0000 | [diff] [blame] | 785 | module_exit(atmel_ssc_modexit); |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 786 | |
Sedji Gaouaou | 6c74250 | 2008-10-03 16:57:50 +0200 | [diff] [blame] | 787 | /* Module information */ |
| 788 | MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com"); |
| 789 | MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); |
| 790 | MODULE_LICENSE("GPL"); |