blob: bd6983d1afbac77ed852c8991cb7b653d4272128 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100011 * Right now, I am very wasteful with the buffers. I allocate memory
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets.
17 *
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
20 *
Greg Ungerer562d2f82005-11-07 14:09:50 +100021 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100023 *
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2005 Macq Electronique SA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070026 */
27
28#include <linux/config.h>
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/string.h>
32#include <linux/ptrace.h>
33#include <linux/errno.h>
34#include <linux/ioport.h>
35#include <linux/slab.h>
36#include <linux/interrupt.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/skbuff.h>
43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
46
47#include <asm/irq.h>
48#include <asm/uaccess.h>
49#include <asm/io.h>
50#include <asm/pgtable.h>
51
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100052#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
Greg Ungerer562d2f82005-11-07 14:09:50 +100053 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
54 defined(CONFIG_M520x)
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include <asm/coldfire.h>
56#include <asm/mcfsim.h>
57#include "fec.h"
58#else
59#include <asm/8xx_immap.h>
60#include <asm/mpc8xx.h>
61#include "commproc.h"
62#endif
63
64#if defined(CONFIG_FEC2)
65#define FEC_MAX_PORTS 2
66#else
67#define FEC_MAX_PORTS 1
68#endif
69
70/*
71 * Define the fixed address of the FEC hardware.
72 */
73static unsigned int fec_hw[] = {
74#if defined(CONFIG_M5272)
75 (MCF_MBAR + 0x840),
76#elif defined(CONFIG_M527x)
77 (MCF_MBAR + 0x1000),
78 (MCF_MBAR + 0x1800),
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +100079#elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 (MCF_MBAR + 0x1000),
Greg Ungerer562d2f82005-11-07 14:09:50 +100081#elif defined(CONFIG_M520x)
82 (MCF_MBAR+0x30000),
Linus Torvalds1da177e2005-04-16 15:20:36 -070083#else
84 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
85#endif
86};
87
88static unsigned char fec_mac_default[] = {
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90};
91
92/*
93 * Some hardware gets it MAC address out of local flash memory.
94 * if this is non-zero then assume it is the address to get MAC from.
95 */
96#if defined(CONFIG_NETtel)
97#define FEC_FLASHMAC 0xf0006006
98#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
99#define FEC_FLASHMAC 0xf0006000
100#elif defined (CONFIG_MTD_KeyTechnology)
101#define FEC_FLASHMAC 0xffe04000
102#elif defined(CONFIG_CANCam)
103#define FEC_FLASHMAC 0xf0020000
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000104#elif defined (CONFIG_M5272C3)
105#define FEC_FLASHMAC (0xffe04000 + 4)
106#elif defined(CONFIG_MOD5272)
107#define FEC_FLASHMAC 0xffc0406b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108#else
109#define FEC_FLASHMAC 0
110#endif
111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112/* Forward declarations of some structures to support different PHYs
113*/
114
115typedef struct {
116 uint mii_data;
117 void (*funct)(uint mii_reg, struct net_device *dev);
118} phy_cmd_t;
119
120typedef struct {
121 uint id;
122 char *name;
123
124 const phy_cmd_t *config;
125 const phy_cmd_t *startup;
126 const phy_cmd_t *ack_int;
127 const phy_cmd_t *shutdown;
128} phy_info_t;
129
130/* The number of Tx and Rx buffers. These are allocated from the page
131 * pool. The code may assume these are power of two, so it it best
132 * to keep them that size.
133 * We don't need to allocate pages for the transmitter. We just use
134 * the skbuffer directly.
135 */
136#define FEC_ENET_RX_PAGES 8
137#define FEC_ENET_RX_FRSIZE 2048
138#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
139#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
140#define FEC_ENET_TX_FRSIZE 2048
141#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
142#define TX_RING_SIZE 16 /* Must be power of two */
143#define TX_RING_MOD_MASK 15 /* for this to work */
144
Greg Ungerer562d2f82005-11-07 14:09:50 +1000145#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
146#error "FEC: descriptor ring size contants too large"
147#endif
148
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149/* Interrupt events/masks.
150*/
151#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
152#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
153#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
154#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
155#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
156#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
157#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
158#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
159#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
160#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
161
162/* The FEC stores dest/src/type, data, and checksum for receive packets.
163 */
164#define PKT_MAXBUF_SIZE 1518
165#define PKT_MINBUF_SIZE 64
166#define PKT_MAXBLR_SIZE 1520
167
168
169/*
170 * The 5270/5271/5280/5282 RX control register also contains maximum frame
171 * size bits. Other FEC hardware does not, so we need to take that into
172 * account when setting it.
173 */
Greg Ungerer562d2f82005-11-07 14:09:50 +1000174#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
175 defined(CONFIG_M520x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
177#else
178#define OPT_FRAME_SIZE 0
179#endif
180
181/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
182 * tx_bd_base always point to the base of the buffer descriptors. The
183 * cur_rx and cur_tx point to the currently available buffer.
184 * The dirty_tx tracks the current buffer that is being sent by the
185 * controller. The cur_tx and dirty_tx are equal under both completely
186 * empty and completely full conditions. The empty/ready indicator in
187 * the buffer descriptor determines the actual condition.
188 */
189struct fec_enet_private {
190 /* Hardware registers of the FEC device */
191 volatile fec_t *hwp;
192
193 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
194 unsigned char *tx_bounce[TX_RING_SIZE];
195 struct sk_buff* tx_skbuff[TX_RING_SIZE];
196 ushort skb_cur;
197 ushort skb_dirty;
198
199 /* CPM dual port RAM relative addresses.
200 */
201 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
202 cbd_t *tx_bd_base;
203 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
204 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
205 struct net_device_stats stats;
206 uint tx_full;
207 spinlock_t lock;
208
209 uint phy_id;
210 uint phy_id_done;
211 uint phy_status;
212 uint phy_speed;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000213 phy_info_t const *phy;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 struct work_struct phy_task;
215
216 uint sequence_done;
217 uint mii_phy_task_queued;
218
219 uint phy_addr;
220
221 int index;
222 int opened;
223 int link;
224 int old_link;
225 int full_duplex;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226};
227
228static int fec_enet_open(struct net_device *dev);
229static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
230static void fec_enet_mii(struct net_device *dev);
231static irqreturn_t fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
232static void fec_enet_tx(struct net_device *dev);
233static void fec_enet_rx(struct net_device *dev);
234static int fec_enet_close(struct net_device *dev);
235static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
236static void set_multicast_list(struct net_device *dev);
237static void fec_restart(struct net_device *dev, int duplex);
238static void fec_stop(struct net_device *dev);
239static void fec_set_mac_address(struct net_device *dev);
240
241
242/* MII processing. We keep this as simple as possible. Requests are
243 * placed on the list (if there is room). When the request is finished
244 * by the MII, an optional function may be called.
245 */
246typedef struct mii_list {
247 uint mii_regval;
248 void (*mii_func)(uint val, struct net_device *dev);
249 struct mii_list *mii_next;
250} mii_list_t;
251
252#define NMII 20
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000253static mii_list_t mii_cmds[NMII];
254static mii_list_t *mii_free;
255static mii_list_t *mii_head;
256static mii_list_t *mii_tail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257
258static int mii_queue(struct net_device *dev, int request,
259 void (*func)(uint, struct net_device *));
260
261/* Make MII read/write commands for the FEC.
262*/
263#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
264#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
265 (VAL & 0xffff))
266#define mk_mii_end 0
267
268/* Transmitter timeout.
269*/
270#define TX_TIMEOUT (2*HZ)
271
272/* Register definitions for the PHY.
273*/
274
275#define MII_REG_CR 0 /* Control Register */
276#define MII_REG_SR 1 /* Status Register */
277#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
278#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
279#define MII_REG_ANAR 4 /* A-N Advertisement Register */
280#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
281#define MII_REG_ANER 6 /* A-N Expansion Register */
282#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
283#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
284
285/* values for phy_status */
286
287#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
288#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
289#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
290#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
291#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
292#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
293#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
294
295#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
296#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
297#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
298#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
299#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
300#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
301#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
302#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
303
304
305static int
306fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
307{
308 struct fec_enet_private *fep;
309 volatile fec_t *fecp;
310 volatile cbd_t *bdp;
311
312 fep = netdev_priv(dev);
313 fecp = (volatile fec_t*)dev->base_addr;
314
315 if (!fep->link) {
316 /* Link is down or autonegotiation is in progress. */
317 return 1;
318 }
319
320 /* Fill in a Tx ring entry */
321 bdp = fep->cur_tx;
322
323#ifndef final_version
324 if (bdp->cbd_sc & BD_ENET_TX_READY) {
325 /* Ooops. All transmit buffers are full. Bail out.
326 * This should not happen, since dev->tbusy should be set.
327 */
328 printk("%s: tx queue full!.\n", dev->name);
329 return 1;
330 }
331#endif
332
333 /* Clear all of the status flags.
334 */
335 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
336
337 /* Set buffer length and buffer pointer.
338 */
339 bdp->cbd_bufaddr = __pa(skb->data);
340 bdp->cbd_datlen = skb->len;
341
342 /*
343 * On some FEC implementations data must be aligned on
344 * 4-byte boundaries. Use bounce buffers to copy data
345 * and get it aligned. Ugh.
346 */
347 if (bdp->cbd_bufaddr & 0x3) {
348 unsigned int index;
349 index = bdp - fep->tx_bd_base;
350 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
351 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
352 }
353
354 /* Save skb pointer.
355 */
356 fep->tx_skbuff[fep->skb_cur] = skb;
357
358 fep->stats.tx_bytes += skb->len;
359 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
360
361 /* Push the data cache so the CPM does not get stale memory
362 * data.
363 */
364 flush_dcache_range((unsigned long)skb->data,
365 (unsigned long)skb->data + skb->len);
366
367 spin_lock_irq(&fep->lock);
368
369 /* Send it on its way. Tell FEC its ready, interrupt when done,
370 * its the last BD of the frame, and to put the CRC on the end.
371 */
372
373 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
374 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
375
376 dev->trans_start = jiffies;
377
378 /* Trigger transmission start */
379 fecp->fec_x_des_active = 0x01000000;
380
381 /* If this was the last BD in the ring, start at the beginning again.
382 */
383 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
384 bdp = fep->tx_bd_base;
385 } else {
386 bdp++;
387 }
388
389 if (bdp == fep->dirty_tx) {
390 fep->tx_full = 1;
391 netif_stop_queue(dev);
392 }
393
394 fep->cur_tx = (cbd_t *)bdp;
395
396 spin_unlock_irq(&fep->lock);
397
398 return 0;
399}
400
401static void
402fec_timeout(struct net_device *dev)
403{
404 struct fec_enet_private *fep = netdev_priv(dev);
405
406 printk("%s: transmit timed out.\n", dev->name);
407 fep->stats.tx_errors++;
408#ifndef final_version
409 {
410 int i;
411 cbd_t *bdp;
412
413 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
414 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
415 (unsigned long)fep->dirty_tx,
416 (unsigned long)fep->cur_rx);
417
418 bdp = fep->tx_bd_base;
419 printk(" tx: %u buffers\n", TX_RING_SIZE);
420 for (i = 0 ; i < TX_RING_SIZE; i++) {
421 printk(" %08x: %04x %04x %08x\n",
422 (uint) bdp,
423 bdp->cbd_sc,
424 bdp->cbd_datlen,
425 (int) bdp->cbd_bufaddr);
426 bdp++;
427 }
428
429 bdp = fep->rx_bd_base;
430 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
431 for (i = 0 ; i < RX_RING_SIZE; i++) {
432 printk(" %08x: %04x %04x %08x\n",
433 (uint) bdp,
434 bdp->cbd_sc,
435 bdp->cbd_datlen,
436 (int) bdp->cbd_bufaddr);
437 bdp++;
438 }
439 }
440#endif
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000441 fec_restart(dev, fep->full_duplex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 netif_wake_queue(dev);
443}
444
445/* The interrupt handler.
446 * This is called from the MPC core interrupt.
447 */
448static irqreturn_t
449fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
450{
451 struct net_device *dev = dev_id;
452 volatile fec_t *fecp;
453 uint int_events;
454 int handled = 0;
455
456 fecp = (volatile fec_t*)dev->base_addr;
457
458 /* Get the interrupt events that caused us to be here.
459 */
460 while ((int_events = fecp->fec_ievent) != 0) {
461 fecp->fec_ievent = int_events;
462
463 /* Handle receive event in its own function.
464 */
465 if (int_events & FEC_ENET_RXF) {
466 handled = 1;
467 fec_enet_rx(dev);
468 }
469
470 /* Transmit OK, or non-fatal error. Update the buffer
471 descriptors. FEC handles all errors, we just discover
472 them as part of the transmit process.
473 */
474 if (int_events & FEC_ENET_TXF) {
475 handled = 1;
476 fec_enet_tx(dev);
477 }
478
479 if (int_events & FEC_ENET_MII) {
480 handled = 1;
481 fec_enet_mii(dev);
482 }
483
484 }
485 return IRQ_RETVAL(handled);
486}
487
488
489static void
490fec_enet_tx(struct net_device *dev)
491{
492 struct fec_enet_private *fep;
493 volatile cbd_t *bdp;
494 struct sk_buff *skb;
495
496 fep = netdev_priv(dev);
497 spin_lock(&fep->lock);
498 bdp = fep->dirty_tx;
499
500 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
501 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
502
503 skb = fep->tx_skbuff[fep->skb_dirty];
504 /* Check for errors. */
505 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
506 BD_ENET_TX_RL | BD_ENET_TX_UN |
507 BD_ENET_TX_CSL)) {
508 fep->stats.tx_errors++;
509 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
510 fep->stats.tx_heartbeat_errors++;
511 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
512 fep->stats.tx_window_errors++;
513 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
514 fep->stats.tx_aborted_errors++;
515 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
516 fep->stats.tx_fifo_errors++;
517 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
518 fep->stats.tx_carrier_errors++;
519 } else {
520 fep->stats.tx_packets++;
521 }
522
523#ifndef final_version
524 if (bdp->cbd_sc & BD_ENET_TX_READY)
525 printk("HEY! Enet xmit interrupt and TX_READY.\n");
526#endif
527 /* Deferred means some collisions occurred during transmit,
528 * but we eventually sent the packet OK.
529 */
530 if (bdp->cbd_sc & BD_ENET_TX_DEF)
531 fep->stats.collisions++;
532
533 /* Free the sk buffer associated with this last transmit.
534 */
535 dev_kfree_skb_any(skb);
536 fep->tx_skbuff[fep->skb_dirty] = NULL;
537 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
538
539 /* Update pointer to next buffer descriptor to be transmitted.
540 */
541 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
542 bdp = fep->tx_bd_base;
543 else
544 bdp++;
545
546 /* Since we have freed up a buffer, the ring is no longer
547 * full.
548 */
549 if (fep->tx_full) {
550 fep->tx_full = 0;
551 if (netif_queue_stopped(dev))
552 netif_wake_queue(dev);
553 }
554 }
555 fep->dirty_tx = (cbd_t *)bdp;
556 spin_unlock(&fep->lock);
557}
558
559
560/* During a receive, the cur_rx points to the current incoming buffer.
561 * When we update through the ring, if the next incoming buffer has
562 * not been given to the system, we just set the empty indicator,
563 * effectively tossing the packet.
564 */
565static void
566fec_enet_rx(struct net_device *dev)
567{
568 struct fec_enet_private *fep;
569 volatile fec_t *fecp;
570 volatile cbd_t *bdp;
571 struct sk_buff *skb;
572 ushort pkt_len;
573 __u8 *data;
574
575 fep = netdev_priv(dev);
576 fecp = (volatile fec_t*)dev->base_addr;
577
578 /* First, grab all of the stats for the incoming packet.
579 * These get messed up if we get called due to a busy condition.
580 */
581 bdp = fep->cur_rx;
582
583while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
584
585#ifndef final_version
586 /* Since we have allocated space to hold a complete frame,
587 * the last indicator should be set.
588 */
589 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
590 printk("FEC ENET: rcv is not +last\n");
591#endif
592
593 if (!fep->opened)
594 goto rx_processing_done;
595
596 /* Check for errors. */
597 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
598 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
599 fep->stats.rx_errors++;
600 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
601 /* Frame too long or too short. */
602 fep->stats.rx_length_errors++;
603 }
604 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
605 fep->stats.rx_frame_errors++;
606 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
607 fep->stats.rx_crc_errors++;
608 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
609 fep->stats.rx_crc_errors++;
610 }
611
612 /* Report late collisions as a frame error.
613 * On this error, the BD is closed, but we don't know what we
614 * have in the buffer. So, just drop this frame on the floor.
615 */
616 if (bdp->cbd_sc & BD_ENET_RX_CL) {
617 fep->stats.rx_errors++;
618 fep->stats.rx_frame_errors++;
619 goto rx_processing_done;
620 }
621
622 /* Process the incoming frame.
623 */
624 fep->stats.rx_packets++;
625 pkt_len = bdp->cbd_datlen;
626 fep->stats.rx_bytes += pkt_len;
627 data = (__u8*)__va(bdp->cbd_bufaddr);
628
629 /* This does 16 byte alignment, exactly what we need.
630 * The packet length includes FCS, but we don't want to
631 * include that when passing upstream as it messes up
632 * bridging applications.
633 */
634 skb = dev_alloc_skb(pkt_len-4);
635
636 if (skb == NULL) {
637 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
638 fep->stats.rx_dropped++;
639 } else {
640 skb->dev = dev;
641 skb_put(skb,pkt_len-4); /* Make room */
642 eth_copy_and_sum(skb,
643 (unsigned char *)__va(bdp->cbd_bufaddr),
644 pkt_len-4, 0);
645 skb->protocol=eth_type_trans(skb,dev);
646 netif_rx(skb);
647 }
648 rx_processing_done:
649
650 /* Clear the status flags for this buffer.
651 */
652 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
653
654 /* Mark the buffer empty.
655 */
656 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
657
658 /* Update BD pointer to next entry.
659 */
660 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
661 bdp = fep->rx_bd_base;
662 else
663 bdp++;
664
665#if 1
666 /* Doing this here will keep the FEC running while we process
667 * incoming frames. On a heavily loaded network, we should be
668 * able to keep up at the expense of system resources.
669 */
670 fecp->fec_r_des_active = 0x01000000;
671#endif
672 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
673 fep->cur_rx = (cbd_t *)bdp;
674
675#if 0
676 /* Doing this here will allow us to process all frames in the
677 * ring before the FEC is allowed to put more there. On a heavily
678 * loaded network, some frames may be lost. Unfortunately, this
679 * increases the interrupt overhead since we can potentially work
680 * our way back to the interrupt return only to come right back
681 * here.
682 */
683 fecp->fec_r_des_active = 0x01000000;
684#endif
685}
686
687
688static void
689fec_enet_mii(struct net_device *dev)
690{
691 struct fec_enet_private *fep;
692 volatile fec_t *ep;
693 mii_list_t *mip;
694 uint mii_reg;
695
696 fep = netdev_priv(dev);
697 ep = fep->hwp;
698 mii_reg = ep->fec_mii_data;
699
700 if ((mip = mii_head) == NULL) {
701 printk("MII and no head!\n");
702 return;
703 }
704
705 if (mip->mii_func != NULL)
706 (*(mip->mii_func))(mii_reg, dev);
707
708 mii_head = mip->mii_next;
709 mip->mii_next = mii_free;
710 mii_free = mip;
711
712 if ((mip = mii_head) != NULL)
713 ep->fec_mii_data = mip->mii_regval;
714}
715
716static int
717mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
718{
719 struct fec_enet_private *fep;
720 unsigned long flags;
721 mii_list_t *mip;
722 int retval;
723
724 /* Add PHY address to register command.
725 */
726 fep = netdev_priv(dev);
727 regval |= fep->phy_addr << 23;
728
729 retval = 0;
730
731 save_flags(flags);
732 cli();
733
734 if ((mip = mii_free) != NULL) {
735 mii_free = mip->mii_next;
736 mip->mii_regval = regval;
737 mip->mii_func = func;
738 mip->mii_next = NULL;
739 if (mii_head) {
740 mii_tail->mii_next = mip;
741 mii_tail = mip;
742 }
743 else {
744 mii_head = mii_tail = mip;
745 fep->hwp->fec_mii_data = regval;
746 }
747 }
748 else {
749 retval = 1;
750 }
751
752 restore_flags(flags);
753
754 return(retval);
755}
756
757static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
758{
759 int k;
760
761 if(!c)
762 return;
763
764 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
765 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
766 }
767}
768
769static void mii_parse_sr(uint mii_reg, struct net_device *dev)
770{
771 struct fec_enet_private *fep = netdev_priv(dev);
772 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000773 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000775 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776
777 if (mii_reg & 0x0004)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000778 status |= PHY_STAT_LINK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 if (mii_reg & 0x0010)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000780 status |= PHY_STAT_FAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 if (mii_reg & 0x0020)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000782 status |= PHY_STAT_ANC;
783
784 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785}
786
787static void mii_parse_cr(uint mii_reg, struct net_device *dev)
788{
789 struct fec_enet_private *fep = netdev_priv(dev);
790 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000791 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000793 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794
795 if (mii_reg & 0x1000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000796 status |= PHY_CONF_ANE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 if (mii_reg & 0x4000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000798 status |= PHY_CONF_LOOP;
799 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800}
801
802static void mii_parse_anar(uint mii_reg, struct net_device *dev)
803{
804 struct fec_enet_private *fep = netdev_priv(dev);
805 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000806 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000808 status = *s & ~(PHY_CONF_SPMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809
810 if (mii_reg & 0x0020)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000811 status |= PHY_CONF_10HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812 if (mii_reg & 0x0040)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000813 status |= PHY_CONF_10FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 if (mii_reg & 0x0080)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000815 status |= PHY_CONF_100HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 if (mii_reg & 0x00100)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000817 status |= PHY_CONF_100FDX;
818 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819}
820
821/* ------------------------------------------------------------------------- */
822/* The Level one LXT970 is used by many boards */
823
824#define MII_LXT970_MIRROR 16 /* Mirror register */
825#define MII_LXT970_IER 17 /* Interrupt Enable Register */
826#define MII_LXT970_ISR 18 /* Interrupt Status Register */
827#define MII_LXT970_CONFIG 19 /* Configuration Register */
828#define MII_LXT970_CSR 20 /* Chip Status Register */
829
830static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
831{
832 struct fec_enet_private *fep = netdev_priv(dev);
833 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000834 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000836 status = *s & ~(PHY_STAT_SPMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 if (mii_reg & 0x0800) {
838 if (mii_reg & 0x1000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000839 status |= PHY_STAT_100FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000841 status |= PHY_STAT_100HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 } else {
843 if (mii_reg & 0x1000)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000844 status |= PHY_STAT_10FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000846 status |= PHY_STAT_10HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000848 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849}
850
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000851static phy_cmd_t const phy_cmd_lxt970_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 { mk_mii_read(MII_REG_CR), mii_parse_cr },
853 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
854 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000855 };
856static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
858 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
859 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000860 };
861static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 /* read SR and ISR to acknowledge */
863 { mk_mii_read(MII_REG_SR), mii_parse_sr },
864 { mk_mii_read(MII_LXT970_ISR), NULL },
865
866 /* find out the current status */
867 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
868 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000869 };
870static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
872 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000873 };
874static phy_info_t const phy_info_lxt970 = {
875 .id = 0x07810000,
876 .name = "LXT970",
877 .config = phy_cmd_lxt970_config,
878 .startup = phy_cmd_lxt970_startup,
879 .ack_int = phy_cmd_lxt970_ack_int,
880 .shutdown = phy_cmd_lxt970_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881};
882
883/* ------------------------------------------------------------------------- */
884/* The Level one LXT971 is used on some of my custom boards */
885
886/* register definitions for the 971 */
887
888#define MII_LXT971_PCR 16 /* Port Control Register */
889#define MII_LXT971_SR2 17 /* Status Register 2 */
890#define MII_LXT971_IER 18 /* Interrupt Enable Register */
891#define MII_LXT971_ISR 19 /* Interrupt Status Register */
892#define MII_LXT971_LCR 20 /* LED Control Register */
893#define MII_LXT971_TCR 30 /* Transmit Control Register */
894
895/*
896 * I had some nice ideas of running the MDIO faster...
897 * The 971 should support 8MHz and I tried it, but things acted really
898 * weird, so 2.5 MHz ought to be enough for anyone...
899 */
900
901static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
902{
903 struct fec_enet_private *fep = netdev_priv(dev);
904 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000905 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000907 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908
909 if (mii_reg & 0x0400) {
910 fep->link = 1;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000911 status |= PHY_STAT_LINK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912 } else {
913 fep->link = 0;
914 }
915 if (mii_reg & 0x0080)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000916 status |= PHY_STAT_ANC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917 if (mii_reg & 0x4000) {
918 if (mii_reg & 0x0200)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000919 status |= PHY_STAT_100FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000921 status |= PHY_STAT_100HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 } else {
923 if (mii_reg & 0x0200)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000924 status |= PHY_STAT_10FDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000926 status |= PHY_STAT_10HDX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 }
928 if (mii_reg & 0x0008)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000929 status |= PHY_STAT_FAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000931 *s = status;
932}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000934static phy_cmd_t const phy_cmd_lxt971_config[] = {
935 /* limit to 10MBit because my prototype board
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936 * doesn't work with 100. */
937 { mk_mii_read(MII_REG_CR), mii_parse_cr },
938 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
939 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
940 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000941 };
942static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
944 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
945 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
946 /* Somehow does the 971 tell me that the link is down
947 * the first read after power-up.
948 * read here to get a valid value in ack_int */
949 { mk_mii_read(MII_REG_SR), mii_parse_sr },
950 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000951 };
952static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
953 /* acknowledge the int before reading status ! */
954 { mk_mii_read(MII_LXT971_ISR), NULL },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700955 /* find out the current status */
956 { mk_mii_read(MII_REG_SR), mii_parse_sr },
957 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700958 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000959 };
960static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
962 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000963 };
964static phy_info_t const phy_info_lxt971 = {
965 .id = 0x0001378e,
966 .name = "LXT971",
967 .config = phy_cmd_lxt971_config,
968 .startup = phy_cmd_lxt971_startup,
969 .ack_int = phy_cmd_lxt971_ack_int,
970 .shutdown = phy_cmd_lxt971_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971};
972
973/* ------------------------------------------------------------------------- */
974/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
975
976/* register definitions */
977
978#define MII_QS6612_MCR 17 /* Mode Control Register */
979#define MII_QS6612_FTR 27 /* Factory Test Register */
980#define MII_QS6612_MCO 28 /* Misc. Control Register */
981#define MII_QS6612_ISR 29 /* Interrupt Source Register */
982#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
983#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
984
985static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
986{
987 struct fec_enet_private *fep = netdev_priv(dev);
988 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000989 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000991 status = *s & ~(PHY_STAT_SPMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992
993 switch((mii_reg >> 2) & 7) {
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +1000994 case 1: status |= PHY_STAT_10HDX; break;
995 case 2: status |= PHY_STAT_100HDX; break;
996 case 5: status |= PHY_STAT_10FDX; break;
997 case 6: status |= PHY_STAT_100FDX; break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998}
999
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001000 *s = status;
1001}
1002
1003static phy_cmd_t const phy_cmd_qs6612_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 /* The PHY powers up isolated on the RPX,
1005 * so send a command to allow operation.
1006 */
1007 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1008
1009 /* parse cr and anar to get some info */
1010 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1011 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1012 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001013 };
1014static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1016 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1017 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001018 };
1019static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 /* we need to read ISR, SR and ANER to acknowledge */
1021 { mk_mii_read(MII_QS6612_ISR), NULL },
1022 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1023 { mk_mii_read(MII_REG_ANER), NULL },
1024
1025 /* read pcr to get info */
1026 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1027 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001028 };
1029static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1031 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001032 };
1033static phy_info_t const phy_info_qs6612 = {
1034 .id = 0x00181440,
1035 .name = "QS6612",
1036 .config = phy_cmd_qs6612_config,
1037 .startup = phy_cmd_qs6612_startup,
1038 .ack_int = phy_cmd_qs6612_ack_int,
1039 .shutdown = phy_cmd_qs6612_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040};
1041
1042/* ------------------------------------------------------------------------- */
1043/* AMD AM79C874 phy */
1044
1045/* register definitions for the 874 */
1046
1047#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1048#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1049#define MII_AM79C874_DR 18 /* Diagnostic Register */
1050#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1051#define MII_AM79C874_MCR 21 /* ModeControl Register */
1052#define MII_AM79C874_DC 23 /* Disconnect Counter */
1053#define MII_AM79C874_REC 24 /* Recieve Error Counter */
1054
1055static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1056{
1057 struct fec_enet_private *fep = netdev_priv(dev);
1058 volatile uint *s = &(fep->phy_status);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001059 uint status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001061 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062
1063 if (mii_reg & 0x0080)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001064 status |= PHY_STAT_ANC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065 if (mii_reg & 0x0400)
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001066 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067 else
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001068 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1069
1070 *s = status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071}
1072
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001073static phy_cmd_t const phy_cmd_am79c874_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1075 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1076 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1077 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001078 };
1079static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1081 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1082 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1083 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001084 };
1085static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 /* find out the current status */
1087 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1088 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1089 /* we only need to read ISR to acknowledge */
1090 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1091 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001092 };
1093static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1095 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001096 };
1097static phy_info_t const phy_info_am79c874 = {
1098 .id = 0x00022561,
1099 .name = "AM79C874",
1100 .config = phy_cmd_am79c874_config,
1101 .startup = phy_cmd_am79c874_startup,
1102 .ack_int = phy_cmd_am79c874_ack_int,
1103 .shutdown = phy_cmd_am79c874_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104};
1105
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001106
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107/* ------------------------------------------------------------------------- */
1108/* Kendin KS8721BL phy */
1109
1110/* register definitions for the 8721 */
1111
1112#define MII_KS8721BL_RXERCR 21
1113#define MII_KS8721BL_ICSR 22
1114#define MII_KS8721BL_PHYCR 31
1115
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001116static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1118 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1119 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001120 };
1121static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1123 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1124 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1125 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001126 };
1127static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128 /* find out the current status */
1129 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1130 /* we only need to read ISR to acknowledge */
1131 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1132 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001133 };
1134static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1136 { mk_mii_end, }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001137 };
1138static phy_info_t const phy_info_ks8721bl = {
1139 .id = 0x00022161,
1140 .name = "KS8721BL",
1141 .config = phy_cmd_ks8721bl_config,
1142 .startup = phy_cmd_ks8721bl_startup,
1143 .ack_int = phy_cmd_ks8721bl_ack_int,
1144 .shutdown = phy_cmd_ks8721bl_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145};
1146
1147/* ------------------------------------------------------------------------- */
Greg Ungerer562d2f82005-11-07 14:09:50 +10001148/* register definitions for the DP83848 */
1149
1150#define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1151
1152static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1153{
1154 struct fec_enet_private *fep = dev->priv;
1155 volatile uint *s = &(fep->phy_status);
1156
1157 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1158
1159 /* Link up */
1160 if (mii_reg & 0x0001) {
1161 fep->link = 1;
1162 *s |= PHY_STAT_LINK;
1163 } else
1164 fep->link = 0;
1165 /* Status of link */
1166 if (mii_reg & 0x0010) /* Autonegotioation complete */
1167 *s |= PHY_STAT_ANC;
1168 if (mii_reg & 0x0002) { /* 10MBps? */
1169 if (mii_reg & 0x0004) /* Full Duplex? */
1170 *s |= PHY_STAT_10FDX;
1171 else
1172 *s |= PHY_STAT_10HDX;
1173 } else { /* 100 Mbps? */
1174 if (mii_reg & 0x0004) /* Full Duplex? */
1175 *s |= PHY_STAT_100FDX;
1176 else
1177 *s |= PHY_STAT_100HDX;
1178 }
1179 if (mii_reg & 0x0008)
1180 *s |= PHY_STAT_FAULT;
1181}
1182
1183static phy_info_t phy_info_dp83848= {
1184 0x020005c9,
1185 "DP83848",
1186
1187 (const phy_cmd_t []) { /* config */
1188 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1189 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1190 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1191 { mk_mii_end, }
1192 },
1193 (const phy_cmd_t []) { /* startup - enable interrupts */
1194 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1195 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1196 { mk_mii_end, }
1197 },
1198 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1199 { mk_mii_end, }
1200 },
1201 (const phy_cmd_t []) { /* shutdown */
1202 { mk_mii_end, }
1203 },
1204};
1205
1206/* ------------------------------------------------------------------------- */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001207
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001208static phy_info_t const * const phy_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 &phy_info_lxt970,
1210 &phy_info_lxt971,
1211 &phy_info_qs6612,
1212 &phy_info_am79c874,
1213 &phy_info_ks8721bl,
Greg Ungerer562d2f82005-11-07 14:09:50 +10001214 &phy_info_dp83848,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215 NULL
1216};
1217
1218/* ------------------------------------------------------------------------- */
1219
1220#ifdef CONFIG_RPXCLASSIC
1221static void
1222mii_link_interrupt(void *dev_id);
1223#else
1224static irqreturn_t
1225mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs);
1226#endif
1227
1228#if defined(CONFIG_M5272)
1229
1230/*
1231 * Code specific to Coldfire 5272 setup.
1232 */
1233static void __inline__ fec_request_intrs(struct net_device *dev)
1234{
1235 volatile unsigned long *icrp;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001236 static const struct idesc {
1237 char *name;
1238 unsigned short irq;
1239 irqreturn_t (*handler)(int, void *, struct pt_regs *);
1240 } *idp, id[] = {
1241 { "fec(RX)", 86, fec_enet_interrupt },
1242 { "fec(TX)", 87, fec_enet_interrupt },
1243 { "fec(OTHER)", 88, fec_enet_interrupt },
1244 { "fec(MII)", 66, mii_link_interrupt },
1245 { NULL },
1246 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247
1248 /* Setup interrupt handlers. */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001249 for (idp = id; idp->name; idp++) {
1250 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1251 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1252 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253
1254 /* Unmask interrupt at ColdFire 5272 SIM */
1255 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1256 *icrp = 0x00000ddd;
1257 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1258 *icrp = (*icrp & 0x70777777) | 0x0d000000;
1259}
1260
1261static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1262{
1263 volatile fec_t *fecp;
1264
1265 fecp = fep->hwp;
1266 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1267 fecp->fec_x_cntrl = 0x00;
1268
1269 /*
1270 * Set MII speed to 2.5 MHz
1271 * See 5272 manual section 11.5.8: MSCR
1272 */
1273 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1274 fecp->fec_mii_speed = fep->phy_speed;
1275
1276 fec_restart(dev, 0);
1277}
1278
1279static void __inline__ fec_get_mac(struct net_device *dev)
1280{
1281 struct fec_enet_private *fep = netdev_priv(dev);
1282 volatile fec_t *fecp;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001283 unsigned char *iap, tmpaddr[ETH_ALEN];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284
1285 fecp = fep->hwp;
1286
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001287 if (FEC_FLASHMAC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288 /*
1289 * Get MAC address from FLASH.
1290 * If it is all 1's or 0's, use the default.
1291 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001292 iap = (unsigned char *)FEC_FLASHMAC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1294 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1295 iap = fec_mac_default;
1296 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1297 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1298 iap = fec_mac_default;
1299 } else {
1300 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1301 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1302 iap = &tmpaddr[0];
1303 }
1304
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001305 memcpy(dev->dev_addr, iap, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306
1307 /* Adjust MAC if using default MAC address */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001308 if (iap == fec_mac_default)
1309 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001310}
1311
1312static void __inline__ fec_enable_phy_intr(void)
1313{
1314}
1315
1316static void __inline__ fec_disable_phy_intr(void)
1317{
1318 volatile unsigned long *icrp;
1319 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1320 *icrp = (*icrp & 0x70777777) | 0x08000000;
1321}
1322
1323static void __inline__ fec_phy_ack_intr(void)
1324{
1325 volatile unsigned long *icrp;
1326 /* Acknowledge the interrupt */
1327 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1328 *icrp = (*icrp & 0x77777777) | 0x08000000;
1329}
1330
1331static void __inline__ fec_localhw_setup(void)
1332{
1333}
1334
1335/*
1336 * Do not need to make region uncached on 5272.
1337 */
1338static void __inline__ fec_uncache(unsigned long addr)
1339{
1340}
1341
1342/* ------------------------------------------------------------------------- */
1343
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001344#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345
1346/*
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001347 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1348 * the 5270/5271/5274/5275 and 5280/5282 setups.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349 */
1350static void __inline__ fec_request_intrs(struct net_device *dev)
1351{
1352 struct fec_enet_private *fep;
1353 int b;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001354 static const struct idesc {
1355 char *name;
1356 unsigned short irq;
1357 } *idp, id[] = {
1358 { "fec(TXF)", 23 },
1359 { "fec(TXB)", 24 },
1360 { "fec(TXFIFO)", 25 },
1361 { "fec(TXCR)", 26 },
1362 { "fec(RXF)", 27 },
1363 { "fec(RXB)", 28 },
1364 { "fec(MII)", 29 },
1365 { "fec(LC)", 30 },
1366 { "fec(HBERR)", 31 },
1367 { "fec(GRA)", 32 },
1368 { "fec(EBERR)", 33 },
1369 { "fec(BABT)", 34 },
1370 { "fec(BABR)", 35 },
1371 { NULL },
1372 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373
1374 fep = netdev_priv(dev);
1375 b = (fep->index) ? 128 : 64;
1376
1377 /* Setup interrupt handlers. */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001378 for (idp = id; idp->name; idp++) {
1379 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1380 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1381 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382
1383 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1384 {
1385 volatile unsigned char *icrp;
1386 volatile unsigned long *imrp;
1387 int i;
1388
1389 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1390 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1391 MCFINTC_ICR0);
1392 for (i = 23; (i < 36); i++)
1393 icrp[i] = 0x23;
1394
1395 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1396 MCFINTC_IMRH);
1397 *imrp &= ~0x0000000f;
1398 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1399 MCFINTC_IMRL);
1400 *imrp &= ~0xff800001;
1401 }
1402
1403#if defined(CONFIG_M528x)
1404 /* Set up gpio outputs for MII lines */
1405 {
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001406 volatile u16 *gpio_paspar;
1407 volatile u8 *gpio_pehlpar;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001408
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001409 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1410 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1411 *gpio_paspar |= 0x0f00;
1412 *gpio_pehlpar = 0xc0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 }
1414#endif
1415}
1416
1417static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1418{
1419 volatile fec_t *fecp;
1420
1421 fecp = fep->hwp;
1422 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1423 fecp->fec_x_cntrl = 0x00;
1424
1425 /*
1426 * Set MII speed to 2.5 MHz
1427 * See 5282 manual section 17.5.4.7: MSCR
1428 */
1429 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1430 fecp->fec_mii_speed = fep->phy_speed;
1431
1432 fec_restart(dev, 0);
1433}
1434
1435static void __inline__ fec_get_mac(struct net_device *dev)
1436{
1437 struct fec_enet_private *fep = netdev_priv(dev);
1438 volatile fec_t *fecp;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001439 unsigned char *iap, tmpaddr[ETH_ALEN];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440
1441 fecp = fep->hwp;
1442
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001443 if (FEC_FLASHMAC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001444 /*
1445 * Get MAC address from FLASH.
1446 * If it is all 1's or 0's, use the default.
1447 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001448 iap = FEC_FLASHMAC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1450 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1451 iap = fec_mac_default;
1452 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1453 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1454 iap = fec_mac_default;
1455 } else {
1456 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1457 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1458 iap = &tmpaddr[0];
1459 }
1460
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001461 memcpy(dev->dev_addr, iap, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462
1463 /* Adjust MAC if using default MAC address */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001464 if (iap == fec_mac_default)
1465 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466}
1467
1468static void __inline__ fec_enable_phy_intr(void)
1469{
1470}
1471
1472static void __inline__ fec_disable_phy_intr(void)
1473{
1474}
1475
1476static void __inline__ fec_phy_ack_intr(void)
1477{
1478}
1479
1480static void __inline__ fec_localhw_setup(void)
1481{
1482}
1483
1484/*
1485 * Do not need to make region uncached on 5272.
1486 */
1487static void __inline__ fec_uncache(unsigned long addr)
1488{
1489}
1490
1491/* ------------------------------------------------------------------------- */
1492
Greg Ungerer562d2f82005-11-07 14:09:50 +10001493#elif defined(CONFIG_M520x)
1494
1495/*
1496 * Code specific to Coldfire 520x
1497 */
1498static void __inline__ fec_request_intrs(struct net_device *dev)
1499{
1500 struct fec_enet_private *fep;
1501 int b;
1502 static const struct idesc {
1503 char *name;
1504 unsigned short irq;
1505 } *idp, id[] = {
1506 { "fec(TXF)", 23 },
1507 { "fec(TXB)", 24 },
1508 { "fec(TXFIFO)", 25 },
1509 { "fec(TXCR)", 26 },
1510 { "fec(RXF)", 27 },
1511 { "fec(RXB)", 28 },
1512 { "fec(MII)", 29 },
1513 { "fec(LC)", 30 },
1514 { "fec(HBERR)", 31 },
1515 { "fec(GRA)", 32 },
1516 { "fec(EBERR)", 33 },
1517 { "fec(BABT)", 34 },
1518 { "fec(BABR)", 35 },
1519 { NULL },
1520 };
1521
1522 fep = netdev_priv(dev);
1523 b = 64 + 13;
1524
1525 /* Setup interrupt handlers. */
1526 for (idp = id; idp->name; idp++) {
1527 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1528 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1529 }
1530
1531 /* Unmask interrupts at ColdFire interrupt controller */
1532 {
1533 volatile unsigned char *icrp;
1534 volatile unsigned long *imrp;
1535
1536 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1537 MCFINTC_ICR0);
1538 for (b = 36; (b < 49); b++)
1539 icrp[b] = 0x04;
1540 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1541 MCFINTC_IMRH);
1542 *imrp &= ~0x0001FFF0;
1543 }
1544 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1545 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1546}
1547
1548static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1549{
1550 volatile fec_t *fecp;
1551
1552 fecp = fep->hwp;
1553 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1554 fecp->fec_x_cntrl = 0x00;
1555
1556 /*
1557 * Set MII speed to 2.5 MHz
1558 * See 5282 manual section 17.5.4.7: MSCR
1559 */
1560 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1561 fecp->fec_mii_speed = fep->phy_speed;
1562
1563 fec_restart(dev, 0);
1564}
1565
1566static void __inline__ fec_get_mac(struct net_device *dev)
1567{
1568 struct fec_enet_private *fep = netdev_priv(dev);
1569 volatile fec_t *fecp;
1570 unsigned char *iap, tmpaddr[ETH_ALEN];
1571
1572 fecp = fep->hwp;
1573
1574 if (FEC_FLASHMAC) {
1575 /*
1576 * Get MAC address from FLASH.
1577 * If it is all 1's or 0's, use the default.
1578 */
1579 iap = FEC_FLASHMAC;
1580 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1581 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1582 iap = fec_mac_default;
1583 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1584 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1585 iap = fec_mac_default;
1586 } else {
1587 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1588 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1589 iap = &tmpaddr[0];
1590 }
1591
1592 memcpy(dev->dev_addr, iap, ETH_ALEN);
1593
1594 /* Adjust MAC if using default MAC address */
1595 if (iap == fec_mac_default)
1596 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1597}
1598
1599static void __inline__ fec_enable_phy_intr(void)
1600{
1601}
1602
1603static void __inline__ fec_disable_phy_intr(void)
1604{
1605}
1606
1607static void __inline__ fec_phy_ack_intr(void)
1608{
1609}
1610
1611static void __inline__ fec_localhw_setup(void)
1612{
1613}
1614
1615static void __inline__ fec_uncache(unsigned long addr)
1616{
1617}
1618
1619/* ------------------------------------------------------------------------- */
1620
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621#else
1622
1623/*
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001624 * Code specific to the MPC860T setup.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625 */
1626static void __inline__ fec_request_intrs(struct net_device *dev)
1627{
1628 volatile immap_t *immap;
1629
1630 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1631
1632 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1633 panic("Could not allocate FEC IRQ!");
1634
1635#ifdef CONFIG_RPXCLASSIC
1636 /* Make Port C, bit 15 an input that causes interrupts.
1637 */
1638 immap->im_ioport.iop_pcpar &= ~0x0001;
1639 immap->im_ioport.iop_pcdir &= ~0x0001;
1640 immap->im_ioport.iop_pcso &= ~0x0001;
1641 immap->im_ioport.iop_pcint |= 0x0001;
1642 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1643
1644 /* Make LEDS reflect Link status.
1645 */
1646 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1647#endif
1648#ifdef CONFIG_FADS
1649 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1650 panic("Could not allocate MII IRQ!");
1651#endif
1652}
1653
1654static void __inline__ fec_get_mac(struct net_device *dev)
1655{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656 bd_t *bd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658 bd = (bd_t *)__res;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001659 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001660
1661#ifdef CONFIG_RPXCLASSIC
1662 /* The Embedded Planet boards have only one MAC address in
1663 * the EEPROM, but can have two Ethernet ports. For the
1664 * FEC port, we create another address by setting one of
1665 * the address bits above something that would have (up to
1666 * now) been allocated.
1667 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001668 dev->dev_adrd[3] |= 0x80;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001670}
1671
1672static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1673{
1674 extern uint _get_IMMR(void);
1675 volatile immap_t *immap;
1676 volatile fec_t *fecp;
1677
1678 fecp = fep->hwp;
1679 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1680
1681 /* Configure all of port D for MII.
1682 */
1683 immap->im_ioport.iop_pdpar = 0x1fff;
1684
1685 /* Bits moved from Rev. D onward.
1686 */
1687 if ((_get_IMMR() & 0xffff) < 0x0501)
1688 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1689 else
1690 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1691
1692 /* Set MII speed to 2.5 MHz
1693 */
1694 fecp->fec_mii_speed = fep->phy_speed =
1695 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1696}
1697
1698static void __inline__ fec_enable_phy_intr(void)
1699{
1700 volatile fec_t *fecp;
1701
1702 fecp = fep->hwp;
1703
1704 /* Enable MII command finished interrupt
1705 */
1706 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1707}
1708
1709static void __inline__ fec_disable_phy_intr(void)
1710{
1711}
1712
1713static void __inline__ fec_phy_ack_intr(void)
1714{
1715}
1716
1717static void __inline__ fec_localhw_setup(void)
1718{
1719 volatile fec_t *fecp;
1720
1721 fecp = fep->hwp;
1722 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1723 /* Enable big endian and don't care about SDMA FC.
1724 */
1725 fecp->fec_fun_code = 0x78000000;
1726}
1727
1728static void __inline__ fec_uncache(unsigned long addr)
1729{
1730 pte_t *pte;
1731 pte = va_to_pte(mem_addr);
1732 pte_val(*pte) |= _PAGE_NO_CACHE;
1733 flush_tlb_page(init_mm.mmap, mem_addr);
1734}
1735
1736#endif
1737
1738/* ------------------------------------------------------------------------- */
1739
1740static void mii_display_status(struct net_device *dev)
1741{
1742 struct fec_enet_private *fep = netdev_priv(dev);
1743 volatile uint *s = &(fep->phy_status);
1744
1745 if (!fep->link && !fep->old_link) {
1746 /* Link is still down - don't print anything */
1747 return;
1748 }
1749
1750 printk("%s: status: ", dev->name);
1751
1752 if (!fep->link) {
1753 printk("link down");
1754 } else {
1755 printk("link up");
1756
1757 switch(*s & PHY_STAT_SPMASK) {
1758 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1759 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1760 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1761 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1762 default:
1763 printk(", Unknown speed/duplex");
1764 }
1765
1766 if (*s & PHY_STAT_ANC)
1767 printk(", auto-negotiation complete");
1768 }
1769
1770 if (*s & PHY_STAT_FAULT)
1771 printk(", remote fault");
1772
1773 printk(".\n");
1774}
1775
1776static void mii_display_config(struct net_device *dev)
1777{
1778 struct fec_enet_private *fep = netdev_priv(dev);
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001779 uint status = fep->phy_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001780
1781 /*
1782 ** When we get here, phy_task is already removed from
1783 ** the workqueue. It is thus safe to allow to reuse it.
1784 */
1785 fep->mii_phy_task_queued = 0;
1786 printk("%s: config: auto-negotiation ", dev->name);
1787
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001788 if (status & PHY_CONF_ANE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789 printk("on");
1790 else
1791 printk("off");
1792
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001793 if (status & PHY_CONF_100FDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001794 printk(", 100FDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001795 if (status & PHY_CONF_100HDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796 printk(", 100HDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001797 if (status & PHY_CONF_10FDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001798 printk(", 10FDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001799 if (status & PHY_CONF_10HDX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800 printk(", 10HDX");
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001801 if (!(status & PHY_CONF_SPMASK))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001802 printk(", No speed/duplex selected?");
1803
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001804 if (status & PHY_CONF_LOOP)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 printk(", loopback enabled");
1806
1807 printk(".\n");
1808
1809 fep->sequence_done = 1;
1810}
1811
1812static void mii_relink(struct net_device *dev)
1813{
1814 struct fec_enet_private *fep = netdev_priv(dev);
1815 int duplex;
1816
1817 /*
1818 ** When we get here, phy_task is already removed from
1819 ** the workqueue. It is thus safe to allow to reuse it.
1820 */
1821 fep->mii_phy_task_queued = 0;
1822 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1823 mii_display_status(dev);
1824 fep->old_link = fep->link;
1825
1826 if (fep->link) {
1827 duplex = 0;
1828 if (fep->phy_status
1829 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1830 duplex = 1;
1831 fec_restart(dev, duplex);
1832 }
1833 else
1834 fec_stop(dev);
1835
1836#if 0
1837 enable_irq(fep->mii_irq);
1838#endif
1839
1840}
1841
1842/* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1843static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1844{
1845 struct fec_enet_private *fep = netdev_priv(dev);
1846
1847 /*
1848 ** We cannot queue phy_task twice in the workqueue. It
1849 ** would cause an endless loop in the workqueue.
1850 ** Fortunately, if the last mii_relink entry has not yet been
1851 ** executed now, it will do the job for the current interrupt,
1852 ** which is just what we want.
1853 */
1854 if (fep->mii_phy_task_queued)
1855 return;
1856
1857 fep->mii_phy_task_queued = 1;
1858 INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
1859 schedule_work(&fep->phy_task);
1860}
1861
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001862/* mii_queue_config is called in interrupt context from fec_enet_mii */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863static void mii_queue_config(uint mii_reg, struct net_device *dev)
1864{
1865 struct fec_enet_private *fep = netdev_priv(dev);
1866
1867 if (fep->mii_phy_task_queued)
1868 return;
1869
1870 fep->mii_phy_task_queued = 1;
1871 INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
1872 schedule_work(&fep->phy_task);
1873}
1874
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10001875phy_cmd_t const phy_cmd_relink[] = {
1876 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1877 { mk_mii_end, }
1878 };
1879phy_cmd_t const phy_cmd_config[] = {
1880 { mk_mii_read(MII_REG_CR), mii_queue_config },
1881 { mk_mii_end, }
1882 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883
1884/* Read remainder of PHY ID.
1885*/
1886static void
1887mii_discover_phy3(uint mii_reg, struct net_device *dev)
1888{
1889 struct fec_enet_private *fep;
1890 int i;
1891
1892 fep = netdev_priv(dev);
1893 fep->phy_id |= (mii_reg & 0xffff);
1894 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1895
1896 for(i = 0; phy_info[i]; i++) {
1897 if(phy_info[i]->id == (fep->phy_id >> 4))
1898 break;
1899 }
1900
1901 if (phy_info[i])
1902 printk(" -- %s\n", phy_info[i]->name);
1903 else
1904 printk(" -- unknown PHY!\n");
1905
1906 fep->phy = phy_info[i];
1907 fep->phy_id_done = 1;
1908}
1909
1910/* Scan all of the MII PHY addresses looking for someone to respond
1911 * with a valid ID. This usually happens quickly.
1912 */
1913static void
1914mii_discover_phy(uint mii_reg, struct net_device *dev)
1915{
1916 struct fec_enet_private *fep;
1917 volatile fec_t *fecp;
1918 uint phytype;
1919
1920 fep = netdev_priv(dev);
1921 fecp = fep->hwp;
1922
1923 if (fep->phy_addr < 32) {
1924 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1925
1926 /* Got first part of ID, now get remainder.
1927 */
1928 fep->phy_id = phytype << 16;
1929 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1930 mii_discover_phy3);
1931 }
1932 else {
1933 fep->phy_addr++;
1934 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1935 mii_discover_phy);
1936 }
1937 } else {
1938 printk("FEC: No PHY device found.\n");
1939 /* Disable external MII interface */
1940 fecp->fec_mii_speed = fep->phy_speed = 0;
1941 fec_disable_phy_intr();
1942 }
1943}
1944
1945/* This interrupt occurs when the PHY detects a link change.
1946*/
1947#ifdef CONFIG_RPXCLASSIC
1948static void
1949mii_link_interrupt(void *dev_id)
1950#else
1951static irqreturn_t
1952mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1953#endif
1954{
1955 struct net_device *dev = dev_id;
1956 struct fec_enet_private *fep = netdev_priv(dev);
1957
1958 fec_phy_ack_intr();
1959
1960#if 0
1961 disable_irq(fep->mii_irq); /* disable now, enable later */
1962#endif
1963
1964 mii_do_cmd(dev, fep->phy->ack_int);
1965 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1966
1967 return IRQ_HANDLED;
1968}
1969
1970static int
1971fec_enet_open(struct net_device *dev)
1972{
1973 struct fec_enet_private *fep = netdev_priv(dev);
1974
1975 /* I should reset the ring buffers here, but I don't yet know
1976 * a simple way to do that.
1977 */
1978 fec_set_mac_address(dev);
1979
1980 fep->sequence_done = 0;
1981 fep->link = 0;
1982
1983 if (fep->phy) {
1984 mii_do_cmd(dev, fep->phy->ack_int);
1985 mii_do_cmd(dev, fep->phy->config);
1986 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1987
1988 /* FIXME: use netif_carrier_{on,off} ; this polls
1989 * until link is up which is wrong... could be
1990 * 30 seconds or more we are trapped in here. -jgarzik
1991 */
1992 while(!fep->sequence_done)
1993 schedule();
1994
1995 mii_do_cmd(dev, fep->phy->startup);
1996
1997 /* Set the initial link state to true. A lot of hardware
1998 * based on this device does not implement a PHY interrupt,
1999 * so we are never notified of link change.
2000 */
2001 fep->link = 1;
2002 } else {
2003 fep->link = 1; /* lets just try it and see */
2004 /* no phy, go full duplex, it's most likely a hub chip */
2005 fec_restart(dev, 1);
2006 }
2007
2008 netif_start_queue(dev);
2009 fep->opened = 1;
2010 return 0; /* Success */
2011}
2012
2013static int
2014fec_enet_close(struct net_device *dev)
2015{
2016 struct fec_enet_private *fep = netdev_priv(dev);
2017
2018 /* Don't know what to do yet.
2019 */
2020 fep->opened = 0;
2021 netif_stop_queue(dev);
2022 fec_stop(dev);
2023
2024 return 0;
2025}
2026
2027static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
2028{
2029 struct fec_enet_private *fep = netdev_priv(dev);
2030
2031 return &fep->stats;
2032}
2033
2034/* Set or clear the multicast filter for this adaptor.
2035 * Skeleton taken from sunlance driver.
2036 * The CPM Ethernet implementation allows Multicast as well as individual
2037 * MAC address filtering. Some of the drivers check to make sure it is
2038 * a group multicast address, and discard those that are not. I guess I
2039 * will do the same for now, but just remove the test if you want
2040 * individual filtering as well (do the upper net layers want or support
2041 * this kind of feature?).
2042 */
2043
2044#define HASH_BITS 6 /* #bits in hash */
2045#define CRC32_POLY 0xEDB88320
2046
2047static void set_multicast_list(struct net_device *dev)
2048{
2049 struct fec_enet_private *fep;
2050 volatile fec_t *ep;
2051 struct dev_mc_list *dmi;
2052 unsigned int i, j, bit, data, crc;
2053 unsigned char hash;
2054
2055 fep = netdev_priv(dev);
2056 ep = fep->hwp;
2057
2058 if (dev->flags&IFF_PROMISC) {
2059 /* Log any net taps. */
2060 printk("%s: Promiscuous mode enabled.\n", dev->name);
2061 ep->fec_r_cntrl |= 0x0008;
2062 } else {
2063
2064 ep->fec_r_cntrl &= ~0x0008;
2065
2066 if (dev->flags & IFF_ALLMULTI) {
2067 /* Catch all multicast addresses, so set the
2068 * filter to all 1's.
2069 */
2070 ep->fec_hash_table_high = 0xffffffff;
2071 ep->fec_hash_table_low = 0xffffffff;
2072 } else {
2073 /* Clear filter and add the addresses in hash register.
2074 */
2075 ep->fec_hash_table_high = 0;
2076 ep->fec_hash_table_low = 0;
2077
2078 dmi = dev->mc_list;
2079
2080 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2081 {
2082 /* Only support group multicast for now.
2083 */
2084 if (!(dmi->dmi_addr[0] & 1))
2085 continue;
2086
2087 /* calculate crc32 value of mac address
2088 */
2089 crc = 0xffffffff;
2090
2091 for (i = 0; i < dmi->dmi_addrlen; i++)
2092 {
2093 data = dmi->dmi_addr[i];
2094 for (bit = 0; bit < 8; bit++, data >>= 1)
2095 {
2096 crc = (crc >> 1) ^
2097 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2098 }
2099 }
2100
2101 /* only upper 6 bits (HASH_BITS) are used
2102 which point to specific bit in he hash registers
2103 */
2104 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2105
2106 if (hash > 31)
2107 ep->fec_hash_table_high |= 1 << (hash - 32);
2108 else
2109 ep->fec_hash_table_low |= 1 << hash;
2110 }
2111 }
2112 }
2113}
2114
2115/* Set a MAC change in hardware.
2116 */
2117static void
2118fec_set_mac_address(struct net_device *dev)
2119{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120 volatile fec_t *fecp;
2121
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002122 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123
2124 /* Set station address. */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002125 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2126 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2127 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2128 (dev->dev_addr[4] << 24);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129
2130}
2131
2132/* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2133 */
2134 /*
2135 * XXX: We need to clean up on failure exits here.
2136 */
2137int __init fec_enet_init(struct net_device *dev)
2138{
2139 struct fec_enet_private *fep = netdev_priv(dev);
2140 unsigned long mem_addr;
2141 volatile cbd_t *bdp;
2142 cbd_t *cbd_base;
2143 volatile fec_t *fecp;
2144 int i, j;
2145 static int index = 0;
2146
2147 /* Only allow us to be probed once. */
2148 if (index >= FEC_MAX_PORTS)
2149 return -ENXIO;
2150
Greg Ungerer562d2f82005-11-07 14:09:50 +10002151 /* Allocate memory for buffer descriptors.
2152 */
2153 mem_addr = __get_free_page(GFP_KERNEL);
2154 if (mem_addr == 0) {
2155 printk("FEC: allocate descriptor memory failed?\n");
2156 return -ENOMEM;
2157 }
2158
Linus Torvalds1da177e2005-04-16 15:20:36 -07002159 /* Create an Ethernet device instance.
2160 */
2161 fecp = (volatile fec_t *) fec_hw[index];
2162
2163 fep->index = index;
2164 fep->hwp = fecp;
2165
2166 /* Whack a reset. We should wait for this.
2167 */
2168 fecp->fec_ecntrl = 1;
2169 udelay(10);
2170
Linus Torvalds1da177e2005-04-16 15:20:36 -07002171 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2172 * this needs some work to get unique addresses.
2173 *
2174 * This is our default MAC address unless the user changes
2175 * it via eth_mac_addr (our dev->set_mac_addr handler).
2176 */
2177 fec_get_mac(dev);
2178
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179 cbd_base = (cbd_t *)mem_addr;
2180 /* XXX: missing check for allocation failure */
2181
2182 fec_uncache(mem_addr);
2183
2184 /* Set receive and transmit descriptor base.
2185 */
2186 fep->rx_bd_base = cbd_base;
2187 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2188
2189 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2190 fep->cur_rx = fep->rx_bd_base;
2191
2192 fep->skb_cur = fep->skb_dirty = 0;
2193
2194 /* Initialize the receive buffer descriptors.
2195 */
2196 bdp = fep->rx_bd_base;
2197 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2198
2199 /* Allocate a page.
2200 */
2201 mem_addr = __get_free_page(GFP_KERNEL);
2202 /* XXX: missing check for allocation failure */
2203
2204 fec_uncache(mem_addr);
2205
2206 /* Initialize the BD for every fragment in the page.
2207 */
2208 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2209 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2210 bdp->cbd_bufaddr = __pa(mem_addr);
2211 mem_addr += FEC_ENET_RX_FRSIZE;
2212 bdp++;
2213 }
2214 }
2215
2216 /* Set the last buffer to wrap.
2217 */
2218 bdp--;
2219 bdp->cbd_sc |= BD_SC_WRAP;
2220
2221 /* ...and the same for transmmit.
2222 */
2223 bdp = fep->tx_bd_base;
2224 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2225 if (j >= FEC_ENET_TX_FRPPG) {
2226 mem_addr = __get_free_page(GFP_KERNEL);
2227 j = 1;
2228 } else {
2229 mem_addr += FEC_ENET_TX_FRSIZE;
2230 j++;
2231 }
2232 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2233
2234 /* Initialize the BD for every fragment in the page.
2235 */
2236 bdp->cbd_sc = 0;
2237 bdp->cbd_bufaddr = 0;
2238 bdp++;
2239 }
2240
2241 /* Set the last buffer to wrap.
2242 */
2243 bdp--;
2244 bdp->cbd_sc |= BD_SC_WRAP;
2245
2246 /* Set receive and transmit descriptor base.
2247 */
2248 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2249 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2250
2251 /* Install our interrupt handlers. This varies depending on
2252 * the architecture.
2253 */
2254 fec_request_intrs(dev);
2255
Greg Ungerer562d2f82005-11-07 14:09:50 +10002256 /* Clear and enable interrupts */
2257 fecp->fec_ievent = 0xffc00000;
2258 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2259 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2260 fecp->fec_hash_table_high = 0;
2261 fecp->fec_hash_table_low = 0;
2262 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2263 fecp->fec_ecntrl = 2;
2264 fecp->fec_r_des_active = 0x01000000;
2265
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266 dev->base_addr = (unsigned long)fecp;
2267
2268 /* The FEC Ethernet specific entries in the device structure. */
2269 dev->open = fec_enet_open;
2270 dev->hard_start_xmit = fec_enet_start_xmit;
2271 dev->tx_timeout = fec_timeout;
2272 dev->watchdog_timeo = TX_TIMEOUT;
2273 dev->stop = fec_enet_close;
2274 dev->get_stats = fec_enet_get_stats;
2275 dev->set_multicast_list = set_multicast_list;
2276
2277 for (i=0; i<NMII-1; i++)
2278 mii_cmds[i].mii_next = &mii_cmds[i+1];
2279 mii_free = mii_cmds;
2280
2281 /* setup MII interface */
2282 fec_set_mii(dev, fep);
2283
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284 /* Queue up command to detect the PHY and initialize the
2285 * remainder of the interface.
2286 */
2287 fep->phy_id_done = 0;
2288 fep->phy_addr = 0;
2289 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2290
2291 index++;
2292 return 0;
2293}
2294
2295/* This function is called to start or restart the FEC during a link
2296 * change. This only happens when switching between half and full
2297 * duplex.
2298 */
2299static void
2300fec_restart(struct net_device *dev, int duplex)
2301{
2302 struct fec_enet_private *fep;
2303 volatile cbd_t *bdp;
2304 volatile fec_t *fecp;
2305 int i;
2306
2307 fep = netdev_priv(dev);
2308 fecp = fep->hwp;
2309
2310 /* Whack a reset. We should wait for this.
2311 */
2312 fecp->fec_ecntrl = 1;
2313 udelay(10);
2314
2315 /* Enable interrupts we wish to service.
2316 */
2317 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2318 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2319
2320 /* Clear any outstanding interrupt.
2321 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002322 fecp->fec_ievent = 0xffc00000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002323 fec_enable_phy_intr();
2324
2325 /* Set station address.
2326 */
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002327 fec_set_mac_address(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002328
2329 /* Reset all multicast.
2330 */
2331 fecp->fec_hash_table_high = 0;
2332 fecp->fec_hash_table_low = 0;
2333
2334 /* Set maximum receive buffer size.
2335 */
2336 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2337
2338 fec_localhw_setup();
2339
2340 /* Set receive and transmit descriptor base.
2341 */
2342 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2343 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2344
2345 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2346 fep->cur_rx = fep->rx_bd_base;
2347
2348 /* Reset SKB transmit buffers.
2349 */
2350 fep->skb_cur = fep->skb_dirty = 0;
2351 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2352 if (fep->tx_skbuff[i] != NULL) {
2353 dev_kfree_skb_any(fep->tx_skbuff[i]);
2354 fep->tx_skbuff[i] = NULL;
2355 }
2356 }
2357
2358 /* Initialize the receive buffer descriptors.
2359 */
2360 bdp = fep->rx_bd_base;
2361 for (i=0; i<RX_RING_SIZE; i++) {
2362
2363 /* Initialize the BD for every fragment in the page.
2364 */
2365 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2366 bdp++;
2367 }
2368
2369 /* Set the last buffer to wrap.
2370 */
2371 bdp--;
2372 bdp->cbd_sc |= BD_SC_WRAP;
2373
2374 /* ...and the same for transmmit.
2375 */
2376 bdp = fep->tx_bd_base;
2377 for (i=0; i<TX_RING_SIZE; i++) {
2378
2379 /* Initialize the BD for every fragment in the page.
2380 */
2381 bdp->cbd_sc = 0;
2382 bdp->cbd_bufaddr = 0;
2383 bdp++;
2384 }
2385
2386 /* Set the last buffer to wrap.
2387 */
2388 bdp--;
2389 bdp->cbd_sc |= BD_SC_WRAP;
2390
2391 /* Enable MII mode.
2392 */
2393 if (duplex) {
2394 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2395 fecp->fec_x_cntrl = 0x04; /* FD enable */
2396 }
2397 else {
2398 /* MII enable|No Rcv on Xmit */
2399 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2400 fecp->fec_x_cntrl = 0x00;
2401 }
2402 fep->full_duplex = duplex;
2403
2404 /* Set MII speed.
2405 */
2406 fecp->fec_mii_speed = fep->phy_speed;
2407
2408 /* And last, enable the transmit and receive processing.
2409 */
2410 fecp->fec_ecntrl = 2;
2411 fecp->fec_r_des_active = 0x01000000;
2412}
2413
2414static void
2415fec_stop(struct net_device *dev)
2416{
2417 volatile fec_t *fecp;
2418 struct fec_enet_private *fep;
2419
2420 fep = netdev_priv(dev);
2421 fecp = fep->hwp;
2422
2423 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2424
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002425 while(!(fecp->fec_ievent & FEC_ENET_GRA));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426
2427 /* Whack a reset. We should wait for this.
2428 */
2429 fecp->fec_ecntrl = 1;
2430 udelay(10);
2431
2432 /* Clear outstanding MII command interrupts.
2433 */
2434 fecp->fec_ievent = FEC_ENET_MII;
2435 fec_enable_phy_intr();
2436
2437 fecp->fec_imask = FEC_ENET_MII;
2438 fecp->fec_mii_speed = fep->phy_speed;
2439}
2440
2441static int __init fec_enet_module_init(void)
2442{
2443 struct net_device *dev;
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002444 int i, j, err;
2445
2446 printk("FEC ENET Version 0.2\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002447
2448 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2449 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2450 if (!dev)
2451 return -ENOMEM;
2452 err = fec_enet_init(dev);
2453 if (err) {
2454 free_netdev(dev);
2455 continue;
2456 }
2457 if (register_netdev(dev) != 0) {
2458 /* XXX: missing cleanup here */
2459 free_netdev(dev);
2460 return -EIO;
2461 }
Greg Ungerer7dd6a2a2005-09-12 11:18:10 +10002462
2463 printk("%s: ethernet ", dev->name);
2464 for (j = 0; (j < 5); j++)
2465 printk("%02x:", dev->dev_addr[j]);
2466 printk("%02x\n", dev->dev_addr[5]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002467 }
2468 return 0;
2469}
2470
2471module_init(fec_enet_module_init);
2472
2473MODULE_LICENSE("GPL");