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Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*-
2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 */
37
38/*
39 * Defintions for the Atheros Wireless LAN controller driver.
40 */
41#ifndef _DEV_ATH_ATHVAR_H
42#define _DEV_ATH_ATHVAR_H
43
44#include <linux/interrupt.h>
45#include <linux/list.h>
46#include <linux/wireless.h>
47#include <linux/if_ether.h>
Bob Copeland3a078872008-06-25 22:35:28 -040048#include <linux/leds.h>
Tobias Doerffele6a3b612009-06-09 17:33:27 +020049#include <linux/rfkill.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020050
51#include "ath5k.h"
52#include "debug.h"
Luis R. Rodriguezaeb63cf2009-08-12 09:57:00 -070053#include "../ath.h"
Jiri Slabyfa1c1142007-08-12 17:33:16 +020054
55#define ATH_RXBUF 40 /* number of RX buffers */
56#define ATH_TXBUF 200 /* number of TX buffers */
57#define ATH_BCBUF 1 /* number of beacon buffers */
58
59struct ath5k_buf {
60 struct list_head list;
Jiri Slabyfa1c1142007-08-12 17:33:16 +020061 struct ath5k_desc *desc; /* virtual addr of desc */
62 dma_addr_t daddr; /* physical addr of desc */
63 struct sk_buff *skb; /* skbuff for buf */
64 dma_addr_t skbaddr;/* physical addr of skb data */
Jiri Slabyfa1c1142007-08-12 17:33:16 +020065};
66
67/*
68 * Data transmit queue state. One of these exists for each
69 * hardware transmit queue. Packets sent to us from above
70 * are assigned to queues based on their priority. Not all
71 * devices support a complete set of hardware transmit queues.
72 * For those devices the array sc_ac2q will map multiple
73 * priorities to fewer hardware queues (typically all to one
74 * hardware queue).
75 */
76struct ath5k_txq {
77 unsigned int qnum; /* hardware q number */
78 u32 *link; /* link ptr in last TX desc */
79 struct list_head q; /* transmit queue */
80 spinlock_t lock; /* lock on q and link */
81 bool setup;
82};
83
Bob Copeland3a078872008-06-25 22:35:28 -040084#define ATH5K_LED_MAX_NAME_LEN 31
85
86/*
87 * State for LED triggers
88 */
89struct ath5k_led
90{
91 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
92 struct ath5k_softc *sc; /* driver state */
93 struct led_classdev led_dev; /* led classdev */
94};
95
Tobias Doerffele6a3b612009-06-09 17:33:27 +020096/* Rfkill */
97struct ath5k_rfkill {
98 /* GPIO PIN for rfkill */
99 u16 gpio;
100 /* polarity of rfkill GPIO PIN */
101 bool polarity;
102 /* RFKILL toggle tasklet */
103 struct tasklet_struct toggleq;
104};
Bob Copeland3a078872008-06-25 22:35:28 -0400105
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200106#if CHAN_DEBUG
107#define ATH_CHAN_MAX (26+26+26+200+200)
108#else
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500109#define ATH_CHAN_MAX (14+14+14+252+20)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200110#endif
111
112/* Software Carrier, keeps track of the driver state
113 * associated with an instance of a device */
114struct ath5k_softc {
115 struct pci_dev *pdev; /* for dma mapping */
Luis R. Rodriguezaeb63cf2009-08-12 09:57:00 -0700116 struct ath_common common;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200117 void __iomem *iobase; /* address of the device */
118 struct mutex lock; /* dev-level lock */
Bob Copelandcec8db22009-07-04 12:59:51 -0400119 struct ieee80211_tx_queue_stats tx_stats[AR5K_NUM_TX_QUEUES];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200120 struct ieee80211_low_level_stats ll_stats;
121 struct ieee80211_hw *hw; /* IEEE 802.11 common */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500122 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200123 struct ieee80211_channel channels[ATH_CHAN_MAX];
Bruno Randolf63266a62008-07-30 17:12:58 +0200124 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
Bob Copelandb7266042009-03-02 21:55:18 -0500125 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
Johannes Berg05c914f2008-09-11 00:01:58 +0200126 enum nl80211_iftype opmode;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200127 struct ath5k_hw *ah; /* Atheros HW */
128
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500129 struct ieee80211_supported_band *curband;
130
Luis R. Rodriguezb4461972008-02-04 10:03:54 -0500131#ifdef CONFIG_ATH5K_DEBUG
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200132 struct ath5k_dbg_info debug; /* debug info */
Luis R. Rodriguezb4461972008-02-04 10:03:54 -0500133#endif /* CONFIG_ATH5K_DEBUG */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200134
135 struct ath5k_buf *bufptr; /* allocated buffer ptr */
136 struct ath5k_desc *desc; /* TX/RX descriptors */
137 dma_addr_t desc_daddr; /* DMA (physical) address */
138 size_t desc_len; /* size of TX/RX descriptors */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200139
Bob Copeland8bdd5b92008-10-16 11:02:06 -0400140 DECLARE_BITMAP(status, 5);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200141#define ATH_STAT_INVALID 0 /* disable hardware accesses */
142#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
143#define ATH_STAT_PROMISC 2
Bob Copeland3a078872008-06-25 22:35:28 -0400144#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
Bob Copeland8bdd5b92008-10-16 11:02:06 -0400145#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200146
147 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
148 unsigned int curmode; /* current phy mode */
149 struct ieee80211_channel *curchan; /* current h/w channel */
150
Johannes Berg32bfd352007-12-19 01:31:26 +0100151 struct ieee80211_vif *vif;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200152
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200153 enum ath5k_int imask; /* interrupt mask copy */
154
155 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
156
157 u8 bssidmask[ETH_ALEN];
158
159 unsigned int led_pin, /* GPIO pin for driving LED */
Bob Copeland5ef40172009-01-22 08:44:19 -0500160 led_on; /* pin setting for LED on */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200161
162 struct tasklet_struct restq; /* reset tasklet */
163
164 unsigned int rxbufsize; /* rx size based on mtu */
165 struct list_head rxbuf; /* receive buffer */
166 spinlock_t rxbuflock;
167 u32 *rxlink; /* link ptr in last RX desc */
168 struct tasklet_struct rxtq; /* rx intr tasklet */
Bob Copeland3a078872008-06-25 22:35:28 -0400169 struct ath5k_led rx_led; /* rx led */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200170
171 struct list_head txbuf; /* transmit buffer */
172 spinlock_t txbuflock;
173 unsigned int txbuf_len; /* buf count in txbuf list */
Bob Copelandcec8db22009-07-04 12:59:51 -0400174 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
175 struct ath5k_txq *txq; /* main tx queue */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200176 struct tasklet_struct txtq; /* tx intr tasklet */
Bob Copeland3a078872008-06-25 22:35:28 -0400177 struct ath5k_led tx_led; /* tx led */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200178
Tobias Doerffele6a3b612009-06-09 17:33:27 +0200179 struct ath5k_rfkill rf_kill;
Tobias Doerffele6a3b612009-06-09 17:33:27 +0200180
Nick Kossifidis6e220662009-08-10 03:31:31 +0300181 struct tasklet_struct calib; /* calibration tasklet */
182
Jiri Slaby00482972008-08-18 21:45:27 +0200183 spinlock_t block; /* protects beacon */
Bob Copelandacf3c1a2009-02-15 12:06:11 -0500184 struct tasklet_struct beacontq; /* beacon intr tasklet */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200185 struct ath5k_buf *bbuf; /* beacon buffer */
186 unsigned int bhalq, /* SW q for outgoing beacons */
187 bmisscount, /* missed beacon transmits */
Bruno Randolfe535c1a2008-01-18 21:51:40 +0900188 bintval, /* beacon interval in TU */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200189 bsent;
Bruno Randolf036cd1e2008-01-19 18:18:21 +0900190 unsigned int nexttbtt; /* next beacon time in TU */
Bob Copelandcec8db22009-07-04 12:59:51 -0400191 struct ath5k_txq *cabq; /* content after beacon */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200192
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500193 int power_level; /* Requested tx power in dbm */
Martin Xu02969b32008-11-24 10:49:27 +0800194 bool assoc; /* assocate state */
Bob Copeland21800492009-07-04 12:59:52 -0400195 bool enable_beacon; /* true if beacons are on */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200196};
197
198#define ath5k_hw_hasbssidmask(_ah) \
199 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
200#define ath5k_hw_hasveol(_ah) \
201 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
202
203#endif