Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 1 | /* arch/arm/mach-msm/acpuclock.c |
| 2 | * |
| 3 | * MSM architecture clock driver |
| 4 | * |
| 5 | * Copyright (C) 2007 Google, Inc. |
| 6 | * Copyright (c) 2007 QUALCOMM Incorporated |
| 7 | * Author: San Mehat <san@android.com> |
| 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and |
| 11 | * may be copied, distributed, and modified under those terms. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 20 | #include <linux/version.h> |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/string.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/cpufreq.h> |
| 29 | #include <linux/mutex.h> |
| 30 | #include <linux/io.h> |
| 31 | #include <mach/board.h> |
| 32 | #include <mach/msm_iomap.h> |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 33 | #include <mach/proc_comm.h> |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 34 | |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 35 | #include "acpuclock.h" |
| 36 | |
| 37 | |
| 38 | #define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) |
| 39 | #define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) |
| 40 | #define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) |
| 41 | |
| 42 | /* |
| 43 | * ARM11 clock configuration for specific ACPU speeds |
| 44 | */ |
| 45 | |
| 46 | #define ACPU_PLL_TCXO -1 |
| 47 | #define ACPU_PLL_0 0 |
| 48 | #define ACPU_PLL_1 1 |
| 49 | #define ACPU_PLL_2 2 |
| 50 | #define ACPU_PLL_3 3 |
| 51 | |
| 52 | #define PERF_SWITCH_DEBUG 0 |
| 53 | #define PERF_SWITCH_STEP_DEBUG 0 |
| 54 | |
| 55 | struct clock_state |
| 56 | { |
| 57 | struct clkctl_acpu_speed *current_speed; |
| 58 | struct mutex lock; |
| 59 | uint32_t acpu_switch_time_us; |
| 60 | uint32_t max_speed_delta_khz; |
| 61 | uint32_t vdd_switch_time_us; |
| 62 | unsigned long power_collapse_khz; |
| 63 | unsigned long wait_for_irq_khz; |
| 64 | }; |
| 65 | |
| 66 | static struct clk *ebi1_clk; |
| 67 | static struct clock_state drv_state = { 0 }; |
| 68 | |
| 69 | static void __init acpuclk_init(void); |
| 70 | |
| 71 | /* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */ |
| 72 | enum { |
| 73 | VDD_0 = 0, |
| 74 | VDD_1 = 1, |
| 75 | VDD_2 = 2, |
| 76 | VDD_3 = 3, |
| 77 | VDD_4 = 3, |
| 78 | VDD_5 = 3, |
| 79 | VDD_6 = 3, |
| 80 | VDD_7 = 7, |
| 81 | VDD_END |
| 82 | }; |
| 83 | |
| 84 | struct clkctl_acpu_speed { |
| 85 | unsigned int a11clk_khz; |
| 86 | int pll; |
| 87 | unsigned int a11clk_src_sel; |
| 88 | unsigned int a11clk_src_div; |
| 89 | unsigned int ahbclk_khz; |
| 90 | unsigned int ahbclk_div; |
| 91 | int vdd; |
| 92 | unsigned int axiclk_khz; |
| 93 | unsigned long lpj; /* loops_per_jiffy */ |
| 94 | /* Index in acpu_freq_tbl[] for steppings. */ |
| 95 | short down; |
| 96 | short up; |
| 97 | }; |
| 98 | |
| 99 | /* |
| 100 | * ACPU speed table. Complete table is shown but certain speeds are commented |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 101 | * out to optimized speed switching. Initalize loops_per_jiffy to 0. |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 102 | * |
| 103 | * Table stepping up/down is optimized for 256mhz jumps while staying on the |
| 104 | * same PLL. |
| 105 | */ |
| 106 | #if (0) |
| 107 | static struct clkctl_acpu_speed acpu_freq_tbl[] = { |
| 108 | { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 }, |
| 109 | { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 }, |
| 110 | { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 }, |
| 111 | { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 }, |
| 112 | { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 }, |
| 113 | { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 }, |
| 114 | { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 }, |
| 115 | { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 }, |
| 116 | { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 }, |
| 117 | { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 }, |
| 118 | { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 }, |
| 119 | { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 }, |
| 120 | { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 }, |
| 121 | { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 }, |
| 122 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 123 | }; |
| 124 | #else /* Table of freq we currently use. */ |
| 125 | static struct clkctl_acpu_speed acpu_freq_tbl[] = { |
| 126 | { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 }, |
| 127 | { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 }, |
| 128 | { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 }, |
| 129 | { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 }, |
| 130 | { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 }, |
| 131 | { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 }, |
| 132 | { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 }, |
| 133 | { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 }, |
| 134 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
| 135 | }; |
| 136 | #endif |
| 137 | |
Daniel Walker | 4eab625 | 2010-03-04 14:06:56 -0800 | [diff] [blame] | 138 | |
| 139 | #ifdef CONFIG_CPU_FREQ_TABLE |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 140 | static struct cpufreq_frequency_table freq_table[] = { |
| 141 | { 0, 122880 }, |
| 142 | { 1, 128000 }, |
| 143 | { 2, 245760 }, |
| 144 | { 3, 384000 }, |
| 145 | { 4, 528000 }, |
| 146 | { 5, CPUFREQ_TABLE_END }, |
| 147 | }; |
Daniel Walker | 4eab625 | 2010-03-04 14:06:56 -0800 | [diff] [blame] | 148 | #endif |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 149 | |
| 150 | static int pc_pll_request(unsigned id, unsigned on) |
| 151 | { |
| 152 | int res; |
| 153 | on = !!on; |
| 154 | |
| 155 | #if PERF_SWITCH_DEBUG |
| 156 | if (on) |
| 157 | printk(KERN_DEBUG "Enabling PLL %d\n", id); |
| 158 | else |
| 159 | printk(KERN_DEBUG "Disabling PLL %d\n", id); |
| 160 | #endif |
| 161 | |
| 162 | res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); |
| 163 | if (res < 0) |
| 164 | return res; |
| 165 | |
| 166 | #if PERF_SWITCH_DEBUG |
| 167 | if (on) |
| 168 | printk(KERN_DEBUG "PLL %d enabled\n", id); |
| 169 | else |
| 170 | printk(KERN_DEBUG "PLL %d disabled\n", id); |
| 171 | #endif |
| 172 | return res; |
| 173 | } |
| 174 | |
| 175 | |
| 176 | /*---------------------------------------------------------------------------- |
| 177 | * ARM11 'owned' clock control |
| 178 | *---------------------------------------------------------------------------*/ |
| 179 | |
| 180 | unsigned long acpuclk_power_collapse(void) { |
| 181 | int ret = acpuclk_get_rate(); |
| 182 | ret *= 1000; |
| 183 | if (ret > drv_state.power_collapse_khz) |
| 184 | acpuclk_set_rate(drv_state.power_collapse_khz, 1); |
| 185 | return ret; |
| 186 | } |
| 187 | |
| 188 | unsigned long acpuclk_get_wfi_rate(void) |
| 189 | { |
| 190 | return drv_state.wait_for_irq_khz; |
| 191 | } |
| 192 | |
| 193 | unsigned long acpuclk_wait_for_irq(void) { |
| 194 | int ret = acpuclk_get_rate(); |
| 195 | ret *= 1000; |
| 196 | if (ret > drv_state.wait_for_irq_khz) |
| 197 | acpuclk_set_rate(drv_state.wait_for_irq_khz, 1); |
| 198 | return ret; |
| 199 | } |
| 200 | |
| 201 | static int acpuclk_set_vdd_level(int vdd) |
| 202 | { |
| 203 | uint32_t current_vdd; |
| 204 | |
| 205 | current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07; |
| 206 | |
| 207 | #if PERF_SWITCH_DEBUG |
| 208 | printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n", |
| 209 | current_vdd, vdd); |
| 210 | #endif |
| 211 | writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); |
| 212 | udelay(drv_state.vdd_switch_time_us); |
| 213 | if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { |
| 214 | #if PERF_SWITCH_DEBUG |
| 215 | printk(KERN_ERR "acpuclock: VDD set failed\n"); |
| 216 | #endif |
| 217 | return -EIO; |
| 218 | } |
| 219 | |
| 220 | #if PERF_SWITCH_DEBUG |
| 221 | printk(KERN_DEBUG "acpuclock: VDD switched\n"); |
| 222 | #endif |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | /* Set proper dividers for the given clock speed. */ |
| 227 | static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { |
| 228 | uint32_t reg_clkctl, reg_clksel, clk_div; |
| 229 | |
| 230 | /* AHB_CLK_DIV */ |
| 231 | clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; |
| 232 | /* |
| 233 | * If the new clock divider is higher than the previous, then |
| 234 | * program the divider before switching the clock |
| 235 | */ |
| 236 | if (hunt_s->ahbclk_div > clk_div) { |
| 237 | reg_clksel = readl(A11S_CLK_SEL_ADDR); |
| 238 | reg_clksel &= ~(0x3 << 1); |
| 239 | reg_clksel |= (hunt_s->ahbclk_div << 1); |
| 240 | writel(reg_clksel, A11S_CLK_SEL_ADDR); |
| 241 | } |
| 242 | if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) { |
| 243 | /* SRC0 */ |
| 244 | |
| 245 | /* Program clock source */ |
| 246 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); |
| 247 | reg_clkctl &= ~(0x07 << 4); |
| 248 | reg_clkctl |= (hunt_s->a11clk_src_sel << 4); |
| 249 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); |
| 250 | |
| 251 | /* Program clock divider */ |
| 252 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); |
| 253 | reg_clkctl &= ~0xf; |
| 254 | reg_clkctl |= hunt_s->a11clk_src_div; |
| 255 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); |
| 256 | |
| 257 | /* Program clock source selection */ |
| 258 | reg_clksel = readl(A11S_CLK_SEL_ADDR); |
| 259 | reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */ |
| 260 | writel(reg_clksel, A11S_CLK_SEL_ADDR); |
| 261 | } else { |
| 262 | /* SRC1 */ |
| 263 | |
| 264 | /* Program clock source */ |
| 265 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); |
| 266 | reg_clkctl &= ~(0x07 << 12); |
| 267 | reg_clkctl |= (hunt_s->a11clk_src_sel << 12); |
| 268 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); |
| 269 | |
| 270 | /* Program clock divider */ |
| 271 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); |
| 272 | reg_clkctl &= ~(0xf << 8); |
| 273 | reg_clkctl |= (hunt_s->a11clk_src_div << 8); |
| 274 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); |
| 275 | |
| 276 | /* Program clock source selection */ |
| 277 | reg_clksel = readl(A11S_CLK_SEL_ADDR); |
| 278 | reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */ |
| 279 | writel(reg_clksel, A11S_CLK_SEL_ADDR); |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * If the new clock divider is lower than the previous, then |
| 284 | * program the divider after switching the clock |
| 285 | */ |
| 286 | if (hunt_s->ahbclk_div < clk_div) { |
| 287 | reg_clksel = readl(A11S_CLK_SEL_ADDR); |
| 288 | reg_clksel &= ~(0x3 << 1); |
| 289 | reg_clksel |= (hunt_s->ahbclk_div << 1); |
| 290 | writel(reg_clksel, A11S_CLK_SEL_ADDR); |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | int acpuclk_set_rate(unsigned long rate, int for_power_collapse) |
| 295 | { |
| 296 | uint32_t reg_clkctl; |
| 297 | struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s; |
| 298 | int rc = 0; |
| 299 | unsigned int plls_enabled = 0, pll; |
| 300 | |
| 301 | strt_s = cur_s = drv_state.current_speed; |
| 302 | |
| 303 | WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n"); |
| 304 | if (cur_s == NULL) |
| 305 | return -ENOENT; |
| 306 | |
| 307 | if (rate == (cur_s->a11clk_khz * 1000)) |
| 308 | return 0; |
| 309 | |
| 310 | for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) { |
| 311 | if (tgt_s->a11clk_khz == (rate / 1000)) |
| 312 | break; |
| 313 | } |
| 314 | |
| 315 | if (tgt_s->a11clk_khz == 0) |
| 316 | return -EINVAL; |
| 317 | |
| 318 | /* Choose the highest speed speed at or below 'rate' with same PLL. */ |
| 319 | if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) { |
| 320 | while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) |
| 321 | tgt_s--; |
| 322 | } |
| 323 | |
| 324 | if (strt_s->pll != ACPU_PLL_TCXO) |
| 325 | plls_enabled |= 1 << strt_s->pll; |
| 326 | |
| 327 | if (!for_power_collapse) { |
| 328 | mutex_lock(&drv_state.lock); |
| 329 | if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { |
| 330 | rc = pc_pll_request(tgt_s->pll, 1); |
| 331 | if (rc < 0) { |
| 332 | pr_err("PLL%d enable failed (%d)\n", |
| 333 | tgt_s->pll, rc); |
| 334 | goto out; |
| 335 | } |
| 336 | plls_enabled |= 1 << tgt_s->pll; |
| 337 | } |
| 338 | /* Increase VDD if needed. */ |
| 339 | if (tgt_s->vdd > cur_s->vdd) { |
| 340 | if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) { |
| 341 | printk(KERN_ERR "Unable to switch ACPU vdd\n"); |
| 342 | goto out; |
| 343 | } |
| 344 | } |
| 345 | } |
| 346 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 347 | /* Set wait states for CPU between frequency changes */ |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 348 | reg_clkctl = readl(A11S_CLK_CNTL_ADDR); |
| 349 | reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ |
| 350 | writel(reg_clkctl, A11S_CLK_CNTL_ADDR); |
| 351 | |
| 352 | #if PERF_SWITCH_DEBUG |
| 353 | printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n", |
| 354 | strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000); |
| 355 | #endif |
| 356 | |
| 357 | while (cur_s != tgt_s) { |
| 358 | /* |
| 359 | * Always jump to target freq if within 256mhz, regulardless of |
| 360 | * PLL. If differnece is greater, use the predefinied |
| 361 | * steppings in the table. |
| 362 | */ |
| 363 | int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz)); |
| 364 | if (d > drv_state.max_speed_delta_khz) { |
| 365 | /* Step up or down depending on target vs current. */ |
| 366 | int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ? |
| 367 | cur_s->up : cur_s->down; |
| 368 | if (clk_index < 0) { /* This should not happen. */ |
| 369 | printk(KERN_ERR "cur:%u target: %u\n", |
| 370 | cur_s->a11clk_khz, tgt_s->a11clk_khz); |
| 371 | rc = -EINVAL; |
| 372 | goto out; |
| 373 | } |
| 374 | cur_s = &acpu_freq_tbl[clk_index]; |
| 375 | } else { |
| 376 | cur_s = tgt_s; |
| 377 | } |
| 378 | #if PERF_SWITCH_STEP_DEBUG |
| 379 | printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", |
| 380 | __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); |
| 381 | #endif |
| 382 | if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO |
| 383 | && !(plls_enabled & (1 << cur_s->pll))) { |
| 384 | rc = pc_pll_request(cur_s->pll, 1); |
| 385 | if (rc < 0) { |
| 386 | pr_err("PLL%d enable failed (%d)\n", |
| 387 | cur_s->pll, rc); |
| 388 | goto out; |
| 389 | } |
| 390 | plls_enabled |= 1 << cur_s->pll; |
| 391 | } |
| 392 | |
| 393 | acpuclk_set_div(cur_s); |
| 394 | drv_state.current_speed = cur_s; |
| 395 | /* Re-adjust lpj for the new clock speed. */ |
| 396 | loops_per_jiffy = cur_s->lpj; |
| 397 | udelay(drv_state.acpu_switch_time_us); |
| 398 | } |
| 399 | |
| 400 | /* Nothing else to do for power collapse. */ |
| 401 | if (for_power_collapse) |
| 402 | return 0; |
| 403 | |
| 404 | /* Disable PLLs we are not using anymore. */ |
| 405 | plls_enabled &= ~(1 << tgt_s->pll); |
| 406 | for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++) |
| 407 | if (plls_enabled & (1 << pll)) { |
| 408 | rc = pc_pll_request(pll, 0); |
| 409 | if (rc < 0) { |
| 410 | pr_err("PLL%d disable failed (%d)\n", pll, rc); |
| 411 | goto out; |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | /* Change the AXI bus frequency if we can. */ |
| 416 | if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { |
| 417 | rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000); |
| 418 | if (rc < 0) |
| 419 | pr_err("Setting AXI min rate failed!\n"); |
| 420 | } |
| 421 | |
| 422 | /* Drop VDD level if we can. */ |
| 423 | if (tgt_s->vdd < strt_s->vdd) { |
| 424 | if (acpuclk_set_vdd_level(tgt_s->vdd) < 0) |
| 425 | printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n"); |
| 426 | } |
| 427 | |
| 428 | #if PERF_SWITCH_DEBUG |
| 429 | printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__); |
| 430 | #endif |
| 431 | out: |
| 432 | if (!for_power_collapse) |
| 433 | mutex_unlock(&drv_state.lock); |
| 434 | return rc; |
| 435 | } |
| 436 | |
| 437 | static void __init acpuclk_init(void) |
| 438 | { |
| 439 | struct clkctl_acpu_speed *speed; |
| 440 | uint32_t div, sel; |
| 441 | int rc; |
| 442 | |
| 443 | /* |
| 444 | * Determine the rate of ACPU clock |
| 445 | */ |
| 446 | |
| 447 | if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ |
| 448 | /* CLK_SRC0_SEL */ |
| 449 | sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; |
| 450 | /* CLK_SRC0_DIV */ |
| 451 | div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f; |
| 452 | } else { |
| 453 | /* CLK_SRC1_SEL */ |
| 454 | sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; |
| 455 | /* CLK_SRC1_DIV */ |
| 456 | div = readl(A11S_CLK_CNTL_ADDR) & 0x0f; |
| 457 | } |
| 458 | |
| 459 | for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) { |
| 460 | if (speed->a11clk_src_sel == sel |
| 461 | && (speed->a11clk_src_div == div)) |
| 462 | break; |
| 463 | } |
| 464 | if (speed->a11clk_khz == 0) { |
| 465 | printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n"); |
| 466 | return; |
| 467 | } |
| 468 | |
| 469 | drv_state.current_speed = speed; |
| 470 | |
| 471 | rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000); |
| 472 | if (rc < 0) |
| 473 | pr_err("Setting AXI min rate failed!\n"); |
| 474 | |
| 475 | printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz); |
| 476 | } |
| 477 | |
| 478 | unsigned long acpuclk_get_rate(void) |
| 479 | { |
| 480 | WARN_ONCE(drv_state.current_speed == NULL, |
| 481 | "acpuclk_get_rate: not initialized\n"); |
| 482 | if (drv_state.current_speed) |
| 483 | return drv_state.current_speed->a11clk_khz; |
| 484 | else |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | uint32_t acpuclk_get_switch_time(void) |
| 489 | { |
| 490 | return drv_state.acpu_switch_time_us; |
| 491 | } |
| 492 | |
| 493 | /*---------------------------------------------------------------------------- |
| 494 | * Clock driver initialization |
| 495 | *---------------------------------------------------------------------------*/ |
| 496 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 497 | /* Initalize the lpj field in the acpu_freq_tbl. */ |
Daniel Walker | 43b39f9 | 2010-03-03 08:54:11 -0800 | [diff] [blame] | 498 | static void __init lpj_init(void) |
| 499 | { |
| 500 | int i; |
| 501 | const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; |
| 502 | for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) { |
| 503 | acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, |
| 504 | base_clk->a11clk_khz, |
| 505 | acpu_freq_tbl[i].a11clk_khz); |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) |
| 510 | { |
| 511 | pr_info("acpu_clock_init()\n"); |
| 512 | |
| 513 | ebi1_clk = clk_get(NULL, "ebi1_clk"); |
| 514 | |
| 515 | mutex_init(&drv_state.lock); |
| 516 | drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; |
| 517 | drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz; |
| 518 | drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; |
| 519 | drv_state.power_collapse_khz = clkdata->power_collapse_khz; |
| 520 | drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz; |
| 521 | acpuclk_init(); |
| 522 | lpj_init(); |
| 523 | #ifdef CONFIG_CPU_FREQ_TABLE |
| 524 | cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); |
| 525 | #endif |
| 526 | } |