Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1 | /************************************************************************* |
| 2 | * myri10ge.c: Myricom Myri-10G Ethernet driver. |
| 3 | * |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 4 | * Copyright (C) 2005 - 2009 Myricom, Inc. |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. Neither the name of Myricom, Inc. nor the names of its contributors |
| 16 | * may be used to endorse or promote products derived from this software |
| 17 | * without specific prior written permission. |
| 18 | * |
Brice Goglin | 4a2e612 | 2007-02-27 17:18:40 +0100 | [diff] [blame] | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
Brice Goglin | 4a2e612 | 2007-02-27 17:18:40 +0100 | [diff] [blame] | 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 | * POSSIBILITY OF SUCH DAMAGE. |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 30 | * |
| 31 | * |
| 32 | * If the eeprom on your board is not recent enough, you will need to get a |
| 33 | * newer firmware image at: |
| 34 | * http://www.myri.com/scs/download-Myri10GE.html |
| 35 | * |
| 36 | * Contact Information: |
| 37 | * <help@myri.com> |
| 38 | * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006 |
| 39 | *************************************************************************/ |
| 40 | |
| 41 | #include <linux/tcp.h> |
| 42 | #include <linux/netdevice.h> |
| 43 | #include <linux/skbuff.h> |
| 44 | #include <linux/string.h> |
| 45 | #include <linux/module.h> |
| 46 | #include <linux/pci.h> |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 47 | #include <linux/dma-mapping.h> |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 48 | #include <linux/etherdevice.h> |
| 49 | #include <linux/if_ether.h> |
| 50 | #include <linux/if_vlan.h> |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 51 | #include <linux/inet_lro.h> |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 52 | #include <linux/dca.h> |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 53 | #include <linux/ip.h> |
| 54 | #include <linux/inet.h> |
| 55 | #include <linux/in.h> |
| 56 | #include <linux/ethtool.h> |
| 57 | #include <linux/firmware.h> |
| 58 | #include <linux/delay.h> |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 59 | #include <linux/timer.h> |
| 60 | #include <linux/vmalloc.h> |
| 61 | #include <linux/crc32.h> |
| 62 | #include <linux/moduleparam.h> |
| 63 | #include <linux/io.h> |
vignesh babu | 199126a | 2007-07-09 11:50:22 -0700 | [diff] [blame] | 64 | #include <linux/log2.h> |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 65 | #include <net/checksum.h> |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 66 | #include <net/ip.h> |
| 67 | #include <net/tcp.h> |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 68 | #include <asm/byteorder.h> |
| 69 | #include <asm/io.h> |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 70 | #include <asm/processor.h> |
| 71 | #ifdef CONFIG_MTRR |
| 72 | #include <asm/mtrr.h> |
| 73 | #endif |
| 74 | |
| 75 | #include "myri10ge_mcp.h" |
| 76 | #include "myri10ge_mcp_gen_header.h" |
| 77 | |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 78 | #define MYRI10GE_VERSION_STR "1.5.0-1.432" |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 79 | |
| 80 | MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); |
| 81 | MODULE_AUTHOR("Maintainer: help@myri.com"); |
| 82 | MODULE_VERSION(MYRI10GE_VERSION_STR); |
| 83 | MODULE_LICENSE("Dual BSD/GPL"); |
| 84 | |
| 85 | #define MYRI10GE_MAX_ETHER_MTU 9014 |
| 86 | |
| 87 | #define MYRI10GE_ETH_STOPPED 0 |
| 88 | #define MYRI10GE_ETH_STOPPING 1 |
| 89 | #define MYRI10GE_ETH_STARTING 2 |
| 90 | #define MYRI10GE_ETH_RUNNING 3 |
| 91 | #define MYRI10GE_ETH_OPEN_FAILED 4 |
| 92 | |
| 93 | #define MYRI10GE_EEPROM_STRINGS_SIZE 256 |
| 94 | #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2) |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 95 | #define MYRI10GE_MAX_LRO_DESCRIPTORS 8 |
| 96 | #define MYRI10GE_LRO_MAX_PKTS 64 |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 97 | |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 98 | #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 99 | #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff |
| 100 | |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 101 | #define MYRI10GE_ALLOC_ORDER 0 |
| 102 | #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE) |
| 103 | #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1) |
| 104 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 105 | #define MYRI10GE_MAX_SLICES 32 |
| 106 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 107 | struct myri10ge_rx_buffer_state { |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 108 | struct page *page; |
| 109 | int page_offset; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 110 | DECLARE_PCI_UNMAP_ADDR(bus) |
| 111 | DECLARE_PCI_UNMAP_LEN(len) |
| 112 | }; |
| 113 | |
| 114 | struct myri10ge_tx_buffer_state { |
| 115 | struct sk_buff *skb; |
| 116 | int last; |
| 117 | DECLARE_PCI_UNMAP_ADDR(bus) |
| 118 | DECLARE_PCI_UNMAP_LEN(len) |
| 119 | }; |
| 120 | |
| 121 | struct myri10ge_cmd { |
| 122 | u32 data0; |
| 123 | u32 data1; |
| 124 | u32 data2; |
| 125 | }; |
| 126 | |
| 127 | struct myri10ge_rx_buf { |
| 128 | struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 129 | struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */ |
| 130 | struct myri10ge_rx_buffer_state *info; |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 131 | struct page *page; |
| 132 | dma_addr_t bus; |
| 133 | int page_offset; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 134 | int cnt; |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 135 | int fill_cnt; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 136 | int alloc_fail; |
| 137 | int mask; /* number of rx slots -1 */ |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 138 | int watchdog_needed; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 139 | }; |
| 140 | |
| 141 | struct myri10ge_tx_buf { |
| 142 | struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */ |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 143 | __be32 __iomem *send_go; /* "go" doorbell ptr */ |
| 144 | __be32 __iomem *send_stop; /* "stop" doorbell ptr */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 145 | struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */ |
| 146 | char *req_bytes; |
| 147 | struct myri10ge_tx_buffer_state *info; |
| 148 | int mask; /* number of transmit slots -1 */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 149 | int req ____cacheline_aligned; /* transmit slots submitted */ |
| 150 | int pkt_start; /* packets started */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 151 | int stop_queue; |
| 152 | int linearized; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 153 | int done ____cacheline_aligned; /* transmit slots completed */ |
| 154 | int pkt_done; /* packets completed */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 155 | int wake_queue; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 156 | int queue_active; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | struct myri10ge_rx_done { |
| 160 | struct mcp_slot *entry; |
| 161 | dma_addr_t bus; |
| 162 | int cnt; |
| 163 | int idx; |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 164 | struct net_lro_mgr lro_mgr; |
| 165 | struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS]; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 166 | }; |
| 167 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 168 | struct myri10ge_slice_netstats { |
| 169 | unsigned long rx_packets; |
| 170 | unsigned long tx_packets; |
| 171 | unsigned long rx_bytes; |
| 172 | unsigned long tx_bytes; |
| 173 | unsigned long rx_dropped; |
| 174 | unsigned long tx_dropped; |
| 175 | }; |
| 176 | |
| 177 | struct myri10ge_slice_state { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 178 | struct myri10ge_tx_buf tx; /* transmit ring */ |
| 179 | struct myri10ge_rx_buf rx_small; |
| 180 | struct myri10ge_rx_buf rx_big; |
| 181 | struct myri10ge_rx_done rx_done; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 182 | struct net_device *dev; |
| 183 | struct napi_struct napi; |
| 184 | struct myri10ge_priv *mgp; |
| 185 | struct myri10ge_slice_netstats stats; |
| 186 | __be32 __iomem *irq_claim; |
| 187 | struct mcp_irq_data *fw_stats; |
| 188 | dma_addr_t fw_stats_bus; |
| 189 | int watchdog_tx_done; |
| 190 | int watchdog_tx_req; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 191 | int watchdog_rx_done; |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 192 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 193 | int cached_dca_tag; |
| 194 | int cpu; |
| 195 | __be32 __iomem *dca_tag; |
| 196 | #endif |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 197 | char irq_desc[32]; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 198 | }; |
| 199 | |
| 200 | struct myri10ge_priv { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 201 | struct myri10ge_slice_state *ss; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 202 | int tx_boundary; /* boundary transmits cannot cross */ |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 203 | int num_slices; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 204 | int running; /* running? */ |
| 205 | int csum_flag; /* rx_csums? */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 206 | int small_bytes; |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 207 | int big_bytes; |
Brice Goglin | fa0a90d | 2008-05-09 02:20:25 +0200 | [diff] [blame] | 208 | int max_intr_slots; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 209 | struct net_device *dev; |
| 210 | struct net_device_stats stats; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 211 | spinlock_t stats_lock; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 212 | u8 __iomem *sram; |
| 213 | int sram_size; |
| 214 | unsigned long board_span; |
| 215 | unsigned long iomem_base; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 216 | __be32 __iomem *irq_deassert; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 217 | char *mac_addr_string; |
| 218 | struct mcp_cmd_response *cmd; |
| 219 | dma_addr_t cmd_bus; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 220 | struct pci_dev *pdev; |
| 221 | int msi_enabled; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 222 | int msix_enabled; |
| 223 | struct msix_entry *msix_vectors; |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 224 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 225 | int dca_enabled; |
| 226 | #endif |
Al Viro | 66341ff | 2007-12-22 18:56:43 +0000 | [diff] [blame] | 227 | u32 link_state; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 228 | unsigned int rdma_tags_available; |
| 229 | int intr_coal_delay; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 230 | __be32 __iomem *intr_coal_delay_ptr; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 231 | int mtrr; |
Brice Goglin | 276e26c | 2007-03-07 20:02:32 +0100 | [diff] [blame] | 232 | int wc_enabled; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 233 | int down_cnt; |
| 234 | wait_queue_head_t down_wq; |
| 235 | struct work_struct watchdog_work; |
| 236 | struct timer_list watchdog_timer; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 237 | int watchdog_resets; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 238 | int watchdog_pause; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 239 | int pause; |
| 240 | char *fw_name; |
| 241 | char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE]; |
Brice Goglin | c0bf880 | 2008-05-09 02:18:24 +0200 | [diff] [blame] | 242 | char *product_code_string; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 243 | char fw_version[128]; |
Brice Goglin | 9dc6f0e | 2007-02-21 18:05:17 +0100 | [diff] [blame] | 244 | int fw_ver_major; |
| 245 | int fw_ver_minor; |
| 246 | int fw_ver_tiny; |
| 247 | int adopted_rx_filter_bug; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 248 | u8 mac_addr[6]; /* eeprom mac address */ |
| 249 | unsigned long serial_number; |
| 250 | int vendor_specific_offset; |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 251 | int fw_multicast_support; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 252 | unsigned long features; |
| 253 | u32 max_tso6; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 254 | u32 read_dma; |
| 255 | u32 write_dma; |
| 256 | u32 read_write_dma; |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 257 | u32 link_changes; |
| 258 | u32 msg_enable; |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 259 | unsigned int board_number; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 260 | int rebooted; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 261 | }; |
| 262 | |
| 263 | static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat"; |
| 264 | static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat"; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 265 | static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat"; |
| 266 | static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat"; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 267 | |
| 268 | static char *myri10ge_fw_name = NULL; |
| 269 | module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 270 | MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 271 | |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 272 | #define MYRI10GE_MAX_BOARDS 8 |
| 273 | static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] = |
Andrew Gallatin | 7fe624f | 2009-04-17 15:45:15 -0700 | [diff] [blame] | 274 | {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL }; |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 275 | module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL, |
| 276 | 0444); |
| 277 | MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board"); |
| 278 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 279 | static int myri10ge_ecrc_enable = 1; |
| 280 | module_param(myri10ge_ecrc_enable, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 281 | MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 282 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 283 | static int myri10ge_small_bytes = -1; /* -1 == auto */ |
| 284 | module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 285 | MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 286 | |
| 287 | static int myri10ge_msi = 1; /* enable msi by default */ |
Brice Goglin | 3621cec | 2006-12-18 11:51:22 +0100 | [diff] [blame] | 288 | module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 289 | MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 290 | |
Brice Goglin | f761fae | 2007-03-21 19:45:56 +0100 | [diff] [blame] | 291 | static int myri10ge_intr_coal_delay = 75; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 292 | module_param(myri10ge_intr_coal_delay, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 293 | MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 294 | |
| 295 | static int myri10ge_flow_control = 1; |
| 296 | module_param(myri10ge_flow_control, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 297 | MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 298 | |
| 299 | static int myri10ge_deassert_wait = 1; |
| 300 | module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR); |
| 301 | MODULE_PARM_DESC(myri10ge_deassert_wait, |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 302 | "Wait when deasserting legacy interrupts"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 303 | |
| 304 | static int myri10ge_force_firmware = 0; |
| 305 | module_param(myri10ge_force_firmware, int, S_IRUGO); |
| 306 | MODULE_PARM_DESC(myri10ge_force_firmware, |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 307 | "Force firmware to assume aligned completions"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 308 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 309 | static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; |
| 310 | module_param(myri10ge_initial_mtu, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 311 | MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 312 | |
| 313 | static int myri10ge_napi_weight = 64; |
| 314 | module_param(myri10ge_napi_weight, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 315 | MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 316 | |
| 317 | static int myri10ge_watchdog_timeout = 1; |
| 318 | module_param(myri10ge_watchdog_timeout, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 319 | MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 320 | |
| 321 | static int myri10ge_max_irq_loops = 1048576; |
| 322 | module_param(myri10ge_max_irq_loops, int, S_IRUGO); |
| 323 | MODULE_PARM_DESC(myri10ge_max_irq_loops, |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 324 | "Set stuck legacy IRQ detection threshold"); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 325 | |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 326 | #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK |
| 327 | |
| 328 | static int myri10ge_debug = -1; /* defaults above */ |
| 329 | module_param(myri10ge_debug, int, 0); |
| 330 | MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)"); |
| 331 | |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 332 | static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS; |
| 333 | module_param(myri10ge_lro_max_pkts, int, S_IRUGO); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 334 | MODULE_PARM_DESC(myri10ge_lro_max_pkts, |
| 335 | "Number of LRO packets to be aggregated"); |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 336 | |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 337 | static int myri10ge_fill_thresh = 256; |
| 338 | module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR); |
Brice Goglin | d1ce3a0 | 2008-05-09 02:16:53 +0200 | [diff] [blame] | 339 | MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed"); |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 340 | |
Brice Goglin | f181137 | 2007-06-11 20:26:31 +0200 | [diff] [blame] | 341 | static int myri10ge_reset_recover = 1; |
| 342 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 343 | static int myri10ge_max_slices = 1; |
| 344 | module_param(myri10ge_max_slices, int, S_IRUGO); |
| 345 | MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues"); |
| 346 | |
| 347 | static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT; |
| 348 | module_param(myri10ge_rss_hash, int, S_IRUGO); |
| 349 | MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do"); |
| 350 | |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 351 | static int myri10ge_dca = 1; |
| 352 | module_param(myri10ge_dca, int, S_IRUGO); |
| 353 | MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible"); |
| 354 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 355 | #define MYRI10GE_FW_OFFSET 1024*1024 |
| 356 | #define MYRI10GE_HIGHPART_TO_U32(X) \ |
| 357 | (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0) |
| 358 | #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X)) |
| 359 | |
| 360 | #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8) |
| 361 | |
Brice Goglin | 2f76216 | 2007-05-07 23:50:37 +0200 | [diff] [blame] | 362 | static void myri10ge_set_multicast_list(struct net_device *dev); |
Stephen Hemminger | 61357325 | 2009-08-31 19:50:58 +0000 | [diff] [blame^] | 363 | static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb, |
| 364 | struct net_device *dev); |
Brice Goglin | 2f76216 | 2007-05-07 23:50:37 +0200 | [diff] [blame] | 365 | |
Brice Goglin | 6250223 | 2006-12-11 11:24:37 +0100 | [diff] [blame] | 366 | static inline void put_be32(__be32 val, __be32 __iomem * p) |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 367 | { |
Brice Goglin | 6250223 | 2006-12-11 11:24:37 +0100 | [diff] [blame] | 368 | __raw_writel((__force __u32) val, (__force void __iomem *)p); |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 369 | } |
| 370 | |
Brice Goglin | 5908182 | 2009-04-16 02:23:56 +0000 | [diff] [blame] | 371 | static struct net_device_stats *myri10ge_get_stats(struct net_device *dev); |
| 372 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 373 | static int |
| 374 | myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd, |
| 375 | struct myri10ge_cmd *data, int atomic) |
| 376 | { |
| 377 | struct mcp_cmd *buf; |
| 378 | char buf_bytes[sizeof(*buf) + 8]; |
| 379 | struct mcp_cmd_response *response = mgp->cmd; |
Brice Goglin | e700f9f | 2006-08-14 17:52:54 -0400 | [diff] [blame] | 380 | char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 381 | u32 dma_low, dma_high, result, value; |
| 382 | int sleep_total = 0; |
| 383 | |
| 384 | /* ensure buf is aligned to 8 bytes */ |
| 385 | buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8); |
| 386 | |
| 387 | buf->data0 = htonl(data->data0); |
| 388 | buf->data1 = htonl(data->data1); |
| 389 | buf->data2 = htonl(data->data2); |
| 390 | buf->cmd = htonl(cmd); |
| 391 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); |
| 392 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); |
| 393 | |
| 394 | buf->response_addr.low = htonl(dma_low); |
| 395 | buf->response_addr.high = htonl(dma_high); |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 396 | response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 397 | mb(); |
| 398 | myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf)); |
| 399 | |
| 400 | /* wait up to 15ms. Longest command is the DMA benchmark, |
| 401 | * which is capped at 5ms, but runs from a timeout handler |
| 402 | * that runs every 7.8ms. So a 15ms timeout leaves us with |
| 403 | * a 2.2ms margin |
| 404 | */ |
| 405 | if (atomic) { |
| 406 | /* if atomic is set, do not sleep, |
| 407 | * and try to get the completion quickly |
| 408 | * (1ms will be enough for those commands) */ |
| 409 | for (sleep_total = 0; |
| 410 | sleep_total < 1000 |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 411 | && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT); |
Brice Goglin | bd2db0c | 2008-05-09 02:18:45 +0200 | [diff] [blame] | 412 | sleep_total += 10) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 413 | udelay(10); |
Brice Goglin | bd2db0c | 2008-05-09 02:18:45 +0200 | [diff] [blame] | 414 | mb(); |
| 415 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 416 | } else { |
| 417 | /* use msleep for most command */ |
| 418 | for (sleep_total = 0; |
| 419 | sleep_total < 15 |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 420 | && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 421 | sleep_total++) |
| 422 | msleep(1); |
| 423 | } |
| 424 | |
| 425 | result = ntohl(response->result); |
| 426 | value = ntohl(response->data); |
| 427 | if (result != MYRI10GE_NO_RESPONSE_RESULT) { |
| 428 | if (result == 0) { |
| 429 | data->data0 = value; |
| 430 | return 0; |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 431 | } else if (result == MXGEFW_CMD_UNKNOWN) { |
| 432 | return -ENOSYS; |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 433 | } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) { |
| 434 | return -E2BIG; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 435 | } else if (result == MXGEFW_CMD_ERROR_RANGE && |
| 436 | cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES && |
| 437 | (data-> |
| 438 | data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) != |
| 439 | 0) { |
| 440 | return -ERANGE; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 441 | } else { |
| 442 | dev_err(&mgp->pdev->dev, |
| 443 | "command %d failed, result = %d\n", |
| 444 | cmd, result); |
| 445 | return -ENXIO; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n", |
| 450 | cmd, result); |
| 451 | return -EAGAIN; |
| 452 | } |
| 453 | |
| 454 | /* |
| 455 | * The eeprom strings on the lanaiX have the format |
| 456 | * SN=x\0 |
| 457 | * MAC=x:x:x:x:x:x\0 |
| 458 | * PT:ddd mmm xx xx:xx:xx xx\0 |
| 459 | * PV:ddd mmm xx xx:xx:xx xx\0 |
| 460 | */ |
| 461 | static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp) |
| 462 | { |
| 463 | char *ptr, *limit; |
| 464 | int i; |
| 465 | |
| 466 | ptr = mgp->eeprom_strings; |
| 467 | limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE; |
| 468 | |
| 469 | while (*ptr != '\0' && ptr < limit) { |
| 470 | if (memcmp(ptr, "MAC=", 4) == 0) { |
| 471 | ptr += 4; |
| 472 | mgp->mac_addr_string = ptr; |
| 473 | for (i = 0; i < 6; i++) { |
| 474 | if ((ptr + 2) > limit) |
| 475 | goto abort; |
| 476 | mgp->mac_addr[i] = |
| 477 | simple_strtoul(ptr, &ptr, 16); |
| 478 | ptr += 1; |
| 479 | } |
| 480 | } |
Brice Goglin | c0bf880 | 2008-05-09 02:18:24 +0200 | [diff] [blame] | 481 | if (memcmp(ptr, "PC=", 3) == 0) { |
| 482 | ptr += 3; |
| 483 | mgp->product_code_string = ptr; |
| 484 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 485 | if (memcmp((const void *)ptr, "SN=", 3) == 0) { |
| 486 | ptr += 3; |
| 487 | mgp->serial_number = simple_strtoul(ptr, &ptr, 10); |
| 488 | } |
| 489 | while (ptr < limit && *ptr++) ; |
| 490 | } |
| 491 | |
| 492 | return 0; |
| 493 | |
| 494 | abort: |
| 495 | dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n"); |
| 496 | return -ENXIO; |
| 497 | } |
| 498 | |
| 499 | /* |
| 500 | * Enable or disable periodic RDMAs from the host to make certain |
| 501 | * chipsets resend dropped PCIe messages |
| 502 | */ |
| 503 | |
| 504 | static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable) |
| 505 | { |
| 506 | char __iomem *submit; |
Brice Goglin | f8fd57c | 2008-05-09 02:17:37 +0200 | [diff] [blame] | 507 | __be32 buf[16] __attribute__ ((__aligned__(8))); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 508 | u32 dma_low, dma_high; |
| 509 | int i; |
| 510 | |
| 511 | /* clear confirmation addr */ |
| 512 | mgp->cmd->data = 0; |
| 513 | mb(); |
| 514 | |
| 515 | /* send a rdma command to the PCIe engine, and wait for the |
| 516 | * response in the confirmation address. The firmware should |
| 517 | * write a -1 there to indicate it is alive and well |
| 518 | */ |
| 519 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); |
| 520 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); |
| 521 | |
| 522 | buf[0] = htonl(dma_high); /* confirm addr MSW */ |
| 523 | buf[1] = htonl(dma_low); /* confirm addr LSW */ |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 524 | buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 525 | buf[3] = htonl(dma_high); /* dummy addr MSW */ |
| 526 | buf[4] = htonl(dma_low); /* dummy addr LSW */ |
| 527 | buf[5] = htonl(enable); /* enable? */ |
| 528 | |
Brice Goglin | e700f9f | 2006-08-14 17:52:54 -0400 | [diff] [blame] | 529 | submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 530 | |
| 531 | myri10ge_pio_copy(submit, &buf, sizeof(buf)); |
| 532 | for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++) |
| 533 | msleep(1); |
| 534 | if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) |
| 535 | dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n", |
| 536 | (enable ? "enable" : "disable")); |
| 537 | } |
| 538 | |
| 539 | static int |
| 540 | myri10ge_validate_firmware(struct myri10ge_priv *mgp, |
| 541 | struct mcp_gen_header *hdr) |
| 542 | { |
| 543 | struct device *dev = &mgp->pdev->dev; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 544 | |
| 545 | /* check firmware type */ |
| 546 | if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) { |
| 547 | dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type)); |
| 548 | return -EINVAL; |
| 549 | } |
| 550 | |
| 551 | /* save firmware version for ethtool */ |
| 552 | strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version)); |
| 553 | |
Brice Goglin | 9dc6f0e | 2007-02-21 18:05:17 +0100 | [diff] [blame] | 554 | sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major, |
| 555 | &mgp->fw_ver_minor, &mgp->fw_ver_tiny); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 556 | |
Brice Goglin | 9dc6f0e | 2007-02-21 18:05:17 +0100 | [diff] [blame] | 557 | if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR |
| 558 | && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 559 | dev_err(dev, "Found firmware version %s\n", mgp->fw_version); |
| 560 | dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR, |
| 561 | MXGEFW_VERSION_MINOR); |
| 562 | return -EINVAL; |
| 563 | } |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size) |
| 568 | { |
| 569 | unsigned crc, reread_crc; |
| 570 | const struct firmware *fw; |
| 571 | struct device *dev = &mgp->pdev->dev; |
David Woodhouse | b0d31d6 | 2008-05-24 00:00:07 +0100 | [diff] [blame] | 572 | unsigned char *fw_readback; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 573 | struct mcp_gen_header *hdr; |
| 574 | size_t hdr_offset; |
| 575 | int status; |
Brice Goglin | e454358 | 2006-07-30 00:14:09 -0400 | [diff] [blame] | 576 | unsigned i; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 577 | |
| 578 | if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) { |
| 579 | dev_err(dev, "Unable to load %s firmware image via hotplug\n", |
| 580 | mgp->fw_name); |
| 581 | status = -EINVAL; |
| 582 | goto abort_with_nothing; |
| 583 | } |
| 584 | |
| 585 | /* check size */ |
| 586 | |
| 587 | if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET || |
| 588 | fw->size < MCP_HEADER_PTR_OFFSET + 4) { |
| 589 | dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size); |
| 590 | status = -EINVAL; |
| 591 | goto abort_with_fw; |
| 592 | } |
| 593 | |
| 594 | /* check id */ |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 595 | hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 596 | if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) { |
| 597 | dev_err(dev, "Bad firmware file\n"); |
| 598 | status = -EINVAL; |
| 599 | goto abort_with_fw; |
| 600 | } |
| 601 | hdr = (void *)(fw->data + hdr_offset); |
| 602 | |
| 603 | status = myri10ge_validate_firmware(mgp, hdr); |
| 604 | if (status != 0) |
| 605 | goto abort_with_fw; |
| 606 | |
| 607 | crc = crc32(~0, fw->data, fw->size); |
Brice Goglin | e454358 | 2006-07-30 00:14:09 -0400 | [diff] [blame] | 608 | for (i = 0; i < fw->size; i += 256) { |
| 609 | myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i, |
| 610 | fw->data + i, |
| 611 | min(256U, (unsigned)(fw->size - i))); |
| 612 | mb(); |
| 613 | readb(mgp->sram); |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 614 | } |
David Woodhouse | b0d31d6 | 2008-05-24 00:00:07 +0100 | [diff] [blame] | 615 | fw_readback = vmalloc(fw->size); |
| 616 | if (!fw_readback) { |
| 617 | status = -ENOMEM; |
| 618 | goto abort_with_fw; |
| 619 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 620 | /* corruption checking is good for parity recovery and buggy chipset */ |
David Woodhouse | b0d31d6 | 2008-05-24 00:00:07 +0100 | [diff] [blame] | 621 | memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size); |
| 622 | reread_crc = crc32(~0, fw_readback, fw->size); |
| 623 | vfree(fw_readback); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 624 | if (crc != reread_crc) { |
| 625 | dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n", |
| 626 | (unsigned)fw->size, reread_crc, crc); |
| 627 | status = -EIO; |
| 628 | goto abort_with_fw; |
| 629 | } |
| 630 | *size = (u32) fw->size; |
| 631 | |
| 632 | abort_with_fw: |
| 633 | release_firmware(fw); |
| 634 | |
| 635 | abort_with_nothing: |
| 636 | return status; |
| 637 | } |
| 638 | |
| 639 | static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp) |
| 640 | { |
| 641 | struct mcp_gen_header *hdr; |
| 642 | struct device *dev = &mgp->pdev->dev; |
| 643 | const size_t bytes = sizeof(struct mcp_gen_header); |
| 644 | size_t hdr_offset; |
| 645 | int status; |
| 646 | |
| 647 | /* find running firmware header */ |
Al Viro | 66341ff | 2007-12-22 18:56:43 +0000 | [diff] [blame] | 648 | hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 649 | |
| 650 | if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) { |
| 651 | dev_err(dev, "Running firmware has bad header offset (%d)\n", |
| 652 | (int)hdr_offset); |
| 653 | return -EIO; |
| 654 | } |
| 655 | |
| 656 | /* copy header of running firmware from SRAM to host memory to |
| 657 | * validate firmware */ |
| 658 | hdr = kmalloc(bytes, GFP_KERNEL); |
| 659 | if (hdr == NULL) { |
| 660 | dev_err(dev, "could not malloc firmware hdr\n"); |
| 661 | return -ENOMEM; |
| 662 | } |
| 663 | memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes); |
| 664 | status = myri10ge_validate_firmware(mgp, hdr); |
| 665 | kfree(hdr); |
Brice Goglin | 9dc6f0e | 2007-02-21 18:05:17 +0100 | [diff] [blame] | 666 | |
| 667 | /* check to see if adopted firmware has bug where adopting |
| 668 | * it will cause broadcasts to be filtered unless the NIC |
| 669 | * is kept in ALLMULTI mode */ |
| 670 | if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 && |
| 671 | mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) { |
| 672 | mgp->adopted_rx_filter_bug = 1; |
| 673 | dev_warn(dev, "Adopting fw %d.%d.%d: " |
| 674 | "working around rx filter bug\n", |
| 675 | mgp->fw_ver_major, mgp->fw_ver_minor, |
| 676 | mgp->fw_ver_tiny); |
| 677 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 678 | return status; |
| 679 | } |
| 680 | |
Adrian Bunk | 0178ec3 | 2008-05-20 00:53:00 +0300 | [diff] [blame] | 681 | static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp) |
Brice Goglin | fa0a90d | 2008-05-09 02:20:25 +0200 | [diff] [blame] | 682 | { |
| 683 | struct myri10ge_cmd cmd; |
| 684 | int status; |
| 685 | |
| 686 | /* probe for IPv6 TSO support */ |
| 687 | mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO; |
| 688 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, |
| 689 | &cmd, 0); |
| 690 | if (status == 0) { |
| 691 | mgp->max_tso6 = cmd.data0; |
| 692 | mgp->features |= NETIF_F_TSO6; |
| 693 | } |
| 694 | |
| 695 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0); |
| 696 | if (status != 0) { |
| 697 | dev_err(&mgp->pdev->dev, |
| 698 | "failed MXGEFW_CMD_GET_RX_RING_SIZE\n"); |
| 699 | return -ENXIO; |
| 700 | } |
| 701 | |
| 702 | mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr)); |
| 703 | |
| 704 | return 0; |
| 705 | } |
| 706 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 707 | static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 708 | { |
| 709 | char __iomem *submit; |
Brice Goglin | f8fd57c | 2008-05-09 02:17:37 +0200 | [diff] [blame] | 710 | __be32 buf[16] __attribute__ ((__aligned__(8))); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 711 | u32 dma_low, dma_high, size; |
| 712 | int status, i; |
| 713 | |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 714 | size = 0; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 715 | status = myri10ge_load_hotplug_firmware(mgp, &size); |
| 716 | if (status) { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 717 | if (!adopt) |
| 718 | return status; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 719 | dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n"); |
| 720 | |
| 721 | /* Do not attempt to adopt firmware if there |
| 722 | * was a bad crc */ |
| 723 | if (status == -EIO) |
| 724 | return status; |
| 725 | |
| 726 | status = myri10ge_adopt_running_firmware(mgp); |
| 727 | if (status != 0) { |
| 728 | dev_err(&mgp->pdev->dev, |
| 729 | "failed to adopt running firmware\n"); |
| 730 | return status; |
| 731 | } |
| 732 | dev_info(&mgp->pdev->dev, |
| 733 | "Successfully adopted running firmware\n"); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 734 | if (mgp->tx_boundary == 4096) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 735 | dev_warn(&mgp->pdev->dev, |
| 736 | "Using firmware currently running on NIC" |
| 737 | ". For optimal\n"); |
| 738 | dev_warn(&mgp->pdev->dev, |
| 739 | "performance consider loading optimized " |
| 740 | "firmware\n"); |
| 741 | dev_warn(&mgp->pdev->dev, "via hotplug\n"); |
| 742 | } |
| 743 | |
| 744 | mgp->fw_name = "adopted"; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 745 | mgp->tx_boundary = 2048; |
Brice Goglin | fa0a90d | 2008-05-09 02:20:25 +0200 | [diff] [blame] | 746 | myri10ge_dummy_rdma(mgp, 1); |
| 747 | status = myri10ge_get_firmware_capabilities(mgp); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 748 | return status; |
| 749 | } |
| 750 | |
| 751 | /* clear confirmation addr */ |
| 752 | mgp->cmd->data = 0; |
| 753 | mb(); |
| 754 | |
| 755 | /* send a reload command to the bootstrap MCP, and wait for the |
| 756 | * response in the confirmation address. The firmware should |
| 757 | * write a -1 there to indicate it is alive and well |
| 758 | */ |
| 759 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); |
| 760 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); |
| 761 | |
| 762 | buf[0] = htonl(dma_high); /* confirm addr MSW */ |
| 763 | buf[1] = htonl(dma_low); /* confirm addr LSW */ |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 764 | buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 765 | |
| 766 | /* FIX: All newest firmware should un-protect the bottom of |
| 767 | * the sram before handoff. However, the very first interfaces |
| 768 | * do not. Therefore the handoff copy must skip the first 8 bytes |
| 769 | */ |
| 770 | buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */ |
| 771 | buf[4] = htonl(size - 8); /* length of code */ |
| 772 | buf[5] = htonl(8); /* where to copy to */ |
| 773 | buf[6] = htonl(0); /* where to jump to */ |
| 774 | |
Brice Goglin | e700f9f | 2006-08-14 17:52:54 -0400 | [diff] [blame] | 775 | submit = mgp->sram + MXGEFW_BOOT_HANDOFF; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 776 | |
| 777 | myri10ge_pio_copy(submit, &buf, sizeof(buf)); |
| 778 | mb(); |
| 779 | msleep(1); |
| 780 | mb(); |
| 781 | i = 0; |
Brice Goglin | d93ca2a | 2008-05-09 02:17:16 +0200 | [diff] [blame] | 782 | while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) { |
| 783 | msleep(1 << i); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 784 | i++; |
| 785 | } |
| 786 | if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) { |
| 787 | dev_err(&mgp->pdev->dev, "handoff failed\n"); |
| 788 | return -ENXIO; |
| 789 | } |
Brice Goglin | 9a71db7 | 2006-07-21 15:49:32 -0400 | [diff] [blame] | 790 | myri10ge_dummy_rdma(mgp, 1); |
Brice Goglin | fa0a90d | 2008-05-09 02:20:25 +0200 | [diff] [blame] | 791 | status = myri10ge_get_firmware_capabilities(mgp); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 792 | |
Brice Goglin | fa0a90d | 2008-05-09 02:20:25 +0200 | [diff] [blame] | 793 | return status; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 794 | } |
| 795 | |
| 796 | static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr) |
| 797 | { |
| 798 | struct myri10ge_cmd cmd; |
| 799 | int status; |
| 800 | |
| 801 | cmd.data0 = ((addr[0] << 24) | (addr[1] << 16) |
| 802 | | (addr[2] << 8) | addr[3]); |
| 803 | |
| 804 | cmd.data1 = ((addr[4] << 8) | (addr[5])); |
| 805 | |
| 806 | status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0); |
| 807 | return status; |
| 808 | } |
| 809 | |
| 810 | static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause) |
| 811 | { |
| 812 | struct myri10ge_cmd cmd; |
| 813 | int status, ctl; |
| 814 | |
| 815 | ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL; |
| 816 | status = myri10ge_send_cmd(mgp, ctl, &cmd, 0); |
| 817 | |
| 818 | if (status) { |
| 819 | printk(KERN_ERR |
| 820 | "myri10ge: %s: Failed to set flow control mode\n", |
| 821 | mgp->dev->name); |
| 822 | return status; |
| 823 | } |
| 824 | mgp->pause = pause; |
| 825 | return 0; |
| 826 | } |
| 827 | |
| 828 | static void |
| 829 | myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic) |
| 830 | { |
| 831 | struct myri10ge_cmd cmd; |
| 832 | int status, ctl; |
| 833 | |
| 834 | ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC; |
| 835 | status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic); |
| 836 | if (status) |
| 837 | printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n", |
| 838 | mgp->dev->name); |
| 839 | } |
| 840 | |
Brice Goglin | 0d6ac25 | 2007-05-07 23:51:45 +0200 | [diff] [blame] | 841 | static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type) |
| 842 | { |
| 843 | struct myri10ge_cmd cmd; |
| 844 | int status; |
| 845 | u32 len; |
| 846 | struct page *dmatest_page; |
| 847 | dma_addr_t dmatest_bus; |
| 848 | char *test = " "; |
| 849 | |
| 850 | dmatest_page = alloc_page(GFP_KERNEL); |
| 851 | if (!dmatest_page) |
| 852 | return -ENOMEM; |
| 853 | dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE, |
| 854 | DMA_BIDIRECTIONAL); |
| 855 | |
| 856 | /* Run a small DMA test. |
| 857 | * The magic multipliers to the length tell the firmware |
| 858 | * to do DMA read, write, or read+write tests. The |
| 859 | * results are returned in cmd.data0. The upper 16 |
| 860 | * bits or the return is the number of transfers completed. |
| 861 | * The lower 16 bits is the time in 0.5us ticks that the |
| 862 | * transfers took to complete. |
| 863 | */ |
| 864 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 865 | len = mgp->tx_boundary; |
Brice Goglin | 0d6ac25 | 2007-05-07 23:51:45 +0200 | [diff] [blame] | 866 | |
| 867 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus); |
| 868 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus); |
| 869 | cmd.data2 = len * 0x10000; |
| 870 | status = myri10ge_send_cmd(mgp, test_type, &cmd, 0); |
| 871 | if (status != 0) { |
| 872 | test = "read"; |
| 873 | goto abort; |
| 874 | } |
| 875 | mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff); |
| 876 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus); |
| 877 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus); |
| 878 | cmd.data2 = len * 0x1; |
| 879 | status = myri10ge_send_cmd(mgp, test_type, &cmd, 0); |
| 880 | if (status != 0) { |
| 881 | test = "write"; |
| 882 | goto abort; |
| 883 | } |
| 884 | mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff); |
| 885 | |
| 886 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus); |
| 887 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus); |
| 888 | cmd.data2 = len * 0x10001; |
| 889 | status = myri10ge_send_cmd(mgp, test_type, &cmd, 0); |
| 890 | if (status != 0) { |
| 891 | test = "read/write"; |
| 892 | goto abort; |
| 893 | } |
| 894 | mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) / |
| 895 | (cmd.data0 & 0xffff); |
| 896 | |
| 897 | abort: |
| 898 | pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); |
| 899 | put_page(dmatest_page); |
| 900 | |
| 901 | if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST) |
| 902 | dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n", |
| 903 | test, status); |
| 904 | |
| 905 | return status; |
| 906 | } |
| 907 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 908 | static int myri10ge_reset(struct myri10ge_priv *mgp) |
| 909 | { |
| 910 | struct myri10ge_cmd cmd; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 911 | struct myri10ge_slice_state *ss; |
| 912 | int i, status; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 913 | size_t bytes; |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 914 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 915 | unsigned long dca_tag_off; |
| 916 | #endif |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 917 | |
| 918 | /* try to send a reset command to the card to see if it |
| 919 | * is alive */ |
| 920 | memset(&cmd, 0, sizeof(cmd)); |
| 921 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0); |
| 922 | if (status != 0) { |
| 923 | dev_err(&mgp->pdev->dev, "failed reset\n"); |
| 924 | return -ENXIO; |
| 925 | } |
Brice Goglin | 0d6ac25 | 2007-05-07 23:51:45 +0200 | [diff] [blame] | 926 | |
| 927 | (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 928 | /* |
| 929 | * Use non-ndis mcp_slot (eg, 4 bytes total, |
| 930 | * no toeplitz hash value returned. Older firmware will |
| 931 | * not understand this command, but will use the correct |
| 932 | * sized mcp_slot, so we ignore error returns |
| 933 | */ |
| 934 | cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN; |
| 935 | (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 936 | |
| 937 | /* Now exchange information about interrupts */ |
| 938 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 939 | bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 940 | cmd.data0 = (u32) bytes; |
| 941 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 942 | |
| 943 | /* |
| 944 | * Even though we already know how many slices are supported |
| 945 | * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES |
| 946 | * has magic side effects, and must be called after a reset. |
| 947 | * It must be called prior to calling any RSS related cmds, |
| 948 | * including assigning an interrupt queue for anything but |
| 949 | * slice 0. It must also be called *after* |
| 950 | * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by |
| 951 | * the firmware to compute offsets. |
| 952 | */ |
| 953 | |
| 954 | if (mgp->num_slices > 1) { |
| 955 | |
| 956 | /* ask the maximum number of slices it supports */ |
| 957 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, |
| 958 | &cmd, 0); |
| 959 | if (status != 0) { |
| 960 | dev_err(&mgp->pdev->dev, |
| 961 | "failed to get number of slices\n"); |
| 962 | } |
| 963 | |
| 964 | /* |
| 965 | * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior |
| 966 | * to setting up the interrupt queue DMA |
| 967 | */ |
| 968 | |
| 969 | cmd.data0 = mgp->num_slices; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 970 | cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE; |
| 971 | if (mgp->dev->real_num_tx_queues > 1) |
| 972 | cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 973 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES, |
| 974 | &cmd, 0); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 975 | |
| 976 | /* Firmware older than 1.4.32 only supports multiple |
| 977 | * RX queues, so if we get an error, first retry using a |
| 978 | * single TX queue before giving up */ |
| 979 | if (status != 0 && mgp->dev->real_num_tx_queues > 1) { |
| 980 | mgp->dev->real_num_tx_queues = 1; |
| 981 | cmd.data0 = mgp->num_slices; |
| 982 | cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE; |
| 983 | status = myri10ge_send_cmd(mgp, |
| 984 | MXGEFW_CMD_ENABLE_RSS_QUEUES, |
| 985 | &cmd, 0); |
| 986 | } |
| 987 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 988 | if (status != 0) { |
| 989 | dev_err(&mgp->pdev->dev, |
| 990 | "failed to set number of slices\n"); |
| 991 | |
| 992 | return status; |
| 993 | } |
| 994 | } |
| 995 | for (i = 0; i < mgp->num_slices; i++) { |
| 996 | ss = &mgp->ss[i]; |
| 997 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus); |
| 998 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus); |
| 999 | cmd.data2 = i; |
| 1000 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, |
| 1001 | &cmd, 0); |
| 1002 | }; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1003 | |
| 1004 | status |= |
| 1005 | myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1006 | for (i = 0; i < mgp->num_slices; i++) { |
| 1007 | ss = &mgp->ss[i]; |
| 1008 | ss->irq_claim = |
| 1009 | (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i); |
| 1010 | } |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 1011 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, |
| 1012 | &cmd, 0); |
| 1013 | mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1014 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1015 | status |= myri10ge_send_cmd |
| 1016 | (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0); |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1017 | mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1018 | if (status != 0) { |
| 1019 | dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n"); |
| 1020 | return status; |
| 1021 | } |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1022 | put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1023 | |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 1024 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1025 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0); |
| 1026 | dca_tag_off = cmd.data0; |
| 1027 | for (i = 0; i < mgp->num_slices; i++) { |
| 1028 | ss = &mgp->ss[i]; |
| 1029 | if (status == 0) { |
| 1030 | ss->dca_tag = (__iomem __be32 *) |
| 1031 | (mgp->sram + dca_tag_off + 4 * i); |
| 1032 | } else { |
| 1033 | ss->dca_tag = NULL; |
| 1034 | } |
| 1035 | } |
Brice Goglin | 4ee2ac5 | 2008-11-23 15:49:28 -0800 | [diff] [blame] | 1036 | #endif /* CONFIG_MYRI10GE_DCA */ |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1037 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1038 | /* reset mcp/driver shared state back to 0 */ |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1039 | |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1040 | mgp->link_changes = 0; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1041 | for (i = 0; i < mgp->num_slices; i++) { |
| 1042 | ss = &mgp->ss[i]; |
| 1043 | |
| 1044 | memset(ss->rx_done.entry, 0, bytes); |
| 1045 | ss->tx.req = 0; |
| 1046 | ss->tx.done = 0; |
| 1047 | ss->tx.pkt_start = 0; |
| 1048 | ss->tx.pkt_done = 0; |
| 1049 | ss->rx_big.cnt = 0; |
| 1050 | ss->rx_small.cnt = 0; |
| 1051 | ss->rx_done.idx = 0; |
| 1052 | ss->rx_done.cnt = 0; |
| 1053 | ss->tx.wake_queue = 0; |
| 1054 | ss->tx.stop_queue = 0; |
| 1055 | } |
| 1056 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1057 | status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1058 | myri10ge_change_pause(mgp, mgp->pause); |
Brice Goglin | 2f76216 | 2007-05-07 23:50:37 +0200 | [diff] [blame] | 1059 | myri10ge_set_multicast_list(mgp->dev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1060 | return status; |
| 1061 | } |
| 1062 | |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 1063 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1064 | static void |
| 1065 | myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag) |
| 1066 | { |
| 1067 | ss->cpu = cpu; |
| 1068 | ss->cached_dca_tag = tag; |
| 1069 | put_be32(htonl(tag), ss->dca_tag); |
| 1070 | } |
| 1071 | |
| 1072 | static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss) |
| 1073 | { |
| 1074 | int cpu = get_cpu(); |
| 1075 | int tag; |
| 1076 | |
| 1077 | if (cpu != ss->cpu) { |
| 1078 | tag = dca_get_tag(cpu); |
| 1079 | if (ss->cached_dca_tag != tag) |
| 1080 | myri10ge_write_dca(ss, cpu, tag); |
| 1081 | } |
| 1082 | put_cpu(); |
| 1083 | } |
| 1084 | |
| 1085 | static void myri10ge_setup_dca(struct myri10ge_priv *mgp) |
| 1086 | { |
| 1087 | int err, i; |
| 1088 | struct pci_dev *pdev = mgp->pdev; |
| 1089 | |
| 1090 | if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled) |
| 1091 | return; |
| 1092 | if (!myri10ge_dca) { |
| 1093 | dev_err(&pdev->dev, "dca disabled by administrator\n"); |
| 1094 | return; |
| 1095 | } |
| 1096 | err = dca_add_requester(&pdev->dev); |
| 1097 | if (err) { |
Brice Goglin | 330554c | 2008-09-12 19:47:26 +0200 | [diff] [blame] | 1098 | if (err != -ENODEV) |
| 1099 | dev_err(&pdev->dev, |
| 1100 | "dca_add_requester() failed, err=%d\n", err); |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1101 | return; |
| 1102 | } |
| 1103 | mgp->dca_enabled = 1; |
| 1104 | for (i = 0; i < mgp->num_slices; i++) |
| 1105 | myri10ge_write_dca(&mgp->ss[i], -1, 0); |
| 1106 | } |
| 1107 | |
| 1108 | static void myri10ge_teardown_dca(struct myri10ge_priv *mgp) |
| 1109 | { |
| 1110 | struct pci_dev *pdev = mgp->pdev; |
| 1111 | int err; |
| 1112 | |
| 1113 | if (!mgp->dca_enabled) |
| 1114 | return; |
| 1115 | mgp->dca_enabled = 0; |
| 1116 | err = dca_remove_requester(&pdev->dev); |
| 1117 | } |
| 1118 | |
| 1119 | static int myri10ge_notify_dca_device(struct device *dev, void *data) |
| 1120 | { |
| 1121 | struct myri10ge_priv *mgp; |
| 1122 | unsigned long event; |
| 1123 | |
| 1124 | mgp = dev_get_drvdata(dev); |
| 1125 | event = *(unsigned long *)data; |
| 1126 | |
| 1127 | if (event == DCA_PROVIDER_ADD) |
| 1128 | myri10ge_setup_dca(mgp); |
| 1129 | else if (event == DCA_PROVIDER_REMOVE) |
| 1130 | myri10ge_teardown_dca(mgp); |
| 1131 | return 0; |
| 1132 | } |
Brice Goglin | 4ee2ac5 | 2008-11-23 15:49:28 -0800 | [diff] [blame] | 1133 | #endif /* CONFIG_MYRI10GE_DCA */ |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1134 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1135 | static inline void |
| 1136 | myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst, |
| 1137 | struct mcp_kreq_ether_recv *src) |
| 1138 | { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1139 | __be32 low; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1140 | |
| 1141 | low = src->addr_low; |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 1142 | src->addr_low = htonl(DMA_BIT_MASK(32)); |
Brice Goglin | e67bda5 | 2006-12-05 17:26:27 +0100 | [diff] [blame] | 1143 | myri10ge_pio_copy(dst, src, 4 * sizeof(*src)); |
| 1144 | mb(); |
| 1145 | myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1146 | mb(); |
| 1147 | src->addr_low = low; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1148 | put_be32(low, &dst->addr_low); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1149 | mb(); |
| 1150 | } |
| 1151 | |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1152 | static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1153 | { |
| 1154 | struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data); |
| 1155 | |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1156 | if ((skb->protocol == htons(ETH_P_8021Q)) && |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1157 | (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) || |
| 1158 | vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) { |
| 1159 | skb->csum = hw_csum; |
Patrick McHardy | 84fa793 | 2006-08-29 16:44:56 -0700 | [diff] [blame] | 1160 | skb->ip_summed = CHECKSUM_COMPLETE; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1161 | } |
| 1162 | } |
| 1163 | |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1164 | static inline void |
| 1165 | myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va, |
| 1166 | struct skb_frag_struct *rx_frags, int len, int hlen) |
| 1167 | { |
| 1168 | struct skb_frag_struct *skb_frags; |
| 1169 | |
| 1170 | skb->len = skb->data_len = len; |
| 1171 | skb->truesize = len + sizeof(struct sk_buff); |
| 1172 | /* attach the page(s) */ |
| 1173 | |
| 1174 | skb_frags = skb_shinfo(skb)->frags; |
| 1175 | while (len > 0) { |
| 1176 | memcpy(skb_frags, rx_frags, sizeof(*skb_frags)); |
| 1177 | len -= rx_frags->size; |
| 1178 | skb_frags++; |
| 1179 | rx_frags++; |
| 1180 | skb_shinfo(skb)->nr_frags++; |
| 1181 | } |
| 1182 | |
| 1183 | /* pskb_may_pull is not available in irq context, but |
| 1184 | * skb_pull() (for ether_pad and eth_type_trans()) requires |
| 1185 | * the beginning of the packet in skb_headlen(), move it |
| 1186 | * manually */ |
Arnaldo Carvalho de Melo | 27d7ff4 | 2007-03-31 11:55:19 -0300 | [diff] [blame] | 1187 | skb_copy_to_linear_data(skb, va, hlen); |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1188 | skb_shinfo(skb)->frags[0].page_offset += hlen; |
| 1189 | skb_shinfo(skb)->frags[0].size -= hlen; |
| 1190 | skb->data_len -= hlen; |
| 1191 | skb->tail += hlen; |
| 1192 | skb_pull(skb, MXGEFW_PAD); |
| 1193 | } |
| 1194 | |
| 1195 | static void |
| 1196 | myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx, |
| 1197 | int bytes, int watchdog) |
| 1198 | { |
| 1199 | struct page *page; |
| 1200 | int idx; |
| 1201 | |
| 1202 | if (unlikely(rx->watchdog_needed && !watchdog)) |
| 1203 | return; |
| 1204 | |
| 1205 | /* try to refill entire ring */ |
| 1206 | while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) { |
| 1207 | idx = rx->fill_cnt & rx->mask; |
Brice Goglin | ae8509b | 2007-04-10 21:21:08 +0200 | [diff] [blame] | 1208 | if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) { |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1209 | /* we can use part of previous page */ |
| 1210 | get_page(rx->page); |
| 1211 | } else { |
| 1212 | /* we need a new page */ |
| 1213 | page = |
| 1214 | alloc_pages(GFP_ATOMIC | __GFP_COMP, |
| 1215 | MYRI10GE_ALLOC_ORDER); |
| 1216 | if (unlikely(page == NULL)) { |
| 1217 | if (rx->fill_cnt - rx->cnt < 16) |
| 1218 | rx->watchdog_needed = 1; |
| 1219 | return; |
| 1220 | } |
| 1221 | rx->page = page; |
| 1222 | rx->page_offset = 0; |
| 1223 | rx->bus = pci_map_page(mgp->pdev, page, 0, |
| 1224 | MYRI10GE_ALLOC_SIZE, |
| 1225 | PCI_DMA_FROMDEVICE); |
| 1226 | } |
| 1227 | rx->info[idx].page = rx->page; |
| 1228 | rx->info[idx].page_offset = rx->page_offset; |
| 1229 | /* note that this is the address of the start of the |
| 1230 | * page */ |
| 1231 | pci_unmap_addr_set(&rx->info[idx], bus, rx->bus); |
| 1232 | rx->shadow[idx].addr_low = |
| 1233 | htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset); |
| 1234 | rx->shadow[idx].addr_high = |
| 1235 | htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus)); |
| 1236 | |
| 1237 | /* start next packet on a cacheline boundary */ |
| 1238 | rx->page_offset += SKB_DATA_ALIGN(bytes); |
Brice Goglin | ae8509b | 2007-04-10 21:21:08 +0200 | [diff] [blame] | 1239 | |
| 1240 | #if MYRI10GE_ALLOC_SIZE > 4096 |
| 1241 | /* don't cross a 4KB boundary */ |
| 1242 | if ((rx->page_offset >> 12) != |
| 1243 | ((rx->page_offset + bytes - 1) >> 12)) |
| 1244 | rx->page_offset = (rx->page_offset + 4096) & ~4095; |
| 1245 | #endif |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1246 | rx->fill_cnt++; |
| 1247 | |
| 1248 | /* copy 8 descriptors to the firmware at a time */ |
| 1249 | if ((idx & 7) == 7) { |
Brice Goglin | e454e7e | 2008-07-21 10:25:50 +0200 | [diff] [blame] | 1250 | myri10ge_submit_8rx(&rx->lanai[idx - 7], |
| 1251 | &rx->shadow[idx - 7]); |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1252 | } |
| 1253 | } |
| 1254 | } |
| 1255 | |
| 1256 | static inline void |
| 1257 | myri10ge_unmap_rx_page(struct pci_dev *pdev, |
| 1258 | struct myri10ge_rx_buffer_state *info, int bytes) |
| 1259 | { |
| 1260 | /* unmap the recvd page if we're the only or last user of it */ |
| 1261 | if (bytes >= MYRI10GE_ALLOC_SIZE / 2 || |
| 1262 | (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) { |
| 1263 | pci_unmap_page(pdev, (pci_unmap_addr(info, bus) |
| 1264 | & ~(MYRI10GE_ALLOC_SIZE - 1)), |
| 1265 | MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE); |
| 1266 | } |
| 1267 | } |
| 1268 | |
| 1269 | #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a |
| 1270 | * page into an skb */ |
| 1271 | |
| 1272 | static inline int |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1273 | myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx, |
Brice Goglin | 52ea6fb | 2006-12-11 11:26:12 +0100 | [diff] [blame] | 1274 | int bytes, int len, __wsum csum) |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1275 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1276 | struct myri10ge_priv *mgp = ss->mgp; |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1277 | struct sk_buff *skb; |
| 1278 | struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME]; |
| 1279 | int i, idx, hlen, remainder; |
| 1280 | struct pci_dev *pdev = mgp->pdev; |
| 1281 | struct net_device *dev = mgp->dev; |
| 1282 | u8 *va; |
| 1283 | |
| 1284 | len += MXGEFW_PAD; |
| 1285 | idx = rx->cnt & rx->mask; |
| 1286 | va = page_address(rx->info[idx].page) + rx->info[idx].page_offset; |
| 1287 | prefetch(va); |
| 1288 | /* Fill skb_frag_struct(s) with data from our receive */ |
| 1289 | for (i = 0, remainder = len; remainder > 0; i++) { |
| 1290 | myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes); |
| 1291 | rx_frags[i].page = rx->info[idx].page; |
| 1292 | rx_frags[i].page_offset = rx->info[idx].page_offset; |
| 1293 | if (remainder < MYRI10GE_ALLOC_SIZE) |
| 1294 | rx_frags[i].size = remainder; |
| 1295 | else |
| 1296 | rx_frags[i].size = MYRI10GE_ALLOC_SIZE; |
| 1297 | rx->cnt++; |
| 1298 | idx = rx->cnt & rx->mask; |
| 1299 | remainder -= MYRI10GE_ALLOC_SIZE; |
| 1300 | } |
| 1301 | |
Brice Goglin | 3a0c7d2 | 2009-05-19 10:15:32 +0000 | [diff] [blame] | 1302 | if (dev->features & NETIF_F_LRO) { |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 1303 | rx_frags[0].page_offset += MXGEFW_PAD; |
| 1304 | rx_frags[0].size -= MXGEFW_PAD; |
| 1305 | len -= MXGEFW_PAD; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1306 | lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags, |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1307 | /* opaque, will come back in get_frag_header */ |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1308 | len, len, |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1309 | (void *)(__force unsigned long)csum, csum); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1310 | |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 1311 | return 1; |
| 1312 | } |
| 1313 | |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1314 | hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN; |
| 1315 | |
Brice Goglin | e636b2e | 2007-10-13 12:32:21 +0200 | [diff] [blame] | 1316 | /* allocate an skb to attach the page(s) to. This is done |
| 1317 | * after trying LRO, so as to avoid skb allocation overheads */ |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1318 | |
| 1319 | skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16); |
| 1320 | if (unlikely(skb == NULL)) { |
Brice Goglin | d6279c8 | 2008-11-20 01:50:04 -0800 | [diff] [blame] | 1321 | ss->stats.rx_dropped++; |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1322 | do { |
| 1323 | i--; |
| 1324 | put_page(rx_frags[i].page); |
| 1325 | } while (i != 0); |
| 1326 | return 0; |
| 1327 | } |
| 1328 | |
| 1329 | /* Attach the pages to the skb, and trim off any padding */ |
| 1330 | myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen); |
| 1331 | if (skb_shinfo(skb)->frags[0].size <= 0) { |
| 1332 | put_page(skb_shinfo(skb)->frags[0].page); |
| 1333 | skb_shinfo(skb)->nr_frags = 0; |
| 1334 | } |
| 1335 | skb->protocol = eth_type_trans(skb, dev); |
David S. Miller | 0c8dfc8 | 2009-01-27 16:22:32 -0800 | [diff] [blame] | 1336 | skb_record_rx_queue(skb, ss - &mgp->ss[0]); |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1337 | |
| 1338 | if (mgp->csum_flag) { |
| 1339 | if ((skb->protocol == htons(ETH_P_IP)) || |
| 1340 | (skb->protocol == htons(ETH_P_IPV6))) { |
| 1341 | skb->csum = csum; |
| 1342 | skb->ip_summed = CHECKSUM_COMPLETE; |
| 1343 | } else |
| 1344 | myri10ge_vlan_ip_csum(skb, csum); |
| 1345 | } |
| 1346 | netif_receive_skb(skb); |
Brice Goglin | dd50f33 | 2006-12-11 11:25:09 +0100 | [diff] [blame] | 1347 | return 1; |
| 1348 | } |
| 1349 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1350 | static inline void |
| 1351 | myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1352 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1353 | struct pci_dev *pdev = ss->mgp->pdev; |
| 1354 | struct myri10ge_tx_buf *tx = &ss->tx; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1355 | struct netdev_queue *dev_queue; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1356 | struct sk_buff *skb; |
| 1357 | int idx, len; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1358 | |
| 1359 | while (tx->pkt_done != mcp_index) { |
| 1360 | idx = tx->done & tx->mask; |
| 1361 | skb = tx->info[idx].skb; |
| 1362 | |
| 1363 | /* Mark as free */ |
| 1364 | tx->info[idx].skb = NULL; |
| 1365 | if (tx->info[idx].last) { |
| 1366 | tx->pkt_done++; |
| 1367 | tx->info[idx].last = 0; |
| 1368 | } |
| 1369 | tx->done++; |
| 1370 | len = pci_unmap_len(&tx->info[idx], len); |
| 1371 | pci_unmap_len_set(&tx->info[idx], len, 0); |
| 1372 | if (skb) { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1373 | ss->stats.tx_bytes += skb->len; |
| 1374 | ss->stats.tx_packets++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1375 | dev_kfree_skb_irq(skb); |
| 1376 | if (len) |
| 1377 | pci_unmap_single(pdev, |
| 1378 | pci_unmap_addr(&tx->info[idx], |
| 1379 | bus), len, |
| 1380 | PCI_DMA_TODEVICE); |
| 1381 | } else { |
| 1382 | if (len) |
| 1383 | pci_unmap_page(pdev, |
| 1384 | pci_unmap_addr(&tx->info[idx], |
| 1385 | bus), len, |
| 1386 | PCI_DMA_TODEVICE); |
| 1387 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1388 | } |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1389 | |
| 1390 | dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss); |
| 1391 | /* |
| 1392 | * Make a minimal effort to prevent the NIC from polling an |
| 1393 | * idle tx queue. If we can't get the lock we leave the queue |
| 1394 | * active. In this case, either a thread was about to start |
| 1395 | * using the queue anyway, or we lost a race and the NIC will |
| 1396 | * waste some of its resources polling an inactive queue for a |
| 1397 | * while. |
| 1398 | */ |
| 1399 | |
| 1400 | if ((ss->mgp->dev->real_num_tx_queues > 1) && |
| 1401 | __netif_tx_trylock(dev_queue)) { |
| 1402 | if (tx->req == tx->done) { |
| 1403 | tx->queue_active = 0; |
| 1404 | put_be32(htonl(1), tx->send_stop); |
Brice Goglin | 8c2f5fa | 2008-11-10 13:58:41 +0100 | [diff] [blame] | 1405 | mb(); |
Brice Goglin | 6824a10 | 2008-10-30 08:59:33 +0100 | [diff] [blame] | 1406 | mmiowb(); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1407 | } |
| 1408 | __netif_tx_unlock(dev_queue); |
| 1409 | } |
| 1410 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1411 | /* start the queue if we've stopped it */ |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1412 | if (netif_tx_queue_stopped(dev_queue) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1413 | && tx->req - tx->done < (tx->mask >> 1)) { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1414 | tx->wake_queue++; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1415 | netif_tx_wake_queue(dev_queue); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1416 | } |
| 1417 | } |
| 1418 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1419 | static inline int |
| 1420 | myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1421 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1422 | struct myri10ge_rx_done *rx_done = &ss->rx_done; |
| 1423 | struct myri10ge_priv *mgp = ss->mgp; |
Brice Goglin | 18af3e7 | 2009-05-24 05:27:41 +0000 | [diff] [blame] | 1424 | struct net_device *netdev = mgp->dev; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1425 | unsigned long rx_bytes = 0; |
| 1426 | unsigned long rx_packets = 0; |
| 1427 | unsigned long rx_ok; |
| 1428 | |
| 1429 | int idx = rx_done->idx; |
| 1430 | int cnt = rx_done->cnt; |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1431 | int work_done = 0; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1432 | u16 length; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1433 | __wsum checksum; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1434 | |
Andrew Gallatin | c956a24 | 2007-10-31 17:40:06 -0400 | [diff] [blame] | 1435 | while (rx_done->entry[idx].length != 0 && work_done < budget) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1436 | length = ntohs(rx_done->entry[idx].length); |
| 1437 | rx_done->entry[idx].length = 0; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1438 | checksum = csum_unfold(rx_done->entry[idx].checksum); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1439 | if (length <= mgp->small_bytes) |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1440 | rx_ok = myri10ge_rx_done(ss, &ss->rx_small, |
Brice Goglin | 52ea6fb | 2006-12-11 11:26:12 +0100 | [diff] [blame] | 1441 | mgp->small_bytes, |
| 1442 | length, checksum); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1443 | else |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1444 | rx_ok = myri10ge_rx_done(ss, &ss->rx_big, |
Brice Goglin | 52ea6fb | 2006-12-11 11:26:12 +0100 | [diff] [blame] | 1445 | mgp->big_bytes, |
| 1446 | length, checksum); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1447 | rx_packets += rx_ok; |
| 1448 | rx_bytes += rx_ok * (unsigned long)length; |
| 1449 | cnt++; |
Brice Goglin | 014377a | 2008-05-09 02:20:47 +0200 | [diff] [blame] | 1450 | idx = cnt & (mgp->max_intr_slots - 1); |
Andrew Gallatin | c956a24 | 2007-10-31 17:40:06 -0400 | [diff] [blame] | 1451 | work_done++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1452 | } |
| 1453 | rx_done->idx = idx; |
| 1454 | rx_done->cnt = cnt; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1455 | ss->stats.rx_packets += rx_packets; |
| 1456 | ss->stats.rx_bytes += rx_bytes; |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 1457 | |
Brice Goglin | 18af3e7 | 2009-05-24 05:27:41 +0000 | [diff] [blame] | 1458 | if (netdev->features & NETIF_F_LRO) |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 1459 | lro_flush_all(&rx_done->lro_mgr); |
| 1460 | |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 1461 | /* restock receive rings if needed */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1462 | if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh) |
| 1463 | myri10ge_alloc_rx_pages(mgp, &ss->rx_small, |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 1464 | mgp->small_bytes + MXGEFW_PAD, 0); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1465 | if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh) |
| 1466 | myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0); |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 1467 | |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1468 | return work_done; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1469 | } |
| 1470 | |
| 1471 | static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp) |
| 1472 | { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1473 | struct mcp_irq_data *stats = mgp->ss[0].fw_stats; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1474 | |
| 1475 | if (unlikely(stats->stats_updated)) { |
Brice Goglin | 798a95d | 2007-06-11 20:26:50 +0200 | [diff] [blame] | 1476 | unsigned link_up = ntohl(stats->link_up); |
| 1477 | if (mgp->link_state != link_up) { |
| 1478 | mgp->link_state = link_up; |
| 1479 | |
| 1480 | if (mgp->link_state == MXGEFW_LINK_UP) { |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1481 | if (netif_msg_link(mgp)) |
| 1482 | printk(KERN_INFO |
| 1483 | "myri10ge: %s: link up\n", |
| 1484 | mgp->dev->name); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1485 | netif_carrier_on(mgp->dev); |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1486 | mgp->link_changes++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1487 | } else { |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1488 | if (netif_msg_link(mgp)) |
| 1489 | printk(KERN_INFO |
Brice Goglin | 798a95d | 2007-06-11 20:26:50 +0200 | [diff] [blame] | 1490 | "myri10ge: %s: link %s\n", |
| 1491 | mgp->dev->name, |
| 1492 | (link_up == MXGEFW_LINK_MYRINET ? |
| 1493 | "mismatch (Myrinet detected)" : |
| 1494 | "down")); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1495 | netif_carrier_off(mgp->dev); |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1496 | mgp->link_changes++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1497 | } |
| 1498 | } |
| 1499 | if (mgp->rdma_tags_available != |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1500 | ntohl(stats->rdma_tags_available)) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1501 | mgp->rdma_tags_available = |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1502 | ntohl(stats->rdma_tags_available); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1503 | printk(KERN_WARNING "myri10ge: %s: RDMA timed out! " |
| 1504 | "%d tags left\n", mgp->dev->name, |
| 1505 | mgp->rdma_tags_available); |
| 1506 | } |
| 1507 | mgp->down_cnt += stats->link_down; |
| 1508 | if (stats->link_down) |
| 1509 | wake_up(&mgp->down_wq); |
| 1510 | } |
| 1511 | } |
| 1512 | |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1513 | static int myri10ge_poll(struct napi_struct *napi, int budget) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1514 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1515 | struct myri10ge_slice_state *ss = |
| 1516 | container_of(napi, struct myri10ge_slice_state, napi); |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1517 | int work_done; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1518 | |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 1519 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1520 | if (ss->mgp->dca_enabled) |
| 1521 | myri10ge_update_dca(ss); |
| 1522 | #endif |
| 1523 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1524 | /* process as many rx events as NAPI will allow */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1525 | work_done = myri10ge_clean_rx_done(ss, budget); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1526 | |
David S. Miller | 4ec2411 | 2008-01-07 20:48:21 -0800 | [diff] [blame] | 1527 | if (work_done < budget) { |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 1528 | napi_complete(napi); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1529 | put_be32(htonl(3), ss->irq_claim); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1530 | } |
Stephen Hemminger | bea3348 | 2007-10-03 16:41:36 -0700 | [diff] [blame] | 1531 | return work_done; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1532 | } |
| 1533 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1534 | static irqreturn_t myri10ge_intr(int irq, void *arg) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1535 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1536 | struct myri10ge_slice_state *ss = arg; |
| 1537 | struct myri10ge_priv *mgp = ss->mgp; |
| 1538 | struct mcp_irq_data *stats = ss->fw_stats; |
| 1539 | struct myri10ge_tx_buf *tx = &ss->tx; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1540 | u32 send_done_count; |
| 1541 | int i; |
| 1542 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1543 | /* an interrupt on a non-zero receive-only slice is implicitly |
| 1544 | * valid since MSI-X irqs are not shared */ |
| 1545 | if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) { |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 1546 | napi_schedule(&ss->napi); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1547 | return (IRQ_HANDLED); |
| 1548 | } |
| 1549 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1550 | /* make sure it is our IRQ, and that the DMA has finished */ |
| 1551 | if (unlikely(!stats->valid)) |
| 1552 | return (IRQ_NONE); |
| 1553 | |
| 1554 | /* low bit indicates receives are present, so schedule |
| 1555 | * napi poll handler */ |
| 1556 | if (stats->valid & 1) |
Ben Hutchings | 288379f | 2009-01-19 16:43:59 -0800 | [diff] [blame] | 1557 | napi_schedule(&ss->napi); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1558 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1559 | if (!mgp->msi_enabled && !mgp->msix_enabled) { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1560 | put_be32(0, mgp->irq_deassert); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1561 | if (!myri10ge_deassert_wait) |
| 1562 | stats->valid = 0; |
| 1563 | mb(); |
| 1564 | } else |
| 1565 | stats->valid = 0; |
| 1566 | |
| 1567 | /* Wait for IRQ line to go low, if using INTx */ |
| 1568 | i = 0; |
| 1569 | while (1) { |
| 1570 | i++; |
| 1571 | /* check for transmit completes and receives */ |
| 1572 | send_done_count = ntohl(stats->send_done_count); |
| 1573 | if (send_done_count != tx->pkt_done) |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1574 | myri10ge_tx_done(ss, (int)send_done_count); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1575 | if (unlikely(i > myri10ge_max_irq_loops)) { |
| 1576 | printk(KERN_WARNING "myri10ge: %s: irq stuck?\n", |
| 1577 | mgp->dev->name); |
| 1578 | stats->valid = 0; |
| 1579 | schedule_work(&mgp->watchdog_work); |
| 1580 | } |
| 1581 | if (likely(stats->valid == 0)) |
| 1582 | break; |
| 1583 | cpu_relax(); |
| 1584 | barrier(); |
| 1585 | } |
| 1586 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1587 | /* Only slice 0 updates stats */ |
| 1588 | if (ss == mgp->ss) |
| 1589 | myri10ge_check_statblock(mgp); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1590 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1591 | put_be32(htonl(3), ss->irq_claim + 1); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1592 | return (IRQ_HANDLED); |
| 1593 | } |
| 1594 | |
| 1595 | static int |
| 1596 | myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) |
| 1597 | { |
Brice Goglin | c0bf880 | 2008-05-09 02:18:24 +0200 | [diff] [blame] | 1598 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1599 | char *ptr; |
| 1600 | int i; |
| 1601 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1602 | cmd->autoneg = AUTONEG_DISABLE; |
| 1603 | cmd->speed = SPEED_10000; |
| 1604 | cmd->duplex = DUPLEX_FULL; |
Brice Goglin | c0bf880 | 2008-05-09 02:18:24 +0200 | [diff] [blame] | 1605 | |
| 1606 | /* |
| 1607 | * parse the product code to deterimine the interface type |
| 1608 | * (CX4, XFP, Quad Ribbon Fiber) by looking at the character |
| 1609 | * after the 3rd dash in the driver's cached copy of the |
| 1610 | * EEPROM's product code string. |
| 1611 | */ |
| 1612 | ptr = mgp->product_code_string; |
| 1613 | if (ptr == NULL) { |
| 1614 | printk(KERN_ERR "myri10ge: %s: Missing product code\n", |
Brice Goglin | 99f5f87 | 2008-05-09 02:19:08 +0200 | [diff] [blame] | 1615 | netdev->name); |
Brice Goglin | c0bf880 | 2008-05-09 02:18:24 +0200 | [diff] [blame] | 1616 | return 0; |
| 1617 | } |
| 1618 | for (i = 0; i < 3; i++, ptr++) { |
| 1619 | ptr = strchr(ptr, '-'); |
| 1620 | if (ptr == NULL) { |
| 1621 | printk(KERN_ERR "myri10ge: %s: Invalid product " |
| 1622 | "code %s\n", netdev->name, |
| 1623 | mgp->product_code_string); |
| 1624 | return 0; |
| 1625 | } |
| 1626 | } |
| 1627 | if (*ptr == 'R' || *ptr == 'Q') { |
| 1628 | /* We've found either an XFP or quad ribbon fiber */ |
| 1629 | cmd->port = PORT_FIBRE; |
| 1630 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1631 | return 0; |
| 1632 | } |
| 1633 | |
| 1634 | static void |
| 1635 | myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info) |
| 1636 | { |
| 1637 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1638 | |
| 1639 | strlcpy(info->driver, "myri10ge", sizeof(info->driver)); |
| 1640 | strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version)); |
| 1641 | strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version)); |
| 1642 | strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info)); |
| 1643 | } |
| 1644 | |
| 1645 | static int |
| 1646 | myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal) |
| 1647 | { |
| 1648 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
Brice Goglin | 99f5f87 | 2008-05-09 02:19:08 +0200 | [diff] [blame] | 1649 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1650 | coal->rx_coalesce_usecs = mgp->intr_coal_delay; |
| 1651 | return 0; |
| 1652 | } |
| 1653 | |
| 1654 | static int |
| 1655 | myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal) |
| 1656 | { |
| 1657 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1658 | |
| 1659 | mgp->intr_coal_delay = coal->rx_coalesce_usecs; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 1660 | put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1661 | return 0; |
| 1662 | } |
| 1663 | |
| 1664 | static void |
| 1665 | myri10ge_get_pauseparam(struct net_device *netdev, |
| 1666 | struct ethtool_pauseparam *pause) |
| 1667 | { |
| 1668 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1669 | |
| 1670 | pause->autoneg = 0; |
| 1671 | pause->rx_pause = mgp->pause; |
| 1672 | pause->tx_pause = mgp->pause; |
| 1673 | } |
| 1674 | |
| 1675 | static int |
| 1676 | myri10ge_set_pauseparam(struct net_device *netdev, |
| 1677 | struct ethtool_pauseparam *pause) |
| 1678 | { |
| 1679 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1680 | |
| 1681 | if (pause->tx_pause != mgp->pause) |
| 1682 | return myri10ge_change_pause(mgp, pause->tx_pause); |
| 1683 | if (pause->rx_pause != mgp->pause) |
| 1684 | return myri10ge_change_pause(mgp, pause->tx_pause); |
| 1685 | if (pause->autoneg != 0) |
| 1686 | return -EINVAL; |
| 1687 | return 0; |
| 1688 | } |
| 1689 | |
| 1690 | static void |
| 1691 | myri10ge_get_ringparam(struct net_device *netdev, |
| 1692 | struct ethtool_ringparam *ring) |
| 1693 | { |
| 1694 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1695 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1696 | ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1; |
| 1697 | ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1698 | ring->rx_jumbo_max_pending = 0; |
Brice Goglin | 6498be3 | 2009-04-16 17:56:57 -0700 | [diff] [blame] | 1699 | ring->tx_max_pending = mgp->ss[0].tx.mask + 1; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1700 | ring->rx_mini_pending = ring->rx_mini_max_pending; |
| 1701 | ring->rx_pending = ring->rx_max_pending; |
| 1702 | ring->rx_jumbo_pending = ring->rx_jumbo_max_pending; |
| 1703 | ring->tx_pending = ring->tx_max_pending; |
| 1704 | } |
| 1705 | |
| 1706 | static u32 myri10ge_get_rx_csum(struct net_device *netdev) |
| 1707 | { |
| 1708 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
Brice Goglin | 99f5f87 | 2008-05-09 02:19:08 +0200 | [diff] [blame] | 1709 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1710 | if (mgp->csum_flag) |
| 1711 | return 1; |
| 1712 | else |
| 1713 | return 0; |
| 1714 | } |
| 1715 | |
| 1716 | static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled) |
| 1717 | { |
| 1718 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
Brice Goglin | 3a0c7d2 | 2009-05-19 10:15:32 +0000 | [diff] [blame] | 1719 | int err = 0; |
Brice Goglin | 99f5f87 | 2008-05-09 02:19:08 +0200 | [diff] [blame] | 1720 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1721 | if (csum_enabled) |
| 1722 | mgp->csum_flag = MXGEFW_FLAGS_CKSUM; |
Brice Goglin | 3a0c7d2 | 2009-05-19 10:15:32 +0000 | [diff] [blame] | 1723 | else { |
| 1724 | u32 flags = ethtool_op_get_flags(netdev); |
| 1725 | err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1726 | mgp->csum_flag = 0; |
Brice Goglin | 3a0c7d2 | 2009-05-19 10:15:32 +0000 | [diff] [blame] | 1727 | |
| 1728 | } |
| 1729 | return err; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1730 | } |
| 1731 | |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 1732 | static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled) |
| 1733 | { |
| 1734 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1735 | unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO); |
| 1736 | |
| 1737 | if (tso_enabled) |
| 1738 | netdev->features |= flags; |
| 1739 | else |
| 1740 | netdev->features &= ~flags; |
| 1741 | return 0; |
| 1742 | } |
| 1743 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1744 | static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1745 | "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", |
| 1746 | "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", |
| 1747 | "rx_length_errors", "rx_over_errors", "rx_crc_errors", |
| 1748 | "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", |
| 1749 | "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", |
| 1750 | "tx_heartbeat_errors", "tx_window_errors", |
| 1751 | /* device-specific stats */ |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1752 | "tx_boundary", "WC", "irq", "MSI", "MSIX", |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1753 | "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs", |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1754 | "serial_number", "watchdog_resets", |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 1755 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 9a6b3b5 | 2008-09-12 19:48:06 +0200 | [diff] [blame] | 1756 | "dca_capable_firmware", "dca_device_present", |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1757 | #endif |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1758 | "link_changes", "link_up", "dropped_link_overflow", |
Brice Goglin | cee505d | 2007-05-07 23:49:25 +0200 | [diff] [blame] | 1759 | "dropped_link_error_or_filtered", |
| 1760 | "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32", |
| 1761 | "dropped_unicast_filtered", "dropped_multicast_filtered", |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1762 | "dropped_runt", "dropped_overrun", "dropped_no_small_buffer", |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1763 | "dropped_no_big_buffer" |
| 1764 | }; |
| 1765 | |
| 1766 | static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = { |
| 1767 | "----------- slice ---------", |
| 1768 | "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done", |
| 1769 | "rx_small_cnt", "rx_big_cnt", |
| 1770 | "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated", |
| 1771 | "LRO flushed", |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 1772 | "LRO avg aggr", "LRO no_desc" |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1773 | }; |
| 1774 | |
| 1775 | #define MYRI10GE_NET_STATS_LEN 21 |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1776 | #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats) |
| 1777 | #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1778 | |
| 1779 | static void |
| 1780 | myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data) |
| 1781 | { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1782 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1783 | int i; |
| 1784 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1785 | switch (stringset) { |
| 1786 | case ETH_SS_STATS: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1787 | memcpy(data, *myri10ge_gstrings_main_stats, |
| 1788 | sizeof(myri10ge_gstrings_main_stats)); |
| 1789 | data += sizeof(myri10ge_gstrings_main_stats); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1790 | for (i = 0; i < mgp->num_slices; i++) { |
| 1791 | memcpy(data, *myri10ge_gstrings_slice_stats, |
| 1792 | sizeof(myri10ge_gstrings_slice_stats)); |
| 1793 | data += sizeof(myri10ge_gstrings_slice_stats); |
| 1794 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1795 | break; |
| 1796 | } |
| 1797 | } |
| 1798 | |
Jeff Garzik | b9f2c04 | 2007-10-03 18:07:32 -0700 | [diff] [blame] | 1799 | static int myri10ge_get_sset_count(struct net_device *netdev, int sset) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1800 | { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1801 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1802 | |
Jeff Garzik | b9f2c04 | 2007-10-03 18:07:32 -0700 | [diff] [blame] | 1803 | switch (sset) { |
| 1804 | case ETH_SS_STATS: |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1805 | return MYRI10GE_MAIN_STATS_LEN + |
| 1806 | mgp->num_slices * MYRI10GE_SLICE_STATS_LEN; |
Jeff Garzik | b9f2c04 | 2007-10-03 18:07:32 -0700 | [diff] [blame] | 1807 | default: |
| 1808 | return -EOPNOTSUPP; |
| 1809 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1810 | } |
| 1811 | |
| 1812 | static void |
| 1813 | myri10ge_get_ethtool_stats(struct net_device *netdev, |
| 1814 | struct ethtool_stats *stats, u64 * data) |
| 1815 | { |
| 1816 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1817 | struct myri10ge_slice_state *ss; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1818 | int slice; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1819 | int i; |
| 1820 | |
Brice Goglin | 5908182 | 2009-04-16 02:23:56 +0000 | [diff] [blame] | 1821 | /* force stats update */ |
| 1822 | (void)myri10ge_get_stats(netdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1823 | for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++) |
| 1824 | data[i] = ((unsigned long *)&mgp->stats)[i]; |
| 1825 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1826 | data[i++] = (unsigned int)mgp->tx_boundary; |
Brice Goglin | 276e26c | 2007-03-07 20:02:32 +0100 | [diff] [blame] | 1827 | data[i++] = (unsigned int)mgp->wc_enabled; |
Brice Goglin | 2c1a108 | 2006-07-03 18:16:46 -0400 | [diff] [blame] | 1828 | data[i++] = (unsigned int)mgp->pdev->irq; |
| 1829 | data[i++] = (unsigned int)mgp->msi_enabled; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1830 | data[i++] = (unsigned int)mgp->msix_enabled; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1831 | data[i++] = (unsigned int)mgp->read_dma; |
| 1832 | data[i++] = (unsigned int)mgp->write_dma; |
| 1833 | data[i++] = (unsigned int)mgp->read_write_dma; |
| 1834 | data[i++] = (unsigned int)mgp->serial_number; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1835 | data[i++] = (unsigned int)mgp->watchdog_resets; |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 1836 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 1837 | data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL); |
| 1838 | data[i++] = (unsigned int)(mgp->dca_enabled); |
| 1839 | #endif |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1840 | data[i++] = (unsigned int)mgp->link_changes; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1841 | |
| 1842 | /* firmware stats are useful only in the first slice */ |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1843 | ss = &mgp->ss[0]; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1844 | data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up); |
| 1845 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1846 | data[i++] = |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1847 | (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered); |
| 1848 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause); |
| 1849 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy); |
| 1850 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32); |
| 1851 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered); |
Brice Goglin | cee505d | 2007-05-07 23:49:25 +0200 | [diff] [blame] | 1852 | data[i++] = |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1853 | (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered); |
| 1854 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt); |
| 1855 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun); |
| 1856 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer); |
| 1857 | data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer); |
| 1858 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1859 | for (slice = 0; slice < mgp->num_slices; slice++) { |
| 1860 | ss = &mgp->ss[slice]; |
| 1861 | data[i++] = slice; |
| 1862 | data[i++] = (unsigned int)ss->tx.pkt_start; |
| 1863 | data[i++] = (unsigned int)ss->tx.pkt_done; |
| 1864 | data[i++] = (unsigned int)ss->tx.req; |
| 1865 | data[i++] = (unsigned int)ss->tx.done; |
| 1866 | data[i++] = (unsigned int)ss->rx_small.cnt; |
| 1867 | data[i++] = (unsigned int)ss->rx_big.cnt; |
| 1868 | data[i++] = (unsigned int)ss->tx.wake_queue; |
| 1869 | data[i++] = (unsigned int)ss->tx.stop_queue; |
| 1870 | data[i++] = (unsigned int)ss->tx.linearized; |
| 1871 | data[i++] = ss->rx_done.lro_mgr.stats.aggregated; |
| 1872 | data[i++] = ss->rx_done.lro_mgr.stats.flushed; |
| 1873 | if (ss->rx_done.lro_mgr.stats.flushed) |
| 1874 | data[i++] = ss->rx_done.lro_mgr.stats.aggregated / |
| 1875 | ss->rx_done.lro_mgr.stats.flushed; |
| 1876 | else |
| 1877 | data[i++] = 0; |
| 1878 | data[i++] = ss->rx_done.lro_mgr.stats.no_desc; |
| 1879 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1880 | } |
| 1881 | |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1882 | static void myri10ge_set_msglevel(struct net_device *netdev, u32 value) |
| 1883 | { |
| 1884 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1885 | mgp->msg_enable = value; |
| 1886 | } |
| 1887 | |
| 1888 | static u32 myri10ge_get_msglevel(struct net_device *netdev) |
| 1889 | { |
| 1890 | struct myri10ge_priv *mgp = netdev_priv(netdev); |
| 1891 | return mgp->msg_enable; |
| 1892 | } |
| 1893 | |
Jeff Garzik | 7282d49 | 2006-09-13 14:30:00 -0400 | [diff] [blame] | 1894 | static const struct ethtool_ops myri10ge_ethtool_ops = { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1895 | .get_settings = myri10ge_get_settings, |
| 1896 | .get_drvinfo = myri10ge_get_drvinfo, |
| 1897 | .get_coalesce = myri10ge_get_coalesce, |
| 1898 | .set_coalesce = myri10ge_set_coalesce, |
| 1899 | .get_pauseparam = myri10ge_get_pauseparam, |
| 1900 | .set_pauseparam = myri10ge_set_pauseparam, |
| 1901 | .get_ringparam = myri10ge_get_ringparam, |
| 1902 | .get_rx_csum = myri10ge_get_rx_csum, |
| 1903 | .set_rx_csum = myri10ge_set_rx_csum, |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 1904 | .set_tx_csum = ethtool_op_set_tx_hw_csum, |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1905 | .set_sg = ethtool_op_set_sg, |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 1906 | .set_tso = myri10ge_set_tso, |
Brice Goglin | 6ffdd07 | 2007-05-30 21:13:59 +0200 | [diff] [blame] | 1907 | .get_link = ethtool_op_get_link, |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1908 | .get_strings = myri10ge_get_strings, |
Jeff Garzik | b9f2c04 | 2007-10-03 18:07:32 -0700 | [diff] [blame] | 1909 | .get_sset_count = myri10ge_get_sset_count, |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 1910 | .get_ethtool_stats = myri10ge_get_ethtool_stats, |
| 1911 | .set_msglevel = myri10ge_set_msglevel, |
Brice Goglin | 3a0c7d2 | 2009-05-19 10:15:32 +0000 | [diff] [blame] | 1912 | .get_msglevel = myri10ge_get_msglevel, |
| 1913 | .get_flags = ethtool_op_get_flags, |
| 1914 | .set_flags = ethtool_op_set_flags |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1915 | }; |
| 1916 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1917 | static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1918 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1919 | struct myri10ge_priv *mgp = ss->mgp; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1920 | struct myri10ge_cmd cmd; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1921 | struct net_device *dev = mgp->dev; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1922 | int tx_ring_size, rx_ring_size; |
| 1923 | int tx_ring_entries, rx_ring_entries; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1924 | int i, slice, status; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1925 | size_t bytes; |
| 1926 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1927 | /* get ring sizes */ |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1928 | slice = ss - mgp->ss; |
| 1929 | cmd.data0 = slice; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1930 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0); |
| 1931 | tx_ring_size = cmd.data0; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1932 | cmd.data0 = slice; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1933 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0); |
Brice Goglin | 355c726 | 2007-03-07 19:59:52 +0100 | [diff] [blame] | 1934 | if (status != 0) |
| 1935 | return status; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1936 | rx_ring_size = cmd.data0; |
| 1937 | |
| 1938 | tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send); |
| 1939 | rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1940 | ss->tx.mask = tx_ring_entries - 1; |
| 1941 | ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1942 | |
Brice Goglin | 355c726 | 2007-03-07 19:59:52 +0100 | [diff] [blame] | 1943 | status = -ENOMEM; |
| 1944 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1945 | /* allocate the host shadow rings */ |
| 1946 | |
| 1947 | bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4) |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1948 | * sizeof(*ss->tx.req_list); |
| 1949 | ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL); |
| 1950 | if (ss->tx.req_bytes == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1951 | goto abort_with_nothing; |
| 1952 | |
| 1953 | /* ensure req_list entries are aligned to 8 bytes */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1954 | ss->tx.req_list = (struct mcp_kreq_ether_send *) |
| 1955 | ALIGN((unsigned long)ss->tx.req_bytes, 8); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 1956 | ss->tx.queue_active = 0; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1957 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1958 | bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow); |
| 1959 | ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL); |
| 1960 | if (ss->rx_small.shadow == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1961 | goto abort_with_tx_req_bytes; |
| 1962 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1963 | bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow); |
| 1964 | ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL); |
| 1965 | if (ss->rx_big.shadow == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1966 | goto abort_with_rx_small_shadow; |
| 1967 | |
| 1968 | /* allocate the host info rings */ |
| 1969 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1970 | bytes = tx_ring_entries * sizeof(*ss->tx.info); |
| 1971 | ss->tx.info = kzalloc(bytes, GFP_KERNEL); |
| 1972 | if (ss->tx.info == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1973 | goto abort_with_rx_big_shadow; |
| 1974 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1975 | bytes = rx_ring_entries * sizeof(*ss->rx_small.info); |
| 1976 | ss->rx_small.info = kzalloc(bytes, GFP_KERNEL); |
| 1977 | if (ss->rx_small.info == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1978 | goto abort_with_tx_info; |
| 1979 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1980 | bytes = rx_ring_entries * sizeof(*ss->rx_big.info); |
| 1981 | ss->rx_big.info = kzalloc(bytes, GFP_KERNEL); |
| 1982 | if (ss->rx_big.info == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1983 | goto abort_with_rx_small_info; |
| 1984 | |
| 1985 | /* Fill the receive rings */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1986 | ss->rx_big.cnt = 0; |
| 1987 | ss->rx_small.cnt = 0; |
| 1988 | ss->rx_big.fill_cnt = 0; |
| 1989 | ss->rx_small.fill_cnt = 0; |
| 1990 | ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE; |
| 1991 | ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE; |
| 1992 | ss->rx_small.watchdog_needed = 0; |
| 1993 | ss->rx_big.watchdog_needed = 0; |
| 1994 | myri10ge_alloc_rx_pages(mgp, &ss->rx_small, |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 1995 | mgp->small_bytes + MXGEFW_PAD, 0); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 1996 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 1997 | if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 1998 | printk(KERN_ERR |
| 1999 | "myri10ge: %s:slice-%d: alloced only %d small bufs\n", |
| 2000 | dev->name, slice, ss->rx_small.fill_cnt); |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2001 | goto abort_with_rx_small_ring; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2002 | } |
| 2003 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2004 | myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0); |
| 2005 | if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2006 | printk(KERN_ERR |
| 2007 | "myri10ge: %s:slice-%d: alloced only %d big bufs\n", |
| 2008 | dev->name, slice, ss->rx_big.fill_cnt); |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2009 | goto abort_with_rx_big_ring; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2010 | } |
| 2011 | |
| 2012 | return 0; |
| 2013 | |
| 2014 | abort_with_rx_big_ring: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2015 | for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) { |
| 2016 | int idx = i & ss->rx_big.mask; |
| 2017 | myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx], |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2018 | mgp->big_bytes); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2019 | put_page(ss->rx_big.info[idx].page); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2020 | } |
| 2021 | |
| 2022 | abort_with_rx_small_ring: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2023 | for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) { |
| 2024 | int idx = i & ss->rx_small.mask; |
| 2025 | myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx], |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2026 | mgp->small_bytes + MXGEFW_PAD); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2027 | put_page(ss->rx_small.info[idx].page); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2028 | } |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2029 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2030 | kfree(ss->rx_big.info); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2031 | |
| 2032 | abort_with_rx_small_info: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2033 | kfree(ss->rx_small.info); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2034 | |
| 2035 | abort_with_tx_info: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2036 | kfree(ss->tx.info); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2037 | |
| 2038 | abort_with_rx_big_shadow: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2039 | kfree(ss->rx_big.shadow); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2040 | |
| 2041 | abort_with_rx_small_shadow: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2042 | kfree(ss->rx_small.shadow); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2043 | |
| 2044 | abort_with_tx_req_bytes: |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2045 | kfree(ss->tx.req_bytes); |
| 2046 | ss->tx.req_bytes = NULL; |
| 2047 | ss->tx.req_list = NULL; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2048 | |
| 2049 | abort_with_nothing: |
| 2050 | return status; |
| 2051 | } |
| 2052 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2053 | static void myri10ge_free_rings(struct myri10ge_slice_state *ss) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2054 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2055 | struct myri10ge_priv *mgp = ss->mgp; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2056 | struct sk_buff *skb; |
| 2057 | struct myri10ge_tx_buf *tx; |
| 2058 | int i, len, idx; |
| 2059 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2060 | /* If not allocated, skip it */ |
| 2061 | if (ss->tx.req_list == NULL) |
| 2062 | return; |
| 2063 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2064 | for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) { |
| 2065 | idx = i & ss->rx_big.mask; |
| 2066 | if (i == ss->rx_big.fill_cnt - 1) |
| 2067 | ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE; |
| 2068 | myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx], |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2069 | mgp->big_bytes); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2070 | put_page(ss->rx_big.info[idx].page); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2071 | } |
| 2072 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2073 | for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) { |
| 2074 | idx = i & ss->rx_small.mask; |
| 2075 | if (i == ss->rx_small.fill_cnt - 1) |
| 2076 | ss->rx_small.info[idx].page_offset = |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2077 | MYRI10GE_ALLOC_SIZE; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2078 | myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx], |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2079 | mgp->small_bytes + MXGEFW_PAD); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2080 | put_page(ss->rx_small.info[idx].page); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2081 | } |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2082 | tx = &ss->tx; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2083 | while (tx->done != tx->req) { |
| 2084 | idx = tx->done & tx->mask; |
| 2085 | skb = tx->info[idx].skb; |
| 2086 | |
| 2087 | /* Mark as free */ |
| 2088 | tx->info[idx].skb = NULL; |
| 2089 | tx->done++; |
| 2090 | len = pci_unmap_len(&tx->info[idx], len); |
| 2091 | pci_unmap_len_set(&tx->info[idx], len, 0); |
| 2092 | if (skb) { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2093 | ss->stats.tx_dropped++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2094 | dev_kfree_skb_any(skb); |
| 2095 | if (len) |
| 2096 | pci_unmap_single(mgp->pdev, |
| 2097 | pci_unmap_addr(&tx->info[idx], |
| 2098 | bus), len, |
| 2099 | PCI_DMA_TODEVICE); |
| 2100 | } else { |
| 2101 | if (len) |
| 2102 | pci_unmap_page(mgp->pdev, |
| 2103 | pci_unmap_addr(&tx->info[idx], |
| 2104 | bus), len, |
| 2105 | PCI_DMA_TODEVICE); |
| 2106 | } |
| 2107 | } |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2108 | kfree(ss->rx_big.info); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2109 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2110 | kfree(ss->rx_small.info); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2111 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2112 | kfree(ss->tx.info); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2113 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2114 | kfree(ss->rx_big.shadow); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2115 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2116 | kfree(ss->rx_small.shadow); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2117 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2118 | kfree(ss->tx.req_bytes); |
| 2119 | ss->tx.req_bytes = NULL; |
| 2120 | ss->tx.req_list = NULL; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2121 | } |
| 2122 | |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2123 | static int myri10ge_request_irq(struct myri10ge_priv *mgp) |
| 2124 | { |
| 2125 | struct pci_dev *pdev = mgp->pdev; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2126 | struct myri10ge_slice_state *ss; |
| 2127 | struct net_device *netdev = mgp->dev; |
| 2128 | int i; |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2129 | int status; |
| 2130 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2131 | mgp->msi_enabled = 0; |
| 2132 | mgp->msix_enabled = 0; |
| 2133 | status = 0; |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2134 | if (myri10ge_msi) { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2135 | if (mgp->num_slices > 1) { |
| 2136 | status = |
| 2137 | pci_enable_msix(pdev, mgp->msix_vectors, |
| 2138 | mgp->num_slices); |
| 2139 | if (status == 0) { |
| 2140 | mgp->msix_enabled = 1; |
| 2141 | } else { |
| 2142 | dev_err(&pdev->dev, |
| 2143 | "Error %d setting up MSI-X\n", status); |
| 2144 | return status; |
| 2145 | } |
| 2146 | } |
| 2147 | if (mgp->msix_enabled == 0) { |
| 2148 | status = pci_enable_msi(pdev); |
| 2149 | if (status != 0) { |
| 2150 | dev_err(&pdev->dev, |
| 2151 | "Error %d setting up MSI; falling back to xPIC\n", |
| 2152 | status); |
| 2153 | } else { |
| 2154 | mgp->msi_enabled = 1; |
| 2155 | } |
| 2156 | } |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2157 | } |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2158 | if (mgp->msix_enabled) { |
| 2159 | for (i = 0; i < mgp->num_slices; i++) { |
| 2160 | ss = &mgp->ss[i]; |
| 2161 | snprintf(ss->irq_desc, sizeof(ss->irq_desc), |
| 2162 | "%s:slice-%d", netdev->name, i); |
| 2163 | status = request_irq(mgp->msix_vectors[i].vector, |
| 2164 | myri10ge_intr, 0, ss->irq_desc, |
| 2165 | ss); |
| 2166 | if (status != 0) { |
| 2167 | dev_err(&pdev->dev, |
| 2168 | "slice %d failed to allocate IRQ\n", i); |
| 2169 | i--; |
| 2170 | while (i >= 0) { |
| 2171 | free_irq(mgp->msix_vectors[i].vector, |
| 2172 | &mgp->ss[i]); |
| 2173 | i--; |
| 2174 | } |
| 2175 | pci_disable_msix(pdev); |
| 2176 | return status; |
| 2177 | } |
| 2178 | } |
| 2179 | } else { |
| 2180 | status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED, |
| 2181 | mgp->dev->name, &mgp->ss[0]); |
| 2182 | if (status != 0) { |
| 2183 | dev_err(&pdev->dev, "failed to allocate IRQ\n"); |
| 2184 | if (mgp->msi_enabled) |
| 2185 | pci_disable_msi(pdev); |
| 2186 | } |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2187 | } |
| 2188 | return status; |
| 2189 | } |
| 2190 | |
| 2191 | static void myri10ge_free_irq(struct myri10ge_priv *mgp) |
| 2192 | { |
| 2193 | struct pci_dev *pdev = mgp->pdev; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2194 | int i; |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2195 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2196 | if (mgp->msix_enabled) { |
| 2197 | for (i = 0; i < mgp->num_slices; i++) |
| 2198 | free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]); |
| 2199 | } else { |
| 2200 | free_irq(pdev->irq, &mgp->ss[0]); |
| 2201 | } |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2202 | if (mgp->msi_enabled) |
| 2203 | pci_disable_msi(pdev); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2204 | if (mgp->msix_enabled) |
| 2205 | pci_disable_msix(pdev); |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2206 | } |
| 2207 | |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 2208 | static int |
| 2209 | myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr, |
| 2210 | void **ip_hdr, void **tcpudp_hdr, |
| 2211 | u64 * hdr_flags, void *priv) |
| 2212 | { |
| 2213 | struct ethhdr *eh; |
| 2214 | struct vlan_ethhdr *veh; |
| 2215 | struct iphdr *iph; |
| 2216 | u8 *va = page_address(frag->page) + frag->page_offset; |
| 2217 | unsigned long ll_hlen; |
Al Viro | 66341ff | 2007-12-22 18:56:43 +0000 | [diff] [blame] | 2218 | /* passed opaque through lro_receive_frags() */ |
| 2219 | __wsum csum = (__force __wsum) (unsigned long)priv; |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 2220 | |
| 2221 | /* find the mac header, aborting if not IPv4 */ |
| 2222 | |
| 2223 | eh = (struct ethhdr *)va; |
| 2224 | *mac_hdr = eh; |
| 2225 | ll_hlen = ETH_HLEN; |
| 2226 | if (eh->h_proto != htons(ETH_P_IP)) { |
| 2227 | if (eh->h_proto == htons(ETH_P_8021Q)) { |
| 2228 | veh = (struct vlan_ethhdr *)va; |
| 2229 | if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP)) |
| 2230 | return -1; |
| 2231 | |
| 2232 | ll_hlen += VLAN_HLEN; |
| 2233 | |
| 2234 | /* |
| 2235 | * HW checksum starts ETH_HLEN bytes into |
| 2236 | * frame, so we must subtract off the VLAN |
| 2237 | * header's checksum before csum can be used |
| 2238 | */ |
| 2239 | csum = csum_sub(csum, csum_partial(va + ETH_HLEN, |
| 2240 | VLAN_HLEN, 0)); |
| 2241 | } else { |
| 2242 | return -1; |
| 2243 | } |
| 2244 | } |
| 2245 | *hdr_flags = LRO_IPV4; |
| 2246 | |
| 2247 | iph = (struct iphdr *)(va + ll_hlen); |
| 2248 | *ip_hdr = iph; |
| 2249 | if (iph->protocol != IPPROTO_TCP) |
| 2250 | return -1; |
Brice Goglin | bcb09dc | 2008-12-09 00:14:27 -0800 | [diff] [blame] | 2251 | if (iph->frag_off & htons(IP_MF | IP_OFFSET)) |
| 2252 | return -1; |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 2253 | *hdr_flags |= LRO_TCP; |
| 2254 | *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2); |
| 2255 | |
| 2256 | /* verify the IP checksum */ |
| 2257 | if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl))) |
| 2258 | return -1; |
| 2259 | |
| 2260 | /* verify the checksum */ |
| 2261 | if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr, |
| 2262 | ntohs(iph->tot_len) - (iph->ihl << 2), |
| 2263 | IPPROTO_TCP, csum))) |
| 2264 | return -1; |
| 2265 | |
| 2266 | return 0; |
| 2267 | } |
| 2268 | |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 2269 | static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice) |
| 2270 | { |
| 2271 | struct myri10ge_cmd cmd; |
| 2272 | struct myri10ge_slice_state *ss; |
| 2273 | int status; |
| 2274 | |
| 2275 | ss = &mgp->ss[slice]; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2276 | status = 0; |
| 2277 | if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) { |
| 2278 | cmd.data0 = slice; |
| 2279 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, |
| 2280 | &cmd, 0); |
| 2281 | ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *) |
| 2282 | (mgp->sram + cmd.data0); |
| 2283 | } |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 2284 | cmd.data0 = slice; |
| 2285 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, |
| 2286 | &cmd, 0); |
| 2287 | ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *) |
| 2288 | (mgp->sram + cmd.data0); |
| 2289 | |
| 2290 | cmd.data0 = slice; |
| 2291 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0); |
| 2292 | ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *) |
| 2293 | (mgp->sram + cmd.data0); |
| 2294 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2295 | ss->tx.send_go = (__iomem __be32 *) |
| 2296 | (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice); |
| 2297 | ss->tx.send_stop = (__iomem __be32 *) |
| 2298 | (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice); |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 2299 | return status; |
| 2300 | |
| 2301 | } |
| 2302 | |
| 2303 | static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice) |
| 2304 | { |
| 2305 | struct myri10ge_cmd cmd; |
| 2306 | struct myri10ge_slice_state *ss; |
| 2307 | int status; |
| 2308 | |
| 2309 | ss = &mgp->ss[slice]; |
| 2310 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus); |
| 2311 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2312 | cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16); |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 2313 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0); |
| 2314 | if (status == -ENOSYS) { |
| 2315 | dma_addr_t bus = ss->fw_stats_bus; |
| 2316 | if (slice != 0) |
| 2317 | return -EINVAL; |
| 2318 | bus += offsetof(struct mcp_irq_data, send_done_count); |
| 2319 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus); |
| 2320 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus); |
| 2321 | status = myri10ge_send_cmd(mgp, |
| 2322 | MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, |
| 2323 | &cmd, 0); |
| 2324 | /* Firmware cannot support multicast without STATS_DMA_V2 */ |
| 2325 | mgp->fw_multicast_support = 0; |
| 2326 | } else { |
| 2327 | mgp->fw_multicast_support = 1; |
| 2328 | } |
| 2329 | return 0; |
| 2330 | } |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 2331 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2332 | static int myri10ge_open(struct net_device *dev) |
| 2333 | { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2334 | struct myri10ge_slice_state *ss; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2335 | struct myri10ge_priv *mgp = netdev_priv(dev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2336 | struct myri10ge_cmd cmd; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2337 | int i, status, big_pow2, slice; |
| 2338 | u8 *itable; |
Andrew Gallatin | 1e6e934 | 2007-09-17 11:37:42 -0700 | [diff] [blame] | 2339 | struct net_lro_mgr *lro_mgr; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2340 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2341 | if (mgp->running != MYRI10GE_ETH_STOPPED) |
| 2342 | return -EBUSY; |
| 2343 | |
| 2344 | mgp->running = MYRI10GE_ETH_STARTING; |
| 2345 | status = myri10ge_reset(mgp); |
| 2346 | if (status != 0) { |
| 2347 | printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name); |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2348 | goto abort_with_nothing; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2349 | } |
| 2350 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2351 | if (mgp->num_slices > 1) { |
| 2352 | cmd.data0 = mgp->num_slices; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2353 | cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE; |
| 2354 | if (mgp->dev->real_num_tx_queues > 1) |
| 2355 | cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2356 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES, |
| 2357 | &cmd, 0); |
| 2358 | if (status != 0) { |
| 2359 | printk(KERN_ERR |
| 2360 | "myri10ge: %s: failed to set number of slices\n", |
| 2361 | dev->name); |
| 2362 | goto abort_with_nothing; |
| 2363 | } |
| 2364 | /* setup the indirection table */ |
| 2365 | cmd.data0 = mgp->num_slices; |
| 2366 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE, |
| 2367 | &cmd, 0); |
| 2368 | |
| 2369 | status |= myri10ge_send_cmd(mgp, |
| 2370 | MXGEFW_CMD_GET_RSS_TABLE_OFFSET, |
| 2371 | &cmd, 0); |
| 2372 | if (status != 0) { |
| 2373 | printk(KERN_ERR |
| 2374 | "myri10ge: %s: failed to setup rss tables\n", |
| 2375 | dev->name); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2376 | goto abort_with_nothing; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2377 | } |
| 2378 | |
| 2379 | /* just enable an identity mapping */ |
| 2380 | itable = mgp->sram + cmd.data0; |
| 2381 | for (i = 0; i < mgp->num_slices; i++) |
| 2382 | __raw_writeb(i, &itable[i]); |
| 2383 | |
| 2384 | cmd.data0 = 1; |
| 2385 | cmd.data1 = myri10ge_rss_hash; |
| 2386 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE, |
| 2387 | &cmd, 0); |
| 2388 | if (status != 0) { |
| 2389 | printk(KERN_ERR |
| 2390 | "myri10ge: %s: failed to enable slices\n", |
| 2391 | dev->name); |
| 2392 | goto abort_with_nothing; |
| 2393 | } |
| 2394 | } |
| 2395 | |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2396 | status = myri10ge_request_irq(mgp); |
| 2397 | if (status != 0) |
| 2398 | goto abort_with_nothing; |
| 2399 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2400 | /* decide what small buffer size to use. For good TCP rx |
| 2401 | * performance, it is important to not receive 1514 byte |
| 2402 | * frames into jumbo buffers, as it confuses the socket buffer |
| 2403 | * accounting code, leading to drops and erratic performance. |
| 2404 | */ |
| 2405 | |
| 2406 | if (dev->mtu <= ETH_DATA_LEN) |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2407 | /* enough for a TCP header */ |
| 2408 | mgp->small_bytes = (128 > SMP_CACHE_BYTES) |
| 2409 | ? (128 - MXGEFW_PAD) |
| 2410 | : (SMP_CACHE_BYTES - MXGEFW_PAD); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2411 | else |
Brice Goglin | de3c450 | 2006-12-11 11:26:38 +0100 | [diff] [blame] | 2412 | /* enough for a vlan encapsulated ETH_DATA_LEN frame */ |
| 2413 | mgp->small_bytes = VLAN_ETH_FRAME_LEN; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2414 | |
| 2415 | /* Override the small buffer size? */ |
| 2416 | if (myri10ge_small_bytes > 0) |
| 2417 | mgp->small_bytes = myri10ge_small_bytes; |
| 2418 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2419 | /* Firmware needs the big buff size as a power of 2. Lie and |
| 2420 | * tell him the buffer is larger, because we only use 1 |
| 2421 | * buffer/pkt, and the mtu will prevent overruns. |
| 2422 | */ |
Brice Goglin | 13348be | 2006-12-11 11:27:19 +0100 | [diff] [blame] | 2423 | big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD; |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2424 | if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) { |
vignesh babu | 199126a | 2007-07-09 11:50:22 -0700 | [diff] [blame] | 2425 | while (!is_power_of_2(big_pow2)) |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2426 | big_pow2++; |
Brice Goglin | 13348be | 2006-12-11 11:27:19 +0100 | [diff] [blame] | 2427 | mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD; |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 2428 | } else { |
| 2429 | big_pow2 = MYRI10GE_ALLOC_SIZE; |
| 2430 | mgp->big_bytes = big_pow2; |
| 2431 | } |
| 2432 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2433 | /* setup the per-slice data structures */ |
| 2434 | for (slice = 0; slice < mgp->num_slices; slice++) { |
| 2435 | ss = &mgp->ss[slice]; |
| 2436 | |
| 2437 | status = myri10ge_get_txrx(mgp, slice); |
| 2438 | if (status != 0) { |
| 2439 | printk(KERN_ERR |
| 2440 | "myri10ge: %s: failed to get ring sizes or locations\n", |
| 2441 | dev->name); |
| 2442 | goto abort_with_rings; |
| 2443 | } |
| 2444 | status = myri10ge_allocate_rings(ss); |
| 2445 | if (status != 0) |
| 2446 | goto abort_with_rings; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2447 | |
| 2448 | /* only firmware which supports multiple TX queues |
| 2449 | * supports setting up the tx stats on non-zero |
| 2450 | * slices */ |
| 2451 | if (slice == 0 || mgp->dev->real_num_tx_queues > 1) |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2452 | status = myri10ge_set_stats(mgp, slice); |
| 2453 | if (status) { |
| 2454 | printk(KERN_ERR |
| 2455 | "myri10ge: %s: Couldn't set stats DMA\n", |
| 2456 | dev->name); |
| 2457 | goto abort_with_rings; |
| 2458 | } |
| 2459 | |
| 2460 | lro_mgr = &ss->rx_done.lro_mgr; |
| 2461 | lro_mgr->dev = dev; |
| 2462 | lro_mgr->features = LRO_F_NAPI; |
| 2463 | lro_mgr->ip_summed = CHECKSUM_COMPLETE; |
| 2464 | lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY; |
| 2465 | lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS; |
| 2466 | lro_mgr->lro_arr = ss->rx_done.lro_desc; |
| 2467 | lro_mgr->get_frag_header = myri10ge_get_frag_header; |
| 2468 | lro_mgr->max_aggr = myri10ge_lro_max_pkts; |
Stanislaw Gruszka | 636d2f6 | 2009-04-15 02:26:49 -0700 | [diff] [blame] | 2469 | lro_mgr->frag_align_pad = 2; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2470 | if (lro_mgr->max_aggr > MAX_SKB_FRAGS) |
| 2471 | lro_mgr->max_aggr = MAX_SKB_FRAGS; |
| 2472 | |
| 2473 | /* must happen prior to any irq */ |
| 2474 | napi_enable(&(ss)->napi); |
| 2475 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2476 | |
| 2477 | /* now give firmware buffers sizes, and MTU */ |
| 2478 | cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN; |
| 2479 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0); |
| 2480 | cmd.data0 = mgp->small_bytes; |
| 2481 | status |= |
| 2482 | myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0); |
| 2483 | cmd.data0 = big_pow2; |
| 2484 | status |= |
| 2485 | myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0); |
| 2486 | if (status) { |
| 2487 | printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n", |
| 2488 | dev->name); |
| 2489 | goto abort_with_rings; |
| 2490 | } |
| 2491 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2492 | /* |
| 2493 | * Set Linux style TSO mode; this is needed only on newer |
| 2494 | * firmware versions. Older versions default to Linux |
| 2495 | * style TSO |
| 2496 | */ |
| 2497 | cmd.data0 = 0; |
| 2498 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0); |
| 2499 | if (status && status != -ENOSYS) { |
| 2500 | printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n", |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2501 | dev->name); |
| 2502 | goto abort_with_rings; |
| 2503 | } |
| 2504 | |
Al Viro | 66341ff | 2007-12-22 18:56:43 +0000 | [diff] [blame] | 2505 | mgp->link_state = ~0U; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2506 | mgp->rdma_tags_available = 15; |
| 2507 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2508 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0); |
| 2509 | if (status) { |
| 2510 | printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n", |
| 2511 | dev->name); |
| 2512 | goto abort_with_rings; |
| 2513 | } |
| 2514 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2515 | mgp->running = MYRI10GE_ETH_RUNNING; |
| 2516 | mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ; |
| 2517 | add_timer(&mgp->watchdog_timer); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2518 | netif_tx_wake_all_queues(dev); |
| 2519 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2520 | return 0; |
| 2521 | |
| 2522 | abort_with_rings: |
Brice Goglin | 051d36f | 2008-10-20 13:54:12 +0200 | [diff] [blame] | 2523 | while (slice) { |
| 2524 | slice--; |
| 2525 | napi_disable(&mgp->ss[slice].napi); |
| 2526 | } |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2527 | for (i = 0; i < mgp->num_slices; i++) |
| 2528 | myri10ge_free_rings(&mgp->ss[i]); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2529 | |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2530 | myri10ge_free_irq(mgp); |
| 2531 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2532 | abort_with_nothing: |
| 2533 | mgp->running = MYRI10GE_ETH_STOPPED; |
| 2534 | return -ENOMEM; |
| 2535 | } |
| 2536 | |
| 2537 | static int myri10ge_close(struct net_device *dev) |
| 2538 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2539 | struct myri10ge_priv *mgp = netdev_priv(dev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2540 | struct myri10ge_cmd cmd; |
| 2541 | int status, old_down_cnt; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2542 | int i; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2543 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2544 | if (mgp->running != MYRI10GE_ETH_RUNNING) |
| 2545 | return 0; |
| 2546 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2547 | if (mgp->ss[0].tx.req_bytes == NULL) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2548 | return 0; |
| 2549 | |
| 2550 | del_timer_sync(&mgp->watchdog_timer); |
| 2551 | mgp->running = MYRI10GE_ETH_STOPPING; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2552 | for (i = 0; i < mgp->num_slices; i++) { |
| 2553 | napi_disable(&mgp->ss[i].napi); |
| 2554 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2555 | netif_carrier_off(dev); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2556 | |
| 2557 | netif_tx_stop_all_queues(dev); |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 2558 | if (mgp->rebooted == 0) { |
| 2559 | old_down_cnt = mgp->down_cnt; |
| 2560 | mb(); |
| 2561 | status = |
| 2562 | myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0); |
| 2563 | if (status) |
| 2564 | printk(KERN_ERR |
| 2565 | "myri10ge: %s: Couldn't bring down link\n", |
| 2566 | dev->name); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2567 | |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 2568 | wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, |
| 2569 | HZ); |
| 2570 | if (old_down_cnt == mgp->down_cnt) |
| 2571 | printk(KERN_ERR "myri10ge: %s never got down irq\n", |
| 2572 | dev->name); |
| 2573 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2574 | netif_tx_disable(dev); |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 2575 | myri10ge_free_irq(mgp); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2576 | for (i = 0; i < mgp->num_slices; i++) |
| 2577 | myri10ge_free_rings(&mgp->ss[i]); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2578 | |
| 2579 | mgp->running = MYRI10GE_ETH_STOPPED; |
| 2580 | return 0; |
| 2581 | } |
| 2582 | |
| 2583 | /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy |
| 2584 | * backwards one at a time and handle ring wraps */ |
| 2585 | |
| 2586 | static inline void |
| 2587 | myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx, |
| 2588 | struct mcp_kreq_ether_send *src, int cnt) |
| 2589 | { |
| 2590 | int idx, starting_slot; |
| 2591 | starting_slot = tx->req; |
| 2592 | while (cnt > 1) { |
| 2593 | cnt--; |
| 2594 | idx = (starting_slot + cnt) & tx->mask; |
| 2595 | myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src)); |
| 2596 | mb(); |
| 2597 | } |
| 2598 | } |
| 2599 | |
| 2600 | /* |
| 2601 | * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy |
| 2602 | * at most 32 bytes at a time, so as to avoid involving the software |
| 2603 | * pio handler in the nic. We re-write the first segment's flags |
| 2604 | * to mark them valid only after writing the entire chain. |
| 2605 | */ |
| 2606 | |
| 2607 | static inline void |
| 2608 | myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src, |
| 2609 | int cnt) |
| 2610 | { |
| 2611 | int idx, i; |
| 2612 | struct mcp_kreq_ether_send __iomem *dstp, *dst; |
| 2613 | struct mcp_kreq_ether_send *srcp; |
| 2614 | u8 last_flags; |
| 2615 | |
| 2616 | idx = tx->req & tx->mask; |
| 2617 | |
| 2618 | last_flags = src->flags; |
| 2619 | src->flags = 0; |
| 2620 | mb(); |
| 2621 | dst = dstp = &tx->lanai[idx]; |
| 2622 | srcp = src; |
| 2623 | |
| 2624 | if ((idx + cnt) < tx->mask) { |
| 2625 | for (i = 0; i < (cnt - 1); i += 2) { |
| 2626 | myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src)); |
| 2627 | mb(); /* force write every 32 bytes */ |
| 2628 | srcp += 2; |
| 2629 | dstp += 2; |
| 2630 | } |
| 2631 | } else { |
| 2632 | /* submit all but the first request, and ensure |
| 2633 | * that it is submitted below */ |
| 2634 | myri10ge_submit_req_backwards(tx, src, cnt); |
| 2635 | i = 0; |
| 2636 | } |
| 2637 | if (i < cnt) { |
| 2638 | /* submit the first request */ |
| 2639 | myri10ge_pio_copy(dstp, srcp, sizeof(*src)); |
| 2640 | mb(); /* barrier before setting valid flag */ |
| 2641 | } |
| 2642 | |
| 2643 | /* re-write the last 32-bits with the valid flags */ |
| 2644 | src->flags = last_flags; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 2645 | put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2646 | tx->req += cnt; |
| 2647 | mb(); |
| 2648 | } |
| 2649 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2650 | /* |
| 2651 | * Transmit a packet. We need to split the packet so that a single |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2652 | * segment does not cross myri10ge->tx_boundary, so this makes segment |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2653 | * counting tricky. So rather than try to count segments up front, we |
| 2654 | * just give up if there are too few segments to hold a reasonably |
| 2655 | * fragmented packet currently available. If we run |
| 2656 | * out of segments while preparing a packet for DMA, we just linearize |
| 2657 | * it and try again. |
| 2658 | */ |
| 2659 | |
Stephen Hemminger | 61357325 | 2009-08-31 19:50:58 +0000 | [diff] [blame^] | 2660 | static netdev_tx_t myri10ge_xmit(struct sk_buff *skb, |
| 2661 | struct net_device *dev) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2662 | { |
| 2663 | struct myri10ge_priv *mgp = netdev_priv(dev); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2664 | struct myri10ge_slice_state *ss; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2665 | struct mcp_kreq_ether_send *req; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2666 | struct myri10ge_tx_buf *tx; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2667 | struct skb_frag_struct *frag; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2668 | struct netdev_queue *netdev_queue; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2669 | dma_addr_t bus; |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 2670 | u32 low; |
| 2671 | __be32 high_swapped; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2672 | unsigned int len; |
| 2673 | int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2674 | u16 pseudo_hdr_offset, cksum_offset, queue; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2675 | int cum_len, seglen, boundary, rdma_count; |
| 2676 | u8 flags, odd_flag; |
| 2677 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2678 | queue = skb_get_queue_mapping(skb); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2679 | ss = &mgp->ss[queue]; |
| 2680 | netdev_queue = netdev_get_tx_queue(mgp->dev, queue); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2681 | tx = &ss->tx; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2682 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2683 | again: |
| 2684 | req = tx->req_list; |
| 2685 | avail = tx->mask - 1 - (tx->req - tx->done); |
| 2686 | |
| 2687 | mss = 0; |
| 2688 | max_segments = MXGEFW_MAX_SEND_DESC; |
| 2689 | |
Brice Goglin | 917690c | 2007-03-27 21:54:53 +0200 | [diff] [blame] | 2690 | if (skb_is_gso(skb)) { |
Herbert Xu | 7967168 | 2006-06-22 02:40:14 -0700 | [diff] [blame] | 2691 | mss = skb_shinfo(skb)->gso_size; |
Brice Goglin | 917690c | 2007-03-27 21:54:53 +0200 | [diff] [blame] | 2692 | max_segments = MYRI10GE_MAX_SEND_DESC_TSO; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2693 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2694 | |
| 2695 | if ((unlikely(avail < max_segments))) { |
| 2696 | /* we are out of transmit resources */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2697 | tx->stop_queue++; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2698 | netif_tx_stop_queue(netdev_queue); |
Patrick McHardy | 5b54814 | 2009-06-12 06:22:29 +0000 | [diff] [blame] | 2699 | return NETDEV_TX_BUSY; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2700 | } |
| 2701 | |
| 2702 | /* Setup checksum offloading, if needed */ |
| 2703 | cksum_offset = 0; |
| 2704 | pseudo_hdr_offset = 0; |
| 2705 | odd_flag = 0; |
| 2706 | flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST); |
Patrick McHardy | 84fa793 | 2006-08-29 16:44:56 -0700 | [diff] [blame] | 2707 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
Arnaldo Carvalho de Melo | ea2ae17 | 2007-04-25 17:55:53 -0700 | [diff] [blame] | 2708 | cksum_offset = skb_transport_offset(skb); |
Al Viro | ff1dcad | 2006-11-20 18:07:29 -0800 | [diff] [blame] | 2709 | pseudo_hdr_offset = cksum_offset + skb->csum_offset; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2710 | /* If the headers are excessively large, then we must |
| 2711 | * fall back to a software checksum */ |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2712 | if (unlikely(!mss && (cksum_offset > 255 || |
| 2713 | pseudo_hdr_offset > 127))) { |
Patrick McHardy | 84fa793 | 2006-08-29 16:44:56 -0700 | [diff] [blame] | 2714 | if (skb_checksum_help(skb)) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2715 | goto drop; |
| 2716 | cksum_offset = 0; |
| 2717 | pseudo_hdr_offset = 0; |
| 2718 | } else { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2719 | odd_flag = MXGEFW_FLAGS_ALIGN_ODD; |
| 2720 | flags |= MXGEFW_FLAGS_CKSUM; |
| 2721 | } |
| 2722 | } |
| 2723 | |
| 2724 | cum_len = 0; |
| 2725 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2726 | if (mss) { /* TSO */ |
| 2727 | /* this removes any CKSUM flag from before */ |
| 2728 | flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST); |
| 2729 | |
| 2730 | /* negative cum_len signifies to the |
| 2731 | * send loop that we are still in the |
| 2732 | * header portion of the TSO packet. |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2733 | * TSO header can be at most 1KB long */ |
Arnaldo Carvalho de Melo | ab6a5bb | 2007-03-18 17:43:48 -0700 | [diff] [blame] | 2734 | cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2735 | |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2736 | /* for IPv6 TSO, the checksum offset stores the |
| 2737 | * TCP header length, to save the firmware from |
| 2738 | * the need to parse the headers */ |
| 2739 | if (skb_is_gso_v6(skb)) { |
| 2740 | cksum_offset = tcp_hdrlen(skb); |
| 2741 | /* Can only handle headers <= max_tso6 long */ |
| 2742 | if (unlikely(-cum_len > mgp->max_tso6)) |
| 2743 | return myri10ge_sw_tso(skb, dev); |
| 2744 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2745 | /* for TSO, pseudo_hdr_offset holds mss. |
| 2746 | * The firmware figures out where to put |
| 2747 | * the checksum by parsing the header. */ |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 2748 | pseudo_hdr_offset = mss; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2749 | } else |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2750 | /* Mark small packets, and pad out tiny packets */ |
| 2751 | if (skb->len <= MXGEFW_SEND_SMALL_SIZE) { |
| 2752 | flags |= MXGEFW_FLAGS_SMALL; |
| 2753 | |
| 2754 | /* pad frames to at least ETH_ZLEN bytes */ |
| 2755 | if (unlikely(skb->len < ETH_ZLEN)) { |
Herbert Xu | 5b057c6 | 2006-06-23 02:06:41 -0700 | [diff] [blame] | 2756 | if (skb_padto(skb, ETH_ZLEN)) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2757 | /* The packet is gone, so we must |
| 2758 | * return 0 */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2759 | ss->stats.tx_dropped += 1; |
Patrick McHardy | 6ed1065 | 2009-06-23 06:03:08 +0000 | [diff] [blame] | 2760 | return NETDEV_TX_OK; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2761 | } |
| 2762 | /* adjust the len to account for the zero pad |
| 2763 | * so that the nic can know how long it is */ |
| 2764 | skb->len = ETH_ZLEN; |
| 2765 | } |
| 2766 | } |
| 2767 | |
| 2768 | /* map the skb for DMA */ |
| 2769 | len = skb->len - skb->data_len; |
| 2770 | idx = tx->req & tx->mask; |
| 2771 | tx->info[idx].skb = skb; |
| 2772 | bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE); |
| 2773 | pci_unmap_addr_set(&tx->info[idx], bus, bus); |
| 2774 | pci_unmap_len_set(&tx->info[idx], len, len); |
| 2775 | |
| 2776 | frag_cnt = skb_shinfo(skb)->nr_frags; |
| 2777 | frag_idx = 0; |
| 2778 | count = 0; |
| 2779 | rdma_count = 0; |
| 2780 | |
| 2781 | /* "rdma_count" is the number of RDMAs belonging to the |
| 2782 | * current packet BEFORE the current send request. For |
| 2783 | * non-TSO packets, this is equal to "count". |
| 2784 | * For TSO packets, rdma_count needs to be reset |
| 2785 | * to 0 after a segment cut. |
| 2786 | * |
| 2787 | * The rdma_count field of the send request is |
| 2788 | * the number of RDMAs of the packet starting at |
| 2789 | * that request. For TSO send requests with one ore more cuts |
| 2790 | * in the middle, this is the number of RDMAs starting |
| 2791 | * after the last cut in the request. All previous |
| 2792 | * segments before the last cut implicitly have 1 RDMA. |
| 2793 | * |
| 2794 | * Since the number of RDMAs is not known beforehand, |
| 2795 | * it must be filled-in retroactively - after each |
| 2796 | * segmentation cut or at the end of the entire packet. |
| 2797 | */ |
| 2798 | |
| 2799 | while (1) { |
| 2800 | /* Break the SKB or Fragment up into pieces which |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2801 | * do not cross mgp->tx_boundary */ |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2802 | low = MYRI10GE_LOWPART_TO_U32(bus); |
| 2803 | high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus)); |
| 2804 | while (len) { |
| 2805 | u8 flags_next; |
| 2806 | int cum_len_next; |
| 2807 | |
| 2808 | if (unlikely(count == max_segments)) |
| 2809 | goto abort_linearize; |
| 2810 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2811 | boundary = |
| 2812 | (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2813 | seglen = boundary - low; |
| 2814 | if (seglen > len) |
| 2815 | seglen = len; |
| 2816 | flags_next = flags & ~MXGEFW_FLAGS_FIRST; |
| 2817 | cum_len_next = cum_len + seglen; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2818 | if (mss) { /* TSO */ |
| 2819 | (req - rdma_count)->rdma_count = rdma_count + 1; |
| 2820 | |
| 2821 | if (likely(cum_len >= 0)) { /* payload */ |
| 2822 | int next_is_first, chop; |
| 2823 | |
| 2824 | chop = (cum_len_next > mss); |
| 2825 | cum_len_next = cum_len_next % mss; |
| 2826 | next_is_first = (cum_len_next == 0); |
| 2827 | flags |= chop * MXGEFW_FLAGS_TSO_CHOP; |
| 2828 | flags_next |= next_is_first * |
| 2829 | MXGEFW_FLAGS_FIRST; |
| 2830 | rdma_count |= -(chop | next_is_first); |
| 2831 | rdma_count += chop & !next_is_first; |
| 2832 | } else if (likely(cum_len_next >= 0)) { /* header ends */ |
| 2833 | int small; |
| 2834 | |
| 2835 | rdma_count = -1; |
| 2836 | cum_len_next = 0; |
| 2837 | seglen = -cum_len; |
| 2838 | small = (mss <= MXGEFW_SEND_SMALL_SIZE); |
| 2839 | flags_next = MXGEFW_FLAGS_TSO_PLD | |
| 2840 | MXGEFW_FLAGS_FIRST | |
| 2841 | (small * MXGEFW_FLAGS_SMALL); |
| 2842 | } |
| 2843 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2844 | req->addr_high = high_swapped; |
| 2845 | req->addr_low = htonl(low); |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 2846 | req->pseudo_hdr_offset = htons(pseudo_hdr_offset); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2847 | req->pad = 0; /* complete solid 16-byte block; does this matter? */ |
| 2848 | req->rdma_count = 1; |
| 2849 | req->length = htons(seglen); |
| 2850 | req->cksum_offset = cksum_offset; |
| 2851 | req->flags = flags | ((cum_len & 1) * odd_flag); |
| 2852 | |
| 2853 | low += seglen; |
| 2854 | len -= seglen; |
| 2855 | cum_len = cum_len_next; |
| 2856 | flags = flags_next; |
| 2857 | req++; |
| 2858 | count++; |
| 2859 | rdma_count++; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2860 | if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) { |
| 2861 | if (unlikely(cksum_offset > seglen)) |
| 2862 | cksum_offset -= seglen; |
| 2863 | else |
| 2864 | cksum_offset = 0; |
| 2865 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2866 | } |
| 2867 | if (frag_idx == frag_cnt) |
| 2868 | break; |
| 2869 | |
| 2870 | /* map next fragment for DMA */ |
| 2871 | idx = (count + tx->req) & tx->mask; |
| 2872 | frag = &skb_shinfo(skb)->frags[frag_idx]; |
| 2873 | frag_idx++; |
| 2874 | len = frag->size; |
| 2875 | bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset, |
| 2876 | len, PCI_DMA_TODEVICE); |
| 2877 | pci_unmap_addr_set(&tx->info[idx], bus, bus); |
| 2878 | pci_unmap_len_set(&tx->info[idx], len, len); |
| 2879 | } |
| 2880 | |
| 2881 | (req - rdma_count)->rdma_count = rdma_count; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2882 | if (mss) |
| 2883 | do { |
| 2884 | req--; |
| 2885 | req->flags |= MXGEFW_FLAGS_TSO_LAST; |
| 2886 | } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP | |
| 2887 | MXGEFW_FLAGS_FIRST))); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2888 | idx = ((count - 1) + tx->req) & tx->mask; |
| 2889 | tx->info[idx].last = 1; |
Brice Goglin | e454e7e | 2008-07-21 10:25:50 +0200 | [diff] [blame] | 2890 | myri10ge_submit_req(tx, tx->req_list, count); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2891 | /* if using multiple tx queues, make sure NIC polls the |
| 2892 | * current slice */ |
| 2893 | if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) { |
| 2894 | tx->queue_active = 1; |
| 2895 | put_be32(htonl(1), tx->send_go); |
Brice Goglin | 8c2f5fa | 2008-11-10 13:58:41 +0100 | [diff] [blame] | 2896 | mb(); |
Brice Goglin | 6824a10 | 2008-10-30 08:59:33 +0100 | [diff] [blame] | 2897 | mmiowb(); |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2898 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2899 | tx->pkt_start++; |
| 2900 | if ((avail - count) < MXGEFW_MAX_SEND_DESC) { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2901 | tx->stop_queue++; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 2902 | netif_tx_stop_queue(netdev_queue); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2903 | } |
Patrick McHardy | 6ed1065 | 2009-06-23 06:03:08 +0000 | [diff] [blame] | 2904 | return NETDEV_TX_OK; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2905 | |
| 2906 | abort_linearize: |
| 2907 | /* Free any DMA resources we've alloced and clear out the skb |
| 2908 | * slot so as to not trip up assertions, and to avoid a |
| 2909 | * double-free if linearizing fails */ |
| 2910 | |
| 2911 | last_idx = (idx + 1) & tx->mask; |
| 2912 | idx = tx->req & tx->mask; |
| 2913 | tx->info[idx].skb = NULL; |
| 2914 | do { |
| 2915 | len = pci_unmap_len(&tx->info[idx], len); |
| 2916 | if (len) { |
| 2917 | if (tx->info[idx].skb != NULL) |
| 2918 | pci_unmap_single(mgp->pdev, |
| 2919 | pci_unmap_addr(&tx->info[idx], |
| 2920 | bus), len, |
| 2921 | PCI_DMA_TODEVICE); |
| 2922 | else |
| 2923 | pci_unmap_page(mgp->pdev, |
| 2924 | pci_unmap_addr(&tx->info[idx], |
| 2925 | bus), len, |
| 2926 | PCI_DMA_TODEVICE); |
| 2927 | pci_unmap_len_set(&tx->info[idx], len, 0); |
| 2928 | tx->info[idx].skb = NULL; |
| 2929 | } |
| 2930 | idx = (idx + 1) & tx->mask; |
| 2931 | } while (idx != last_idx); |
Herbert Xu | 89114af | 2006-07-08 13:34:32 -0700 | [diff] [blame] | 2932 | if (skb_is_gso(skb)) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2933 | printk(KERN_ERR |
| 2934 | "myri10ge: %s: TSO but wanted to linearize?!?!?\n", |
| 2935 | mgp->dev->name); |
| 2936 | goto drop; |
| 2937 | } |
| 2938 | |
Andrew Morton | bec0e85 | 2006-06-22 14:47:19 -0700 | [diff] [blame] | 2939 | if (skb_linearize(skb)) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2940 | goto drop; |
| 2941 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2942 | tx->linearized++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2943 | goto again; |
| 2944 | |
| 2945 | drop: |
| 2946 | dev_kfree_skb_any(skb); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2947 | ss->stats.tx_dropped += 1; |
Patrick McHardy | 6ed1065 | 2009-06-23 06:03:08 +0000 | [diff] [blame] | 2948 | return NETDEV_TX_OK; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2949 | |
| 2950 | } |
| 2951 | |
Stephen Hemminger | 61357325 | 2009-08-31 19:50:58 +0000 | [diff] [blame^] | 2952 | static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb, |
| 2953 | struct net_device *dev) |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2954 | { |
| 2955 | struct sk_buff *segs, *curr; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 2956 | struct myri10ge_priv *mgp = netdev_priv(dev); |
Brice Goglin | d6279c8 | 2008-11-20 01:50:04 -0800 | [diff] [blame] | 2957 | struct myri10ge_slice_state *ss; |
Stephen Hemminger | 61357325 | 2009-08-31 19:50:58 +0000 | [diff] [blame^] | 2958 | netdev_tx_t status; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2959 | |
| 2960 | segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6); |
Hirofumi Nakagawa | 801678c | 2008-04-29 01:03:09 -0700 | [diff] [blame] | 2961 | if (IS_ERR(segs)) |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2962 | goto drop; |
| 2963 | |
| 2964 | while (segs) { |
| 2965 | curr = segs; |
| 2966 | segs = segs->next; |
| 2967 | curr->next = NULL; |
| 2968 | status = myri10ge_xmit(curr, dev); |
| 2969 | if (status != 0) { |
| 2970 | dev_kfree_skb_any(curr); |
| 2971 | if (segs != NULL) { |
| 2972 | curr = segs; |
| 2973 | segs = segs->next; |
| 2974 | curr->next = NULL; |
| 2975 | dev_kfree_skb_any(segs); |
| 2976 | } |
| 2977 | goto drop; |
| 2978 | } |
| 2979 | } |
| 2980 | dev_kfree_skb_any(skb); |
Patrick McHardy | ec634fe | 2009-07-05 19:23:38 -0700 | [diff] [blame] | 2981 | return NETDEV_TX_OK; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2982 | |
| 2983 | drop: |
Brice Goglin | d6279c8 | 2008-11-20 01:50:04 -0800 | [diff] [blame] | 2984 | ss = &mgp->ss[skb_get_queue_mapping(skb)]; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2985 | dev_kfree_skb_any(skb); |
Brice Goglin | d6279c8 | 2008-11-20 01:50:04 -0800 | [diff] [blame] | 2986 | ss->stats.tx_dropped += 1; |
Patrick McHardy | ec634fe | 2009-07-05 19:23:38 -0700 | [diff] [blame] | 2987 | return NETDEV_TX_OK; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 2988 | } |
| 2989 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 2990 | static struct net_device_stats *myri10ge_get_stats(struct net_device *dev) |
| 2991 | { |
| 2992 | struct myri10ge_priv *mgp = netdev_priv(dev); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2993 | struct myri10ge_slice_netstats *slice_stats; |
| 2994 | struct net_device_stats *stats = &mgp->stats; |
| 2995 | int i; |
| 2996 | |
Brice Goglin | 5908182 | 2009-04-16 02:23:56 +0000 | [diff] [blame] | 2997 | spin_lock(&mgp->stats_lock); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 2998 | memset(stats, 0, sizeof(*stats)); |
| 2999 | for (i = 0; i < mgp->num_slices; i++) { |
| 3000 | slice_stats = &mgp->ss[i].stats; |
| 3001 | stats->rx_packets += slice_stats->rx_packets; |
| 3002 | stats->tx_packets += slice_stats->tx_packets; |
| 3003 | stats->rx_bytes += slice_stats->rx_bytes; |
| 3004 | stats->tx_bytes += slice_stats->tx_bytes; |
| 3005 | stats->rx_dropped += slice_stats->rx_dropped; |
| 3006 | stats->tx_dropped += slice_stats->tx_dropped; |
| 3007 | } |
Brice Goglin | 5908182 | 2009-04-16 02:23:56 +0000 | [diff] [blame] | 3008 | spin_unlock(&mgp->stats_lock); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3009 | return stats; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3010 | } |
| 3011 | |
| 3012 | static void myri10ge_set_multicast_list(struct net_device *dev) |
| 3013 | { |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3014 | struct myri10ge_priv *mgp = netdev_priv(dev); |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3015 | struct myri10ge_cmd cmd; |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3016 | struct dev_mc_list *mc_list; |
Brice Goglin | 6250223 | 2006-12-11 11:24:37 +0100 | [diff] [blame] | 3017 | __be32 data[2] = { 0, 0 }; |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3018 | int err; |
| 3019 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3020 | /* can be called from atomic contexts, |
| 3021 | * pass 1 to force atomicity in myri10ge_send_cmd() */ |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3022 | myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1); |
| 3023 | |
| 3024 | /* This firmware is known to not support multicast */ |
Brice Goglin | 2f76216 | 2007-05-07 23:50:37 +0200 | [diff] [blame] | 3025 | if (!mgp->fw_multicast_support) |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3026 | return; |
| 3027 | |
| 3028 | /* Disable multicast filtering */ |
| 3029 | |
| 3030 | err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1); |
| 3031 | if (err != 0) { |
| 3032 | printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI," |
| 3033 | " error status: %d\n", dev->name, err); |
| 3034 | goto abort; |
| 3035 | } |
| 3036 | |
Brice Goglin | 2f76216 | 2007-05-07 23:50:37 +0200 | [diff] [blame] | 3037 | if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) { |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3038 | /* request to disable multicast filtering, so quit here */ |
| 3039 | return; |
| 3040 | } |
| 3041 | |
| 3042 | /* Flush the filters */ |
| 3043 | |
| 3044 | err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, |
| 3045 | &cmd, 1); |
| 3046 | if (err != 0) { |
| 3047 | printk(KERN_ERR |
| 3048 | "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS" |
| 3049 | ", error status: %d\n", dev->name, err); |
| 3050 | goto abort; |
| 3051 | } |
| 3052 | |
| 3053 | /* Walk the multicast list, and add each address */ |
| 3054 | for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) { |
Al Viro | 40f6cff | 2006-11-20 13:48:32 -0500 | [diff] [blame] | 3055 | memcpy(data, &mc_list->dmi_addr, 6); |
| 3056 | cmd.data0 = ntohl(data[0]); |
| 3057 | cmd.data1 = ntohl(data[1]); |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3058 | err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP, |
| 3059 | &cmd, 1); |
| 3060 | |
| 3061 | if (err != 0) { |
| 3062 | printk(KERN_ERR "myri10ge: %s: Failed " |
| 3063 | "MXGEFW_JOIN_MULTICAST_GROUP, error status:" |
| 3064 | "%d\t", dev->name, err); |
Johannes Berg | e174961 | 2008-10-27 15:59:26 -0700 | [diff] [blame] | 3065 | printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr); |
Brice Goglin | 85a7ea1 | 2006-08-21 17:36:56 -0400 | [diff] [blame] | 3066 | goto abort; |
| 3067 | } |
| 3068 | } |
| 3069 | /* Enable multicast filtering */ |
| 3070 | err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1); |
| 3071 | if (err != 0) { |
| 3072 | printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI," |
| 3073 | "error status: %d\n", dev->name, err); |
| 3074 | goto abort; |
| 3075 | } |
| 3076 | |
| 3077 | return; |
| 3078 | |
| 3079 | abort: |
| 3080 | return; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3081 | } |
| 3082 | |
| 3083 | static int myri10ge_set_mac_address(struct net_device *dev, void *addr) |
| 3084 | { |
| 3085 | struct sockaddr *sa = addr; |
| 3086 | struct myri10ge_priv *mgp = netdev_priv(dev); |
| 3087 | int status; |
| 3088 | |
| 3089 | if (!is_valid_ether_addr(sa->sa_data)) |
| 3090 | return -EADDRNOTAVAIL; |
| 3091 | |
| 3092 | status = myri10ge_update_mac_address(mgp, sa->sa_data); |
| 3093 | if (status != 0) { |
| 3094 | printk(KERN_ERR |
| 3095 | "myri10ge: %s: changing mac address failed with %d\n", |
| 3096 | dev->name, status); |
| 3097 | return status; |
| 3098 | } |
| 3099 | |
| 3100 | /* change the dev structure */ |
| 3101 | memcpy(dev->dev_addr, sa->sa_data, 6); |
| 3102 | return 0; |
| 3103 | } |
| 3104 | |
| 3105 | static int myri10ge_change_mtu(struct net_device *dev, int new_mtu) |
| 3106 | { |
| 3107 | struct myri10ge_priv *mgp = netdev_priv(dev); |
| 3108 | int error = 0; |
| 3109 | |
| 3110 | if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) { |
| 3111 | printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n", |
| 3112 | dev->name, new_mtu); |
| 3113 | return -EINVAL; |
| 3114 | } |
| 3115 | printk(KERN_INFO "%s: changing mtu from %d to %d\n", |
| 3116 | dev->name, dev->mtu, new_mtu); |
| 3117 | if (mgp->running) { |
| 3118 | /* if we change the mtu on an active device, we must |
| 3119 | * reset the device so the firmware sees the change */ |
| 3120 | myri10ge_close(dev); |
| 3121 | dev->mtu = new_mtu; |
| 3122 | myri10ge_open(dev); |
| 3123 | } else |
| 3124 | dev->mtu = new_mtu; |
| 3125 | |
| 3126 | return error; |
| 3127 | } |
| 3128 | |
| 3129 | /* |
| 3130 | * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary. |
| 3131 | * Only do it if the bridge is a root port since we don't want to disturb |
| 3132 | * any other device, except if forced with myri10ge_ecrc_enable > 1. |
| 3133 | */ |
| 3134 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3135 | static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp) |
| 3136 | { |
| 3137 | struct pci_dev *bridge = mgp->pdev->bus->self; |
| 3138 | struct device *dev = &mgp->pdev->dev; |
| 3139 | unsigned cap; |
| 3140 | unsigned err_cap; |
| 3141 | u16 val; |
| 3142 | u8 ext_type; |
| 3143 | int ret; |
| 3144 | |
| 3145 | if (!myri10ge_ecrc_enable || !bridge) |
| 3146 | return; |
| 3147 | |
| 3148 | /* check that the bridge is a root port */ |
| 3149 | cap = pci_find_capability(bridge, PCI_CAP_ID_EXP); |
| 3150 | pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val); |
| 3151 | ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4; |
| 3152 | if (ext_type != PCI_EXP_TYPE_ROOT_PORT) { |
| 3153 | if (myri10ge_ecrc_enable > 1) { |
Brice Goglin | eca3fd8 | 2008-05-09 02:19:29 +0200 | [diff] [blame] | 3154 | struct pci_dev *prev_bridge, *old_bridge = bridge; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3155 | |
| 3156 | /* Walk the hierarchy up to the root port |
| 3157 | * where ECRC has to be enabled */ |
| 3158 | do { |
Brice Goglin | eca3fd8 | 2008-05-09 02:19:29 +0200 | [diff] [blame] | 3159 | prev_bridge = bridge; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3160 | bridge = bridge->bus->self; |
Brice Goglin | eca3fd8 | 2008-05-09 02:19:29 +0200 | [diff] [blame] | 3161 | if (!bridge || prev_bridge == bridge) { |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3162 | dev_err(dev, |
| 3163 | "Failed to find root port" |
| 3164 | " to force ECRC\n"); |
| 3165 | return; |
| 3166 | } |
| 3167 | cap = |
| 3168 | pci_find_capability(bridge, PCI_CAP_ID_EXP); |
| 3169 | pci_read_config_word(bridge, |
| 3170 | cap + PCI_CAP_FLAGS, &val); |
| 3171 | ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4; |
| 3172 | } while (ext_type != PCI_EXP_TYPE_ROOT_PORT); |
| 3173 | |
| 3174 | dev_info(dev, |
| 3175 | "Forcing ECRC on non-root port %s" |
| 3176 | " (enabling on root port %s)\n", |
| 3177 | pci_name(old_bridge), pci_name(bridge)); |
| 3178 | } else { |
| 3179 | dev_err(dev, |
| 3180 | "Not enabling ECRC on non-root port %s\n", |
| 3181 | pci_name(bridge)); |
| 3182 | return; |
| 3183 | } |
| 3184 | } |
| 3185 | |
| 3186 | cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3187 | if (!cap) |
| 3188 | return; |
| 3189 | |
| 3190 | ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap); |
| 3191 | if (ret) { |
| 3192 | dev_err(dev, "failed reading ext-conf-space of %s\n", |
| 3193 | pci_name(bridge)); |
| 3194 | dev_err(dev, "\t pci=nommconf in use? " |
| 3195 | "or buggy/incomplete/absent ACPI MCFG attr?\n"); |
| 3196 | return; |
| 3197 | } |
| 3198 | if (!(err_cap & PCI_ERR_CAP_ECRC_GENC)) |
| 3199 | return; |
| 3200 | |
| 3201 | err_cap |= PCI_ERR_CAP_ECRC_GENE; |
| 3202 | pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap); |
| 3203 | dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3204 | } |
| 3205 | |
| 3206 | /* |
| 3207 | * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput |
| 3208 | * when the PCI-E Completion packets are aligned on an 8-byte |
| 3209 | * boundary. Some PCI-E chip sets always align Completion packets; on |
| 3210 | * the ones that do not, the alignment can be enforced by enabling |
| 3211 | * ECRC generation (if supported). |
| 3212 | * |
| 3213 | * When PCI-E Completion packets are not aligned, it is actually more |
| 3214 | * efficient to limit Read-DMA transactions to 2KB, rather than 4KB. |
| 3215 | * |
| 3216 | * If the driver can neither enable ECRC nor verify that it has |
| 3217 | * already been enabled, then it must use a firmware image which works |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3218 | * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3219 | * should also ensure that it never gives the device a Read-DMA which is |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3220 | * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3221 | * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat) |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3222 | * firmware image, and set tx_boundary to 4KB. |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3223 | */ |
| 3224 | |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3225 | static void myri10ge_firmware_probe(struct myri10ge_priv *mgp) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3226 | { |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3227 | struct pci_dev *pdev = mgp->pdev; |
| 3228 | struct device *dev = &pdev->dev; |
Brice Goglin | 302d242 | 2007-08-24 08:57:17 +0200 | [diff] [blame] | 3229 | int status; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3230 | |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3231 | mgp->tx_boundary = 4096; |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3232 | /* |
| 3233 | * Verify the max read request size was set to 4KB |
| 3234 | * before trying the test with 4KB. |
| 3235 | */ |
Brice Goglin | 302d242 | 2007-08-24 08:57:17 +0200 | [diff] [blame] | 3236 | status = pcie_get_readrq(pdev); |
| 3237 | if (status < 0) { |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3238 | dev_err(dev, "Couldn't read max read req size: %d\n", status); |
| 3239 | goto abort; |
| 3240 | } |
Brice Goglin | 302d242 | 2007-08-24 08:57:17 +0200 | [diff] [blame] | 3241 | if (status != 4096) { |
| 3242 | dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3243 | mgp->tx_boundary = 2048; |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3244 | } |
| 3245 | /* |
| 3246 | * load the optimized firmware (which assumes aligned PCIe |
| 3247 | * completions) in order to see if it works on this host. |
| 3248 | */ |
| 3249 | mgp->fw_name = myri10ge_fw_aligned; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3250 | status = myri10ge_load_firmware(mgp, 1); |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3251 | if (status != 0) { |
| 3252 | goto abort; |
| 3253 | } |
| 3254 | |
| 3255 | /* |
| 3256 | * Enable ECRC if possible |
| 3257 | */ |
| 3258 | myri10ge_enable_ecrc(mgp); |
| 3259 | |
| 3260 | /* |
| 3261 | * Run a DMA test which watches for unaligned completions and |
| 3262 | * aborts on the first one seen. |
| 3263 | */ |
| 3264 | |
| 3265 | status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST); |
| 3266 | if (status == 0) |
| 3267 | return; /* keep the aligned firmware */ |
| 3268 | |
| 3269 | if (status != -E2BIG) |
| 3270 | dev_warn(dev, "DMA test failed: %d\n", status); |
| 3271 | if (status == -ENOSYS) |
| 3272 | dev_warn(dev, "Falling back to ethp! " |
| 3273 | "Please install up to date fw\n"); |
| 3274 | abort: |
| 3275 | /* fall back to using the unaligned firmware */ |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3276 | mgp->tx_boundary = 2048; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3277 | mgp->fw_name = myri10ge_fw_unaligned; |
| 3278 | |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3279 | } |
| 3280 | |
| 3281 | static void myri10ge_select_firmware(struct myri10ge_priv *mgp) |
| 3282 | { |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 3283 | int overridden = 0; |
| 3284 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3285 | if (myri10ge_force_firmware == 0) { |
Brice Goglin | ce7f936 | 2006-08-31 01:32:59 -0400 | [diff] [blame] | 3286 | int link_width, exp_cap; |
| 3287 | u16 lnk; |
| 3288 | |
| 3289 | exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP); |
| 3290 | pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); |
| 3291 | link_width = (lnk >> 4) & 0x3f; |
| 3292 | |
Brice Goglin | ce7f936 | 2006-08-31 01:32:59 -0400 | [diff] [blame] | 3293 | /* Check to see if Link is less than 8 or if the |
| 3294 | * upstream bridge is known to provide aligned |
| 3295 | * completions */ |
| 3296 | if (link_width < 8) { |
| 3297 | dev_info(&mgp->pdev->dev, "PCIE x%d Link\n", |
| 3298 | link_width); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3299 | mgp->tx_boundary = 4096; |
Brice Goglin | ce7f936 | 2006-08-31 01:32:59 -0400 | [diff] [blame] | 3300 | mgp->fw_name = myri10ge_fw_aligned; |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3301 | } else { |
| 3302 | myri10ge_firmware_probe(mgp); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3303 | } |
| 3304 | } else { |
| 3305 | if (myri10ge_force_firmware == 1) { |
| 3306 | dev_info(&mgp->pdev->dev, |
| 3307 | "Assuming aligned completions (forced)\n"); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3308 | mgp->tx_boundary = 4096; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3309 | mgp->fw_name = myri10ge_fw_aligned; |
| 3310 | } else { |
| 3311 | dev_info(&mgp->pdev->dev, |
| 3312 | "Assuming unaligned completions (forced)\n"); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3313 | mgp->tx_boundary = 2048; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3314 | mgp->fw_name = myri10ge_fw_unaligned; |
| 3315 | } |
| 3316 | } |
| 3317 | if (myri10ge_fw_name != NULL) { |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 3318 | overridden = 1; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3319 | mgp->fw_name = myri10ge_fw_name; |
| 3320 | } |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 3321 | if (mgp->board_number < MYRI10GE_MAX_BOARDS && |
| 3322 | myri10ge_fw_names[mgp->board_number] != NULL && |
| 3323 | strlen(myri10ge_fw_names[mgp->board_number])) { |
| 3324 | mgp->fw_name = myri10ge_fw_names[mgp->board_number]; |
| 3325 | overridden = 1; |
| 3326 | } |
| 3327 | if (overridden) |
| 3328 | dev_info(&mgp->pdev->dev, "overriding firmware to %s\n", |
| 3329 | mgp->fw_name); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3330 | } |
| 3331 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3332 | #ifdef CONFIG_PM |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3333 | static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state) |
| 3334 | { |
| 3335 | struct myri10ge_priv *mgp; |
| 3336 | struct net_device *netdev; |
| 3337 | |
| 3338 | mgp = pci_get_drvdata(pdev); |
| 3339 | if (mgp == NULL) |
| 3340 | return -EINVAL; |
| 3341 | netdev = mgp->dev; |
| 3342 | |
| 3343 | netif_device_detach(netdev); |
| 3344 | if (netif_running(netdev)) { |
| 3345 | printk(KERN_INFO "myri10ge: closing %s\n", netdev->name); |
| 3346 | rtnl_lock(); |
| 3347 | myri10ge_close(netdev); |
| 3348 | rtnl_unlock(); |
| 3349 | } |
| 3350 | myri10ge_dummy_rdma(mgp, 0); |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3351 | pci_save_state(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3352 | pci_disable_device(pdev); |
Brice Goglin | 1a63e84 | 2006-12-18 11:52:34 +0100 | [diff] [blame] | 3353 | |
| 3354 | return pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3355 | } |
| 3356 | |
| 3357 | static int myri10ge_resume(struct pci_dev *pdev) |
| 3358 | { |
| 3359 | struct myri10ge_priv *mgp; |
| 3360 | struct net_device *netdev; |
| 3361 | int status; |
| 3362 | u16 vendor; |
| 3363 | |
| 3364 | mgp = pci_get_drvdata(pdev); |
| 3365 | if (mgp == NULL) |
| 3366 | return -EINVAL; |
| 3367 | netdev = mgp->dev; |
| 3368 | pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */ |
| 3369 | msleep(5); /* give card time to respond */ |
| 3370 | pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor); |
| 3371 | if (vendor == 0xffff) { |
| 3372 | printk(KERN_ERR "myri10ge: %s: device disappeared!\n", |
| 3373 | mgp->dev->name); |
| 3374 | return -EIO; |
| 3375 | } |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3376 | |
Brice Goglin | 1a63e84 | 2006-12-18 11:52:34 +0100 | [diff] [blame] | 3377 | status = pci_restore_state(pdev); |
| 3378 | if (status) |
| 3379 | return status; |
Brice Goglin | 4c2248c | 2006-07-09 21:10:18 -0400 | [diff] [blame] | 3380 | |
| 3381 | status = pci_enable_device(pdev); |
Brice Goglin | 1a63e84 | 2006-12-18 11:52:34 +0100 | [diff] [blame] | 3382 | if (status) { |
Brice Goglin | 4c2248c | 2006-07-09 21:10:18 -0400 | [diff] [blame] | 3383 | dev_err(&pdev->dev, "failed to enable device\n"); |
Brice Goglin | 1a63e84 | 2006-12-18 11:52:34 +0100 | [diff] [blame] | 3384 | return status; |
Brice Goglin | 4c2248c | 2006-07-09 21:10:18 -0400 | [diff] [blame] | 3385 | } |
| 3386 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3387 | pci_set_master(pdev); |
| 3388 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3389 | myri10ge_reset(mgp); |
Brice Goglin | 013b68b | 2006-08-09 00:07:53 -0400 | [diff] [blame] | 3390 | myri10ge_dummy_rdma(mgp, 1); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3391 | |
| 3392 | /* Save configuration space to be restored if the |
| 3393 | * nic resets due to a parity error */ |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3394 | pci_save_state(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3395 | |
| 3396 | if (netif_running(netdev)) { |
| 3397 | rtnl_lock(); |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 3398 | status = myri10ge_open(netdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3399 | rtnl_unlock(); |
Brice Goglin | df30a74 | 2006-12-18 11:50:40 +0100 | [diff] [blame] | 3400 | if (status != 0) |
| 3401 | goto abort_with_enabled; |
| 3402 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3403 | } |
| 3404 | netif_device_attach(netdev); |
| 3405 | |
| 3406 | return 0; |
| 3407 | |
Brice Goglin | 4c2248c | 2006-07-09 21:10:18 -0400 | [diff] [blame] | 3408 | abort_with_enabled: |
| 3409 | pci_disable_device(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3410 | return -EIO; |
| 3411 | |
| 3412 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3413 | #endif /* CONFIG_PM */ |
| 3414 | |
| 3415 | static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp) |
| 3416 | { |
| 3417 | struct pci_dev *pdev = mgp->pdev; |
| 3418 | int vs = mgp->vendor_specific_offset; |
| 3419 | u32 reboot; |
| 3420 | |
| 3421 | /*enter read32 mode */ |
| 3422 | pci_write_config_byte(pdev, vs + 0x10, 0x3); |
| 3423 | |
| 3424 | /*read REBOOT_STATUS (0xfffffff0) */ |
| 3425 | pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0); |
| 3426 | pci_read_config_dword(pdev, vs + 0x14, &reboot); |
| 3427 | return reboot; |
| 3428 | } |
| 3429 | |
| 3430 | /* |
| 3431 | * This watchdog is used to check whether the board has suffered |
| 3432 | * from a parity error and needs to be recovered. |
| 3433 | */ |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 3434 | static void myri10ge_watchdog(struct work_struct *work) |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3435 | { |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 3436 | struct myri10ge_priv *mgp = |
Brice Goglin | 6250223 | 2006-12-11 11:24:37 +0100 | [diff] [blame] | 3437 | container_of(work, struct myri10ge_priv, watchdog_work); |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3438 | struct myri10ge_tx_buf *tx; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3439 | u32 reboot; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3440 | int status, rebooted; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3441 | int i; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3442 | u16 cmd, vendor; |
| 3443 | |
| 3444 | mgp->watchdog_resets++; |
| 3445 | pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd); |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3446 | rebooted = 0; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3447 | if ((cmd & PCI_COMMAND_MASTER) == 0) { |
| 3448 | /* Bus master DMA disabled? Check to see |
| 3449 | * if the card rebooted due to a parity error |
| 3450 | * For now, just report it */ |
| 3451 | reboot = myri10ge_read_reboot(mgp); |
| 3452 | printk(KERN_ERR |
Brice Goglin | f181137 | 2007-06-11 20:26:31 +0200 | [diff] [blame] | 3453 | "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n", |
| 3454 | mgp->dev->name, reboot, |
| 3455 | myri10ge_reset_recover ? " " : " not"); |
| 3456 | if (myri10ge_reset_recover == 0) |
| 3457 | return; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3458 | rtnl_lock(); |
| 3459 | mgp->rebooted = 1; |
| 3460 | rebooted = 1; |
| 3461 | myri10ge_close(mgp->dev); |
Brice Goglin | f181137 | 2007-06-11 20:26:31 +0200 | [diff] [blame] | 3462 | myri10ge_reset_recover--; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3463 | mgp->rebooted = 0; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3464 | /* |
| 3465 | * A rebooted nic will come back with config space as |
| 3466 | * it was after power was applied to PCIe bus. |
| 3467 | * Attempt to restore config space which was saved |
| 3468 | * when the driver was loaded, or the last time the |
| 3469 | * nic was resumed from power saving mode. |
| 3470 | */ |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3471 | pci_restore_state(mgp->pdev); |
Brice Goglin | 7adda30 | 2006-12-18 11:50:00 +0100 | [diff] [blame] | 3472 | |
| 3473 | /* save state again for accounting reasons */ |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3474 | pci_save_state(mgp->pdev); |
Brice Goglin | 7adda30 | 2006-12-18 11:50:00 +0100 | [diff] [blame] | 3475 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3476 | } else { |
| 3477 | /* if we get back -1's from our slot, perhaps somebody |
| 3478 | * powered off our card. Don't try to reset it in |
| 3479 | * this case */ |
| 3480 | if (cmd == 0xffff) { |
| 3481 | pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor); |
| 3482 | if (vendor == 0xffff) { |
| 3483 | printk(KERN_ERR |
| 3484 | "myri10ge: %s: device disappeared!\n", |
| 3485 | mgp->dev->name); |
| 3486 | return; |
| 3487 | } |
| 3488 | } |
| 3489 | /* Perhaps it is a software error. Try to reset */ |
| 3490 | |
| 3491 | printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n", |
| 3492 | mgp->dev->name); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3493 | for (i = 0; i < mgp->num_slices; i++) { |
| 3494 | tx = &mgp->ss[i].tx; |
| 3495 | printk(KERN_INFO |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3496 | "myri10ge: %s: (%d): %d %d %d %d %d %d\n", |
| 3497 | mgp->dev->name, i, tx->queue_active, tx->req, |
| 3498 | tx->done, tx->pkt_start, tx->pkt_done, |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3499 | (int)ntohl(mgp->ss[i].fw_stats-> |
| 3500 | send_done_count)); |
| 3501 | msleep(2000); |
| 3502 | printk(KERN_INFO |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3503 | "myri10ge: %s: (%d): %d %d %d %d %d %d\n", |
| 3504 | mgp->dev->name, i, tx->queue_active, tx->req, |
| 3505 | tx->done, tx->pkt_start, tx->pkt_done, |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3506 | (int)ntohl(mgp->ss[i].fw_stats-> |
| 3507 | send_done_count)); |
| 3508 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3509 | } |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3510 | |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3511 | if (!rebooted) { |
| 3512 | rtnl_lock(); |
| 3513 | myri10ge_close(mgp->dev); |
| 3514 | } |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3515 | status = myri10ge_load_firmware(mgp, 1); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3516 | if (status != 0) |
| 3517 | printk(KERN_ERR "myri10ge: %s: failed to load firmware\n", |
| 3518 | mgp->dev->name); |
| 3519 | else |
| 3520 | myri10ge_open(mgp->dev); |
| 3521 | rtnl_unlock(); |
| 3522 | } |
| 3523 | |
| 3524 | /* |
| 3525 | * We use our own timer routine rather than relying upon |
| 3526 | * netdev->tx_timeout because we have a very large hardware transmit |
| 3527 | * queue. Due to the large queue, the netdev->tx_timeout function |
| 3528 | * cannot detect a NIC with a parity error in a timely fashion if the |
| 3529 | * NIC is lightly loaded. |
| 3530 | */ |
| 3531 | static void myri10ge_watchdog_timer(unsigned long arg) |
| 3532 | { |
| 3533 | struct myri10ge_priv *mgp; |
Brice Goglin | b53bef8 | 2008-05-09 02:20:03 +0200 | [diff] [blame] | 3534 | struct myri10ge_slice_state *ss; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3535 | int i, reset_needed, busy_slice_cnt; |
Brice Goglin | 626fda9 | 2007-08-09 09:02:14 +0200 | [diff] [blame] | 3536 | u32 rx_pause_cnt; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3537 | u16 cmd; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3538 | |
| 3539 | mgp = (struct myri10ge_priv *)arg; |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 3540 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3541 | rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause); |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3542 | busy_slice_cnt = 0; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3543 | for (i = 0, reset_needed = 0; |
| 3544 | i < mgp->num_slices && reset_needed == 0; ++i) { |
Brice Goglin | c7dab99 | 2006-12-11 11:25:42 +0100 | [diff] [blame] | 3545 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3546 | ss = &mgp->ss[i]; |
| 3547 | if (ss->rx_small.watchdog_needed) { |
| 3548 | myri10ge_alloc_rx_pages(mgp, &ss->rx_small, |
| 3549 | mgp->small_bytes + MXGEFW_PAD, |
| 3550 | 1); |
| 3551 | if (ss->rx_small.fill_cnt - ss->rx_small.cnt >= |
| 3552 | myri10ge_fill_thresh) |
| 3553 | ss->rx_small.watchdog_needed = 0; |
Brice Goglin | 626fda9 | 2007-08-09 09:02:14 +0200 | [diff] [blame] | 3554 | } |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3555 | if (ss->rx_big.watchdog_needed) { |
| 3556 | myri10ge_alloc_rx_pages(mgp, &ss->rx_big, |
| 3557 | mgp->big_bytes, 1); |
| 3558 | if (ss->rx_big.fill_cnt - ss->rx_big.cnt >= |
| 3559 | myri10ge_fill_thresh) |
| 3560 | ss->rx_big.watchdog_needed = 0; |
| 3561 | } |
| 3562 | |
| 3563 | if (ss->tx.req != ss->tx.done && |
| 3564 | ss->tx.done == ss->watchdog_tx_done && |
| 3565 | ss->watchdog_tx_req != ss->watchdog_tx_done) { |
| 3566 | /* nic seems like it might be stuck.. */ |
| 3567 | if (rx_pause_cnt != mgp->watchdog_pause) { |
| 3568 | if (net_ratelimit()) |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3569 | printk(KERN_WARNING |
| 3570 | "myri10ge %s slice %d:" |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3571 | "TX paused, check link partner\n", |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3572 | mgp->dev->name, i); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3573 | } else { |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3574 | printk(KERN_WARNING |
| 3575 | "myri10ge %s slice %d stuck:", |
| 3576 | mgp->dev->name, i); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3577 | reset_needed = 1; |
| 3578 | } |
| 3579 | } |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3580 | if (ss->watchdog_tx_done != ss->tx.done || |
| 3581 | ss->watchdog_rx_done != ss->rx_done.cnt) { |
| 3582 | busy_slice_cnt++; |
| 3583 | } |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3584 | ss->watchdog_tx_done = ss->tx.done; |
| 3585 | ss->watchdog_tx_req = ss->tx.req; |
Brice Goglin | d023421 | 2009-08-07 10:44:22 +0000 | [diff] [blame] | 3586 | ss->watchdog_rx_done = ss->rx_done.cnt; |
| 3587 | } |
| 3588 | /* if we've sent or received no traffic, poll the NIC to |
| 3589 | * ensure it is still there. Otherwise, we risk not noticing |
| 3590 | * an error in a timely fashion */ |
| 3591 | if (busy_slice_cnt == 0) { |
| 3592 | pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd); |
| 3593 | if ((cmd & PCI_COMMAND_MASTER) == 0) { |
| 3594 | reset_needed = 1; |
| 3595 | } |
Brice Goglin | 626fda9 | 2007-08-09 09:02:14 +0200 | [diff] [blame] | 3596 | } |
Brice Goglin | 626fda9 | 2007-08-09 09:02:14 +0200 | [diff] [blame] | 3597 | mgp->watchdog_pause = rx_pause_cnt; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3598 | |
| 3599 | if (reset_needed) { |
| 3600 | schedule_work(&mgp->watchdog_work); |
| 3601 | } else { |
| 3602 | /* rearm timer */ |
| 3603 | mod_timer(&mgp->watchdog_timer, |
| 3604 | jiffies + myri10ge_watchdog_timeout * HZ); |
| 3605 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3606 | } |
| 3607 | |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 3608 | static void myri10ge_free_slices(struct myri10ge_priv *mgp) |
| 3609 | { |
| 3610 | struct myri10ge_slice_state *ss; |
| 3611 | struct pci_dev *pdev = mgp->pdev; |
| 3612 | size_t bytes; |
| 3613 | int i; |
| 3614 | |
| 3615 | if (mgp->ss == NULL) |
| 3616 | return; |
| 3617 | |
| 3618 | for (i = 0; i < mgp->num_slices; i++) { |
| 3619 | ss = &mgp->ss[i]; |
| 3620 | if (ss->rx_done.entry != NULL) { |
| 3621 | bytes = mgp->max_intr_slots * |
| 3622 | sizeof(*ss->rx_done.entry); |
| 3623 | dma_free_coherent(&pdev->dev, bytes, |
| 3624 | ss->rx_done.entry, ss->rx_done.bus); |
| 3625 | ss->rx_done.entry = NULL; |
| 3626 | } |
| 3627 | if (ss->fw_stats != NULL) { |
| 3628 | bytes = sizeof(*ss->fw_stats); |
| 3629 | dma_free_coherent(&pdev->dev, bytes, |
| 3630 | ss->fw_stats, ss->fw_stats_bus); |
| 3631 | ss->fw_stats = NULL; |
| 3632 | } |
| 3633 | } |
| 3634 | kfree(mgp->ss); |
| 3635 | mgp->ss = NULL; |
| 3636 | } |
| 3637 | |
| 3638 | static int myri10ge_alloc_slices(struct myri10ge_priv *mgp) |
| 3639 | { |
| 3640 | struct myri10ge_slice_state *ss; |
| 3641 | struct pci_dev *pdev = mgp->pdev; |
| 3642 | size_t bytes; |
| 3643 | int i; |
| 3644 | |
| 3645 | bytes = sizeof(*mgp->ss) * mgp->num_slices; |
| 3646 | mgp->ss = kzalloc(bytes, GFP_KERNEL); |
| 3647 | if (mgp->ss == NULL) { |
| 3648 | return -ENOMEM; |
| 3649 | } |
| 3650 | |
| 3651 | for (i = 0; i < mgp->num_slices; i++) { |
| 3652 | ss = &mgp->ss[i]; |
| 3653 | bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry); |
| 3654 | ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes, |
| 3655 | &ss->rx_done.bus, |
| 3656 | GFP_KERNEL); |
| 3657 | if (ss->rx_done.entry == NULL) |
| 3658 | goto abort; |
| 3659 | memset(ss->rx_done.entry, 0, bytes); |
| 3660 | bytes = sizeof(*ss->fw_stats); |
| 3661 | ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes, |
| 3662 | &ss->fw_stats_bus, |
| 3663 | GFP_KERNEL); |
| 3664 | if (ss->fw_stats == NULL) |
| 3665 | goto abort; |
| 3666 | ss->mgp = mgp; |
| 3667 | ss->dev = mgp->dev; |
| 3668 | netif_napi_add(ss->dev, &ss->napi, myri10ge_poll, |
| 3669 | myri10ge_napi_weight); |
| 3670 | } |
| 3671 | return 0; |
| 3672 | abort: |
| 3673 | myri10ge_free_slices(mgp); |
| 3674 | return -ENOMEM; |
| 3675 | } |
| 3676 | |
| 3677 | /* |
| 3678 | * This function determines the number of slices supported. |
| 3679 | * The number slices is the minumum of the number of CPUS, |
| 3680 | * the number of MSI-X irqs supported, the number of slices |
| 3681 | * supported by the firmware |
| 3682 | */ |
| 3683 | static void myri10ge_probe_slices(struct myri10ge_priv *mgp) |
| 3684 | { |
| 3685 | struct myri10ge_cmd cmd; |
| 3686 | struct pci_dev *pdev = mgp->pdev; |
| 3687 | char *old_fw; |
| 3688 | int i, status, ncpus, msix_cap; |
| 3689 | |
| 3690 | mgp->num_slices = 1; |
| 3691 | msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX); |
| 3692 | ncpus = num_online_cpus(); |
| 3693 | |
| 3694 | if (myri10ge_max_slices == 1 || msix_cap == 0 || |
| 3695 | (myri10ge_max_slices == -1 && ncpus < 2)) |
| 3696 | return; |
| 3697 | |
| 3698 | /* try to load the slice aware rss firmware */ |
| 3699 | old_fw = mgp->fw_name; |
Brice Goglin | 13b2738 | 2008-08-13 21:05:52 +0200 | [diff] [blame] | 3700 | if (myri10ge_fw_name != NULL) { |
| 3701 | dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n", |
| 3702 | myri10ge_fw_name); |
| 3703 | mgp->fw_name = myri10ge_fw_name; |
| 3704 | } else if (old_fw == myri10ge_fw_aligned) |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 3705 | mgp->fw_name = myri10ge_fw_rss_aligned; |
| 3706 | else |
| 3707 | mgp->fw_name = myri10ge_fw_rss_unaligned; |
| 3708 | status = myri10ge_load_firmware(mgp, 0); |
| 3709 | if (status != 0) { |
| 3710 | dev_info(&pdev->dev, "Rss firmware not found\n"); |
| 3711 | return; |
| 3712 | } |
| 3713 | |
| 3714 | /* hit the board with a reset to ensure it is alive */ |
| 3715 | memset(&cmd, 0, sizeof(cmd)); |
| 3716 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0); |
| 3717 | if (status != 0) { |
| 3718 | dev_err(&mgp->pdev->dev, "failed reset\n"); |
| 3719 | goto abort_with_fw; |
| 3720 | return; |
| 3721 | } |
| 3722 | |
| 3723 | mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot); |
| 3724 | |
| 3725 | /* tell it the size of the interrupt queues */ |
| 3726 | cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot); |
| 3727 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0); |
| 3728 | if (status != 0) { |
| 3729 | dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n"); |
| 3730 | goto abort_with_fw; |
| 3731 | } |
| 3732 | |
| 3733 | /* ask the maximum number of slices it supports */ |
| 3734 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0); |
| 3735 | if (status != 0) |
| 3736 | goto abort_with_fw; |
| 3737 | else |
| 3738 | mgp->num_slices = cmd.data0; |
| 3739 | |
| 3740 | /* Only allow multiple slices if MSI-X is usable */ |
| 3741 | if (!myri10ge_msi) { |
| 3742 | goto abort_with_fw; |
| 3743 | } |
| 3744 | |
| 3745 | /* if the admin did not specify a limit to how many |
| 3746 | * slices we should use, cap it automatically to the |
| 3747 | * number of CPUs currently online */ |
| 3748 | if (myri10ge_max_slices == -1) |
| 3749 | myri10ge_max_slices = ncpus; |
| 3750 | |
| 3751 | if (mgp->num_slices > myri10ge_max_slices) |
| 3752 | mgp->num_slices = myri10ge_max_slices; |
| 3753 | |
| 3754 | /* Now try to allocate as many MSI-X vectors as we have |
| 3755 | * slices. We give up on MSI-X if we can only get a single |
| 3756 | * vector. */ |
| 3757 | |
| 3758 | mgp->msix_vectors = kzalloc(mgp->num_slices * |
| 3759 | sizeof(*mgp->msix_vectors), GFP_KERNEL); |
| 3760 | if (mgp->msix_vectors == NULL) |
| 3761 | goto disable_msix; |
| 3762 | for (i = 0; i < mgp->num_slices; i++) { |
| 3763 | mgp->msix_vectors[i].entry = i; |
| 3764 | } |
| 3765 | |
| 3766 | while (mgp->num_slices > 1) { |
| 3767 | /* make sure it is a power of two */ |
| 3768 | while (!is_power_of_2(mgp->num_slices)) |
| 3769 | mgp->num_slices--; |
| 3770 | if (mgp->num_slices == 1) |
| 3771 | goto disable_msix; |
| 3772 | status = pci_enable_msix(pdev, mgp->msix_vectors, |
| 3773 | mgp->num_slices); |
| 3774 | if (status == 0) { |
| 3775 | pci_disable_msix(pdev); |
| 3776 | return; |
| 3777 | } |
| 3778 | if (status > 0) |
| 3779 | mgp->num_slices = status; |
| 3780 | else |
| 3781 | goto disable_msix; |
| 3782 | } |
| 3783 | |
| 3784 | disable_msix: |
| 3785 | if (mgp->msix_vectors != NULL) { |
| 3786 | kfree(mgp->msix_vectors); |
| 3787 | mgp->msix_vectors = NULL; |
| 3788 | } |
| 3789 | |
| 3790 | abort_with_fw: |
| 3791 | mgp->num_slices = 1; |
| 3792 | mgp->fw_name = old_fw; |
| 3793 | myri10ge_load_firmware(mgp, 0); |
| 3794 | } |
Brice Goglin | 7792973 | 2008-05-09 02:21:10 +0200 | [diff] [blame] | 3795 | |
Stephen Hemminger | 8126089 | 2008-11-21 17:30:35 -0800 | [diff] [blame] | 3796 | static const struct net_device_ops myri10ge_netdev_ops = { |
| 3797 | .ndo_open = myri10ge_open, |
| 3798 | .ndo_stop = myri10ge_close, |
| 3799 | .ndo_start_xmit = myri10ge_xmit, |
| 3800 | .ndo_get_stats = myri10ge_get_stats, |
| 3801 | .ndo_validate_addr = eth_validate_addr, |
| 3802 | .ndo_change_mtu = myri10ge_change_mtu, |
| 3803 | .ndo_set_multicast_list = myri10ge_set_multicast_list, |
| 3804 | .ndo_set_mac_address = myri10ge_set_mac_address, |
| 3805 | }; |
| 3806 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3807 | static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 3808 | { |
| 3809 | struct net_device *netdev; |
| 3810 | struct myri10ge_priv *mgp; |
| 3811 | struct device *dev = &pdev->dev; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3812 | int i; |
| 3813 | int status = -ENXIO; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3814 | int dac_enabled; |
Brice Goglin | 00b5e50 | 2008-11-20 01:50:28 -0800 | [diff] [blame] | 3815 | unsigned hdr_offset, ss_offset; |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 3816 | static int board_number; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3817 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3818 | netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3819 | if (netdev == NULL) { |
| 3820 | dev_err(dev, "Could not allocate ethernet device\n"); |
| 3821 | return -ENOMEM; |
| 3822 | } |
| 3823 | |
Maik Hampel | b245fb6 | 2007-06-28 17:07:26 +0200 | [diff] [blame] | 3824 | SET_NETDEV_DEV(netdev, &pdev->dev); |
| 3825 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3826 | mgp = netdev_priv(netdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3827 | mgp->dev = netdev; |
| 3828 | mgp->pdev = pdev; |
| 3829 | mgp->csum_flag = MXGEFW_FLAGS_CKSUM; |
| 3830 | mgp->pause = myri10ge_flow_control; |
| 3831 | mgp->intr_coal_delay = myri10ge_intr_coal_delay; |
Brice Goglin | c58ac5c | 2006-08-21 17:36:49 -0400 | [diff] [blame] | 3832 | mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT); |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 3833 | mgp->board_number = board_number; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3834 | init_waitqueue_head(&mgp->down_wq); |
| 3835 | |
| 3836 | if (pci_enable_device(pdev)) { |
| 3837 | dev_err(&pdev->dev, "pci_enable_device call failed\n"); |
| 3838 | status = -ENODEV; |
| 3839 | goto abort_with_netdev; |
| 3840 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3841 | |
| 3842 | /* Find the vendor-specific cap so we can check |
| 3843 | * the reboot register later on */ |
| 3844 | mgp->vendor_specific_offset |
| 3845 | = pci_find_capability(pdev, PCI_CAP_ID_VNDR); |
| 3846 | |
| 3847 | /* Set our max read request to 4KB */ |
Brice Goglin | 302d242 | 2007-08-24 08:57:17 +0200 | [diff] [blame] | 3848 | status = pcie_set_readrq(pdev, 4096); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3849 | if (status != 0) { |
| 3850 | dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n", |
| 3851 | status); |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 3852 | goto abort_with_enabled; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3853 | } |
| 3854 | |
| 3855 | pci_set_master(pdev); |
| 3856 | dac_enabled = 1; |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 3857 | status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3858 | if (status != 0) { |
| 3859 | dac_enabled = 0; |
| 3860 | dev_err(&pdev->dev, |
Joe Perches | 898eb71 | 2007-10-18 03:06:30 -0700 | [diff] [blame] | 3861 | "64-bit pci address mask was refused, " |
| 3862 | "trying 32-bit\n"); |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 3863 | status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3864 | } |
| 3865 | if (status != 0) { |
| 3866 | dev_err(&pdev->dev, "Error %d setting DMA mask\n", status); |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 3867 | goto abort_with_enabled; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3868 | } |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 3869 | (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 3870 | mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd), |
| 3871 | &mgp->cmd_bus, GFP_KERNEL); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3872 | if (mgp->cmd == NULL) |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 3873 | goto abort_with_enabled; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3874 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3875 | mgp->board_span = pci_resource_len(pdev, 0); |
| 3876 | mgp->iomem_base = pci_resource_start(pdev, 0); |
| 3877 | mgp->mtrr = -1; |
Brice Goglin | 276e26c | 2007-03-07 20:02:32 +0100 | [diff] [blame] | 3878 | mgp->wc_enabled = 0; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3879 | #ifdef CONFIG_MTRR |
| 3880 | mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span, |
| 3881 | MTRR_TYPE_WRCOMB, 1); |
Brice Goglin | 276e26c | 2007-03-07 20:02:32 +0100 | [diff] [blame] | 3882 | if (mgp->mtrr >= 0) |
| 3883 | mgp->wc_enabled = 1; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3884 | #endif |
Brice Goglin | c7f8099 | 2008-07-21 10:26:25 +0200 | [diff] [blame] | 3885 | mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3886 | if (mgp->sram == NULL) { |
| 3887 | dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n", |
| 3888 | mgp->board_span, mgp->iomem_base); |
| 3889 | status = -ENXIO; |
Brice Goglin | c7f8099 | 2008-07-21 10:26:25 +0200 | [diff] [blame] | 3890 | goto abort_with_mtrr; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3891 | } |
Brice Goglin | 00b5e50 | 2008-11-20 01:50:28 -0800 | [diff] [blame] | 3892 | hdr_offset = |
| 3893 | ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc; |
| 3894 | ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs); |
| 3895 | mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset)); |
| 3896 | if (mgp->sram_size > mgp->board_span || |
| 3897 | mgp->sram_size <= MYRI10GE_FW_OFFSET) { |
| 3898 | dev_err(&pdev->dev, |
| 3899 | "invalid sram_size %dB or board span %ldB\n", |
| 3900 | mgp->sram_size, mgp->board_span); |
| 3901 | goto abort_with_ioremap; |
| 3902 | } |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3903 | memcpy_fromio(mgp->eeprom_strings, |
Brice Goglin | 00b5e50 | 2008-11-20 01:50:28 -0800 | [diff] [blame] | 3904 | mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3905 | memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2); |
| 3906 | status = myri10ge_read_mac_addr(mgp); |
| 3907 | if (status) |
| 3908 | goto abort_with_ioremap; |
| 3909 | |
| 3910 | for (i = 0; i < ETH_ALEN; i++) |
| 3911 | netdev->dev_addr[i] = mgp->mac_addr[i]; |
| 3912 | |
Brice Goglin | 5443e9e | 2007-05-07 23:52:22 +0200 | [diff] [blame] | 3913 | myri10ge_select_firmware(mgp); |
| 3914 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3915 | status = myri10ge_load_firmware(mgp, 1); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3916 | if (status != 0) { |
| 3917 | dev_err(&pdev->dev, "failed to load firmware\n"); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3918 | goto abort_with_ioremap; |
| 3919 | } |
| 3920 | myri10ge_probe_slices(mgp); |
| 3921 | status = myri10ge_alloc_slices(mgp); |
| 3922 | if (status != 0) { |
| 3923 | dev_err(&pdev->dev, "failed to alloc slice state\n"); |
| 3924 | goto abort_with_firmware; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3925 | } |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3926 | netdev->real_num_tx_queues = mgp->num_slices; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3927 | status = myri10ge_reset(mgp); |
| 3928 | if (status != 0) { |
| 3929 | dev_err(&pdev->dev, "failed reset\n"); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3930 | goto abort_with_slices; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3931 | } |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 3932 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 3933 | myri10ge_setup_dca(mgp); |
| 3934 | #endif |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3935 | pci_set_drvdata(pdev, mgp); |
| 3936 | if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU) |
| 3937 | myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; |
| 3938 | if ((myri10ge_initial_mtu + ETH_HLEN) < 68) |
| 3939 | myri10ge_initial_mtu = 68; |
Stephen Hemminger | 8126089 | 2008-11-21 17:30:35 -0800 | [diff] [blame] | 3940 | |
| 3941 | netdev->netdev_ops = &myri10ge_netdev_ops; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3942 | netdev->mtu = myri10ge_initial_mtu; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3943 | netdev->base_addr = mgp->iomem_base; |
Brice Goglin | 4f93fde | 2007-10-13 12:34:01 +0200 | [diff] [blame] | 3944 | netdev->features = mgp->features; |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 3945 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3946 | if (dac_enabled) |
| 3947 | netdev->features |= NETIF_F_HIGHDMA; |
Brice Goglin | 2552c31 | 2009-05-24 05:27:51 +0000 | [diff] [blame] | 3948 | netdev->features |= NETIF_F_LRO; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3949 | |
Brice Goglin | dddc045 | 2009-05-24 05:27:59 +0000 | [diff] [blame] | 3950 | netdev->vlan_features |= mgp->features; |
| 3951 | if (mgp->fw_ver_tiny < 37) |
| 3952 | netdev->vlan_features &= ~NETIF_F_TSO6; |
| 3953 | if (mgp->fw_ver_tiny < 32) |
| 3954 | netdev->vlan_features &= ~NETIF_F_TSO; |
| 3955 | |
Brice Goglin | 21d05db | 2007-01-09 21:05:04 +0100 | [diff] [blame] | 3956 | /* make sure we can get an irq, and that MSI can be |
| 3957 | * setup (if available). Also ensure netdev->irq |
| 3958 | * is set to correct value if MSI is enabled */ |
| 3959 | status = myri10ge_request_irq(mgp); |
| 3960 | if (status != 0) |
| 3961 | goto abort_with_firmware; |
| 3962 | netdev->irq = pdev->irq; |
| 3963 | myri10ge_free_irq(mgp); |
| 3964 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3965 | /* Save configuration space to be restored if the |
| 3966 | * nic resets due to a parity error */ |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3967 | pci_save_state(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3968 | |
| 3969 | /* Setup the watchdog timer */ |
| 3970 | setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer, |
| 3971 | (unsigned long)mgp); |
| 3972 | |
Brice Goglin | 5908182 | 2009-04-16 02:23:56 +0000 | [diff] [blame] | 3973 | spin_lock_init(&mgp->stats_lock); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3974 | SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops); |
David Howells | c402895 | 2006-11-22 14:57:56 +0000 | [diff] [blame] | 3975 | INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3976 | status = register_netdev(netdev); |
| 3977 | if (status != 0) { |
| 3978 | dev_err(&pdev->dev, "register_netdev failed: %d\n", status); |
Brice Goglin | 7adda30 | 2006-12-18 11:50:00 +0100 | [diff] [blame] | 3979 | goto abort_with_state; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3980 | } |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3981 | if (mgp->msix_enabled) |
| 3982 | dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n", |
| 3983 | mgp->num_slices, mgp->tx_boundary, mgp->fw_name, |
| 3984 | (mgp->wc_enabled ? "Enabled" : "Disabled")); |
| 3985 | else |
| 3986 | dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n", |
| 3987 | mgp->msi_enabled ? "MSI" : "xPIC", |
| 3988 | netdev->irq, mgp->tx_boundary, mgp->fw_name, |
| 3989 | (mgp->wc_enabled ? "Enabled" : "Disabled")); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3990 | |
Brice Goglin | 2d90b0a | 2009-04-16 02:24:59 +0000 | [diff] [blame] | 3991 | board_number++; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3992 | return 0; |
| 3993 | |
Brice Goglin | 7adda30 | 2006-12-18 11:50:00 +0100 | [diff] [blame] | 3994 | abort_with_state: |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 3995 | pci_restore_state(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 3996 | |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 3997 | abort_with_slices: |
| 3998 | myri10ge_free_slices(mgp); |
| 3999 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4000 | abort_with_firmware: |
| 4001 | myri10ge_dummy_rdma(mgp, 0); |
| 4002 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4003 | abort_with_ioremap: |
Brice Goglin | 0f84001 | 2009-01-05 18:16:14 -0800 | [diff] [blame] | 4004 | if (mgp->mac_addr_string != NULL) |
| 4005 | dev_err(&pdev->dev, |
| 4006 | "myri10ge_probe() failed: MAC=%s, SN=%ld\n", |
| 4007 | mgp->mac_addr_string, mgp->serial_number); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4008 | iounmap(mgp->sram); |
| 4009 | |
Brice Goglin | c7f8099 | 2008-07-21 10:26:25 +0200 | [diff] [blame] | 4010 | abort_with_mtrr: |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4011 | #ifdef CONFIG_MTRR |
| 4012 | if (mgp->mtrr >= 0) |
| 4013 | mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); |
| 4014 | #endif |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 4015 | dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), |
| 4016 | mgp->cmd, mgp->cmd_bus); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4017 | |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 4018 | abort_with_enabled: |
| 4019 | pci_disable_device(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4020 | |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 4021 | abort_with_netdev: |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4022 | free_netdev(netdev); |
| 4023 | return status; |
| 4024 | } |
| 4025 | |
| 4026 | /* |
| 4027 | * myri10ge_remove |
| 4028 | * |
| 4029 | * Does what is necessary to shutdown one Myrinet device. Called |
| 4030 | * once for each Myrinet card by the kernel when a module is |
| 4031 | * unloaded. |
| 4032 | */ |
| 4033 | static void myri10ge_remove(struct pci_dev *pdev) |
| 4034 | { |
| 4035 | struct myri10ge_priv *mgp; |
| 4036 | struct net_device *netdev; |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4037 | |
| 4038 | mgp = pci_get_drvdata(pdev); |
| 4039 | if (mgp == NULL) |
| 4040 | return; |
| 4041 | |
| 4042 | flush_scheduled_work(); |
| 4043 | netdev = mgp->dev; |
| 4044 | unregister_netdev(netdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4045 | |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 4046 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 4047 | myri10ge_teardown_dca(mgp); |
| 4048 | #endif |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4049 | myri10ge_dummy_rdma(mgp, 0); |
| 4050 | |
Brice Goglin | 7adda30 | 2006-12-18 11:50:00 +0100 | [diff] [blame] | 4051 | /* avoid a memory leak */ |
Brice Goglin | 83f6e15 | 2006-12-18 11:52:02 +0100 | [diff] [blame] | 4052 | pci_restore_state(pdev); |
Brice Goglin | 7adda30 | 2006-12-18 11:50:00 +0100 | [diff] [blame] | 4053 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4054 | iounmap(mgp->sram); |
| 4055 | |
| 4056 | #ifdef CONFIG_MTRR |
| 4057 | if (mgp->mtrr >= 0) |
| 4058 | mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); |
| 4059 | #endif |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 4060 | myri10ge_free_slices(mgp); |
| 4061 | if (mgp->msix_vectors != NULL) |
| 4062 | kfree(mgp->msix_vectors); |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 4063 | dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), |
| 4064 | mgp->cmd, mgp->cmd_bus); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4065 | |
| 4066 | free_netdev(netdev); |
Brice Goglin | e3fd553 | 2009-01-17 08:27:19 +0000 | [diff] [blame] | 4067 | pci_disable_device(pdev); |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4068 | pci_set_drvdata(pdev, NULL); |
| 4069 | } |
| 4070 | |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 4071 | #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008 |
Brice Goglin | a07bc1f | 2007-09-14 00:40:14 +0200 | [diff] [blame] | 4072 | #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009 |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4073 | |
| 4074 | static struct pci_device_id myri10ge_pci_tbl[] = { |
Brice Goglin | b10c066 | 2006-06-08 10:25:00 -0400 | [diff] [blame] | 4075 | {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)}, |
Brice Goglin | a07bc1f | 2007-09-14 00:40:14 +0200 | [diff] [blame] | 4076 | {PCI_DEVICE |
| 4077 | (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)}, |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4078 | {0}, |
| 4079 | }; |
| 4080 | |
Brice Goglin | 9713107 | 2009-04-16 02:29:22 +0000 | [diff] [blame] | 4081 | MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl); |
| 4082 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4083 | static struct pci_driver myri10ge_driver = { |
| 4084 | .name = "myri10ge", |
| 4085 | .probe = myri10ge_probe, |
| 4086 | .remove = myri10ge_remove, |
| 4087 | .id_table = myri10ge_pci_tbl, |
| 4088 | #ifdef CONFIG_PM |
| 4089 | .suspend = myri10ge_suspend, |
| 4090 | .resume = myri10ge_resume, |
| 4091 | #endif |
| 4092 | }; |
| 4093 | |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 4094 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 4095 | static int |
| 4096 | myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p) |
| 4097 | { |
| 4098 | int err = driver_for_each_device(&myri10ge_driver.driver, |
| 4099 | NULL, &event, |
| 4100 | myri10ge_notify_dca_device); |
| 4101 | |
| 4102 | if (err) |
| 4103 | return NOTIFY_BAD; |
| 4104 | return NOTIFY_DONE; |
| 4105 | } |
| 4106 | |
| 4107 | static struct notifier_block myri10ge_dca_notifier = { |
| 4108 | .notifier_call = myri10ge_notify_dca, |
| 4109 | .next = NULL, |
| 4110 | .priority = 0, |
| 4111 | }; |
Brice Goglin | 4ee2ac5 | 2008-11-23 15:49:28 -0800 | [diff] [blame] | 4112 | #endif /* CONFIG_MYRI10GE_DCA */ |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 4113 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4114 | static __init int myri10ge_init_module(void) |
| 4115 | { |
| 4116 | printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name, |
| 4117 | MYRI10GE_VERSION_STR); |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 4118 | |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 4119 | if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) { |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 4120 | printk(KERN_ERR |
| 4121 | "%s: Illegal rssh hash type %d, defaulting to source port\n", |
| 4122 | myri10ge_driver.name, myri10ge_rss_hash); |
| 4123 | myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT; |
| 4124 | } |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 4125 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 4126 | dca_register_notify(&myri10ge_dca_notifier); |
| 4127 | #endif |
Brice Goglin | 236bb5e | 2008-09-28 15:34:21 +0000 | [diff] [blame] | 4128 | if (myri10ge_max_slices > MYRI10GE_MAX_SLICES) |
| 4129 | myri10ge_max_slices = MYRI10GE_MAX_SLICES; |
Brice Goglin | 0dcffac | 2008-05-09 02:21:49 +0200 | [diff] [blame] | 4130 | |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4131 | return pci_register_driver(&myri10ge_driver); |
| 4132 | } |
| 4133 | |
| 4134 | module_init(myri10ge_init_module); |
| 4135 | |
| 4136 | static __exit void myri10ge_cleanup_module(void) |
| 4137 | { |
Jeff Garzik | 5dd2d33 | 2008-10-16 05:09:31 -0400 | [diff] [blame] | 4138 | #ifdef CONFIG_MYRI10GE_DCA |
Brice Goglin | 981813d | 2008-05-09 02:22:16 +0200 | [diff] [blame] | 4139 | dca_unregister_notify(&myri10ge_dca_notifier); |
| 4140 | #endif |
Brice Goglin | 0da34b6 | 2006-05-23 06:10:15 -0400 | [diff] [blame] | 4141 | pci_unregister_driver(&myri10ge_driver); |
| 4142 | } |
| 4143 | |
| 4144 | module_exit(myri10ge_cleanup_module); |