blob: 9a829a7cbc60c11b14606327c2cb940868a675fc [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34#include <linux/ata.h>
Alan4bb64fb2007-02-16 01:40:04 -080035#include "sis.h"
Jeff Garzik669a5db2006-08-29 18:12:40 -040036
37#define DRV_NAME "pata_sis"
Alan Cox2e413f52007-03-07 16:54:24 +000038#define DRV_VERSION "0.5.1"
Jeff Garzik669a5db2006-08-29 18:12:40 -040039
40struct sis_chipset {
Tejun Heo1626aeb2007-05-04 12:43:58 +020041 u16 device; /* PCI host ID */
42 const struct ata_port_info *info; /* Info block */
Jeff Garzik669a5db2006-08-29 18:12:40 -040043 /* Probably add family, cable detect type etc here to clean
44 up code later */
45};
46
Jakub W. Jozwicki J7dcbc1f2007-01-09 09:01:19 +090047struct sis_laptop {
48 u16 device;
49 u16 subvendor;
50 u16 subdevice;
51};
52
53static const struct sis_laptop sis_laptop[] = {
54 /* devid, subvendor, subdev */
55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
56 /* end marker */
57 { 0, }
58};
59
60static int sis_short_ata40(struct pci_dev *dev)
61{
62 const struct sis_laptop *lap = &sis_laptop[0];
63
64 while (lap->device) {
65 if (lap->device == dev->device &&
66 lap->subvendor == dev->subsystem_vendor &&
67 lap->subdevice == dev->subsystem_device)
68 return 1;
69 lap++;
70 }
71
72 return 0;
73}
74
Jeff Garzik669a5db2006-08-29 18:12:40 -040075/**
Alan Coxdd668d12007-05-21 15:00:53 +010076 * sis_old_port_base - return PCI configuration base for dev
Jeff Garzik669a5db2006-08-29 18:12:40 -040077 * @adev: device
78 *
79 * Returns the base of the PCI configuration registers for this port
80 * number.
81 */
82
Alan Coxdd668d12007-05-21 15:00:53 +010083static int sis_old_port_base(struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -040084{
85 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
86}
87
88/**
Alan Cox2e413f52007-03-07 16:54:24 +000089 * sis_133_cable_detect - check for 40/80 pin
Jeff Garzik669a5db2006-08-29 18:12:40 -040090 * @ap: Port
Tejun Heod4b2bab2007-02-02 16:50:52 +090091 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -040092 *
93 * Perform cable detection for the later UDMA133 capable
94 * SiS chipset.
95 */
96
Alan Cox2e413f52007-03-07 16:54:24 +000097static int sis_133_cable_detect(struct ata_port *ap)
98{
99 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
100 u16 tmp;
101
102 /* The top bit of this register is the cable detect bit */
103 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
104 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
105 return ATA_CBL_PATA40;
106 return ATA_CBL_PATA80;
107}
108
109/**
110 * sis_66_cable_detect - check for 40/80 pin
111 * @ap: Port
Tejun Heod4b2bab2007-02-02 16:50:52 +0900112 * @deadline: deadline jiffies for the operation
Alan Cox2e413f52007-03-07 16:54:24 +0000113 *
114 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
115 * SiS IDE controllers.
116 */
117
118static int sis_66_cable_detect(struct ata_port *ap)
119{
120 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
121 u8 tmp;
122
123 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
124 pci_read_config_byte(pdev, 0x48, &tmp);
125 tmp >>= ap->port_no;
126 if ((tmp & 0x10) && !sis_short_ata40(pdev))
127 return ATA_CBL_PATA40;
128 return ATA_CBL_PATA80;
129}
130
131
132/**
133 * sis_pre_reset - probe begin
134 * @ap: ATA port
Tejun Heod4b2bab2007-02-02 16:50:52 +0900135 * @deadline: deadline jiffies for the operation
Alan Cox2e413f52007-03-07 16:54:24 +0000136 *
137 * Set up cable type and use generic probe init
138 */
139
Jeff Garzik27c78b32007-03-09 09:41:19 -0500140static int sis_pre_reset(struct ata_port *ap, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141{
142 static const struct pci_bits sis_enable_bits[] = {
143 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
144 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
145 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400146
Jeff Garzik669a5db2006-08-29 18:12:40 -0400147 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400148
Alan Coxc9619222006-09-26 17:53:38 +0100149 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
150 return -ENOENT;
Tejun Heod4b2bab2007-02-02 16:50:52 +0900151
Alan Cox15ce0942007-05-25 20:50:24 +0100152 /* Clear the FIFO settings. We can't enable the FIFO until
153 we know we are poking at a disk */
154 pci_write_config_byte(pdev, 0x4B, 0);
Tejun Heod4b2bab2007-02-02 16:50:52 +0900155 return ata_std_prereset(ap, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400156}
157
Alan Cox2e413f52007-03-07 16:54:24 +0000158
Jeff Garzik669a5db2006-08-29 18:12:40 -0400159/**
160 * sis_error_handler - Probe specified port on PATA host controller
161 * @ap: Port to probe
162 *
163 * LOCKING:
164 * None (inherited from caller).
165 */
166
Alan Cox2e413f52007-03-07 16:54:24 +0000167static void sis_error_handler(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400168{
Alan Cox2e413f52007-03-07 16:54:24 +0000169 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400170}
171
172/**
173 * sis_set_fifo - Set RWP fifo bits for this device
174 * @ap: Port
175 * @adev: Device
176 *
177 * SIS chipsets implement prefetch/postwrite bits for each device
178 * on both channels. This functionality is not ATAPI compatible and
179 * must be configured according to the class of device present
180 */
181
182static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
183{
184 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
185 u8 fifoctrl;
186 u8 mask = 0x11;
187
188 mask <<= (2 * ap->port_no);
189 mask <<= adev->devno;
190
191 /* This holds various bits including the FIFO control */
192 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
193 fifoctrl &= ~mask;
194
195 /* Enable for ATA (disk) only */
196 if (adev->class == ATA_DEV_ATA)
197 fifoctrl |= mask;
198 pci_write_config_byte(pdev, 0x4B, fifoctrl);
199}
200
201/**
202 * sis_old_set_piomode - Initialize host controller PATA PIO timings
203 * @ap: Port whose timings we are configuring
204 * @adev: Device we are configuring for.
205 *
206 * Set PIO mode for device, in host controller PCI config space. This
207 * function handles PIO set up for all chips that are pre ATA100 and
208 * also early ATA100 devices.
209 *
210 * LOCKING:
211 * None (inherited from caller).
212 */
213
214static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
215{
216 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxdd668d12007-05-21 15:00:53 +0100217 int port = sis_old_port_base(adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400218 u8 t1, t2;
219 int speed = adev->pio_mode - XFER_PIO_0;
220
221 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
222 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
223
224 sis_set_fifo(ap, adev);
225
226 pci_read_config_byte(pdev, port, &t1);
227 pci_read_config_byte(pdev, port + 1, &t2);
228
229 t1 &= ~0x0F; /* Clear active/recovery timings */
230 t2 &= ~0x07;
231
232 t1 |= active[speed];
233 t2 |= recovery[speed];
234
235 pci_write_config_byte(pdev, port, t1);
236 pci_write_config_byte(pdev, port + 1, t2);
237}
238
239/**
240 * sis_100_set_pioode - Initialize host controller PATA PIO timings
241 * @ap: Port whose timings we are configuring
242 * @adev: Device we are configuring for.
243 *
244 * Set PIO mode for device, in host controller PCI config space. This
245 * function handles PIO set up for ATA100 devices and early ATA133.
246 *
247 * LOCKING:
248 * None (inherited from caller).
249 */
250
251static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
252{
253 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxdd668d12007-05-21 15:00:53 +0100254 int port = sis_old_port_base(adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400255 int speed = adev->pio_mode - XFER_PIO_0;
256
257 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
258
259 sis_set_fifo(ap, adev);
260
261 pci_write_config_byte(pdev, port, actrec[speed]);
262}
263
264/**
265 * sis_133_set_pioode - Initialize host controller PATA PIO timings
266 * @ap: Port whose timings we are configuring
267 * @adev: Device we are configuring for.
268 *
269 * Set PIO mode for device, in host controller PCI config space. This
270 * function handles PIO set up for the later ATA133 devices.
271 *
272 * LOCKING:
273 * None (inherited from caller).
274 */
275
276static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
277{
278 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
279 int port = 0x40;
280 u32 t1;
281 u32 reg54;
282 int speed = adev->pio_mode - XFER_PIO_0;
283
284 const u32 timing133[] = {
285 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
286 0x0C266000,
287 0x04263000,
288 0x0C0A3000,
289 0x05093000
290 };
291 const u32 timing100[] = {
292 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
293 0x091C4000,
294 0x031C2000,
295 0x09072000,
296 0x04062000
297 };
298
299 sis_set_fifo(ap, adev);
300
301 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
302 pci_read_config_dword(pdev, 0x54, &reg54);
303 if (reg54 & 0x40000000)
304 port = 0x70;
305 port += 8 * ap->port_no + 4 * adev->devno;
306
307 pci_read_config_dword(pdev, port, &t1);
308 t1 &= 0xC0C00FFF; /* Mask out timing */
309
310 if (t1 & 0x08) /* 100 or 133 ? */
311 t1 |= timing133[speed];
312 else
313 t1 |= timing100[speed];
314 pci_write_config_byte(pdev, port, t1);
315}
316
317/**
318 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
319 * @ap: Port whose timings we are configuring
320 * @adev: Device to program
321 *
322 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
323 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
324 * the old ide/pci driver.
325 *
326 * LOCKING:
327 * None (inherited from caller).
328 */
329
330static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
331{
332 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
333 int speed = adev->dma_mode - XFER_MW_DMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100334 int drive_pci = sis_old_port_base(adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400335 u16 timing;
336
337 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
338 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
339
340 pci_read_config_word(pdev, drive_pci, &timing);
341
342 if (adev->dma_mode < XFER_UDMA_0) {
343 /* bits 3-0 hold recovery timing bits 8-10 active timing and
344 the higer bits are dependant on the device */
345 timing &= ~ 0x870F;
346 timing |= mwdma_bits[speed];
347 pci_write_config_word(pdev, drive_pci, timing);
348 } else {
349 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
350 speed = adev->dma_mode - XFER_UDMA_0;
351 timing &= ~0x6000;
352 timing |= udma_bits[speed];
353 }
354}
355
356/**
357 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
358 * @ap: Port whose timings we are configuring
359 * @adev: Device to program
360 *
361 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
362 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
363 * the old ide/pci driver.
364 *
365 * LOCKING:
366 * None (inherited from caller).
367 */
368
369static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
370{
371 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
372 int speed = adev->dma_mode - XFER_MW_DMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100373 int drive_pci = sis_old_port_base(adev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400374 u16 timing;
375
376 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
377 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
378
379 pci_read_config_word(pdev, drive_pci, &timing);
380
381 if (adev->dma_mode < XFER_UDMA_0) {
382 /* bits 3-0 hold recovery timing bits 8-10 active timing and
383 the higer bits are dependant on the device, bit 15 udma */
Alan Coxdd668d12007-05-21 15:00:53 +0100384 timing &= ~0x870F;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400385 timing |= mwdma_bits[speed];
386 } else {
387 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
388 speed = adev->dma_mode - XFER_UDMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100389 timing &= ~0xF000;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400390 timing |= udma_bits[speed];
391 }
392 pci_write_config_word(pdev, drive_pci, timing);
393}
394
395/**
396 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
397 * @ap: Port whose timings we are configuring
398 * @adev: Device to program
399 *
400 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
401 * Handles UDMA66 and early UDMA100 devices.
402 *
403 * LOCKING:
404 * None (inherited from caller).
405 */
406
407static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
408{
409 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
410 int speed = adev->dma_mode - XFER_MW_DMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100411 int drive_pci = sis_old_port_base(adev);
412 u8 timing;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400413
Alan Coxdd668d12007-05-21 15:00:53 +0100414 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400415
Alan Coxdd668d12007-05-21 15:00:53 +0100416 pci_read_config_byte(pdev, drive_pci + 1, &timing);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400417
418 if (adev->dma_mode < XFER_UDMA_0) {
419 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
420 } else {
Alan Coxdd668d12007-05-21 15:00:53 +0100421 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400422 speed = adev->dma_mode - XFER_UDMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100423 timing &= ~0x8F;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400424 timing |= udma_bits[speed];
425 }
Alan Coxdd668d12007-05-21 15:00:53 +0100426 pci_write_config_byte(pdev, drive_pci + 1, timing);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400427}
428
429/**
430 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
431 * @ap: Port whose timings we are configuring
432 * @adev: Device to program
433 *
434 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
435 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
436 * the old ide/pci driver.
437 *
438 * LOCKING:
439 * None (inherited from caller).
440 */
441
442static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
443{
444 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
445 int speed = adev->dma_mode - XFER_MW_DMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100446 int drive_pci = sis_old_port_base(adev);
447 u8 timing;
448 /* Low 4 bits are timing */
449 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400450
Alan Coxdd668d12007-05-21 15:00:53 +0100451 pci_read_config_byte(pdev, drive_pci + 1, &timing);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400452
453 if (adev->dma_mode < XFER_UDMA_0) {
454 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
455 } else {
Alan Coxdd668d12007-05-21 15:00:53 +0100456 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400457 speed = adev->dma_mode - XFER_UDMA_0;
Alan Coxdd668d12007-05-21 15:00:53 +0100458 timing &= ~0x8F;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400459 timing |= udma_bits[speed];
460 }
Alan Coxdd668d12007-05-21 15:00:53 +0100461 pci_write_config_byte(pdev, drive_pci + 1, timing);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400462}
463
464/**
465 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
466 * @ap: Port whose timings we are configuring
467 * @adev: Device to program
468 *
469 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
470 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
471 * the old ide/pci driver.
472 *
473 * LOCKING:
474 * None (inherited from caller).
475 */
476
477static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
478{
479 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
480 int speed = adev->dma_mode - XFER_MW_DMA_0;
481 int port = 0x40;
482 u32 t1;
483 u32 reg54;
484
485 /* bits 4- cycle time 8 - cvs time */
Alan Cox2e413f52007-03-07 16:54:24 +0000486 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
487 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400488
489 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
490 pci_read_config_dword(pdev, 0x54, &reg54);
491 if (reg54 & 0x40000000)
492 port = 0x70;
493 port += (8 * ap->port_no) + (4 * adev->devno);
494
495 pci_read_config_dword(pdev, port, &t1);
496
497 if (adev->dma_mode < XFER_UDMA_0) {
498 t1 &= ~0x00000004;
499 /* FIXME: need data sheet to add MWDMA here. Also lacking on
500 ide/pci driver */
501 } else {
502 speed = adev->dma_mode - XFER_UDMA_0;
503 /* if & 8 no UDMA133 - need info for ... */
504 t1 &= ~0x00000FF0;
505 t1 |= 0x00000004;
506 if (t1 & 0x08)
507 t1 |= timing_u133[speed];
508 else
509 t1 |= timing_u100[speed];
510 }
511 pci_write_config_dword(pdev, port, t1);
512}
513
514static struct scsi_host_template sis_sht = {
515 .module = THIS_MODULE,
516 .name = DRV_NAME,
517 .ioctl = ata_scsi_ioctl,
518 .queuecommand = ata_scsi_queuecmd,
519 .can_queue = ATA_DEF_QUEUE,
520 .this_id = ATA_SHT_THIS_ID,
521 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400522 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
523 .emulated = ATA_SHT_EMULATED,
524 .use_clustering = ATA_SHT_USE_CLUSTERING,
525 .proc_name = DRV_NAME,
526 .dma_boundary = ATA_DMA_BOUNDARY,
527 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900528 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400529 .bios_param = ata_std_bios_param,
530};
531
532static const struct ata_port_operations sis_133_ops = {
533 .port_disable = ata_port_disable,
534 .set_piomode = sis_133_set_piomode,
535 .set_dmamode = sis_133_set_dmamode,
536 .mode_filter = ata_pci_default_filter,
537
538 .tf_load = ata_tf_load,
539 .tf_read = ata_tf_read,
540 .check_status = ata_check_status,
541 .exec_command = ata_exec_command,
542 .dev_select = ata_std_dev_select,
543
544 .freeze = ata_bmdma_freeze,
545 .thaw = ata_bmdma_thaw,
Alan Cox2e413f52007-03-07 16:54:24 +0000546 .error_handler = sis_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400547 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Cox2e413f52007-03-07 16:54:24 +0000548 .cable_detect = sis_133_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400549
550 .bmdma_setup = ata_bmdma_setup,
551 .bmdma_start = ata_bmdma_start,
552 .bmdma_stop = ata_bmdma_stop,
553 .bmdma_status = ata_bmdma_status,
554 .qc_prep = ata_qc_prep,
555 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900556 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400557
Jeff Garzik669a5db2006-08-29 18:12:40 -0400558 .irq_handler = ata_interrupt,
559 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900560 .irq_on = ata_irq_on,
561 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400562
563 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400564};
565
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200566static const struct ata_port_operations sis_133_for_sata_ops = {
567 .port_disable = ata_port_disable,
568 .set_piomode = sis_133_set_piomode,
569 .set_dmamode = sis_133_set_dmamode,
570 .mode_filter = ata_pci_default_filter,
571
572 .tf_load = ata_tf_load,
573 .tf_read = ata_tf_read,
574 .check_status = ata_check_status,
575 .exec_command = ata_exec_command,
576 .dev_select = ata_std_dev_select,
577
578 .freeze = ata_bmdma_freeze,
579 .thaw = ata_bmdma_thaw,
580 .error_handler = ata_bmdma_error_handler,
581 .post_internal_cmd = ata_bmdma_post_internal_cmd,
582 .cable_detect = sis_133_cable_detect,
583
584 .bmdma_setup = ata_bmdma_setup,
585 .bmdma_start = ata_bmdma_start,
586 .bmdma_stop = ata_bmdma_stop,
587 .bmdma_status = ata_bmdma_status,
588 .qc_prep = ata_qc_prep,
589 .qc_issue = ata_qc_issue_prot,
590 .data_xfer = ata_data_xfer,
591
592 .irq_handler = ata_interrupt,
593 .irq_clear = ata_bmdma_irq_clear,
594 .irq_on = ata_irq_on,
595 .irq_ack = ata_irq_ack,
596
597 .port_start = ata_port_start,
598};
599
Jeff Garzik669a5db2006-08-29 18:12:40 -0400600static const struct ata_port_operations sis_133_early_ops = {
601 .port_disable = ata_port_disable,
602 .set_piomode = sis_100_set_piomode,
603 .set_dmamode = sis_133_early_set_dmamode,
604 .mode_filter = ata_pci_default_filter,
605
606 .tf_load = ata_tf_load,
607 .tf_read = ata_tf_read,
608 .check_status = ata_check_status,
609 .exec_command = ata_exec_command,
610 .dev_select = ata_std_dev_select,
611
612 .freeze = ata_bmdma_freeze,
613 .thaw = ata_bmdma_thaw,
Alan Cox2e413f52007-03-07 16:54:24 +0000614 .error_handler = sis_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400615 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Cox2e413f52007-03-07 16:54:24 +0000616 .cable_detect = sis_66_cable_detect,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400617
Jeff Garzik669a5db2006-08-29 18:12:40 -0400618 .bmdma_setup = ata_bmdma_setup,
619 .bmdma_start = ata_bmdma_start,
620 .bmdma_stop = ata_bmdma_stop,
621 .bmdma_status = ata_bmdma_status,
622 .qc_prep = ata_qc_prep,
623 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900624 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400625
Jeff Garzik669a5db2006-08-29 18:12:40 -0400626 .irq_handler = ata_interrupt,
627 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900628 .irq_on = ata_irq_on,
629 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400630
631 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400632};
633
634static const struct ata_port_operations sis_100_ops = {
635 .port_disable = ata_port_disable,
636 .set_piomode = sis_100_set_piomode,
637 .set_dmamode = sis_100_set_dmamode,
638 .mode_filter = ata_pci_default_filter,
639
640 .tf_load = ata_tf_load,
641 .tf_read = ata_tf_read,
642 .check_status = ata_check_status,
643 .exec_command = ata_exec_command,
644 .dev_select = ata_std_dev_select,
645
646 .freeze = ata_bmdma_freeze,
647 .thaw = ata_bmdma_thaw,
Alan Cox2e413f52007-03-07 16:54:24 +0000648 .error_handler = sis_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400649 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Cox2e413f52007-03-07 16:54:24 +0000650 .cable_detect = sis_66_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400651
652 .bmdma_setup = ata_bmdma_setup,
653 .bmdma_start = ata_bmdma_start,
654 .bmdma_stop = ata_bmdma_stop,
655 .bmdma_status = ata_bmdma_status,
656 .qc_prep = ata_qc_prep,
657 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900658 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400659
Jeff Garzik669a5db2006-08-29 18:12:40 -0400660 .irq_handler = ata_interrupt,
661 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900662 .irq_on = ata_irq_on,
663 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400664
665 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400666};
667
668static const struct ata_port_operations sis_66_ops = {
669 .port_disable = ata_port_disable,
670 .set_piomode = sis_old_set_piomode,
671 .set_dmamode = sis_66_set_dmamode,
672 .mode_filter = ata_pci_default_filter,
673
674 .tf_load = ata_tf_load,
675 .tf_read = ata_tf_read,
676 .check_status = ata_check_status,
677 .exec_command = ata_exec_command,
678 .dev_select = ata_std_dev_select,
Alan Cox2e413f52007-03-07 16:54:24 +0000679 .cable_detect = sis_66_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400680
681 .freeze = ata_bmdma_freeze,
682 .thaw = ata_bmdma_thaw,
Alan Cox2e413f52007-03-07 16:54:24 +0000683 .error_handler = sis_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400684 .post_internal_cmd = ata_bmdma_post_internal_cmd,
685
686 .bmdma_setup = ata_bmdma_setup,
687 .bmdma_start = ata_bmdma_start,
688 .bmdma_stop = ata_bmdma_stop,
689 .bmdma_status = ata_bmdma_status,
690 .qc_prep = ata_qc_prep,
691 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900692 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400693
Jeff Garzik669a5db2006-08-29 18:12:40 -0400694 .irq_handler = ata_interrupt,
695 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900696 .irq_on = ata_irq_on,
697 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400698
699 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400700};
701
702static const struct ata_port_operations sis_old_ops = {
703 .port_disable = ata_port_disable,
704 .set_piomode = sis_old_set_piomode,
705 .set_dmamode = sis_old_set_dmamode,
706 .mode_filter = ata_pci_default_filter,
707
708 .tf_load = ata_tf_load,
709 .tf_read = ata_tf_read,
710 .check_status = ata_check_status,
711 .exec_command = ata_exec_command,
712 .dev_select = ata_std_dev_select,
713
714 .freeze = ata_bmdma_freeze,
715 .thaw = ata_bmdma_thaw,
Alan Cox2e413f52007-03-07 16:54:24 +0000716 .error_handler = sis_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400717 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Cox2e413f52007-03-07 16:54:24 +0000718 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400719
720 .bmdma_setup = ata_bmdma_setup,
721 .bmdma_start = ata_bmdma_start,
722 .bmdma_stop = ata_bmdma_stop,
723 .bmdma_status = ata_bmdma_status,
724 .qc_prep = ata_qc_prep,
725 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900726 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400727
Jeff Garzik669a5db2006-08-29 18:12:40 -0400728 .irq_handler = ata_interrupt,
729 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900730 .irq_on = ata_irq_on,
731 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400732
733 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400734};
735
Tejun Heo1626aeb2007-05-04 12:43:58 +0200736static const struct ata_port_info sis_info = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400737 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400738 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400739 .pio_mask = 0x1f, /* pio0-4 */
740 .mwdma_mask = 0x07,
741 .udma_mask = 0,
742 .port_ops = &sis_old_ops,
743};
Tejun Heo1626aeb2007-05-04 12:43:58 +0200744static const struct ata_port_info sis_info33 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400745 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400746 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400747 .pio_mask = 0x1f, /* pio0-4 */
748 .mwdma_mask = 0x07,
749 .udma_mask = ATA_UDMA2, /* UDMA 33 */
750 .port_ops = &sis_old_ops,
751};
Tejun Heo1626aeb2007-05-04 12:43:58 +0200752static const struct ata_port_info sis_info66 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400753 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400754 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400755 .pio_mask = 0x1f, /* pio0-4 */
756 .udma_mask = ATA_UDMA4, /* UDMA 66 */
757 .port_ops = &sis_66_ops,
758};
Tejun Heo1626aeb2007-05-04 12:43:58 +0200759static const struct ata_port_info sis_info100 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400760 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400761 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400762 .pio_mask = 0x1f, /* pio0-4 */
763 .udma_mask = ATA_UDMA5,
764 .port_ops = &sis_100_ops,
765};
Tejun Heo1626aeb2007-05-04 12:43:58 +0200766static const struct ata_port_info sis_info100_early = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400767 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400768 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400769 .udma_mask = ATA_UDMA5,
770 .pio_mask = 0x1f, /* pio0-4 */
771 .port_ops = &sis_66_ops,
772};
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200773static const struct ata_port_info sis_info133 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400774 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400775 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400776 .pio_mask = 0x1f, /* pio0-4 */
777 .udma_mask = ATA_UDMA6,
778 .port_ops = &sis_133_ops,
779};
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200780const struct ata_port_info sis_info133_for_sata = {
781 .sht = &sis_sht,
782 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
783 .pio_mask = 0x1f, /* pio0-4 */
784 .udma_mask = ATA_UDMA6,
785 .port_ops = &sis_133_for_sata_ops,
786};
Tejun Heo1626aeb2007-05-04 12:43:58 +0200787static const struct ata_port_info sis_info133_early = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400788 .sht = &sis_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400789 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400790 .pio_mask = 0x1f, /* pio0-4 */
791 .udma_mask = ATA_UDMA6,
792 .port_ops = &sis_133_early_ops,
793};
794
Alan9b14dec2007-01-08 16:11:07 +0000795/* Privately shared with the SiS180 SATA driver, not for use elsewhere */
Uwe Kozioleka3cabb22007-06-14 23:40:43 +0200796EXPORT_SYMBOL_GPL(sis_info133_for_sata);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400797
798static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
799{
800 u16 regw;
801 u8 reg;
802
803 if (sis->info == &sis_info133) {
804 pci_read_config_word(pdev, 0x50, &regw);
805 if (regw & 0x08)
806 pci_write_config_word(pdev, 0x50, regw & ~0x08);
807 pci_read_config_word(pdev, 0x52, &regw);
808 if (regw & 0x08)
809 pci_write_config_word(pdev, 0x52, regw & ~0x08);
810 return;
811 }
812
813 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
814 /* Fix up latency */
815 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
816 /* Set compatibility bit */
817 pci_read_config_byte(pdev, 0x49, &reg);
818 if (!(reg & 0x01))
819 pci_write_config_byte(pdev, 0x49, reg | 0x01);
820 return;
821 }
822
823 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
824 /* Fix up latency */
825 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
826 /* Set compatibility bit */
827 pci_read_config_byte(pdev, 0x52, &reg);
828 if (!(reg & 0x04))
829 pci_write_config_byte(pdev, 0x52, reg | 0x04);
830 return;
831 }
832
833 if (sis->info == &sis_info33) {
834 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
835 if (( reg & 0x0F ) != 0x00)
836 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
837 /* Fall through to ATA16 fixup below */
838 }
839
840 if (sis->info == &sis_info || sis->info == &sis_info33) {
841 /* force per drive recovery and active timings
842 needed on ATA_33 and below chips */
843 pci_read_config_byte(pdev, 0x52, &reg);
844 if (!(reg & 0x08))
845 pci_write_config_byte(pdev, 0x52, reg|0x08);
846 return;
847 }
848
849 BUG();
850}
851
852/**
853 * sis_init_one - Register SiS ATA PCI device with kernel services
854 * @pdev: PCI device to register
855 * @ent: Entry in sis_pci_tbl matching with @pdev
856 *
857 * Called from kernel PCI layer. We probe for combined mode (sigh),
858 * and then hand over control to libata, for it to do the rest.
859 *
860 * LOCKING:
861 * Inherited from PCI layer (may sleep).
862 *
863 * RETURNS:
864 * Zero on success, or -ERRNO value.
865 */
866
867static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
868{
869 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +0200870 struct ata_port_info port;
871 const struct ata_port_info *ppi[] = { &port, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400872 struct pci_dev *host = NULL;
873 struct sis_chipset *chipset = NULL;
Alan Coxf3769e92007-04-19 11:09:52 +0100874 struct sis_chipset *sets;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400875
876 static struct sis_chipset sis_chipsets[] = {
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500877
Alan Coxaf323a22006-09-12 17:15:12 +0100878 { 0x0968, &sis_info133 },
879 { 0x0966, &sis_info133 },
880 { 0x0965, &sis_info133 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400881 { 0x0745, &sis_info100 },
882 { 0x0735, &sis_info100 },
883 { 0x0733, &sis_info100 },
884 { 0x0635, &sis_info100 },
885 { 0x0633, &sis_info100 },
886
887 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
888 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
889
890 { 0x0640, &sis_info66 },
891 { 0x0630, &sis_info66 },
892 { 0x0620, &sis_info66 },
893 { 0x0540, &sis_info66 },
894 { 0x0530, &sis_info66 },
895
896 { 0x5600, &sis_info33 },
897 { 0x5598, &sis_info33 },
898 { 0x5597, &sis_info33 },
899 { 0x5591, &sis_info33 },
900 { 0x5582, &sis_info33 },
901 { 0x5581, &sis_info33 },
902
903 { 0x5596, &sis_info },
904 { 0x5571, &sis_info },
905 { 0x5517, &sis_info },
906 { 0x5511, &sis_info },
907
908 {0}
909 };
910 static struct sis_chipset sis133_early = {
911 0x0, &sis_info133_early
912 };
913 static struct sis_chipset sis133 = {
914 0x0, &sis_info133
915 };
916 static struct sis_chipset sis100_early = {
917 0x0, &sis_info100_early
918 };
919 static struct sis_chipset sis100 = {
920 0x0, &sis_info100
921 };
922
923 if (!printed_version++)
924 dev_printk(KERN_DEBUG, &pdev->dev,
925 "version " DRV_VERSION "\n");
926
927 /* We have to find the bridge first */
928
Alan Coxf3769e92007-04-19 11:09:52 +0100929 for (sets = &sis_chipsets[0]; sets->device; sets++) {
930 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400931 if (host != NULL) {
Alan Coxf3769e92007-04-19 11:09:52 +0100932 chipset = sets; /* Match found */
933 if (sets->device == 0x630) { /* SIS630 */
Auke Kok44c10132007-06-08 15:46:36 -0700934 if (host->revision >= 0x30) /* 630 ET */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400935 chipset = &sis100_early;
936 }
937 break;
938 }
939 }
940
941 /* Look for concealed bridges */
Alan Coxf3769e92007-04-19 11:09:52 +0100942 if (chipset == NULL) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400943 /* Second check */
944 u32 idemisc;
945 u16 trueid;
946
947 /* Disable ID masking and register remapping then
948 see what the real ID is */
949
950 pci_read_config_dword(pdev, 0x54, &idemisc);
951 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
952 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
953 pci_write_config_dword(pdev, 0x54, idemisc);
954
955 switch(trueid) {
956 case 0x5518: /* SIS 962/963 */
957 chipset = &sis133;
958 if ((idemisc & 0x40000000) == 0) {
959 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
960 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
961 }
962 break;
963 case 0x0180: /* SIS 965/965L */
964 chipset = &sis133;
965 break;
966 case 0x1180: /* SIS 966/966L */
967 chipset = &sis133;
968 break;
969 }
970 }
971
972 /* Further check */
973 if (chipset == NULL) {
974 struct pci_dev *lpc_bridge;
975 u16 trueid;
976 u8 prefctl;
977 u8 idecfg;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400978
979 /* Try the second unmasking technique */
980 pci_read_config_byte(pdev, 0x4a, &idecfg);
981 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
982 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
983 pci_write_config_byte(pdev, 0x4a, idecfg);
984
985 switch(trueid) {
986 case 0x5517:
987 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
988 if (lpc_bridge == NULL)
989 break;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400990 pci_read_config_byte(pdev, 0x49, &prefctl);
991 pci_dev_put(lpc_bridge);
992
Auke Kok44c10132007-06-08 15:46:36 -0700993 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400994 chipset = &sis133_early;
995 break;
996 }
997 chipset = &sis100;
998 break;
999 }
1000 }
1001 pci_dev_put(host);
1002
1003 /* No chipset info, no support */
1004 if (chipset == NULL)
1005 return -ENODEV;
1006
Tejun Heo1626aeb2007-05-04 12:43:58 +02001007 port = *chipset->info;
1008 port.private_data = chipset;
Jeff Garzik669a5db2006-08-29 18:12:40 -04001009
1010 sis_fixup(pdev, chipset);
1011
Tejun Heo1626aeb2007-05-04 12:43:58 +02001012 return ata_pci_init_one(pdev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001013}
1014
1015static const struct pci_device_id sis_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001016 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
1017 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
Uwe Kozioleka3cabb22007-06-14 23:40:43 +02001018 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001019
Jeff Garzik669a5db2006-08-29 18:12:40 -04001020 { }
1021};
1022
1023static struct pci_driver sis_pci_driver = {
1024 .name = DRV_NAME,
1025 .id_table = sis_pci_tbl,
1026 .probe = sis_init_one,
1027 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +09001028#ifdef CONFIG_PM
Alan62d64ae2006-11-27 16:27:20 +00001029 .suspend = ata_pci_device_suspend,
1030 .resume = ata_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +09001031#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -04001032};
1033
1034static int __init sis_init(void)
1035{
1036 return pci_register_driver(&sis_pci_driver);
1037}
1038
1039static void __exit sis_exit(void)
1040{
1041 pci_unregister_driver(&sis_pci_driver);
1042}
1043
Jeff Garzik669a5db2006-08-29 18:12:40 -04001044module_init(sis_init);
1045module_exit(sis_exit);
1046
1047MODULE_AUTHOR("Alan Cox");
1048MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1049MODULE_LICENSE("GPL");
1050MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1051MODULE_VERSION(DRV_VERSION);
1052