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Brett Russ20f733e2005-09-01 18:26:17 -04001/*
2 * sata_mv.c - Marvell SATA support
3 *
Mark Lord40f21b12009-03-10 18:51:04 -04004 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
Jeff Garzik8b260242005-11-12 12:32:50 -05005 * Copyright 2005: EMC Corporation, all rights reserved.
Jeff Garzike2b1be52005-11-18 14:04:23 -05006 * Copyright 2005 Red Hat, Inc. All rights reserved.
Brett Russ20f733e2005-09-01 18:26:17 -04007 *
Mark Lord40f21b12009-03-10 18:51:04 -04008 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
Brett Russ20f733e2005-09-01 18:26:17 -040011 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
Jeff Garzik4a05e202007-05-24 23:40:15 -040028/*
Mark Lord85afb932008-04-19 14:54:41 -040029 * sata_mv TODO list:
30 *
Mark Lord85afb932008-04-19 14:54:41 -040031 * --> Develop a low-power-consumption strategy, and implement it.
32 *
Mark Lord2b748a02009-03-10 22:01:17 -040033 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
Mark Lord85afb932008-04-19 14:54:41 -040034 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
Jeff Garzik4a05e202007-05-24 23:40:15 -040042
Mark Lord65ad7fe2009-04-06 15:24:14 -040043/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
Brett Russ20f733e2005-09-01 18:26:17 -040052#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
Andrew Morton8d8b6002008-02-04 23:43:44 -080059#include <linux/dmapool.h>
Brett Russ20f733e2005-09-01 18:26:17 -040060#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050061#include <linux/device.h>
Saeed Bisharac77a2f42009-12-06 18:26:18 +020062#include <linux/clk.h>
Saeed Bisharaf351b2d2008-02-01 18:08:03 -050063#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
Lennert Buytenhek15a32632008-03-27 14:51:39 -040065#include <linux/mbus.h>
Mark Lordc46938c2008-05-02 14:02:28 -040066#include <linux/bitops.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090067#include <linux/gfp.h>
Brett Russ20f733e2005-09-01 18:26:17 -040068#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050069#include <scsi/scsi_cmnd.h>
Jeff Garzik6c087722007-10-12 00:16:23 -040070#include <scsi/scsi_device.h>
Brett Russ20f733e2005-09-01 18:26:17 -040071#include <linux/libata.h>
Brett Russ20f733e2005-09-01 18:26:17 -040072
73#define DRV_NAME "sata_mv"
Mark Lordcae5a292009-04-06 16:43:45 -040074#define DRV_VERSION "1.28"
Brett Russ20f733e2005-09-01 18:26:17 -040075
Mark Lord40f21b12009-03-10 18:51:04 -040076/*
77 * module options
78 */
79
80static int msi;
81#ifdef CONFIG_PCI
82module_param(msi, int, S_IRUGO);
83MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84#endif
85
Mark Lord2b748a02009-03-10 22:01:17 -040086static int irq_coalescing_io_count;
87module_param(irq_coalescing_io_count, int, S_IRUGO);
88MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91static int irq_coalescing_usecs;
92module_param(irq_coalescing_usecs, int, S_IRUGO);
93MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
Brett Russ20f733e2005-09-01 18:26:17 -040096enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
Mark Lord2b748a02009-03-10 22:01:17 -0400105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
Brett Russ20f733e2005-09-01 18:26:17 -0400110 MV_PCI_REG_BASE = 0,
Mark Lord615ab952006-05-19 16:24:56 -0400111
Mark Lord2b748a02009-03-10 22:01:17 -0400112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
Mark Lordcae5a292009-04-06 16:43:45 -0400119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
Mark Lord2b748a02009-03-10 22:01:17 -0400121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
Mark Lordcae5a292009-04-06 16:43:45 -0400123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
Mark Lord2b748a02009-03-10 22:01:17 -0400125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
Mark Lordcae5a292009-04-06 16:43:45 -0400129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
Mark Lord2b748a02009-03-10 22:01:17 -0400131
Mark Lordcae5a292009-04-06 16:43:45 -0400132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
Brett Russ20f733e2005-09-01 18:26:17 -0400136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
Brett Russ31961942005-09-30 01:36:00 -0400142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
Brett Russ31961942005-09-30 01:36:00 -0400147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
Mark Lordda2fa9b2008-01-26 18:32:45 -0500151 MV_MAX_SG_CT = 256,
Brett Russ31961942005-09-30 01:36:00 -0400152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
Brett Russ31961942005-09-30 01:36:00 -0400153
Mark Lord352fab72008-04-19 14:43:42 -0400154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
Brett Russ20f733e2005-09-01 18:26:17 -0400155 MV_PORT_HC_SHIFT = 2,
Mark Lord352fab72008-04-19 14:43:42 -0400156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
Brett Russ20f733e2005-09-01 18:26:17 -0400159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100162
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
Mark Lordad3aef52008-05-14 09:21:43 -0400164
Mark Lord91b1a842009-01-30 18:46:39 -0500165 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
Brett Russ20f733e2005-09-01 18:26:17 -0400166
Mark Lord40f21b12009-03-10 18:51:04 -0400167 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
168 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
Mark Lord91b1a842009-01-30 18:46:39 -0500169
170 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
Mark Lordad3aef52008-05-14 09:21:43 -0400171
Brett Russ31961942005-09-30 01:36:00 -0400172 CRQB_FLAG_READ = (1 << 0),
173 CRQB_TAG_SHIFT = 1,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400174 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
Mark Lorde12bef52008-03-31 19:33:56 -0400175 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400176 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
Brett Russ31961942005-09-30 01:36:00 -0400177 CRQB_CMD_ADDR_SHIFT = 8,
178 CRQB_CMD_CS = (0x2 << 11),
179 CRQB_CMD_LAST = (1 << 15),
180
181 CRPB_FLAG_STATUS_SHIFT = 8,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400182 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
183 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
Brett Russ31961942005-09-30 01:36:00 -0400184
185 EPRD_FLAG_END_OF_TBL = (1 << 31),
186
Brett Russ20f733e2005-09-01 18:26:17 -0400187 /* PCI interface registers */
188
Mark Lordcae5a292009-04-06 16:43:45 -0400189 MV_PCI_COMMAND = 0xc00,
190 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
191 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
Brett Russ31961942005-09-30 01:36:00 -0400192
Mark Lordcae5a292009-04-06 16:43:45 -0400193 PCI_MAIN_CMD_STS = 0xd30,
Brett Russ20f733e2005-09-01 18:26:17 -0400194 STOP_PCI_MASTER = (1 << 2),
195 PCI_MASTER_EMPTY = (1 << 3),
196 GLOB_SFT_RST = (1 << 4),
197
Mark Lordcae5a292009-04-06 16:43:45 -0400198 MV_PCI_MODE = 0xd00,
Mark Lord8e7decd2008-05-02 02:07:51 -0400199 MV_PCI_MODE_MASK = 0x30,
200
Jeff Garzik522479f2005-11-12 22:14:02 -0500201 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
202 MV_PCI_DISC_TIMER = 0xd04,
203 MV_PCI_MSI_TRIGGER = 0xc38,
204 MV_PCI_SERR_MASK = 0xc28,
Mark Lordcae5a292009-04-06 16:43:45 -0400205 MV_PCI_XBAR_TMOUT = 0x1d04,
Jeff Garzik522479f2005-11-12 22:14:02 -0500206 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
207 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
208 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
209 MV_PCI_ERR_COMMAND = 0x1d50,
210
Mark Lordcae5a292009-04-06 16:43:45 -0400211 PCI_IRQ_CAUSE = 0x1d58,
212 PCI_IRQ_MASK = 0x1d5c,
Brett Russ20f733e2005-09-01 18:26:17 -0400213 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
214
Mark Lordcae5a292009-04-06 16:43:45 -0400215 PCIE_IRQ_CAUSE = 0x1900,
216 PCIE_IRQ_MASK = 0x1910,
Mark Lord646a4da2008-01-26 18:30:37 -0500217 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
Mark Lord02a121d2007-12-01 13:07:22 -0500218
Mark Lord7368f912008-04-25 11:24:24 -0400219 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
Mark Lordcae5a292009-04-06 16:43:45 -0400220 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
221 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
222 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
223 SOC_HC_MAIN_IRQ_MASK = 0x20024,
Mark Lord40f21b12009-03-10 18:51:04 -0400224 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
225 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
Brett Russ20f733e2005-09-01 18:26:17 -0400226 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
227 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
Mark Lord2b748a02009-03-10 22:01:17 -0400228 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
229 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
Brett Russ20f733e2005-09-01 18:26:17 -0400230 PCI_ERR = (1 << 18),
Mark Lord40f21b12009-03-10 18:51:04 -0400231 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
232 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
233 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
234 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
235 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400236 GPIO_INT = (1 << 22),
237 SELF_INT = (1 << 23),
238 TWSI_INT = (1 << 24),
239 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
Jeff Garzikfb621e22007-02-25 04:19:45 -0500240 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
Mark Lorde12bef52008-03-31 19:33:56 -0400241 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
Brett Russ20f733e2005-09-01 18:26:17 -0400242
243 /* SATAHC registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400244 HC_CFG = 0x00,
Brett Russ20f733e2005-09-01 18:26:17 -0400245
Mark Lordcae5a292009-04-06 16:43:45 -0400246 HC_IRQ_CAUSE = 0x14,
Mark Lord352fab72008-04-19 14:43:42 -0400247 DMA_IRQ = (1 << 0), /* shift by port # */
248 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
Brett Russ20f733e2005-09-01 18:26:17 -0400249 DEV_IRQ = (1 << 8), /* shift by port # */
250
Mark Lord2b748a02009-03-10 22:01:17 -0400251 /*
252 * Per-HC (Host-Controller) interrupt coalescing feature.
253 * This is present on all chip generations.
254 *
255 * Coalescing defers the interrupt until either the IO_THRESHOLD
256 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
257 */
Mark Lordcae5a292009-04-06 16:43:45 -0400258 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
259 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
Mark Lord2b748a02009-03-10 22:01:17 -0400260
Mark Lordcae5a292009-04-06 16:43:45 -0400261 SOC_LED_CTRL = 0x2c,
Mark Lord000b3442009-03-15 11:33:19 -0400262 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
263 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
264 /* with dev activity LED */
265
Brett Russ20f733e2005-09-01 18:26:17 -0400266 /* Shadow block registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400267 SHD_BLK = 0x100,
268 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
Brett Russ20f733e2005-09-01 18:26:17 -0400269
270 /* SATA registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400271 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
272 SATA_ACTIVE = 0x350,
273 FIS_IRQ_CAUSE = 0x364,
274 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
Mark Lord17c5aab2008-04-16 14:56:51 -0400275
Mark Lordcae5a292009-04-06 16:43:45 -0400276 LTMODE = 0x30c, /* requires read-after-write */
Mark Lord17c5aab2008-04-16 14:56:51 -0400277 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
278
Mark Lordcae5a292009-04-06 16:43:45 -0400279 PHY_MODE2 = 0x330,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500280 PHY_MODE3 = 0x310,
Mark Lordcae5a292009-04-06 16:43:45 -0400281
282 PHY_MODE4 = 0x314, /* requires read-after-write */
Mark Lordba069e32008-05-31 16:46:34 -0400283 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
284 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
285 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
286 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
287
Mark Lordcae5a292009-04-06 16:43:45 -0400288 SATA_IFCTL = 0x344,
289 SATA_TESTCTL = 0x348,
290 SATA_IFSTAT = 0x34c,
291 VENDOR_UNIQUE_FIS = 0x35c,
Mark Lord17c5aab2008-04-16 14:56:51 -0400292
Mark Lordcae5a292009-04-06 16:43:45 -0400293 FISCFG = 0x360,
Mark Lord8e7decd2008-05-02 02:07:51 -0400294 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
295 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
Mark Lord17c5aab2008-04-16 14:56:51 -0400296
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200297 PHY_MODE9_GEN2 = 0x398,
298 PHY_MODE9_GEN1 = 0x39c,
299 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
300
Jeff Garzikc9d39132005-11-13 17:47:51 -0500301 MV5_PHY_MODE = 0x74,
Mark Lordcae5a292009-04-06 16:43:45 -0400302 MV5_LTMODE = 0x30,
303 MV5_PHY_CTL = 0x0C,
304 SATA_IFCFG = 0x050,
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500305
306 MV_M2_PREAMP_MASK = 0x7e0,
Brett Russ20f733e2005-09-01 18:26:17 -0400307
308 /* Port registers */
Mark Lordcae5a292009-04-06 16:43:45 -0400309 EDMA_CFG = 0,
Mark Lord0c589122008-01-26 18:31:16 -0500310 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
311 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
312 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
313 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
314 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
Mark Lorde12bef52008-03-31 19:33:56 -0400315 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
316 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
Brett Russ20f733e2005-09-01 18:26:17 -0400317
Mark Lordcae5a292009-04-06 16:43:45 -0400318 EDMA_ERR_IRQ_CAUSE = 0x8,
319 EDMA_ERR_IRQ_MASK = 0xc,
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400320 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
321 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
322 EDMA_ERR_DEV = (1 << 2), /* device error */
323 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
324 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
325 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400326 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
327 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400328 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400329 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400330 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
331 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
332 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
333 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
Mark Lord646a4da2008-01-26 18:30:37 -0500334
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400335 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500336 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
337 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
338 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
339 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
340
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400341 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500342
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400343 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500344 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
345 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
346 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
347 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
348 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
349
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400350 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
Mark Lord646a4da2008-01-26 18:30:37 -0500351
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400352 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400353 EDMA_ERR_OVERRUN_5 = (1 << 5),
354 EDMA_ERR_UNDERRUN_5 = (1 << 6),
Mark Lord646a4da2008-01-26 18:30:37 -0500355
356 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
357 EDMA_ERR_LNK_CTRL_RX_1 |
358 EDMA_ERR_LNK_CTRL_RX_3 |
Mark Lord85afb932008-04-19 14:54:41 -0400359 EDMA_ERR_LNK_CTRL_TX,
Mark Lord646a4da2008-01-26 18:30:37 -0500360
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400361 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
362 EDMA_ERR_PRD_PAR |
363 EDMA_ERR_DEV_DCON |
364 EDMA_ERR_DEV_CON |
365 EDMA_ERR_SERR |
366 EDMA_ERR_SELF_DIS |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400367 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400368 EDMA_ERR_CRPB_PAR |
369 EDMA_ERR_INTRL_PAR |
370 EDMA_ERR_IORDY |
371 EDMA_ERR_LNK_CTRL_RX_2 |
372 EDMA_ERR_LNK_DATA_RX |
373 EDMA_ERR_LNK_DATA_TX |
374 EDMA_ERR_TRANS_PROTO,
Mark Lorde12bef52008-03-31 19:33:56 -0400375
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400376 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
377 EDMA_ERR_PRD_PAR |
378 EDMA_ERR_DEV_DCON |
379 EDMA_ERR_DEV_CON |
380 EDMA_ERR_OVERRUN_5 |
381 EDMA_ERR_UNDERRUN_5 |
382 EDMA_ERR_SELF_DIS_5 |
Jeff Garzik6c1153e2007-07-13 15:20:15 -0400383 EDMA_ERR_CRQB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400384 EDMA_ERR_CRPB_PAR |
385 EDMA_ERR_INTRL_PAR |
386 EDMA_ERR_IORDY,
Brett Russ20f733e2005-09-01 18:26:17 -0400387
Mark Lordcae5a292009-04-06 16:43:45 -0400388 EDMA_REQ_Q_BASE_HI = 0x10,
389 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400390
Mark Lordcae5a292009-04-06 16:43:45 -0400391 EDMA_REQ_Q_OUT_PTR = 0x18,
Brett Russ31961942005-09-30 01:36:00 -0400392 EDMA_REQ_Q_PTR_SHIFT = 5,
393
Mark Lordcae5a292009-04-06 16:43:45 -0400394 EDMA_RSP_Q_BASE_HI = 0x1c,
395 EDMA_RSP_Q_IN_PTR = 0x20,
396 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
Brett Russ31961942005-09-30 01:36:00 -0400397 EDMA_RSP_Q_PTR_SHIFT = 3,
398
Mark Lordcae5a292009-04-06 16:43:45 -0400399 EDMA_CMD = 0x28, /* EDMA command register */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400400 EDMA_EN = (1 << 0), /* enable EDMA */
401 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
Mark Lord8e7decd2008-05-02 02:07:51 -0400402 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
Brett Russ20f733e2005-09-01 18:26:17 -0400403
Mark Lordcae5a292009-04-06 16:43:45 -0400404 EDMA_STATUS = 0x30, /* EDMA engine status */
Mark Lord8e7decd2008-05-02 02:07:51 -0400405 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
406 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
407
Mark Lordcae5a292009-04-06 16:43:45 -0400408 EDMA_IORDY_TMOUT = 0x34,
409 EDMA_ARB_CFG = 0x38,
Mark Lord8e7decd2008-05-02 02:07:51 -0400410
Mark Lordcae5a292009-04-06 16:43:45 -0400411 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
412 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
Mark Lordda142652009-01-30 18:51:54 -0500413
Mark Lordcae5a292009-04-06 16:43:45 -0400414 BMDMA_CMD = 0x224, /* bmdma command register */
415 BMDMA_STATUS = 0x228, /* bmdma status register */
416 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
417 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
Mark Lordda142652009-01-30 18:51:54 -0500418
Brett Russ31961942005-09-30 01:36:00 -0400419 /* Host private flags (hp_flags) */
420 MV_HP_FLAG_MSI = (1 << 0),
Jeff Garzik47c2b672005-11-12 21:13:17 -0500421 MV_HP_ERRATA_50XXB0 = (1 << 1),
422 MV_HP_ERRATA_50XXB2 = (1 << 2),
423 MV_HP_ERRATA_60X1B2 = (1 << 3),
424 MV_HP_ERRATA_60X1C0 = (1 << 4),
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400425 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
426 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
427 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
Mark Lord02a121d2007-12-01 13:07:22 -0500428 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
Mark Lord616d4a92008-05-02 02:08:32 -0400429 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
Mark Lord1f398472008-05-27 17:54:48 -0400430 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
Mark Lord000b3442009-03-15 11:33:19 -0400431 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
Brett Russ20f733e2005-09-01 18:26:17 -0400432
Brett Russ31961942005-09-30 01:36:00 -0400433 /* Port private flags (pp_flags) */
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400434 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
Mark Lord72109162008-01-26 18:31:33 -0500435 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
Mark Lord00f42ea2008-05-02 02:11:45 -0400436 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
Mark Lord29d187b2008-05-02 02:15:37 -0400437 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
Mark Lordd16ab3f2009-02-25 15:17:43 -0500438 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
Brett Russ31961942005-09-30 01:36:00 -0400439};
440
Jeff Garzikee9ccdf2007-07-12 15:51:22 -0400441#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
442#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
Jeff Garzike4e7b892006-01-31 12:18:41 -0500443#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
Mark Lord8e7decd2008-05-02 02:07:51 -0400444#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
Mark Lord1f398472008-05-27 17:54:48 -0400445#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500446
Lennert Buytenhek15a32632008-03-27 14:51:39 -0400447#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
448#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
449
Jeff Garzik095fec82005-11-12 09:50:49 -0500450enum {
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400451 /* DMA boundary 0xffff is required by the s/g splitting
452 * we need on /length/ in mv_fill-sg().
453 */
454 MV_DMA_BOUNDARY = 0xffffU,
Jeff Garzik095fec82005-11-12 09:50:49 -0500455
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400456 /* mask of register bits containing lower 32 bits
457 * of EDMA request queue DMA address
458 */
Jeff Garzik095fec82005-11-12 09:50:49 -0500459 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
460
Jeff Garzik0ea9e172007-07-13 17:06:45 -0400461 /* ditto, for response queue */
Jeff Garzik095fec82005-11-12 09:50:49 -0500462 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
463};
464
Jeff Garzik522479f2005-11-12 22:14:02 -0500465enum chip_type {
466 chip_504x,
467 chip_508x,
468 chip_5080,
469 chip_604x,
470 chip_608x,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500471 chip_6042,
472 chip_7042,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500473 chip_soc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500474};
475
Brett Russ31961942005-09-30 01:36:00 -0400476/* Command ReQuest Block: 32B */
477struct mv_crqb {
Mark Lorde1469872006-05-22 19:02:03 -0400478 __le32 sg_addr;
479 __le32 sg_addr_hi;
480 __le16 ctrl_flags;
481 __le16 ata_cmd[11];
Brett Russ31961942005-09-30 01:36:00 -0400482};
483
Jeff Garzike4e7b892006-01-31 12:18:41 -0500484struct mv_crqb_iie {
Mark Lorde1469872006-05-22 19:02:03 -0400485 __le32 addr;
486 __le32 addr_hi;
487 __le32 flags;
488 __le32 len;
489 __le32 ata_cmd[4];
Jeff Garzike4e7b892006-01-31 12:18:41 -0500490};
491
Brett Russ31961942005-09-30 01:36:00 -0400492/* Command ResPonse Block: 8B */
493struct mv_crpb {
Mark Lorde1469872006-05-22 19:02:03 -0400494 __le16 id;
495 __le16 flags;
496 __le32 tmstmp;
Brett Russ31961942005-09-30 01:36:00 -0400497};
498
499/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
500struct mv_sg {
Mark Lorde1469872006-05-22 19:02:03 -0400501 __le32 addr;
502 __le32 flags_size;
503 __le32 addr_hi;
504 __le32 reserved;
Brett Russ20f733e2005-09-01 18:26:17 -0400505};
506
Mark Lord08da1752009-02-25 15:13:03 -0500507/*
508 * We keep a local cache of a few frequently accessed port
509 * registers here, to avoid having to read them (very slow)
510 * when switching between EDMA and non-EDMA modes.
511 */
512struct mv_cached_regs {
513 u32 fiscfg;
514 u32 ltmode;
515 u32 haltcond;
Mark Lordc01e8a22009-02-25 15:14:48 -0500516 u32 unknown_rsvd;
Mark Lord08da1752009-02-25 15:13:03 -0500517};
518
Brett Russ20f733e2005-09-01 18:26:17 -0400519struct mv_port_priv {
Brett Russ31961942005-09-30 01:36:00 -0400520 struct mv_crqb *crqb;
521 dma_addr_t crqb_dma;
522 struct mv_crpb *crpb;
523 dma_addr_t crpb_dma;
Mark Lordeb73d552008-01-29 13:24:00 -0500524 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
525 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400526
527 unsigned int req_idx;
528 unsigned int resp_idx;
529
Brett Russ31961942005-09-30 01:36:00 -0400530 u32 pp_flags;
Mark Lord08da1752009-02-25 15:13:03 -0500531 struct mv_cached_regs cached;
Mark Lord29d187b2008-05-02 02:15:37 -0400532 unsigned int delayed_eh_pmp_map;
Brett Russ20f733e2005-09-01 18:26:17 -0400533};
534
Jeff Garzikbca1c4e2005-11-12 12:48:15 -0500535struct mv_port_signal {
536 u32 amps;
537 u32 pre;
538};
539
Mark Lord02a121d2007-12-01 13:07:22 -0500540struct mv_host_priv {
541 u32 hp_flags;
Saeed Bishara1bfeff02009-12-17 01:05:00 -0500542 unsigned int board_idx;
Mark Lord96e2c482008-05-17 13:38:00 -0400543 u32 main_irq_mask;
Mark Lord02a121d2007-12-01 13:07:22 -0500544 struct mv_port_signal signal[8];
545 const struct mv_hw_ops *ops;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500546 int n_ports;
547 void __iomem *base;
Mark Lord7368f912008-04-25 11:24:24 -0400548 void __iomem *main_irq_cause_addr;
549 void __iomem *main_irq_mask_addr;
Mark Lordcae5a292009-04-06 16:43:45 -0400550 u32 irq_cause_offset;
551 u32 irq_mask_offset;
Mark Lord02a121d2007-12-01 13:07:22 -0500552 u32 unmask_all_irqs;
Saeed Bisharac77a2f42009-12-06 18:26:18 +0200553
554#if defined(CONFIG_HAVE_CLK)
555 struct clk *clk;
556#endif
Mark Lordda2fa9b2008-01-26 18:32:45 -0500557 /*
558 * These consistent DMA memory pools give us guaranteed
559 * alignment for hardware-accessed data structures,
560 * and less memory waste in accomplishing the alignment.
561 */
562 struct dma_pool *crqb_pool;
563 struct dma_pool *crpb_pool;
564 struct dma_pool *sg_tbl_pool;
Mark Lord02a121d2007-12-01 13:07:22 -0500565};
566
Jeff Garzik47c2b672005-11-12 21:13:17 -0500567struct mv_hw_ops {
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500568 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
569 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500570 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
571 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
572 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500573 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
574 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500575 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100576 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500577};
578
Tejun Heo82ef04f2008-07-31 17:02:40 +0900579static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
580static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
581static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
582static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
Brett Russ31961942005-09-30 01:36:00 -0400583static int mv_port_start(struct ata_port *ap);
584static void mv_port_stop(struct ata_port *ap);
Mark Lord3e4a1392008-05-02 02:10:02 -0400585static int mv_qc_defer(struct ata_queued_cmd *qc);
Brett Russ31961942005-09-30 01:36:00 -0400586static void mv_qc_prep(struct ata_queued_cmd *qc);
Jeff Garzike4e7b892006-01-31 12:18:41 -0500587static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900588static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900589static int mv_hardreset(struct ata_link *link, unsigned int *class,
590 unsigned long deadline);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400591static void mv_eh_freeze(struct ata_port *ap);
592static void mv_eh_thaw(struct ata_port *ap);
Mark Lordf2738272008-01-26 18:32:29 -0500593static void mv6_dev_config(struct ata_device *dev);
Brett Russ20f733e2005-09-01 18:26:17 -0400594
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500595static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
596 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500597static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
598static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
599 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500600static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
601 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500602static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100603static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500604
Jeff Garzik2a47ce02005-11-12 23:05:14 -0500605static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 unsigned int port);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500607static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
608static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
609 void __iomem *mmio);
Jeff Garzikc9d39132005-11-13 17:47:51 -0500610static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
611 unsigned int n_hc);
Jeff Garzik522479f2005-11-12 22:14:02 -0500612static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500613static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
614 void __iomem *mmio);
615static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
616 void __iomem *mmio);
617static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
618 void __iomem *mmio, unsigned int n_hc);
619static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
620 void __iomem *mmio);
621static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200622static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
623 void __iomem *mmio, unsigned int port);
Saeed Bishara7bb3c522008-01-30 11:50:45 -1100624static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
Mark Lorde12bef52008-03-31 19:33:56 -0400625static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500626 unsigned int port_no);
Mark Lorde12bef52008-03-31 19:33:56 -0400627static int mv_stop_edma(struct ata_port *ap);
Mark Lordb5624682008-03-31 19:34:40 -0400628static int mv_stop_edma_engine(void __iomem *port_mmio);
Mark Lord00b81232009-01-30 18:47:51 -0500629static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
Jeff Garzik47c2b672005-11-12 21:13:17 -0500630
Mark Lorde49856d2008-04-16 14:59:07 -0400631static void mv_pmp_select(struct ata_port *ap, int pmp);
632static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
633 unsigned long deadline);
634static int mv_softreset(struct ata_link *link, unsigned int *class,
635 unsigned long deadline);
Mark Lord29d187b2008-05-02 02:15:37 -0400636static void mv_pmp_error_handler(struct ata_port *ap);
Mark Lord4c299ca2008-05-02 02:16:20 -0400637static void mv_process_crpb_entries(struct ata_port *ap,
638 struct mv_port_priv *pp);
Brett Russ20f733e2005-09-01 18:26:17 -0400639
Mark Lordda142652009-01-30 18:51:54 -0500640static void mv_sff_irq_clear(struct ata_port *ap);
641static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
642static void mv_bmdma_setup(struct ata_queued_cmd *qc);
643static void mv_bmdma_start(struct ata_queued_cmd *qc);
644static void mv_bmdma_stop(struct ata_queued_cmd *qc);
645static u8 mv_bmdma_status(struct ata_port *ap);
Mark Lordd16ab3f2009-02-25 15:17:43 -0500646static u8 mv_sff_check_status(struct ata_port *ap);
Mark Lordda142652009-01-30 18:51:54 -0500647
Mark Lordeb73d552008-01-29 13:24:00 -0500648/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
649 * because we have to allow room for worst case splitting of
650 * PRDs for 64K boundaries in mv_fill_sg().
651 */
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400652static struct scsi_host_template mv5_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900653 ATA_BASE_SHT(DRV_NAME),
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400654 .sg_tablesize = MV_MAX_SG_CT / 2,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400655 .dma_boundary = MV_DMA_BOUNDARY,
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400656};
657
658static struct scsi_host_template mv6_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900659 ATA_NCQ_SHT(DRV_NAME),
Mark Lord138bfdd2008-01-26 18:33:18 -0500660 .can_queue = MV_MAX_Q_DEPTH - 1,
Jeff Garzikbaf14aa2007-10-09 13:51:57 -0400661 .sg_tablesize = MV_MAX_SG_CT / 2,
Brett Russ20f733e2005-09-01 18:26:17 -0400662 .dma_boundary = MV_DMA_BOUNDARY,
Brett Russ20f733e2005-09-01 18:26:17 -0400663};
664
Tejun Heo029cfd62008-03-25 12:22:49 +0900665static struct ata_port_operations mv5_ops = {
666 .inherits = &ata_sff_port_ops,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500667
Alan Coxc96f1732009-03-24 10:23:46 +0000668 .lost_interrupt = ATA_OP_NULL,
669
Mark Lord3e4a1392008-05-02 02:10:02 -0400670 .qc_defer = mv_qc_defer,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500671 .qc_prep = mv_qc_prep,
672 .qc_issue = mv_qc_issue,
673
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400674 .freeze = mv_eh_freeze,
675 .thaw = mv_eh_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900676 .hardreset = mv_hardreset,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400677
Jeff Garzikc9d39132005-11-13 17:47:51 -0500678 .scr_read = mv5_scr_read,
679 .scr_write = mv5_scr_write,
680
681 .port_start = mv_port_start,
682 .port_stop = mv_port_stop,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500683};
684
Tejun Heo029cfd62008-03-25 12:22:49 +0900685static struct ata_port_operations mv6_ops = {
Tejun Heo8930ff22010-05-10 21:41:33 +0200686 .inherits = &ata_bmdma_port_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400687
Tejun Heo8930ff22010-05-10 21:41:33 +0200688 .lost_interrupt = ATA_OP_NULL,
689
690 .qc_defer = mv_qc_defer,
691 .qc_prep = mv_qc_prep,
692 .qc_issue = mv_qc_issue,
693
694 .dev_config = mv6_dev_config,
695
696 .freeze = mv_eh_freeze,
697 .thaw = mv_eh_thaw,
698 .hardreset = mv_hardreset,
699 .softreset = mv_softreset,
Mark Lorde49856d2008-04-16 14:59:07 -0400700 .pmp_hardreset = mv_pmp_hardreset,
701 .pmp_softreset = mv_softreset,
Mark Lord29d187b2008-05-02 02:15:37 -0400702 .error_handler = mv_pmp_error_handler,
Mark Lordda142652009-01-30 18:51:54 -0500703
Tejun Heo8930ff22010-05-10 21:41:33 +0200704 .scr_read = mv_scr_read,
705 .scr_write = mv_scr_write,
706
Mark Lord40f21b12009-03-10 18:51:04 -0400707 .sff_check_status = mv_sff_check_status,
Mark Lordda142652009-01-30 18:51:54 -0500708 .sff_irq_clear = mv_sff_irq_clear,
709 .check_atapi_dma = mv_check_atapi_dma,
710 .bmdma_setup = mv_bmdma_setup,
711 .bmdma_start = mv_bmdma_start,
712 .bmdma_stop = mv_bmdma_stop,
713 .bmdma_status = mv_bmdma_status,
Tejun Heo8930ff22010-05-10 21:41:33 +0200714
715 .port_start = mv_port_start,
716 .port_stop = mv_port_stop,
Brett Russ20f733e2005-09-01 18:26:17 -0400717};
718
Tejun Heo029cfd62008-03-25 12:22:49 +0900719static struct ata_port_operations mv_iie_ops = {
720 .inherits = &mv6_ops,
721 .dev_config = ATA_OP_NULL,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500722 .qc_prep = mv_qc_prep_iie,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500723};
724
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100725static const struct ata_port_info mv_port_info[] = {
Brett Russ20f733e2005-09-01 18:26:17 -0400726 { /* chip_504x */
Mark Lord91b1a842009-01-30 18:46:39 -0500727 .flags = MV_GEN_I_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400728 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400729 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500730 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400731 },
732 { /* chip_508x */
Mark Lord91b1a842009-01-30 18:46:39 -0500733 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400734 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400735 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500736 .port_ops = &mv5_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400737 },
Jeff Garzik47c2b672005-11-12 21:13:17 -0500738 { /* chip_5080 */
Mark Lord91b1a842009-01-30 18:46:39 -0500739 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400740 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400741 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500742 .port_ops = &mv5_ops,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500743 },
Brett Russ20f733e2005-09-01 18:26:17 -0400744 { /* chip_604x */
Mark Lord91b1a842009-01-30 18:46:39 -0500745 .flags = MV_GEN_II_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400746 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400747 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500748 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400749 },
750 { /* chip_608x */
Mark Lord91b1a842009-01-30 18:46:39 -0500751 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
Mark Lordc361acb2009-04-06 15:22:21 -0400752 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400753 .udma_mask = ATA_UDMA6,
Jeff Garzikc9d39132005-11-13 17:47:51 -0500754 .port_ops = &mv6_ops,
Brett Russ20f733e2005-09-01 18:26:17 -0400755 },
Jeff Garzike4e7b892006-01-31 12:18:41 -0500756 { /* chip_6042 */
Mark Lord91b1a842009-01-30 18:46:39 -0500757 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400758 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400759 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500760 .port_ops = &mv_iie_ops,
761 },
762 { /* chip_7042 */
Mark Lord91b1a842009-01-30 18:46:39 -0500763 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400764 .pio_mask = ATA_PIO4,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400765 .udma_mask = ATA_UDMA6,
Jeff Garzike4e7b892006-01-31 12:18:41 -0500766 .port_ops = &mv_iie_ops,
767 },
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500768 { /* chip_soc */
Mark Lord91b1a842009-01-30 18:46:39 -0500769 .flags = MV_GEN_IIE_FLAGS,
Mark Lordc361acb2009-04-06 15:22:21 -0400770 .pio_mask = ATA_PIO4,
Mark Lord17c5aab2008-04-16 14:56:51 -0400771 .udma_mask = ATA_UDMA6,
772 .port_ops = &mv_iie_ops,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500773 },
Brett Russ20f733e2005-09-01 18:26:17 -0400774};
775
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500776static const struct pci_device_id mv_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400777 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
778 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
779 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
780 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
Mark Lord46c57842008-09-04 18:21:07 -0400781 /* RocketRAID 1720/174x have different identifiers */
782 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
Mark Lord44622542009-01-27 16:33:13 -0500783 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
784 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
Brett Russ20f733e2005-09-01 18:26:17 -0400785
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400786 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
787 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
788 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
789 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
790 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
Jeff Garzik29179532005-11-11 08:08:03 -0500791
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400792 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
793
Florian Attenbergerd9f9c6b2007-07-02 17:09:29 +0200794 /* Adaptec 1430SA */
795 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
796
Mark Lord02a121d2007-12-01 13:07:22 -0500797 /* Marvell 7042 support */
Morrison, Tom6a3d5862007-03-06 02:38:10 -0800798 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
799
Mark Lord02a121d2007-12-01 13:07:22 -0500800 /* Highpoint RocketRAID PCIe series */
801 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
802 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
803
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400804 { } /* terminate list */
Brett Russ20f733e2005-09-01 18:26:17 -0400805};
806
Jeff Garzik47c2b672005-11-12 21:13:17 -0500807static const struct mv_hw_ops mv5xxx_ops = {
808 .phy_errata = mv5_phy_errata,
809 .enable_leds = mv5_enable_leds,
810 .read_preamp = mv5_read_preamp,
811 .reset_hc = mv5_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500812 .reset_flash = mv5_reset_flash,
813 .reset_bus = mv5_reset_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500814};
815
816static const struct mv_hw_ops mv6xxx_ops = {
817 .phy_errata = mv6_phy_errata,
818 .enable_leds = mv6_enable_leds,
819 .read_preamp = mv6_read_preamp,
820 .reset_hc = mv6_reset_hc,
Jeff Garzik522479f2005-11-12 22:14:02 -0500821 .reset_flash = mv6_reset_flash,
822 .reset_bus = mv_reset_pci_bus,
Jeff Garzik47c2b672005-11-12 21:13:17 -0500823};
824
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500825static const struct mv_hw_ops mv_soc_ops = {
826 .phy_errata = mv6_phy_errata,
827 .enable_leds = mv_soc_enable_leds,
828 .read_preamp = mv_soc_read_preamp,
829 .reset_hc = mv_soc_reset_hc,
830 .reset_flash = mv_soc_reset_flash,
831 .reset_bus = mv_soc_reset_bus,
832};
833
Martin Michlmayr29b7e432009-05-04 20:58:50 +0200834static const struct mv_hw_ops mv_soc_65n_ops = {
835 .phy_errata = mv_soc_65n_phy_errata,
836 .enable_leds = mv_soc_enable_leds,
837 .reset_hc = mv_soc_reset_hc,
838 .reset_flash = mv_soc_reset_flash,
839 .reset_bus = mv_soc_reset_bus,
840};
841
Brett Russ20f733e2005-09-01 18:26:17 -0400842/*
843 * Functions
844 */
845
846static inline void writelfl(unsigned long data, void __iomem *addr)
847{
848 writel(data, addr);
849 (void) readl(addr); /* flush to avoid PCI posted write */
850}
851
Jeff Garzikc9d39132005-11-13 17:47:51 -0500852static inline unsigned int mv_hc_from_port(unsigned int port)
853{
854 return port >> MV_PORT_HC_SHIFT;
855}
856
857static inline unsigned int mv_hardport_from_port(unsigned int port)
858{
859 return port & MV_PORT_MASK;
860}
861
Mark Lord1cfd19a2008-04-19 15:05:50 -0400862/*
863 * Consolidate some rather tricky bit shift calculations.
864 * This is hot-path stuff, so not a function.
865 * Simple code, with two return values, so macro rather than inline.
866 *
867 * port is the sole input, in range 0..7.
Mark Lord7368f912008-04-25 11:24:24 -0400868 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
869 * hardport is the other output, in range 0..3.
Mark Lord1cfd19a2008-04-19 15:05:50 -0400870 *
871 * Note that port and hardport may be the same variable in some cases.
872 */
873#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
874{ \
875 shift = mv_hc_from_port(port) * HC_SHIFT; \
876 hardport = mv_hardport_from_port(port); \
877 shift += hardport * 2; \
878}
879
Mark Lord352fab72008-04-19 14:43:42 -0400880static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
881{
Mark Lordcae5a292009-04-06 16:43:45 -0400882 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
Mark Lord352fab72008-04-19 14:43:42 -0400883}
884
Jeff Garzikc9d39132005-11-13 17:47:51 -0500885static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
886 unsigned int port)
887{
888 return mv_hc_base(base, mv_hc_from_port(port));
889}
890
Brett Russ20f733e2005-09-01 18:26:17 -0400891static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
892{
Jeff Garzikc9d39132005-11-13 17:47:51 -0500893 return mv_hc_base_from_port(base, port) +
Jeff Garzik8b260242005-11-12 12:32:50 -0500894 MV_SATAHC_ARBTR_REG_SZ +
Jeff Garzikc9d39132005-11-13 17:47:51 -0500895 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
Brett Russ20f733e2005-09-01 18:26:17 -0400896}
897
Mark Lorde12bef52008-03-31 19:33:56 -0400898static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
899{
900 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
901 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
902
903 return hc_mmio + ofs;
904}
905
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500906static inline void __iomem *mv_host_base(struct ata_host *host)
907{
908 struct mv_host_priv *hpriv = host->private_data;
909 return hpriv->base;
910}
911
Brett Russ20f733e2005-09-01 18:26:17 -0400912static inline void __iomem *mv_ap_base(struct ata_port *ap)
913{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -0500914 return mv_port_base(mv_host_base(ap->host), ap->port_no);
Brett Russ20f733e2005-09-01 18:26:17 -0400915}
916
Jeff Garzikcca39742006-08-24 03:19:22 -0400917static inline int mv_get_hc_count(unsigned long port_flags)
Brett Russ20f733e2005-09-01 18:26:17 -0400918{
Jeff Garzikcca39742006-08-24 03:19:22 -0400919 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
Brett Russ20f733e2005-09-01 18:26:17 -0400920}
921
Mark Lord08da1752009-02-25 15:13:03 -0500922/**
923 * mv_save_cached_regs - (re-)initialize cached port registers
924 * @ap: the port whose registers we are caching
925 *
926 * Initialize the local cache of port registers,
927 * so that reading them over and over again can
928 * be avoided on the hotter paths of this driver.
929 * This saves a few microseconds each time we switch
930 * to/from EDMA mode to perform (eg.) a drive cache flush.
931 */
932static void mv_save_cached_regs(struct ata_port *ap)
933{
934 void __iomem *port_mmio = mv_ap_base(ap);
935 struct mv_port_priv *pp = ap->private_data;
936
Mark Lordcae5a292009-04-06 16:43:45 -0400937 pp->cached.fiscfg = readl(port_mmio + FISCFG);
938 pp->cached.ltmode = readl(port_mmio + LTMODE);
939 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
940 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
Mark Lord08da1752009-02-25 15:13:03 -0500941}
942
943/**
944 * mv_write_cached_reg - write to a cached port register
945 * @addr: hardware address of the register
946 * @old: pointer to cached value of the register
947 * @new: new value for the register
948 *
949 * Write a new value to a cached register,
950 * but only if the value is different from before.
951 */
952static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
953{
954 if (new != *old) {
Mark Lord12f3b6d2009-04-06 15:26:24 -0400955 unsigned long laddr;
Mark Lord08da1752009-02-25 15:13:03 -0500956 *old = new;
Mark Lord12f3b6d2009-04-06 15:26:24 -0400957 /*
958 * Workaround for 88SX60x1-B2 FEr SATA#13:
959 * Read-after-write is needed to prevent generating 64-bit
960 * write cycles on the PCI bus for SATA interface registers
961 * at offsets ending in 0x4 or 0xc.
962 *
963 * Looks like a lot of fuss, but it avoids an unnecessary
964 * +1 usec read-after-write delay for unaffected registers.
965 */
966 laddr = (long)addr & 0xffff;
967 if (laddr >= 0x300 && laddr <= 0x33c) {
968 laddr &= 0x000f;
969 if (laddr == 0x4 || laddr == 0xc) {
970 writelfl(new, addr); /* read after write */
971 return;
972 }
973 }
974 writel(new, addr); /* unaffected by the errata */
Mark Lord08da1752009-02-25 15:13:03 -0500975 }
976}
977
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400978static void mv_set_edma_ptrs(void __iomem *port_mmio,
979 struct mv_host_priv *hpriv,
980 struct mv_port_priv *pp)
981{
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400982 u32 index;
983
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400984 /*
985 * initialize request queue
986 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400987 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
988 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400989
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400990 WARN_ON(pp->crqb_dma & 0x3ff);
Mark Lordcae5a292009-04-06 16:43:45 -0400991 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -0400992 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
Mark Lordcae5a292009-04-06 16:43:45 -0400993 port_mmio + EDMA_REQ_Q_IN_PTR);
994 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
Jeff Garzikc5d3e452007-07-11 18:30:50 -0400995
996 /*
997 * initialize response queue
998 */
Mark Lordfcfb1f72008-04-19 15:06:40 -0400999 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1000 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001001
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001002 WARN_ON(pp->crpb_dma & 0xff);
Mark Lordcae5a292009-04-06 16:43:45 -04001003 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1004 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001005 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
Mark Lordcae5a292009-04-06 16:43:45 -04001006 port_mmio + EDMA_RSP_Q_OUT_PTR);
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001007}
1008
Mark Lord2b748a02009-03-10 22:01:17 -04001009static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1010{
1011 /*
1012 * When writing to the main_irq_mask in hardware,
1013 * we must ensure exclusivity between the interrupt coalescing bits
1014 * and the corresponding individual port DONE_IRQ bits.
1015 *
1016 * Note that this register is really an "IRQ enable" register,
1017 * not an "IRQ mask" register as Marvell's naming might suggest.
1018 */
1019 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1020 mask &= ~DONE_IRQ_0_3;
1021 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1022 mask &= ~DONE_IRQ_4_7;
1023 writelfl(mask, hpriv->main_irq_mask_addr);
1024}
1025
Mark Lordc4de5732008-05-17 13:35:21 -04001026static void mv_set_main_irq_mask(struct ata_host *host,
1027 u32 disable_bits, u32 enable_bits)
1028{
1029 struct mv_host_priv *hpriv = host->private_data;
1030 u32 old_mask, new_mask;
1031
Mark Lord96e2c482008-05-17 13:38:00 -04001032 old_mask = hpriv->main_irq_mask;
Mark Lordc4de5732008-05-17 13:35:21 -04001033 new_mask = (old_mask & ~disable_bits) | enable_bits;
Mark Lord96e2c482008-05-17 13:38:00 -04001034 if (new_mask != old_mask) {
1035 hpriv->main_irq_mask = new_mask;
Mark Lord2b748a02009-03-10 22:01:17 -04001036 mv_write_main_irq_mask(new_mask, hpriv);
Mark Lord96e2c482008-05-17 13:38:00 -04001037 }
Mark Lordc4de5732008-05-17 13:35:21 -04001038}
1039
1040static void mv_enable_port_irqs(struct ata_port *ap,
1041 unsigned int port_bits)
1042{
1043 unsigned int shift, hardport, port = ap->port_no;
1044 u32 disable_bits, enable_bits;
1045
1046 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1047
1048 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1049 enable_bits = port_bits << shift;
1050 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1051}
1052
Mark Lord00b81232009-01-30 18:47:51 -05001053static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1054 void __iomem *port_mmio,
1055 unsigned int port_irqs)
1056{
1057 struct mv_host_priv *hpriv = ap->host->private_data;
1058 int hardport = mv_hardport_from_port(ap->port_no);
1059 void __iomem *hc_mmio = mv_hc_base_from_port(
1060 mv_host_base(ap->host), ap->port_no);
1061 u32 hc_irq_cause;
1062
1063 /* clear EDMA event indicators, if any */
Mark Lordcae5a292009-04-06 16:43:45 -04001064 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001065
1066 /* clear pending irq events */
1067 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lordcae5a292009-04-06 16:43:45 -04001068 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001069
1070 /* clear FIS IRQ Cause */
1071 if (IS_GEN_IIE(hpriv))
Mark Lordcae5a292009-04-06 16:43:45 -04001072 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
Mark Lord00b81232009-01-30 18:47:51 -05001073
1074 mv_enable_port_irqs(ap, port_irqs);
1075}
1076
Mark Lord2b748a02009-03-10 22:01:17 -04001077static void mv_set_irq_coalescing(struct ata_host *host,
1078 unsigned int count, unsigned int usecs)
1079{
1080 struct mv_host_priv *hpriv = host->private_data;
1081 void __iomem *mmio = hpriv->base, *hc_mmio;
1082 u32 coal_enable = 0;
1083 unsigned long flags;
Mark Lord6abf4672009-03-11 00:56:00 -04001084 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
Mark Lord2b748a02009-03-10 22:01:17 -04001085 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1086 ALL_PORTS_COAL_DONE;
1087
1088 /* Disable IRQ coalescing if either threshold is zero */
1089 if (!usecs || !count) {
1090 clks = count = 0;
1091 } else {
1092 /* Respect maximum limits of the hardware */
1093 clks = usecs * COAL_CLOCKS_PER_USEC;
1094 if (clks > MAX_COAL_TIME_THRESHOLD)
1095 clks = MAX_COAL_TIME_THRESHOLD;
1096 if (count > MAX_COAL_IO_COUNT)
1097 count = MAX_COAL_IO_COUNT;
1098 }
1099
1100 spin_lock_irqsave(&host->lock, flags);
Mark Lord6abf4672009-03-11 00:56:00 -04001101 mv_set_main_irq_mask(host, coal_disable, 0);
Mark Lord2b748a02009-03-10 22:01:17 -04001102
Mark Lord6abf4672009-03-11 00:56:00 -04001103 if (is_dual_hc && !IS_GEN_I(hpriv)) {
Mark Lord2b748a02009-03-10 22:01:17 -04001104 /*
Mark Lord6abf4672009-03-11 00:56:00 -04001105 * GEN_II/GEN_IIE with dual host controllers:
1106 * one set of global thresholds for the entire chip.
Mark Lord2b748a02009-03-10 22:01:17 -04001107 */
Mark Lordcae5a292009-04-06 16:43:45 -04001108 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1109 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
Mark Lord2b748a02009-03-10 22:01:17 -04001110 /* clear leftover coal IRQ bit */
Mark Lordcae5a292009-04-06 16:43:45 -04001111 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001112 if (count)
1113 coal_enable = ALL_PORTS_COAL_DONE;
1114 clks = count = 0; /* force clearing of regular regs below */
Mark Lord2b748a02009-03-10 22:01:17 -04001115 }
Mark Lord6abf4672009-03-11 00:56:00 -04001116
Mark Lord2b748a02009-03-10 22:01:17 -04001117 /*
1118 * All chips: independent thresholds for each HC on the chip.
1119 */
1120 hc_mmio = mv_hc_base_from_port(mmio, 0);
Mark Lordcae5a292009-04-06 16:43:45 -04001121 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1122 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1123 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001124 if (count)
1125 coal_enable |= PORTS_0_3_COAL_DONE;
1126 if (is_dual_hc) {
Mark Lord2b748a02009-03-10 22:01:17 -04001127 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
Mark Lordcae5a292009-04-06 16:43:45 -04001128 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1129 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1130 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
Mark Lord6abf4672009-03-11 00:56:00 -04001131 if (count)
1132 coal_enable |= PORTS_4_7_COAL_DONE;
Mark Lord2b748a02009-03-10 22:01:17 -04001133 }
Mark Lord2b748a02009-03-10 22:01:17 -04001134
Mark Lord6abf4672009-03-11 00:56:00 -04001135 mv_set_main_irq_mask(host, 0, coal_enable);
Mark Lord2b748a02009-03-10 22:01:17 -04001136 spin_unlock_irqrestore(&host->lock, flags);
1137}
1138
Brett Russ05b308e2005-10-05 17:08:53 -04001139/**
Mark Lord00b81232009-01-30 18:47:51 -05001140 * mv_start_edma - Enable eDMA engine
Brett Russ05b308e2005-10-05 17:08:53 -04001141 * @base: port base address
1142 * @pp: port private data
1143 *
Tejun Heobeec7db2006-02-11 19:11:13 +09001144 * Verify the local cache of the eDMA state is accurate with a
1145 * WARN_ON.
Brett Russ05b308e2005-10-05 17:08:53 -04001146 *
1147 * LOCKING:
1148 * Inherited from caller.
1149 */
Mark Lord00b81232009-01-30 18:47:51 -05001150static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
Mark Lord72109162008-01-26 18:31:33 -05001151 struct mv_port_priv *pp, u8 protocol)
Brett Russ31961942005-09-30 01:36:00 -04001152{
Mark Lord72109162008-01-26 18:31:33 -05001153 int want_ncq = (protocol == ATA_PROT_NCQ);
1154
1155 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1156 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1157 if (want_ncq != using_ncq)
Mark Lordb5624682008-03-31 19:34:40 -04001158 mv_stop_edma(ap);
Mark Lord72109162008-01-26 18:31:33 -05001159 }
Jeff Garzikc5d3e452007-07-11 18:30:50 -04001160 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
Mark Lord0c589122008-01-26 18:31:16 -05001161 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lord0c589122008-01-26 18:31:16 -05001162
Mark Lord00b81232009-01-30 18:47:51 -05001163 mv_edma_cfg(ap, want_ncq, 1);
Mark Lord0c589122008-01-26 18:31:16 -05001164
Mark Lordf630d562008-01-26 18:31:00 -05001165 mv_set_edma_ptrs(port_mmio, hpriv, pp);
Mark Lord00b81232009-01-30 18:47:51 -05001166 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04001167
Mark Lordcae5a292009-04-06 16:43:45 -04001168 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
Brett Russafb0edd2005-10-05 17:08:42 -04001169 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1170 }
Brett Russ31961942005-09-30 01:36:00 -04001171}
1172
Mark Lord9b2c4e02008-05-02 02:09:14 -04001173static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1174{
1175 void __iomem *port_mmio = mv_ap_base(ap);
1176 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1177 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1178 int i;
1179
1180 /*
1181 * Wait for the EDMA engine to finish transactions in progress.
Mark Lordc46938c2008-05-02 14:02:28 -04001182 * No idea what a good "timeout" value might be, but measurements
1183 * indicate that it often requires hundreds of microseconds
1184 * with two drives in-use. So we use the 15msec value above
1185 * as a rough guess at what even more drives might require.
Mark Lord9b2c4e02008-05-02 02:09:14 -04001186 */
1187 for (i = 0; i < timeout; ++i) {
Mark Lordcae5a292009-04-06 16:43:45 -04001188 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
Mark Lord9b2c4e02008-05-02 02:09:14 -04001189 if ((edma_stat & empty_idle) == empty_idle)
1190 break;
1191 udelay(per_loop);
1192 }
Joe Perchesa9a79df2011-04-15 15:51:59 -07001193 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
Mark Lord9b2c4e02008-05-02 02:09:14 -04001194}
1195
Brett Russ05b308e2005-10-05 17:08:53 -04001196/**
Mark Lorde12bef52008-03-31 19:33:56 -04001197 * mv_stop_edma_engine - Disable eDMA engine
Mark Lordb5624682008-03-31 19:34:40 -04001198 * @port_mmio: io base address
Brett Russ05b308e2005-10-05 17:08:53 -04001199 *
1200 * LOCKING:
1201 * Inherited from caller.
1202 */
Mark Lordb5624682008-03-31 19:34:40 -04001203static int mv_stop_edma_engine(void __iomem *port_mmio)
Brett Russ31961942005-09-30 01:36:00 -04001204{
Mark Lordb5624682008-03-31 19:34:40 -04001205 int i;
Brett Russ31961942005-09-30 01:36:00 -04001206
Mark Lordb5624682008-03-31 19:34:40 -04001207 /* Disable eDMA. The disable bit auto clears. */
Mark Lordcae5a292009-04-06 16:43:45 -04001208 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
Jeff Garzik8b260242005-11-12 12:32:50 -05001209
Mark Lordb5624682008-03-31 19:34:40 -04001210 /* Wait for the chip to confirm eDMA is off. */
1211 for (i = 10000; i > 0; i--) {
Mark Lordcae5a292009-04-06 16:43:45 -04001212 u32 reg = readl(port_mmio + EDMA_CMD);
Jeff Garzik4537deb2007-07-12 14:30:19 -04001213 if (!(reg & EDMA_EN))
Mark Lordb5624682008-03-31 19:34:40 -04001214 return 0;
1215 udelay(10);
Brett Russ31961942005-09-30 01:36:00 -04001216 }
Mark Lordb5624682008-03-31 19:34:40 -04001217 return -EIO;
Brett Russ31961942005-09-30 01:36:00 -04001218}
1219
Mark Lorde12bef52008-03-31 19:33:56 -04001220static int mv_stop_edma(struct ata_port *ap)
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001221{
Mark Lordb5624682008-03-31 19:34:40 -04001222 void __iomem *port_mmio = mv_ap_base(ap);
1223 struct mv_port_priv *pp = ap->private_data;
Mark Lord66e57a22009-01-30 18:52:58 -05001224 int err = 0;
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001225
Mark Lordb5624682008-03-31 19:34:40 -04001226 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1227 return 0;
1228 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lord9b2c4e02008-05-02 02:09:14 -04001229 mv_wait_for_edma_empty_idle(ap);
Mark Lordb5624682008-03-31 19:34:40 -04001230 if (mv_stop_edma_engine(port_mmio)) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07001231 ata_port_err(ap, "Unable to stop eDMA\n");
Mark Lord66e57a22009-01-30 18:52:58 -05001232 err = -EIO;
Mark Lordb5624682008-03-31 19:34:40 -04001233 }
Mark Lord66e57a22009-01-30 18:52:58 -05001234 mv_edma_cfg(ap, 0, 0);
1235 return err;
Jeff Garzik0ea9e172007-07-13 17:06:45 -04001236}
1237
Jeff Garzik8a70f8d2005-10-05 17:19:47 -04001238#ifdef ATA_DEBUG
Brett Russ31961942005-09-30 01:36:00 -04001239static void mv_dump_mem(void __iomem *start, unsigned bytes)
1240{
Brett Russ31961942005-09-30 01:36:00 -04001241 int b, w;
1242 for (b = 0; b < bytes; ) {
1243 DPRINTK("%p: ", start + b);
1244 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001245 printk("%08x ", readl(start + b));
Brett Russ31961942005-09-30 01:36:00 -04001246 b += sizeof(u32);
1247 }
1248 printk("\n");
1249 }
Brett Russ31961942005-09-30 01:36:00 -04001250}
Jeff Garzik8a70f8d2005-10-05 17:19:47 -04001251#endif
1252
Brett Russ31961942005-09-30 01:36:00 -04001253static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1254{
1255#ifdef ATA_DEBUG
1256 int b, w;
1257 u32 dw;
1258 for (b = 0; b < bytes; ) {
1259 DPRINTK("%02x: ", b);
1260 for (w = 0; b < bytes && w < 4; w++) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001261 (void) pci_read_config_dword(pdev, b, &dw);
1262 printk("%08x ", dw);
Brett Russ31961942005-09-30 01:36:00 -04001263 b += sizeof(u32);
1264 }
1265 printk("\n");
1266 }
1267#endif
1268}
1269static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1270 struct pci_dev *pdev)
1271{
1272#ifdef ATA_DEBUG
Jeff Garzik8b260242005-11-12 12:32:50 -05001273 void __iomem *hc_base = mv_hc_base(mmio_base,
Brett Russ31961942005-09-30 01:36:00 -04001274 port >> MV_PORT_HC_SHIFT);
1275 void __iomem *port_base;
1276 int start_port, num_ports, p, start_hc, num_hcs, hc;
1277
1278 if (0 > port) {
1279 start_hc = start_port = 0;
1280 num_ports = 8; /* shld be benign for 4 port devs */
1281 num_hcs = 2;
1282 } else {
1283 start_hc = port >> MV_PORT_HC_SHIFT;
1284 start_port = port;
1285 num_ports = num_hcs = 1;
1286 }
Jeff Garzik8b260242005-11-12 12:32:50 -05001287 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
Brett Russ31961942005-09-30 01:36:00 -04001288 num_ports > 1 ? num_ports - 1 : start_port);
1289
1290 if (NULL != pdev) {
1291 DPRINTK("PCI config space regs:\n");
1292 mv_dump_pci_cfg(pdev, 0x68);
1293 }
1294 DPRINTK("PCI regs:\n");
1295 mv_dump_mem(mmio_base+0xc00, 0x3c);
1296 mv_dump_mem(mmio_base+0xd00, 0x34);
1297 mv_dump_mem(mmio_base+0xf00, 0x4);
1298 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1299 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
Dan Alonid220c372006-04-10 23:20:22 -07001300 hc_base = mv_hc_base(mmio_base, hc);
Brett Russ31961942005-09-30 01:36:00 -04001301 DPRINTK("HC regs (HC %i):\n", hc);
1302 mv_dump_mem(hc_base, 0x1c);
1303 }
1304 for (p = start_port; p < start_port + num_ports; p++) {
1305 port_base = mv_port_base(mmio_base, p);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001306 DPRINTK("EDMA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001307 mv_dump_mem(port_base, 0x54);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001308 DPRINTK("SATA regs (port %i):\n", p);
Brett Russ31961942005-09-30 01:36:00 -04001309 mv_dump_mem(port_base+0x300, 0x60);
1310 }
1311#endif
1312}
1313
Brett Russ20f733e2005-09-01 18:26:17 -04001314static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1315{
1316 unsigned int ofs;
1317
1318 switch (sc_reg_in) {
1319 case SCR_STATUS:
1320 case SCR_CONTROL:
1321 case SCR_ERROR:
Mark Lordcae5a292009-04-06 16:43:45 -04001322 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
Brett Russ20f733e2005-09-01 18:26:17 -04001323 break;
1324 case SCR_ACTIVE:
Mark Lordcae5a292009-04-06 16:43:45 -04001325 ofs = SATA_ACTIVE; /* active is not with the others */
Brett Russ20f733e2005-09-01 18:26:17 -04001326 break;
1327 default:
1328 ofs = 0xffffffffU;
1329 break;
1330 }
1331 return ofs;
1332}
1333
Tejun Heo82ef04f2008-07-31 17:02:40 +09001334static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Brett Russ20f733e2005-09-01 18:26:17 -04001335{
1336 unsigned int ofs = mv_scr_offset(sc_reg_in);
1337
Tejun Heoda3dbb12007-07-16 14:29:40 +09001338 if (ofs != 0xffffffffU) {
Tejun Heo82ef04f2008-07-31 17:02:40 +09001339 *val = readl(mv_ap_base(link->ap) + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001340 return 0;
1341 } else
1342 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001343}
1344
Tejun Heo82ef04f2008-07-31 17:02:40 +09001345static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Brett Russ20f733e2005-09-01 18:26:17 -04001346{
1347 unsigned int ofs = mv_scr_offset(sc_reg_in);
1348
Tejun Heoda3dbb12007-07-16 14:29:40 +09001349 if (ofs != 0xffffffffU) {
Mark Lord20091772009-04-06 15:24:57 -04001350 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1351 if (sc_reg_in == SCR_CONTROL) {
1352 /*
1353 * Workaround for 88SX60x1 FEr SATA#26:
1354 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001355 * COMRESETs have to take care not to accidentally
Mark Lord20091772009-04-06 15:24:57 -04001356 * put the drive to sleep when writing SCR_CONTROL.
1357 * Setting bits 12..15 prevents this problem.
1358 *
1359 * So if we see an outbound COMMRESET, set those bits.
1360 * Ditto for the followup write that clears the reset.
1361 *
1362 * The proprietary driver does this for
1363 * all chip versions, and so do we.
1364 */
1365 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1366 val |= 0xf000;
1367 }
1368 writelfl(val, addr);
Tejun Heoda3dbb12007-07-16 14:29:40 +09001369 return 0;
1370 } else
1371 return -EINVAL;
Brett Russ20f733e2005-09-01 18:26:17 -04001372}
1373
Mark Lordf2738272008-01-26 18:32:29 -05001374static void mv6_dev_config(struct ata_device *adev)
1375{
1376 /*
Mark Lorde49856d2008-04-16 14:59:07 -04001377 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1378 *
1379 * Gen-II does not support NCQ over a port multiplier
1380 * (no FIS-based switching).
Mark Lordf2738272008-01-26 18:32:29 -05001381 */
Mark Lorde49856d2008-04-16 14:59:07 -04001382 if (adev->flags & ATA_DFLAG_NCQ) {
Mark Lord352fab72008-04-19 14:43:42 -04001383 if (sata_pmp_attached(adev->link->ap)) {
Mark Lorde49856d2008-04-16 14:59:07 -04001384 adev->flags &= ~ATA_DFLAG_NCQ;
Joe Perchesa9a79df2011-04-15 15:51:59 -07001385 ata_dev_info(adev,
Mark Lord352fab72008-04-19 14:43:42 -04001386 "NCQ disabled for command-based switching\n");
Mark Lord352fab72008-04-19 14:43:42 -04001387 }
Mark Lorde49856d2008-04-16 14:59:07 -04001388 }
Mark Lordf2738272008-01-26 18:32:29 -05001389}
1390
Mark Lord3e4a1392008-05-02 02:10:02 -04001391static int mv_qc_defer(struct ata_queued_cmd *qc)
1392{
1393 struct ata_link *link = qc->dev->link;
1394 struct ata_port *ap = link->ap;
1395 struct mv_port_priv *pp = ap->private_data;
1396
1397 /*
Mark Lord29d187b2008-05-02 02:15:37 -04001398 * Don't allow new commands if we're in a delayed EH state
1399 * for NCQ and/or FIS-based switching.
1400 */
1401 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1402 return ATA_DEFER_PORT;
Gwendal Grignou159a7ff2009-10-12 15:44:00 -07001403
1404 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1405 * can run concurrently.
1406 * set excl_link when we want to send a PIO command in DMA mode
1407 * or a non-NCQ command in NCQ mode.
1408 * When we receive a command from that link, and there are no
1409 * outstanding commands, mark a flag to clear excl_link and let
1410 * the command go through.
1411 */
1412 if (unlikely(ap->excl_link)) {
1413 if (link == ap->excl_link) {
1414 if (ap->nr_active_links)
1415 return ATA_DEFER_PORT;
1416 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1417 return 0;
1418 } else
1419 return ATA_DEFER_PORT;
1420 }
1421
Mark Lord29d187b2008-05-02 02:15:37 -04001422 /*
Mark Lord3e4a1392008-05-02 02:10:02 -04001423 * If the port is completely idle, then allow the new qc.
1424 */
1425 if (ap->nr_active_links == 0)
1426 return 0;
1427
Tejun Heo4bdee6c2008-08-13 20:24:16 +09001428 /*
1429 * The port is operating in host queuing mode (EDMA) with NCQ
1430 * enabled, allow multiple NCQ commands. EDMA also allows
1431 * queueing multiple DMA commands but libata core currently
1432 * doesn't allow it.
1433 */
1434 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
Gwendal Grignou159a7ff2009-10-12 15:44:00 -07001435 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1436 if (ata_is_ncq(qc->tf.protocol))
1437 return 0;
1438 else {
1439 ap->excl_link = link;
1440 return ATA_DEFER_PORT;
1441 }
1442 }
Tejun Heo4bdee6c2008-08-13 20:24:16 +09001443
Mark Lord3e4a1392008-05-02 02:10:02 -04001444 return ATA_DEFER_PORT;
1445}
1446
Mark Lord08da1752009-02-25 15:13:03 -05001447static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
Mark Lorde49856d2008-04-16 14:59:07 -04001448{
Mark Lord08da1752009-02-25 15:13:03 -05001449 struct mv_port_priv *pp = ap->private_data;
1450 void __iomem *port_mmio;
Mark Lord00f42ea2008-05-02 02:11:45 -04001451
Mark Lord08da1752009-02-25 15:13:03 -05001452 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1453 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1454 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
Mark Lord00f42ea2008-05-02 02:11:45 -04001455
Mark Lord08da1752009-02-25 15:13:03 -05001456 ltmode = *old_ltmode & ~LTMODE_BIT8;
1457 haltcond = *old_haltcond | EDMA_ERR_DEV;
Mark Lord00f42ea2008-05-02 02:11:45 -04001458
1459 if (want_fbs) {
Mark Lord08da1752009-02-25 15:13:03 -05001460 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1461 ltmode = *old_ltmode | LTMODE_BIT8;
Mark Lord4c299ca2008-05-02 02:16:20 -04001462 if (want_ncq)
Mark Lord08da1752009-02-25 15:13:03 -05001463 haltcond &= ~EDMA_ERR_DEV;
Mark Lord4c299ca2008-05-02 02:16:20 -04001464 else
Mark Lord08da1752009-02-25 15:13:03 -05001465 fiscfg |= FISCFG_WAIT_DEV_ERR;
1466 } else {
1467 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
Mark Lorde49856d2008-04-16 14:59:07 -04001468 }
Mark Lord00f42ea2008-05-02 02:11:45 -04001469
Mark Lord08da1752009-02-25 15:13:03 -05001470 port_mmio = mv_ap_base(ap);
Mark Lordcae5a292009-04-06 16:43:45 -04001471 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1472 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1473 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
Mark Lord0c589122008-01-26 18:31:16 -05001474}
Jeff Garzike4e7b892006-01-31 12:18:41 -05001475
Mark Lorddd2890f2008-05-02 02:10:56 -04001476static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1477{
1478 struct mv_host_priv *hpriv = ap->host->private_data;
1479 u32 old, new;
1480
1481 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
Mark Lordcae5a292009-04-06 16:43:45 -04001482 old = readl(hpriv->base + GPIO_PORT_CTL);
Mark Lorddd2890f2008-05-02 02:10:56 -04001483 if (want_ncq)
1484 new = old | (1 << 22);
1485 else
1486 new = old & ~(1 << 22);
1487 if (new != old)
Mark Lordcae5a292009-04-06 16:43:45 -04001488 writel(new, hpriv->base + GPIO_PORT_CTL);
Mark Lorddd2890f2008-05-02 02:10:56 -04001489}
1490
Mark Lordc01e8a22009-02-25 15:14:48 -05001491/**
Mark Lord40f21b12009-03-10 18:51:04 -04001492 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1493 * @ap: Port being initialized
Mark Lordc01e8a22009-02-25 15:14:48 -05001494 *
1495 * There are two DMA modes on these chips: basic DMA, and EDMA.
1496 *
1497 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1498 * of basic DMA on the GEN_IIE versions of the chips.
1499 *
1500 * This bit survives EDMA resets, and must be set for basic DMA
1501 * to function, and should be cleared when EDMA is active.
1502 */
1503static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1504{
1505 struct mv_port_priv *pp = ap->private_data;
1506 u32 new, *old = &pp->cached.unknown_rsvd;
1507
1508 if (enable_bmdma)
1509 new = *old | 1;
1510 else
1511 new = *old & ~1;
Mark Lordcae5a292009-04-06 16:43:45 -04001512 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
Mark Lordc01e8a22009-02-25 15:14:48 -05001513}
1514
Mark Lord000b3442009-03-15 11:33:19 -04001515/*
1516 * SOC chips have an issue whereby the HDD LEDs don't always blink
1517 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1518 * of the SOC takes care of it, generating a steady blink rate when
1519 * any drive on the chip is active.
1520 *
1521 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1522 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1523 *
1524 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1525 * LED operation works then, and provides better (more accurate) feedback.
1526 *
1527 * Note that this code assumes that an SOC never has more than one HC onboard.
1528 */
1529static void mv_soc_led_blink_enable(struct ata_port *ap)
1530{
1531 struct ata_host *host = ap->host;
1532 struct mv_host_priv *hpriv = host->private_data;
1533 void __iomem *hc_mmio;
1534 u32 led_ctrl;
1535
1536 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1537 return;
1538 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1539 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
Mark Lordcae5a292009-04-06 16:43:45 -04001540 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1541 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
Mark Lord000b3442009-03-15 11:33:19 -04001542}
1543
1544static void mv_soc_led_blink_disable(struct ata_port *ap)
1545{
1546 struct ata_host *host = ap->host;
1547 struct mv_host_priv *hpriv = host->private_data;
1548 void __iomem *hc_mmio;
1549 u32 led_ctrl;
1550 unsigned int port;
1551
1552 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1553 return;
1554
1555 /* disable led-blink only if no ports are using NCQ */
1556 for (port = 0; port < hpriv->n_ports; port++) {
1557 struct ata_port *this_ap = host->ports[port];
1558 struct mv_port_priv *pp = this_ap->private_data;
1559
1560 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1561 return;
1562 }
1563
1564 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1565 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
Mark Lordcae5a292009-04-06 16:43:45 -04001566 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1567 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
Mark Lord000b3442009-03-15 11:33:19 -04001568}
1569
Mark Lord00b81232009-01-30 18:47:51 -05001570static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
Jeff Garzike4e7b892006-01-31 12:18:41 -05001571{
1572 u32 cfg;
Mark Lorde12bef52008-03-31 19:33:56 -04001573 struct mv_port_priv *pp = ap->private_data;
1574 struct mv_host_priv *hpriv = ap->host->private_data;
1575 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001576
1577 /* set up non-NCQ EDMA configuration */
1578 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
Mark Lordd16ab3f2009-02-25 15:17:43 -05001579 pp->pp_flags &=
1580 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001581
1582 if (IS_GEN_I(hpriv))
1583 cfg |= (1 << 8); /* enab config burst size mask */
1584
Mark Lorddd2890f2008-05-02 02:10:56 -04001585 else if (IS_GEN_II(hpriv)) {
Jeff Garzike4e7b892006-01-31 12:18:41 -05001586 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
Mark Lorddd2890f2008-05-02 02:10:56 -04001587 mv_60x1_errata_sata25(ap, want_ncq);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001588
Mark Lorddd2890f2008-05-02 02:10:56 -04001589 } else if (IS_GEN_IIE(hpriv)) {
Mark Lord00f42ea2008-05-02 02:11:45 -04001590 int want_fbs = sata_pmp_attached(ap);
1591 /*
1592 * Possible future enhancement:
1593 *
1594 * The chip can use FBS with non-NCQ, if we allow it,
1595 * But first we need to have the error handling in place
1596 * for this mode (datasheet section 7.3.15.4.2.3).
1597 * So disallow non-NCQ FBS for now.
1598 */
1599 want_fbs &= want_ncq;
1600
Mark Lord08da1752009-02-25 15:13:03 -05001601 mv_config_fbs(ap, want_ncq, want_fbs);
Mark Lord00f42ea2008-05-02 02:11:45 -04001602
1603 if (want_fbs) {
1604 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1605 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1606 }
1607
Jeff Garzike728eab2007-02-25 02:53:41 -05001608 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
Mark Lord00b81232009-01-30 18:47:51 -05001609 if (want_edma) {
1610 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1611 if (!IS_SOC(hpriv))
1612 cfg |= (1 << 18); /* enab early completion */
1613 }
Mark Lord616d4a92008-05-02 02:08:32 -04001614 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1615 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
Mark Lordc01e8a22009-02-25 15:14:48 -05001616 mv_bmdma_enable_iie(ap, !want_edma);
Mark Lord000b3442009-03-15 11:33:19 -04001617
1618 if (IS_SOC(hpriv)) {
1619 if (want_ncq)
1620 mv_soc_led_blink_enable(ap);
1621 else
1622 mv_soc_led_blink_disable(ap);
1623 }
Jeff Garzike4e7b892006-01-31 12:18:41 -05001624 }
1625
Mark Lord72109162008-01-26 18:31:33 -05001626 if (want_ncq) {
1627 cfg |= EDMA_CFG_NCQ;
1628 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
Mark Lord00b81232009-01-30 18:47:51 -05001629 }
Mark Lord72109162008-01-26 18:31:33 -05001630
Mark Lordcae5a292009-04-06 16:43:45 -04001631 writelfl(cfg, port_mmio + EDMA_CFG);
Jeff Garzike4e7b892006-01-31 12:18:41 -05001632}
1633
Mark Lordda2fa9b2008-01-26 18:32:45 -05001634static void mv_port_free_dma_mem(struct ata_port *ap)
1635{
1636 struct mv_host_priv *hpriv = ap->host->private_data;
1637 struct mv_port_priv *pp = ap->private_data;
Mark Lordeb73d552008-01-29 13:24:00 -05001638 int tag;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001639
1640 if (pp->crqb) {
1641 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1642 pp->crqb = NULL;
1643 }
1644 if (pp->crpb) {
1645 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1646 pp->crpb = NULL;
1647 }
Mark Lordeb73d552008-01-29 13:24:00 -05001648 /*
1649 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1650 * For later hardware, we have one unique sg_tbl per NCQ tag.
1651 */
1652 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1653 if (pp->sg_tbl[tag]) {
1654 if (tag == 0 || !IS_GEN_I(hpriv))
1655 dma_pool_free(hpriv->sg_tbl_pool,
1656 pp->sg_tbl[tag],
1657 pp->sg_tbl_dma[tag]);
1658 pp->sg_tbl[tag] = NULL;
1659 }
Mark Lordda2fa9b2008-01-26 18:32:45 -05001660 }
1661}
1662
Brett Russ05b308e2005-10-05 17:08:53 -04001663/**
1664 * mv_port_start - Port specific init/start routine.
1665 * @ap: ATA channel to manipulate
1666 *
1667 * Allocate and point to DMA memory, init port private memory,
1668 * zero indices.
1669 *
1670 * LOCKING:
1671 * Inherited from caller.
1672 */
Brett Russ31961942005-09-30 01:36:00 -04001673static int mv_port_start(struct ata_port *ap)
1674{
Jeff Garzikcca39742006-08-24 03:19:22 -04001675 struct device *dev = ap->host->dev;
1676 struct mv_host_priv *hpriv = ap->host->private_data;
Brett Russ31961942005-09-30 01:36:00 -04001677 struct mv_port_priv *pp;
Mark Lord933cb8e2009-04-06 12:30:43 -04001678 unsigned long flags;
James Bottomleydde20202008-02-19 11:36:56 +01001679 int tag;
Brett Russ31961942005-09-30 01:36:00 -04001680
Tejun Heo24dc5f32007-01-20 16:00:28 +09001681 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Jeff Garzik6037d6b2005-11-04 22:08:00 -05001682 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001683 return -ENOMEM;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001684 ap->private_data = pp;
Brett Russ31961942005-09-30 01:36:00 -04001685
Mark Lordda2fa9b2008-01-26 18:32:45 -05001686 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1687 if (!pp->crqb)
1688 return -ENOMEM;
1689 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001690
Mark Lordda2fa9b2008-01-26 18:32:45 -05001691 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1692 if (!pp->crpb)
1693 goto out_port_free_dma_mem;
1694 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
Brett Russ31961942005-09-30 01:36:00 -04001695
Mark Lord3bd0a702008-06-18 12:11:16 -04001696 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1697 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1698 ap->flags |= ATA_FLAG_AN;
Mark Lordeb73d552008-01-29 13:24:00 -05001699 /*
1700 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1701 * For later hardware, we need one unique sg_tbl per NCQ tag.
1702 */
1703 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1704 if (tag == 0 || !IS_GEN_I(hpriv)) {
1705 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1706 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1707 if (!pp->sg_tbl[tag])
1708 goto out_port_free_dma_mem;
1709 } else {
1710 pp->sg_tbl[tag] = pp->sg_tbl[0];
1711 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1712 }
1713 }
Mark Lord933cb8e2009-04-06 12:30:43 -04001714
1715 spin_lock_irqsave(ap->lock, flags);
Mark Lord08da1752009-02-25 15:13:03 -05001716 mv_save_cached_regs(ap);
Mark Lord66e57a22009-01-30 18:52:58 -05001717 mv_edma_cfg(ap, 0, 0);
Mark Lord933cb8e2009-04-06 12:30:43 -04001718 spin_unlock_irqrestore(ap->lock, flags);
1719
Brett Russ31961942005-09-30 01:36:00 -04001720 return 0;
Mark Lordda2fa9b2008-01-26 18:32:45 -05001721
1722out_port_free_dma_mem:
1723 mv_port_free_dma_mem(ap);
1724 return -ENOMEM;
Brett Russ31961942005-09-30 01:36:00 -04001725}
1726
Brett Russ05b308e2005-10-05 17:08:53 -04001727/**
1728 * mv_port_stop - Port specific cleanup/stop routine.
1729 * @ap: ATA channel to manipulate
1730 *
1731 * Stop DMA, cleanup port memory.
1732 *
1733 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04001734 * This routine uses the host lock to protect the DMA stop.
Brett Russ05b308e2005-10-05 17:08:53 -04001735 */
Brett Russ31961942005-09-30 01:36:00 -04001736static void mv_port_stop(struct ata_port *ap)
1737{
Mark Lord933cb8e2009-04-06 12:30:43 -04001738 unsigned long flags;
1739
1740 spin_lock_irqsave(ap->lock, flags);
Mark Lorde12bef52008-03-31 19:33:56 -04001741 mv_stop_edma(ap);
Mark Lord88e675e2008-05-17 13:36:30 -04001742 mv_enable_port_irqs(ap, 0);
Mark Lord933cb8e2009-04-06 12:30:43 -04001743 spin_unlock_irqrestore(ap->lock, flags);
Mark Lordda2fa9b2008-01-26 18:32:45 -05001744 mv_port_free_dma_mem(ap);
Brett Russ31961942005-09-30 01:36:00 -04001745}
1746
Brett Russ05b308e2005-10-05 17:08:53 -04001747/**
1748 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1749 * @qc: queued command whose SG list to source from
1750 *
1751 * Populate the SG list and mark the last entry.
1752 *
1753 * LOCKING:
1754 * Inherited from caller.
1755 */
Jeff Garzik6c087722007-10-12 00:16:23 -04001756static void mv_fill_sg(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04001757{
1758 struct mv_port_priv *pp = qc->ap->private_data;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001759 struct scatterlist *sg;
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001760 struct mv_sg *mv_sg, *last_sg = NULL;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001761 unsigned int si;
Brett Russ31961942005-09-30 01:36:00 -04001762
Mark Lordeb73d552008-01-29 13:24:00 -05001763 mv_sg = pp->sg_tbl[qc->tag];
Tejun Heoff2aeb12007-12-05 16:43:11 +09001764 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikd88184f2007-02-26 01:26:06 -05001765 dma_addr_t addr = sg_dma_address(sg);
1766 u32 sg_len = sg_dma_len(sg);
Brett Russ31961942005-09-30 01:36:00 -04001767
Olof Johansson4007b492007-10-02 20:45:27 -05001768 while (sg_len) {
1769 u32 offset = addr & 0xffff;
1770 u32 len = sg_len;
Brett Russ31961942005-09-30 01:36:00 -04001771
Mark Lord32cd11a2009-02-01 16:50:32 -05001772 if (offset + len > 0x10000)
Olof Johansson4007b492007-10-02 20:45:27 -05001773 len = 0x10000 - offset;
Jeff Garzik972c26b2005-10-18 22:14:54 -04001774
Olof Johansson4007b492007-10-02 20:45:27 -05001775 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1776 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
Jeff Garzik6c087722007-10-12 00:16:23 -04001777 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
Mark Lord32cd11a2009-02-01 16:50:32 -05001778 mv_sg->reserved = 0;
Olof Johansson4007b492007-10-02 20:45:27 -05001779
1780 sg_len -= len;
1781 addr += len;
1782
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001783 last_sg = mv_sg;
Olof Johansson4007b492007-10-02 20:45:27 -05001784 mv_sg++;
Olof Johansson4007b492007-10-02 20:45:27 -05001785 }
Brett Russ31961942005-09-30 01:36:00 -04001786 }
Jeff Garzik3be6cbd2007-10-18 16:21:18 -04001787
1788 if (likely(last_sg))
1789 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
Mark Lord32cd11a2009-02-01 16:50:32 -05001790 mb(); /* ensure data structure is visible to the chipset */
Brett Russ31961942005-09-30 01:36:00 -04001791}
1792
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001793static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
Brett Russ31961942005-09-30 01:36:00 -04001794{
Mark Lord559eeda2006-05-19 16:40:15 -04001795 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
Brett Russ31961942005-09-30 01:36:00 -04001796 (last ? CRQB_CMD_LAST : 0);
Mark Lord559eeda2006-05-19 16:40:15 -04001797 *cmdw = cpu_to_le16(tmp);
Brett Russ31961942005-09-30 01:36:00 -04001798}
1799
Brett Russ05b308e2005-10-05 17:08:53 -04001800/**
Mark Lordda142652009-01-30 18:51:54 -05001801 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1802 * @ap: Port associated with this ATA transaction.
1803 *
1804 * We need this only for ATAPI bmdma transactions,
1805 * as otherwise we experience spurious interrupts
1806 * after libata-sff handles the bmdma interrupts.
1807 */
1808static void mv_sff_irq_clear(struct ata_port *ap)
1809{
1810 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1811}
1812
1813/**
1814 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1815 * @qc: queued command to check for chipset/DMA compatibility.
1816 *
1817 * The bmdma engines cannot handle speculative data sizes
1818 * (bytecount under/over flow). So only allow DMA for
1819 * data transfer commands with known data sizes.
1820 *
1821 * LOCKING:
1822 * Inherited from caller.
1823 */
1824static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1825{
1826 struct scsi_cmnd *scmd = qc->scsicmd;
1827
1828 if (scmd) {
1829 switch (scmd->cmnd[0]) {
1830 case READ_6:
1831 case READ_10:
1832 case READ_12:
1833 case WRITE_6:
1834 case WRITE_10:
1835 case WRITE_12:
1836 case GPCMD_READ_CD:
1837 case GPCMD_SEND_DVD_STRUCTURE:
1838 case GPCMD_SEND_CUE_SHEET:
1839 return 0; /* DMA is safe */
1840 }
1841 }
1842 return -EOPNOTSUPP; /* use PIO instead */
1843}
1844
1845/**
1846 * mv_bmdma_setup - Set up BMDMA transaction
1847 * @qc: queued command to prepare DMA for.
1848 *
1849 * LOCKING:
1850 * Inherited from caller.
1851 */
1852static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1853{
1854 struct ata_port *ap = qc->ap;
1855 void __iomem *port_mmio = mv_ap_base(ap);
1856 struct mv_port_priv *pp = ap->private_data;
1857
1858 mv_fill_sg(qc);
1859
1860 /* clear all DMA cmd bits */
Mark Lordcae5a292009-04-06 16:43:45 -04001861 writel(0, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001862
1863 /* load PRD table addr. */
1864 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
Mark Lordcae5a292009-04-06 16:43:45 -04001865 port_mmio + BMDMA_PRD_HIGH);
Mark Lordda142652009-01-30 18:51:54 -05001866 writelfl(pp->sg_tbl_dma[qc->tag],
Mark Lordcae5a292009-04-06 16:43:45 -04001867 port_mmio + BMDMA_PRD_LOW);
Mark Lordda142652009-01-30 18:51:54 -05001868
1869 /* issue r/w command */
1870 ap->ops->sff_exec_command(ap, &qc->tf);
1871}
1872
1873/**
1874 * mv_bmdma_start - Start a BMDMA transaction
1875 * @qc: queued command to start DMA on.
1876 *
1877 * LOCKING:
1878 * Inherited from caller.
1879 */
1880static void mv_bmdma_start(struct ata_queued_cmd *qc)
1881{
1882 struct ata_port *ap = qc->ap;
1883 void __iomem *port_mmio = mv_ap_base(ap);
1884 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1885 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1886
1887 /* start host DMA transaction */
Mark Lordcae5a292009-04-06 16:43:45 -04001888 writelfl(cmd, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001889}
1890
1891/**
1892 * mv_bmdma_stop - Stop BMDMA transfer
1893 * @qc: queued command to stop DMA on.
1894 *
1895 * Clears the ATA_DMA_START flag in the bmdma control register
1896 *
1897 * LOCKING:
1898 * Inherited from caller.
1899 */
Mark Lord44b73382010-08-19 21:40:44 -04001900static void mv_bmdma_stop_ap(struct ata_port *ap)
Mark Lordda142652009-01-30 18:51:54 -05001901{
Mark Lordda142652009-01-30 18:51:54 -05001902 void __iomem *port_mmio = mv_ap_base(ap);
1903 u32 cmd;
1904
1905 /* clear start/stop bit */
Mark Lordcae5a292009-04-06 16:43:45 -04001906 cmd = readl(port_mmio + BMDMA_CMD);
Mark Lord44b73382010-08-19 21:40:44 -04001907 if (cmd & ATA_DMA_START) {
1908 cmd &= ~ATA_DMA_START;
1909 writelfl(cmd, port_mmio + BMDMA_CMD);
Mark Lordda142652009-01-30 18:51:54 -05001910
Mark Lord44b73382010-08-19 21:40:44 -04001911 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1912 ata_sff_dma_pause(ap);
1913 }
1914}
1915
1916static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1917{
1918 mv_bmdma_stop_ap(qc->ap);
Mark Lordda142652009-01-30 18:51:54 -05001919}
1920
1921/**
1922 * mv_bmdma_status - Read BMDMA status
1923 * @ap: port for which to retrieve DMA status.
1924 *
1925 * Read and return equivalent of the sff BMDMA status register.
1926 *
1927 * LOCKING:
1928 * Inherited from caller.
1929 */
1930static u8 mv_bmdma_status(struct ata_port *ap)
1931{
1932 void __iomem *port_mmio = mv_ap_base(ap);
1933 u32 reg, status;
1934
1935 /*
1936 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1937 * and the ATA_DMA_INTR bit doesn't exist.
1938 */
Mark Lordcae5a292009-04-06 16:43:45 -04001939 reg = readl(port_mmio + BMDMA_STATUS);
Mark Lordda142652009-01-30 18:51:54 -05001940 if (reg & ATA_DMA_ACTIVE)
1941 status = ATA_DMA_ACTIVE;
Mark Lord44b73382010-08-19 21:40:44 -04001942 else if (reg & ATA_DMA_ERR)
Mark Lordda142652009-01-30 18:51:54 -05001943 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
Mark Lord44b73382010-08-19 21:40:44 -04001944 else {
1945 /*
1946 * Just because DMA_ACTIVE is 0 (DMA completed),
1947 * this does _not_ mean the device is "done".
1948 * So we should not yet be signalling ATA_DMA_INTR
1949 * in some cases. Eg. DSM/TRIM, and perhaps others.
1950 */
1951 mv_bmdma_stop_ap(ap);
1952 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1953 status = 0;
1954 else
1955 status = ATA_DMA_INTR;
1956 }
Mark Lordda142652009-01-30 18:51:54 -05001957 return status;
1958}
1959
Mark Lord299b3f82009-04-13 11:29:34 -04001960static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1961{
1962 struct ata_taskfile *tf = &qc->tf;
1963 /*
1964 * Workaround for 88SX60x1 FEr SATA#24.
1965 *
1966 * Chip may corrupt WRITEs if multi_count >= 4kB.
1967 * Note that READs are unaffected.
1968 *
1969 * It's not clear if this errata really means "4K bytes",
1970 * or if it always happens for multi_count > 7
1971 * regardless of device sector_size.
1972 *
1973 * So, for safety, any write with multi_count > 7
1974 * gets converted here into a regular PIO write instead:
1975 */
1976 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1977 if (qc->dev->multi_count > 7) {
1978 switch (tf->command) {
1979 case ATA_CMD_WRITE_MULTI:
1980 tf->command = ATA_CMD_PIO_WRITE;
1981 break;
1982 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1983 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1984 /* fall through */
1985 case ATA_CMD_WRITE_MULTI_EXT:
1986 tf->command = ATA_CMD_PIO_WRITE_EXT;
1987 break;
1988 }
1989 }
1990 }
1991}
1992
Mark Lordda142652009-01-30 18:51:54 -05001993/**
Brett Russ05b308e2005-10-05 17:08:53 -04001994 * mv_qc_prep - Host specific command preparation.
1995 * @qc: queued command to prepare
1996 *
1997 * This routine simply redirects to the general purpose routine
1998 * if command is not DMA. Else, it handles prep of the CRQB
1999 * (command request block), does some sanity checking, and calls
2000 * the SG load routine.
2001 *
2002 * LOCKING:
2003 * Inherited from caller.
2004 */
Brett Russ31961942005-09-30 01:36:00 -04002005static void mv_qc_prep(struct ata_queued_cmd *qc)
2006{
2007 struct ata_port *ap = qc->ap;
2008 struct mv_port_priv *pp = ap->private_data;
Mark Lorde1469872006-05-22 19:02:03 -04002009 __le16 *cw;
Mark Lord8d2b4502009-04-13 11:27:18 -04002010 struct ata_taskfile *tf = &qc->tf;
Brett Russ31961942005-09-30 01:36:00 -04002011 u16 flags = 0;
Mark Lorda6432432006-05-19 16:36:36 -04002012 unsigned in_index;
Brett Russ31961942005-09-30 01:36:00 -04002013
Mark Lord299b3f82009-04-13 11:29:34 -04002014 switch (tf->protocol) {
2015 case ATA_PROT_DMA:
Mark Lord44b73382010-08-19 21:40:44 -04002016 if (tf->command == ATA_CMD_DSM)
2017 return;
2018 /* fall-thru */
Mark Lord299b3f82009-04-13 11:29:34 -04002019 case ATA_PROT_NCQ:
2020 break; /* continue below */
2021 case ATA_PROT_PIO:
2022 mv_rw_multi_errata_sata24(qc);
Brett Russ31961942005-09-30 01:36:00 -04002023 return;
Mark Lord299b3f82009-04-13 11:29:34 -04002024 default:
2025 return;
2026 }
Brett Russ20f733e2005-09-01 18:26:17 -04002027
Brett Russ31961942005-09-30 01:36:00 -04002028 /* Fill in command request block
2029 */
Mark Lord8d2b4502009-04-13 11:27:18 -04002030 if (!(tf->flags & ATA_TFLAG_WRITE))
Brett Russ31961942005-09-30 01:36:00 -04002031 flags |= CRQB_FLAG_READ;
Tejun Heobeec7db2006-02-11 19:11:13 +09002032 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Brett Russ31961942005-09-30 01:36:00 -04002033 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04002034 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Brett Russ31961942005-09-30 01:36:00 -04002035
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002036 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04002037 in_index = pp->req_idx;
Brett Russ31961942005-09-30 01:36:00 -04002038
Mark Lorda6432432006-05-19 16:36:36 -04002039 pp->crqb[in_index].sg_addr =
Mark Lordeb73d552008-01-29 13:24:00 -05002040 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
Mark Lorda6432432006-05-19 16:36:36 -04002041 pp->crqb[in_index].sg_addr_hi =
Mark Lordeb73d552008-01-29 13:24:00 -05002042 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Mark Lorda6432432006-05-19 16:36:36 -04002043 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2044
2045 cw = &pp->crqb[in_index].ata_cmd[0];
Brett Russ31961942005-09-30 01:36:00 -04002046
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002047 /* Sadly, the CRQB cannot accommodate all registers--there are
Brett Russ31961942005-09-30 01:36:00 -04002048 * only 11 bytes...so we must pick and choose required
2049 * registers based on the command. So, we drop feature and
2050 * hob_feature for [RW] DMA commands, but they are needed for
Mark Lordcd12e1f2009-01-19 18:06:28 -05002051 * NCQ. NCQ will drop hob_nsect, which is not needed there
2052 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
Brett Russ31961942005-09-30 01:36:00 -04002053 */
2054 switch (tf->command) {
2055 case ATA_CMD_READ:
2056 case ATA_CMD_READ_EXT:
2057 case ATA_CMD_WRITE:
2058 case ATA_CMD_WRITE_EXT:
Jens Axboec15d85c2006-02-15 15:59:25 +01002059 case ATA_CMD_WRITE_FUA_EXT:
Brett Russ31961942005-09-30 01:36:00 -04002060 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2061 break;
Brett Russ31961942005-09-30 01:36:00 -04002062 case ATA_CMD_FPDMA_READ:
2063 case ATA_CMD_FPDMA_WRITE:
Jeff Garzik8b260242005-11-12 12:32:50 -05002064 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
Brett Russ31961942005-09-30 01:36:00 -04002065 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2066 break;
Brett Russ31961942005-09-30 01:36:00 -04002067 default:
2068 /* The only other commands EDMA supports in non-queued and
2069 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2070 * of which are defined/used by Linux. If we get here, this
2071 * driver needs work.
2072 *
2073 * FIXME: modify libata to give qc_prep a return value and
2074 * return error here.
2075 */
2076 BUG_ON(tf->command);
2077 break;
2078 }
2079 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2080 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2081 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2082 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2083 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2084 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2085 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2086 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2087 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2088
Jeff Garzike4e7b892006-01-31 12:18:41 -05002089 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
Brett Russ31961942005-09-30 01:36:00 -04002090 return;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002091 mv_fill_sg(qc);
2092}
2093
2094/**
2095 * mv_qc_prep_iie - Host specific command preparation.
2096 * @qc: queued command to prepare
2097 *
2098 * This routine simply redirects to the general purpose routine
2099 * if command is not DMA. Else, it handles prep of the CRQB
2100 * (command request block), does some sanity checking, and calls
2101 * the SG load routine.
2102 *
2103 * LOCKING:
2104 * Inherited from caller.
2105 */
2106static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2107{
2108 struct ata_port *ap = qc->ap;
2109 struct mv_port_priv *pp = ap->private_data;
2110 struct mv_crqb_iie *crqb;
Mark Lord8d2b4502009-04-13 11:27:18 -04002111 struct ata_taskfile *tf = &qc->tf;
Mark Lorda6432432006-05-19 16:36:36 -04002112 unsigned in_index;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002113 u32 flags = 0;
2114
Mark Lord8d2b4502009-04-13 11:27:18 -04002115 if ((tf->protocol != ATA_PROT_DMA) &&
2116 (tf->protocol != ATA_PROT_NCQ))
Jeff Garzike4e7b892006-01-31 12:18:41 -05002117 return;
Mark Lord44b73382010-08-19 21:40:44 -04002118 if (tf->command == ATA_CMD_DSM)
2119 return; /* use bmdma for this */
Jeff Garzike4e7b892006-01-31 12:18:41 -05002120
Mark Lorde12bef52008-03-31 19:33:56 -04002121 /* Fill in Gen IIE command request block */
Mark Lord8d2b4502009-04-13 11:27:18 -04002122 if (!(tf->flags & ATA_TFLAG_WRITE))
Jeff Garzike4e7b892006-01-31 12:18:41 -05002123 flags |= CRQB_FLAG_READ;
2124
Tejun Heobeec7db2006-02-11 19:11:13 +09002125 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
Jeff Garzike4e7b892006-01-31 12:18:41 -05002126 flags |= qc->tag << CRQB_TAG_SHIFT;
Mark Lord8c0aeb42008-01-26 18:31:48 -05002127 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
Mark Lorde49856d2008-04-16 14:59:07 -04002128 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
Jeff Garzike4e7b892006-01-31 12:18:41 -05002129
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002130 /* get current queue index from software */
Mark Lordfcfb1f72008-04-19 15:06:40 -04002131 in_index = pp->req_idx;
Mark Lorda6432432006-05-19 16:36:36 -04002132
2133 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
Mark Lordeb73d552008-01-29 13:24:00 -05002134 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2135 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
Jeff Garzike4e7b892006-01-31 12:18:41 -05002136 crqb->flags = cpu_to_le32(flags);
2137
Jeff Garzike4e7b892006-01-31 12:18:41 -05002138 crqb->ata_cmd[0] = cpu_to_le32(
2139 (tf->command << 16) |
2140 (tf->feature << 24)
2141 );
2142 crqb->ata_cmd[1] = cpu_to_le32(
2143 (tf->lbal << 0) |
2144 (tf->lbam << 8) |
2145 (tf->lbah << 16) |
2146 (tf->device << 24)
2147 );
2148 crqb->ata_cmd[2] = cpu_to_le32(
2149 (tf->hob_lbal << 0) |
2150 (tf->hob_lbam << 8) |
2151 (tf->hob_lbah << 16) |
2152 (tf->hob_feature << 24)
2153 );
2154 crqb->ata_cmd[3] = cpu_to_le32(
2155 (tf->nsect << 0) |
2156 (tf->hob_nsect << 8)
2157 );
2158
2159 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2160 return;
Brett Russ31961942005-09-30 01:36:00 -04002161 mv_fill_sg(qc);
2162}
2163
Brett Russ05b308e2005-10-05 17:08:53 -04002164/**
Mark Lordd16ab3f2009-02-25 15:17:43 -05002165 * mv_sff_check_status - fetch device status, if valid
2166 * @ap: ATA port to fetch status from
2167 *
2168 * When using command issue via mv_qc_issue_fis(),
2169 * the initial ATA_BUSY state does not show up in the
2170 * ATA status (shadow) register. This can confuse libata!
2171 *
2172 * So we have a hook here to fake ATA_BUSY for that situation,
2173 * until the first time a BUSY, DRQ, or ERR bit is seen.
2174 *
2175 * The rest of the time, it simply returns the ATA status register.
2176 */
2177static u8 mv_sff_check_status(struct ata_port *ap)
2178{
2179 u8 stat = ioread8(ap->ioaddr.status_addr);
2180 struct mv_port_priv *pp = ap->private_data;
2181
2182 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2183 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2184 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2185 else
2186 stat = ATA_BUSY;
2187 }
2188 return stat;
2189}
2190
2191/**
Mark Lord70f8b792009-02-25 15:19:20 -05002192 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2193 * @fis: fis to be sent
2194 * @nwords: number of 32-bit words in the fis
2195 */
2196static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2197{
2198 void __iomem *port_mmio = mv_ap_base(ap);
2199 u32 ifctl, old_ifctl, ifstat;
2200 int i, timeout = 200, final_word = nwords - 1;
2201
2202 /* Initiate FIS transmission mode */
Mark Lordcae5a292009-04-06 16:43:45 -04002203 old_ifctl = readl(port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002204 ifctl = 0x100 | (old_ifctl & 0xf);
Mark Lordcae5a292009-04-06 16:43:45 -04002205 writelfl(ifctl, port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002206
2207 /* Send all words of the FIS except for the final word */
2208 for (i = 0; i < final_word; ++i)
Mark Lordcae5a292009-04-06 16:43:45 -04002209 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
Mark Lord70f8b792009-02-25 15:19:20 -05002210
2211 /* Flag end-of-transmission, and then send the final word */
Mark Lordcae5a292009-04-06 16:43:45 -04002212 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2213 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
Mark Lord70f8b792009-02-25 15:19:20 -05002214
2215 /*
2216 * Wait for FIS transmission to complete.
2217 * This typically takes just a single iteration.
2218 */
2219 do {
Mark Lordcae5a292009-04-06 16:43:45 -04002220 ifstat = readl(port_mmio + SATA_IFSTAT);
Mark Lord70f8b792009-02-25 15:19:20 -05002221 } while (!(ifstat & 0x1000) && --timeout);
2222
2223 /* Restore original port configuration */
Mark Lordcae5a292009-04-06 16:43:45 -04002224 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
Mark Lord70f8b792009-02-25 15:19:20 -05002225
2226 /* See if it worked */
2227 if ((ifstat & 0x3000) != 0x1000) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07002228 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2229 __func__, ifstat);
Mark Lord70f8b792009-02-25 15:19:20 -05002230 return AC_ERR_OTHER;
2231 }
2232 return 0;
2233}
2234
2235/**
2236 * mv_qc_issue_fis - Issue a command directly as a FIS
2237 * @qc: queued command to start
2238 *
2239 * Note that the ATA shadow registers are not updated
2240 * after command issue, so the device will appear "READY"
2241 * if polled, even while it is BUSY processing the command.
2242 *
2243 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2244 *
2245 * Note: we don't get updated shadow regs on *completion*
2246 * of non-data commands. So avoid sending them via this function,
2247 * as they will appear to have completed immediately.
2248 *
2249 * GEN_IIE has special registers that we could get the result tf from,
2250 * but earlier chipsets do not. For now, we ignore those registers.
2251 */
2252static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2253{
2254 struct ata_port *ap = qc->ap;
2255 struct mv_port_priv *pp = ap->private_data;
2256 struct ata_link *link = qc->dev->link;
2257 u32 fis[5];
2258 int err = 0;
2259
2260 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
Thiago Farina4c4a90f2009-11-08 14:30:57 -05002261 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
Mark Lord70f8b792009-02-25 15:19:20 -05002262 if (err)
2263 return err;
2264
2265 switch (qc->tf.protocol) {
2266 case ATAPI_PROT_PIO:
2267 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2268 /* fall through */
2269 case ATAPI_PROT_NODATA:
2270 ap->hsm_task_state = HSM_ST_FIRST;
2271 break;
2272 case ATA_PROT_PIO:
2273 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2274 if (qc->tf.flags & ATA_TFLAG_WRITE)
2275 ap->hsm_task_state = HSM_ST_FIRST;
2276 else
2277 ap->hsm_task_state = HSM_ST;
2278 break;
2279 default:
2280 ap->hsm_task_state = HSM_ST_LAST;
2281 break;
2282 }
2283
2284 if (qc->tf.flags & ATA_TFLAG_POLLING)
Gwendal Grignouea3c6452010-08-31 16:20:36 -07002285 ata_sff_queue_pio_task(link, 0);
Mark Lord70f8b792009-02-25 15:19:20 -05002286 return 0;
2287}
2288
2289/**
Brett Russ05b308e2005-10-05 17:08:53 -04002290 * mv_qc_issue - Initiate a command to the host
2291 * @qc: queued command to start
2292 *
2293 * This routine simply redirects to the general purpose routine
2294 * if command is not DMA. Else, it sanity checks our local
2295 * caches of the request producer/consumer indices then enables
2296 * DMA and bumps the request producer index.
2297 *
2298 * LOCKING:
2299 * Inherited from caller.
2300 */
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002301static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
Brett Russ31961942005-09-30 01:36:00 -04002302{
Mark Lordf48765c2009-01-30 18:48:41 -05002303 static int limit_warnings = 10;
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002304 struct ata_port *ap = qc->ap;
2305 void __iomem *port_mmio = mv_ap_base(ap);
2306 struct mv_port_priv *pp = ap->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002307 u32 in_index;
Mark Lord42ed8932009-02-25 15:15:39 -05002308 unsigned int port_irqs;
Brett Russ31961942005-09-30 01:36:00 -04002309
Mark Lordd16ab3f2009-02-25 15:17:43 -05002310 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2311
Mark Lordf48765c2009-01-30 18:48:41 -05002312 switch (qc->tf.protocol) {
2313 case ATA_PROT_DMA:
Mark Lord44b73382010-08-19 21:40:44 -04002314 if (qc->tf.command == ATA_CMD_DSM) {
2315 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2316 return AC_ERR_OTHER;
2317 break; /* use bmdma for this */
2318 }
2319 /* fall thru */
Mark Lordf48765c2009-01-30 18:48:41 -05002320 case ATA_PROT_NCQ:
2321 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2322 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2323 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2324
2325 /* Write the request in pointer to kick the EDMA to life */
2326 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
Mark Lordcae5a292009-04-06 16:43:45 -04002327 port_mmio + EDMA_REQ_Q_IN_PTR);
Mark Lordf48765c2009-01-30 18:48:41 -05002328 return 0;
2329
2330 case ATA_PROT_PIO:
Mark Lordc6112bd2008-06-18 12:13:02 -04002331 /*
2332 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2333 *
2334 * Someday, we might implement special polling workarounds
2335 * for these, but it all seems rather unnecessary since we
2336 * normally use only DMA for commands which transfer more
2337 * than a single block of data.
2338 *
2339 * Much of the time, this could just work regardless.
2340 * So for now, just log the incident, and allow the attempt.
2341 */
Mark Lordc7843e82008-06-18 21:57:42 -04002342 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
Mark Lordc6112bd2008-06-18 12:13:02 -04002343 --limit_warnings;
Joe Perchesa9a79df2011-04-15 15:51:59 -07002344 ata_link_warn(qc->dev->link, DRV_NAME
2345 ": attempting PIO w/multiple DRQ: "
2346 "this may fail due to h/w errata\n");
Mark Lordc6112bd2008-06-18 12:13:02 -04002347 }
Mark Lordf48765c2009-01-30 18:48:41 -05002348 /* drop through */
Mark Lord42ed8932009-02-25 15:15:39 -05002349 case ATA_PROT_NODATA:
Mark Lordf48765c2009-01-30 18:48:41 -05002350 case ATAPI_PROT_PIO:
Mark Lord42ed8932009-02-25 15:15:39 -05002351 case ATAPI_PROT_NODATA:
2352 if (ap->flags & ATA_FLAG_PIO_POLLING)
2353 qc->tf.flags |= ATA_TFLAG_POLLING;
2354 break;
Brett Russ31961942005-09-30 01:36:00 -04002355 }
Mark Lord42ed8932009-02-25 15:15:39 -05002356
2357 if (qc->tf.flags & ATA_TFLAG_POLLING)
2358 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2359 else
2360 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2361
2362 /*
2363 * We're about to send a non-EDMA capable command to the
2364 * port. Turn off EDMA so there won't be problems accessing
2365 * shadow block, etc registers.
2366 */
2367 mv_stop_edma(ap);
2368 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2369 mv_pmp_select(ap, qc->dev->link->pmp);
Mark Lord70f8b792009-02-25 15:19:20 -05002370
2371 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2372 struct mv_host_priv *hpriv = ap->host->private_data;
2373 /*
2374 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
Mark Lord40f21b12009-03-10 18:51:04 -04002375 *
Mark Lord70f8b792009-02-25 15:19:20 -05002376 * After any NCQ error, the READ_LOG_EXT command
2377 * from libata-eh *must* use mv_qc_issue_fis().
2378 * Otherwise it might fail, due to chip errata.
2379 *
2380 * Rather than special-case it, we'll just *always*
2381 * use this method here for READ_LOG_EXT, making for
2382 * easier testing.
2383 */
2384 if (IS_GEN_II(hpriv))
2385 return mv_qc_issue_fis(qc);
2386 }
Tejun Heo360ff782010-05-10 21:41:42 +02002387 return ata_bmdma_qc_issue(qc);
Brett Russ31961942005-09-30 01:36:00 -04002388}
2389
Mark Lord8f767f82008-04-19 14:53:07 -04002390static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2391{
2392 struct mv_port_priv *pp = ap->private_data;
2393 struct ata_queued_cmd *qc;
2394
2395 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2396 return NULL;
2397 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Tejun Heo3e4ec342010-05-10 21:41:30 +02002398 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2399 return qc;
2400 return NULL;
Mark Lord8f767f82008-04-19 14:53:07 -04002401}
2402
Mark Lord29d187b2008-05-02 02:15:37 -04002403static void mv_pmp_error_handler(struct ata_port *ap)
2404{
2405 unsigned int pmp, pmp_map;
2406 struct mv_port_priv *pp = ap->private_data;
2407
2408 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2409 /*
2410 * Perform NCQ error analysis on failed PMPs
2411 * before we freeze the port entirely.
2412 *
2413 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2414 */
2415 pmp_map = pp->delayed_eh_pmp_map;
2416 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2417 for (pmp = 0; pmp_map != 0; pmp++) {
2418 unsigned int this_pmp = (1 << pmp);
2419 if (pmp_map & this_pmp) {
2420 struct ata_link *link = &ap->pmp_link[pmp];
2421 pmp_map &= ~this_pmp;
2422 ata_eh_analyze_ncq_error(link);
2423 }
2424 }
2425 ata_port_freeze(ap);
2426 }
2427 sata_pmp_error_handler(ap);
2428}
2429
Mark Lord4c299ca2008-05-02 02:16:20 -04002430static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2431{
2432 void __iomem *port_mmio = mv_ap_base(ap);
2433
Mark Lordcae5a292009-04-06 16:43:45 -04002434 return readl(port_mmio + SATA_TESTCTL) >> 16;
Mark Lord4c299ca2008-05-02 02:16:20 -04002435}
2436
Mark Lord4c299ca2008-05-02 02:16:20 -04002437static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2438{
2439 struct ata_eh_info *ehi;
2440 unsigned int pmp;
2441
2442 /*
2443 * Initialize EH info for PMPs which saw device errors
2444 */
2445 ehi = &ap->link.eh_info;
2446 for (pmp = 0; pmp_map != 0; pmp++) {
2447 unsigned int this_pmp = (1 << pmp);
2448 if (pmp_map & this_pmp) {
2449 struct ata_link *link = &ap->pmp_link[pmp];
2450
2451 pmp_map &= ~this_pmp;
2452 ehi = &link->eh_info;
2453 ata_ehi_clear_desc(ehi);
2454 ata_ehi_push_desc(ehi, "dev err");
2455 ehi->err_mask |= AC_ERR_DEV;
2456 ehi->action |= ATA_EH_RESET;
2457 ata_link_abort(link);
2458 }
2459 }
2460}
2461
Mark Lord06aaca32008-05-19 09:01:24 -04002462static int mv_req_q_empty(struct ata_port *ap)
2463{
2464 void __iomem *port_mmio = mv_ap_base(ap);
2465 u32 in_ptr, out_ptr;
2466
Mark Lordcae5a292009-04-06 16:43:45 -04002467 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
Mark Lord06aaca32008-05-19 09:01:24 -04002468 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
Mark Lordcae5a292009-04-06 16:43:45 -04002469 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
Mark Lord06aaca32008-05-19 09:01:24 -04002470 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2471 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2472}
2473
Mark Lord4c299ca2008-05-02 02:16:20 -04002474static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2475{
2476 struct mv_port_priv *pp = ap->private_data;
2477 int failed_links;
2478 unsigned int old_map, new_map;
2479
2480 /*
2481 * Device error during FBS+NCQ operation:
2482 *
2483 * Set a port flag to prevent further I/O being enqueued.
2484 * Leave the EDMA running to drain outstanding commands from this port.
2485 * Perform the post-mortem/EH only when all responses are complete.
2486 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2487 */
2488 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2489 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2490 pp->delayed_eh_pmp_map = 0;
2491 }
2492 old_map = pp->delayed_eh_pmp_map;
2493 new_map = old_map | mv_get_err_pmp_map(ap);
2494
2495 if (old_map != new_map) {
2496 pp->delayed_eh_pmp_map = new_map;
2497 mv_pmp_eh_prep(ap, new_map & ~old_map);
2498 }
Mark Lordc46938c2008-05-02 14:02:28 -04002499 failed_links = hweight16(new_map);
Mark Lord4c299ca2008-05-02 02:16:20 -04002500
Joe Perchesa9a79df2011-04-15 15:51:59 -07002501 ata_port_info(ap,
2502 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2503 __func__, pp->delayed_eh_pmp_map,
2504 ap->qc_active, failed_links,
2505 ap->nr_active_links);
Mark Lord4c299ca2008-05-02 02:16:20 -04002506
Mark Lord06aaca32008-05-19 09:01:24 -04002507 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
Mark Lord4c299ca2008-05-02 02:16:20 -04002508 mv_process_crpb_entries(ap, pp);
2509 mv_stop_edma(ap);
2510 mv_eh_freeze(ap);
Joe Perchesa9a79df2011-04-15 15:51:59 -07002511 ata_port_info(ap, "%s: done\n", __func__);
Mark Lord4c299ca2008-05-02 02:16:20 -04002512 return 1; /* handled */
2513 }
Joe Perchesa9a79df2011-04-15 15:51:59 -07002514 ata_port_info(ap, "%s: waiting\n", __func__);
Mark Lord4c299ca2008-05-02 02:16:20 -04002515 return 1; /* handled */
2516}
2517
2518static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2519{
2520 /*
2521 * Possible future enhancement:
2522 *
2523 * FBS+non-NCQ operation is not yet implemented.
2524 * See related notes in mv_edma_cfg().
2525 *
2526 * Device error during FBS+non-NCQ operation:
2527 *
2528 * We need to snapshot the shadow registers for each failed command.
2529 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2530 */
2531 return 0; /* not handled */
2532}
2533
2534static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2535{
2536 struct mv_port_priv *pp = ap->private_data;
2537
2538 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2539 return 0; /* EDMA was not active: not handled */
2540 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2541 return 0; /* FBS was not active: not handled */
2542
2543 if (!(edma_err_cause & EDMA_ERR_DEV))
2544 return 0; /* non DEV error: not handled */
2545 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2546 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2547 return 0; /* other problems: not handled */
2548
2549 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2550 /*
2551 * EDMA should NOT have self-disabled for this case.
2552 * If it did, then something is wrong elsewhere,
2553 * and we cannot handle it here.
2554 */
2555 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07002556 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2557 __func__, edma_err_cause, pp->pp_flags);
Mark Lord4c299ca2008-05-02 02:16:20 -04002558 return 0; /* not handled */
2559 }
2560 return mv_handle_fbs_ncq_dev_err(ap);
2561 } else {
2562 /*
2563 * EDMA should have self-disabled for this case.
2564 * If it did not, then something is wrong elsewhere,
2565 * and we cannot handle it here.
2566 */
2567 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
Joe Perchesa9a79df2011-04-15 15:51:59 -07002568 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2569 __func__, edma_err_cause, pp->pp_flags);
Mark Lord4c299ca2008-05-02 02:16:20 -04002570 return 0; /* not handled */
2571 }
2572 return mv_handle_fbs_non_ncq_dev_err(ap);
2573 }
2574 return 0; /* not handled */
2575}
2576
Mark Lorda9010322008-05-02 02:14:02 -04002577static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
Mark Lord8f767f82008-04-19 14:53:07 -04002578{
Mark Lord8f767f82008-04-19 14:53:07 -04002579 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lorda9010322008-05-02 02:14:02 -04002580 char *when = "idle";
Mark Lord8f767f82008-04-19 14:53:07 -04002581
Mark Lord8f767f82008-04-19 14:53:07 -04002582 ata_ehi_clear_desc(ehi);
Tejun Heo3e4ec342010-05-10 21:41:30 +02002583 if (edma_was_enabled) {
Mark Lorda9010322008-05-02 02:14:02 -04002584 when = "EDMA enabled";
Mark Lord8f767f82008-04-19 14:53:07 -04002585 } else {
2586 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2587 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
Mark Lorda9010322008-05-02 02:14:02 -04002588 when = "polling";
Mark Lord8f767f82008-04-19 14:53:07 -04002589 }
Mark Lorda9010322008-05-02 02:14:02 -04002590 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
Mark Lord8f767f82008-04-19 14:53:07 -04002591 ehi->err_mask |= AC_ERR_OTHER;
2592 ehi->action |= ATA_EH_RESET;
2593 ata_port_freeze(ap);
2594}
2595
Brett Russ05b308e2005-10-05 17:08:53 -04002596/**
Brett Russ05b308e2005-10-05 17:08:53 -04002597 * mv_err_intr - Handle error interrupts on the port
2598 * @ap: ATA channel to manipulate
2599 *
Mark Lord8d073792008-04-19 15:07:49 -04002600 * Most cases require a full reset of the chip's state machine,
2601 * which also performs a COMRESET.
2602 * Also, if the port disabled DMA, update our cached copy to match.
Brett Russ05b308e2005-10-05 17:08:53 -04002603 *
2604 * LOCKING:
2605 * Inherited from caller.
2606 */
Mark Lord37b90462008-05-02 02:12:34 -04002607static void mv_err_intr(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04002608{
Brett Russ31961942005-09-30 01:36:00 -04002609 void __iomem *port_mmio = mv_ap_base(ap);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002610 u32 edma_err_cause, eh_freeze_mask, serr = 0;
Mark Lorde4006072008-05-14 09:19:30 -04002611 u32 fis_cause = 0;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002612 struct mv_port_priv *pp = ap->private_data;
2613 struct mv_host_priv *hpriv = ap->host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002614 unsigned int action = 0, err_mask = 0;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002615 struct ata_eh_info *ehi = &ap->link.eh_info;
Mark Lord37b90462008-05-02 02:12:34 -04002616 struct ata_queued_cmd *qc;
2617 int abort = 0;
Brett Russ20f733e2005-09-01 18:26:17 -04002618
Mark Lord8d073792008-04-19 15:07:49 -04002619 /*
Mark Lord37b90462008-05-02 02:12:34 -04002620 * Read and clear the SError and err_cause bits.
Mark Lorde4006072008-05-14 09:19:30 -04002621 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2622 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
Mark Lord8d073792008-04-19 15:07:49 -04002623 */
Mark Lord37b90462008-05-02 02:12:34 -04002624 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2625 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2626
Mark Lordcae5a292009-04-06 16:43:45 -04002627 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
Mark Lorde4006072008-05-14 09:19:30 -04002628 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lordcae5a292009-04-06 16:43:45 -04002629 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2630 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
Mark Lorde4006072008-05-14 09:19:30 -04002631 }
Mark Lordcae5a292009-04-06 16:43:45 -04002632 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002633
Mark Lord4c299ca2008-05-02 02:16:20 -04002634 if (edma_err_cause & EDMA_ERR_DEV) {
2635 /*
2636 * Device errors during FIS-based switching operation
2637 * require special handling.
2638 */
2639 if (mv_handle_dev_err(ap, edma_err_cause))
2640 return;
2641 }
2642
Mark Lord37b90462008-05-02 02:12:34 -04002643 qc = mv_get_active_qc(ap);
2644 ata_ehi_clear_desc(ehi);
2645 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2646 edma_err_cause, pp->pp_flags);
Mark Lorde4006072008-05-14 09:19:30 -04002647
Mark Lordc443c502008-05-14 09:24:39 -04002648 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
Mark Lorde4006072008-05-14 09:19:30 -04002649 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
Mark Lordcae5a292009-04-06 16:43:45 -04002650 if (fis_cause & FIS_IRQ_CAUSE_AN) {
Mark Lordc443c502008-05-14 09:24:39 -04002651 u32 ec = edma_err_cause &
2652 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2653 sata_async_notification(ap);
2654 if (!ec)
2655 return; /* Just an AN; no need for the nukes */
2656 ata_ehi_push_desc(ehi, "SDB notify");
2657 }
2658 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002659 /*
Mark Lord352fab72008-04-19 14:43:42 -04002660 * All generations share these EDMA error cause bits:
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002661 */
Mark Lord37b90462008-05-02 02:12:34 -04002662 if (edma_err_cause & EDMA_ERR_DEV) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002663 err_mask |= AC_ERR_DEV;
Mark Lord37b90462008-05-02 02:12:34 -04002664 action |= ATA_EH_RESET;
2665 ata_ehi_push_desc(ehi, "dev error");
2666 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002667 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002668 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002669 EDMA_ERR_INTRL_PAR)) {
2670 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002671 action |= ATA_EH_RESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09002672 ata_ehi_push_desc(ehi, "parity error");
Brett Russafb0edd2005-10-05 17:08:42 -04002673 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002674 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2675 ata_ehi_hotplugged(ehi);
2676 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
Tejun Heob64bbc32007-07-16 14:29:39 +09002677 "dev disconnect" : "dev connect");
Tejun Heocf480622008-01-24 00:05:14 +09002678 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002679 }
2680
Mark Lord352fab72008-04-19 14:43:42 -04002681 /*
2682 * Gen-I has a different SELF_DIS bit,
2683 * different FREEZE bits, and no SERR bit:
2684 */
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04002685 if (IS_GEN_I(hpriv)) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002686 eh_freeze_mask = EDMA_EH_FREEZE_5;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002687 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002688 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09002689 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002690 }
2691 } else {
2692 eh_freeze_mask = EDMA_EH_FREEZE;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002693 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002694 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Tejun Heob64bbc32007-07-16 14:29:39 +09002695 ata_ehi_push_desc(ehi, "EDMA self-disable");
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002696 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002697 if (edma_err_cause & EDMA_ERR_SERR) {
Mark Lord8d073792008-04-19 15:07:49 -04002698 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2699 err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002700 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002701 }
2702 }
Brett Russ20f733e2005-09-01 18:26:17 -04002703
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002704 if (!err_mask) {
2705 err_mask = AC_ERR_OTHER;
Tejun Heocf480622008-01-24 00:05:14 +09002706 action |= ATA_EH_RESET;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002707 }
2708
2709 ehi->serror |= serr;
2710 ehi->action |= action;
2711
2712 if (qc)
2713 qc->err_mask |= err_mask;
2714 else
2715 ehi->err_mask |= err_mask;
2716
Mark Lord37b90462008-05-02 02:12:34 -04002717 if (err_mask == AC_ERR_DEV) {
2718 /*
2719 * Cannot do ata_port_freeze() here,
2720 * because it would kill PIO access,
2721 * which is needed for further diagnosis.
2722 */
2723 mv_eh_freeze(ap);
2724 abort = 1;
2725 } else if (edma_err_cause & eh_freeze_mask) {
2726 /*
2727 * Note to self: ata_port_freeze() calls ata_port_abort()
2728 */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002729 ata_port_freeze(ap);
Mark Lord37b90462008-05-02 02:12:34 -04002730 } else {
2731 abort = 1;
2732 }
2733
2734 if (abort) {
2735 if (qc)
2736 ata_link_abort(qc->dev->link);
2737 else
2738 ata_port_abort(ap);
2739 }
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002740}
2741
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002742static bool mv_process_crpb_response(struct ata_port *ap,
Mark Lordfcfb1f72008-04-19 15:06:40 -04002743 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2744{
Tejun Heo752e3862010-06-25 15:02:59 +02002745 u8 ata_status;
2746 u16 edma_status = le16_to_cpu(response->flags);
Tejun Heo752e3862010-06-25 15:02:59 +02002747
2748 /*
2749 * edma_status from a response queue entry:
2750 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2751 * MSB is saved ATA status from command completion.
2752 */
2753 if (!ncq_enabled) {
2754 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2755 if (err_cause) {
2756 /*
2757 * Error will be seen/handled by
2758 * mv_err_intr(). So do nothing at all here.
2759 */
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002760 return false;
Tejun Heo752e3862010-06-25 15:02:59 +02002761 }
2762 }
2763 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2764 if (!ac_err_mask(ata_status))
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002765 return true;
Tejun Heo752e3862010-06-25 15:02:59 +02002766 /* else: leave it for mv_err_intr() */
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002767 return false;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002768}
2769
2770static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002771{
2772 void __iomem *port_mmio = mv_ap_base(ap);
2773 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002774 u32 in_index;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002775 bool work_done = false;
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002776 u32 done_mask = 0;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002777 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002778
Mark Lordfcfb1f72008-04-19 15:06:40 -04002779 /* Get the hardware queue position index */
Mark Lordcae5a292009-04-06 16:43:45 -04002780 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002781 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2782
Mark Lordfcfb1f72008-04-19 15:06:40 -04002783 /* Process new responses from since the last time we looked */
2784 while (in_index != pp->resp_idx) {
Jeff Garzik6c1153e2007-07-13 15:20:15 -04002785 unsigned int tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002786 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002787
Mark Lordfcfb1f72008-04-19 15:06:40 -04002788 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002789
Mark Lordfcfb1f72008-04-19 15:06:40 -04002790 if (IS_GEN_I(hpriv)) {
2791 /* 50xx: no NCQ, only one command active at a time */
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002792 tag = ap->link.active_tag;
Mark Lordfcfb1f72008-04-19 15:06:40 -04002793 } else {
2794 /* Gen II/IIE: get command tag from CRPB entry */
2795 tag = le16_to_cpu(response->id) & 0x1f;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002796 }
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002797 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2798 done_mask |= 1 << tag;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002799 work_done = true;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002800 }
2801
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002802 if (work_done) {
2803 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2804
2805 /* Update the software queue position index in hardware */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002806 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
Mark Lordfcfb1f72008-04-19 15:06:40 -04002807 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
Mark Lordcae5a292009-04-06 16:43:45 -04002808 port_mmio + EDMA_RSP_Q_OUT_PTR);
Tejun Heo1aadf5c2010-06-25 15:03:34 +02002809 }
Brett Russ20f733e2005-09-01 18:26:17 -04002810}
2811
Mark Lorda9010322008-05-02 02:14:02 -04002812static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2813{
2814 struct mv_port_priv *pp;
2815 int edma_was_enabled;
2816
Mark Lorda9010322008-05-02 02:14:02 -04002817 /*
2818 * Grab a snapshot of the EDMA_EN flag setting,
2819 * so that we have a consistent view for this port,
2820 * even if something we call of our routines changes it.
2821 */
2822 pp = ap->private_data;
2823 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2824 /*
2825 * Process completed CRPB response(s) before other events.
2826 */
2827 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2828 mv_process_crpb_entries(ap, pp);
Mark Lord4c299ca2008-05-02 02:16:20 -04002829 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2830 mv_handle_fbs_ncq_dev_err(ap);
Mark Lorda9010322008-05-02 02:14:02 -04002831 }
2832 /*
2833 * Handle chip-reported errors, or continue on to handle PIO.
2834 */
2835 if (unlikely(port_cause & ERR_IRQ)) {
2836 mv_err_intr(ap);
2837 } else if (!edma_was_enabled) {
2838 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2839 if (qc)
Tejun Heoc3b28892010-05-19 22:10:21 +02002840 ata_bmdma_port_intr(ap, qc);
Mark Lorda9010322008-05-02 02:14:02 -04002841 else
2842 mv_unexpected_intr(ap, edma_was_enabled);
2843 }
2844}
2845
Brett Russ05b308e2005-10-05 17:08:53 -04002846/**
2847 * mv_host_intr - Handle all interrupts on the given host controller
Jeff Garzikcca39742006-08-24 03:19:22 -04002848 * @host: host specific structure
Mark Lord7368f912008-04-25 11:24:24 -04002849 * @main_irq_cause: Main interrupt cause register for the chip.
Brett Russ05b308e2005-10-05 17:08:53 -04002850 *
2851 * LOCKING:
2852 * Inherited from caller.
2853 */
Mark Lord7368f912008-04-25 11:24:24 -04002854static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
Brett Russ20f733e2005-09-01 18:26:17 -04002855{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002856 struct mv_host_priv *hpriv = host->private_data;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002857 void __iomem *mmio = hpriv->base, *hc_mmio;
Mark Lorda3718c12008-04-19 15:07:18 -04002858 unsigned int handled = 0, port;
Brett Russ20f733e2005-09-01 18:26:17 -04002859
Mark Lord2b748a02009-03-10 22:01:17 -04002860 /* If asserted, clear the "all ports" IRQ coalescing bit */
2861 if (main_irq_cause & ALL_PORTS_COAL_DONE)
Mark Lordcae5a292009-04-06 16:43:45 -04002862 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
Mark Lord2b748a02009-03-10 22:01:17 -04002863
Mark Lorda3718c12008-04-19 15:07:18 -04002864 for (port = 0; port < hpriv->n_ports; port++) {
Jeff Garzikcca39742006-08-24 03:19:22 -04002865 struct ata_port *ap = host->ports[port];
Mark Lordeabd5eb2008-05-02 02:13:27 -04002866 unsigned int p, shift, hardport, port_cause;
2867
Mark Lorda3718c12008-04-19 15:07:18 -04002868 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
Mark Lorda3718c12008-04-19 15:07:18 -04002869 /*
Mark Lordeabd5eb2008-05-02 02:13:27 -04002870 * Each hc within the host has its own hc_irq_cause register,
2871 * where the interrupting ports bits get ack'd.
Mark Lorda3718c12008-04-19 15:07:18 -04002872 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002873 if (hardport == 0) { /* first port on this hc ? */
2874 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2875 u32 port_mask, ack_irqs;
2876 /*
2877 * Skip this entire hc if nothing pending for any ports
2878 */
2879 if (!hc_cause) {
2880 port += MV_PORTS_PER_HC - 1;
2881 continue;
2882 }
2883 /*
2884 * We don't need/want to read the hc_irq_cause register,
2885 * because doing so hurts performance, and
2886 * main_irq_cause already gives us everything we need.
2887 *
2888 * But we do have to *write* to the hc_irq_cause to ack
2889 * the ports that we are handling this time through.
2890 *
2891 * This requires that we create a bitmap for those
2892 * ports which interrupted us, and use that bitmap
2893 * to ack (only) those ports via hc_irq_cause.
2894 */
2895 ack_irqs = 0;
Mark Lord2b748a02009-03-10 22:01:17 -04002896 if (hc_cause & PORTS_0_3_COAL_DONE)
2897 ack_irqs = HC_COAL_IRQ;
Mark Lordeabd5eb2008-05-02 02:13:27 -04002898 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2899 if ((port + p) >= hpriv->n_ports)
2900 break;
2901 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2902 if (hc_cause & port_mask)
2903 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2904 }
Mark Lorda3718c12008-04-19 15:07:18 -04002905 hc_mmio = mv_hc_base_from_port(mmio, port);
Mark Lordcae5a292009-04-06 16:43:45 -04002906 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
Mark Lorda3718c12008-04-19 15:07:18 -04002907 handled = 1;
2908 }
Mark Lorda9010322008-05-02 02:14:02 -04002909 /*
2910 * Handle interrupts signalled for this port:
2911 */
Mark Lordeabd5eb2008-05-02 02:13:27 -04002912 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
Mark Lorda9010322008-05-02 02:14:02 -04002913 if (port_cause)
2914 mv_port_intr(ap, port_cause);
Brett Russ20f733e2005-09-01 18:26:17 -04002915 }
Mark Lorda3718c12008-04-19 15:07:18 -04002916 return handled;
Brett Russ20f733e2005-09-01 18:26:17 -04002917}
2918
Mark Lorda3718c12008-04-19 15:07:18 -04002919static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002920{
Mark Lord02a121d2007-12-01 13:07:22 -05002921 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002922 struct ata_port *ap;
2923 struct ata_queued_cmd *qc;
2924 struct ata_eh_info *ehi;
2925 unsigned int i, err_mask, printed = 0;
2926 u32 err_cause;
2927
Mark Lordcae5a292009-04-06 16:43:45 -04002928 err_cause = readl(mmio + hpriv->irq_cause_offset);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002929
Joe Perchesa44fec12011-04-15 15:51:58 -07002930 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002931
2932 DPRINTK("All regs @ PCI error\n");
2933 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2934
Mark Lordcae5a292009-04-06 16:43:45 -04002935 writelfl(0, mmio + hpriv->irq_cause_offset);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002936
2937 for (i = 0; i < host->n_ports; i++) {
2938 ap = host->ports[i];
Tejun Heo936fd732007-08-06 18:36:23 +09002939 if (!ata_link_offline(&ap->link)) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002940 ehi = &ap->link.eh_info;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002941 ata_ehi_clear_desc(ehi);
2942 if (!printed++)
2943 ata_ehi_push_desc(ehi,
2944 "PCI err cause 0x%08x", err_cause);
2945 err_mask = AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002946 ehi->action = ATA_EH_RESET;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002947 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002948 if (qc)
2949 qc->err_mask |= err_mask;
2950 else
2951 ehi->err_mask |= err_mask;
2952
2953 ata_port_freeze(ap);
2954 }
2955 }
Mark Lorda3718c12008-04-19 15:07:18 -04002956 return 1; /* handled */
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002957}
2958
Brett Russ05b308e2005-10-05 17:08:53 -04002959/**
Jeff Garzikc5d3e452007-07-11 18:30:50 -04002960 * mv_interrupt - Main interrupt event handler
Brett Russ05b308e2005-10-05 17:08:53 -04002961 * @irq: unused
2962 * @dev_instance: private data; in this case the host structure
Brett Russ05b308e2005-10-05 17:08:53 -04002963 *
2964 * Read the read only register to determine if any host
2965 * controllers have pending interrupts. If so, call lower level
2966 * routine to handle. Also check for PCI errors which are only
2967 * reported here.
2968 *
Jeff Garzik8b260242005-11-12 12:32:50 -05002969 * LOCKING:
Jeff Garzikcca39742006-08-24 03:19:22 -04002970 * This routine holds the host lock while processing pending
Brett Russ05b308e2005-10-05 17:08:53 -04002971 * interrupts.
2972 */
David Howells7d12e782006-10-05 14:55:46 +01002973static irqreturn_t mv_interrupt(int irq, void *dev_instance)
Brett Russ20f733e2005-09-01 18:26:17 -04002974{
Jeff Garzikcca39742006-08-24 03:19:22 -04002975 struct ata_host *host = dev_instance;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05002976 struct mv_host_priv *hpriv = host->private_data;
Mark Lorda3718c12008-04-19 15:07:18 -04002977 unsigned int handled = 0;
Mark Lord6d3c30e2009-01-21 10:31:29 -05002978 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
Mark Lord96e2c482008-05-17 13:38:00 -04002979 u32 main_irq_cause, pending_irqs;
Brett Russ20f733e2005-09-01 18:26:17 -04002980
Mark Lord646a4da2008-01-26 18:30:37 -05002981 spin_lock(&host->lock);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002982
2983 /* for MSI: block new interrupts while in here */
2984 if (using_msi)
Mark Lord2b748a02009-03-10 22:01:17 -04002985 mv_write_main_irq_mask(0, hpriv);
Mark Lord6d3c30e2009-01-21 10:31:29 -05002986
Mark Lord7368f912008-04-25 11:24:24 -04002987 main_irq_cause = readl(hpriv->main_irq_cause_addr);
Mark Lord96e2c482008-05-17 13:38:00 -04002988 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
Mark Lord352fab72008-04-19 14:43:42 -04002989 /*
2990 * Deal with cases where we either have nothing pending, or have read
2991 * a bogus register value which can indicate HW removal or PCI fault.
Brett Russ20f733e2005-09-01 18:26:17 -04002992 */
Mark Lorda44253d2008-05-17 13:37:07 -04002993 if (pending_irqs && main_irq_cause != 0xffffffffU) {
Mark Lord1f398472008-05-27 17:54:48 -04002994 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
Mark Lorda3718c12008-04-19 15:07:18 -04002995 handled = mv_pci_error(host, hpriv->base);
2996 else
Mark Lorda44253d2008-05-17 13:37:07 -04002997 handled = mv_host_intr(host, pending_irqs);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04002998 }
Mark Lord6d3c30e2009-01-21 10:31:29 -05002999
3000 /* for MSI: unmask; interrupt cause bits will retrigger now */
3001 if (using_msi)
Mark Lord2b748a02009-03-10 22:01:17 -04003002 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
Mark Lord6d3c30e2009-01-21 10:31:29 -05003003
Mark Lord9d51af72009-03-10 16:28:51 -04003004 spin_unlock(&host->lock);
3005
Brett Russ20f733e2005-09-01 18:26:17 -04003006 return IRQ_RETVAL(handled);
3007}
3008
Jeff Garzikc9d39132005-11-13 17:47:51 -05003009static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3010{
3011 unsigned int ofs;
3012
3013 switch (sc_reg_in) {
3014 case SCR_STATUS:
3015 case SCR_ERROR:
3016 case SCR_CONTROL:
3017 ofs = sc_reg_in * sizeof(u32);
3018 break;
3019 default:
3020 ofs = 0xffffffffU;
3021 break;
3022 }
3023 return ofs;
3024}
3025
Tejun Heo82ef04f2008-07-31 17:02:40 +09003026static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003027{
Tejun Heo82ef04f2008-07-31 17:02:40 +09003028 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003029 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09003030 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003031 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3032
Tejun Heoda3dbb12007-07-16 14:29:40 +09003033 if (ofs != 0xffffffffU) {
3034 *val = readl(addr + ofs);
3035 return 0;
3036 } else
3037 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003038}
3039
Tejun Heo82ef04f2008-07-31 17:02:40 +09003040static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003041{
Tejun Heo82ef04f2008-07-31 17:02:40 +09003042 struct mv_host_priv *hpriv = link->ap->host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003043 void __iomem *mmio = hpriv->base;
Tejun Heo82ef04f2008-07-31 17:02:40 +09003044 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003045 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3046
Tejun Heoda3dbb12007-07-16 14:29:40 +09003047 if (ofs != 0xffffffffU) {
Tejun Heo0d5ff562007-02-01 15:06:36 +09003048 writelfl(val, addr + ofs);
Tejun Heoda3dbb12007-07-16 14:29:40 +09003049 return 0;
3050 } else
3051 return -EINVAL;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003052}
3053
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003054static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik522479f2005-11-12 22:14:02 -05003055{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003056 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzik522479f2005-11-12 22:14:02 -05003057 int early_5080;
3058
Auke Kok44c10132007-06-08 15:46:36 -07003059 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
Jeff Garzik522479f2005-11-12 22:14:02 -05003060
3061 if (!early_5080) {
3062 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3063 tmp |= (1 << 0);
3064 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3065 }
3066
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003067 mv_reset_pci_bus(host, mmio);
Jeff Garzik522479f2005-11-12 22:14:02 -05003068}
3069
3070static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3071{
Mark Lordcae5a292009-04-06 16:43:45 -04003072 writel(0x0fcfffff, mmio + FLASH_CTL);
Jeff Garzik522479f2005-11-12 22:14:02 -05003073}
3074
Jeff Garzik47c2b672005-11-12 21:13:17 -05003075static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003076 void __iomem *mmio)
3077{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003078 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3079 u32 tmp;
3080
3081 tmp = readl(phy_mmio + MV5_PHY_MODE);
3082
3083 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3084 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003085}
3086
Jeff Garzik47c2b672005-11-12 21:13:17 -05003087static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003088{
Jeff Garzik522479f2005-11-12 22:14:02 -05003089 u32 tmp;
3090
Mark Lordcae5a292009-04-06 16:43:45 -04003091 writel(0, mmio + GPIO_PORT_CTL);
Jeff Garzik522479f2005-11-12 22:14:02 -05003092
3093 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3094
3095 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3096 tmp |= ~(1 << 0);
3097 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003098}
3099
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003100static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3101 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003102{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003103 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3104 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3105 u32 tmp;
3106 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3107
3108 if (fix_apm_sq) {
Mark Lordcae5a292009-04-06 16:43:45 -04003109 tmp = readl(phy_mmio + MV5_LTMODE);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003110 tmp |= (1 << 19);
Mark Lordcae5a292009-04-06 16:43:45 -04003111 writel(tmp, phy_mmio + MV5_LTMODE);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003112
Mark Lordcae5a292009-04-06 16:43:45 -04003113 tmp = readl(phy_mmio + MV5_PHY_CTL);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003114 tmp &= ~0x3;
3115 tmp |= 0x1;
Mark Lordcae5a292009-04-06 16:43:45 -04003116 writel(tmp, phy_mmio + MV5_PHY_CTL);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003117 }
3118
3119 tmp = readl(phy_mmio + MV5_PHY_MODE);
3120 tmp &= ~mask;
3121 tmp |= hpriv->signal[port].pre;
3122 tmp |= hpriv->signal[port].amps;
3123 writel(tmp, phy_mmio + MV5_PHY_MODE);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003124}
3125
Jeff Garzikc9d39132005-11-13 17:47:51 -05003126
3127#undef ZERO
3128#define ZERO(reg) writel(0, port_mmio + (reg))
3129static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3130 unsigned int port)
Jeff Garzik47c2b672005-11-12 21:13:17 -05003131{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003132 void __iomem *port_mmio = mv_port_base(mmio, port);
3133
Mark Lorde12bef52008-03-31 19:33:56 -04003134 mv_reset_channel(hpriv, mmio, port);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003135
3136 ZERO(0x028); /* command */
Mark Lordcae5a292009-04-06 16:43:45 -04003137 writel(0x11f, port_mmio + EDMA_CFG);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003138 ZERO(0x004); /* timer */
3139 ZERO(0x008); /* irq err cause */
3140 ZERO(0x00c); /* irq err mask */
3141 ZERO(0x010); /* rq bah */
3142 ZERO(0x014); /* rq inp */
3143 ZERO(0x018); /* rq outp */
3144 ZERO(0x01c); /* respq bah */
3145 ZERO(0x024); /* respq outp */
3146 ZERO(0x020); /* respq inp */
3147 ZERO(0x02c); /* test control */
Mark Lordcae5a292009-04-06 16:43:45 -04003148 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
Jeff Garzikc9d39132005-11-13 17:47:51 -05003149}
3150#undef ZERO
3151
3152#define ZERO(reg) writel(0, hc_mmio + (reg))
3153static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3154 unsigned int hc)
3155{
3156 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3157 u32 tmp;
3158
3159 ZERO(0x00c);
3160 ZERO(0x010);
3161 ZERO(0x014);
3162 ZERO(0x018);
3163
3164 tmp = readl(hc_mmio + 0x20);
3165 tmp &= 0x1c1c1c1c;
3166 tmp |= 0x03030303;
3167 writel(tmp, hc_mmio + 0x20);
3168}
3169#undef ZERO
3170
3171static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3172 unsigned int n_hc)
3173{
3174 unsigned int hc, port;
3175
3176 for (hc = 0; hc < n_hc; hc++) {
3177 for (port = 0; port < MV_PORTS_PER_HC; port++)
3178 mv5_reset_hc_port(hpriv, mmio,
3179 (hc * MV_PORTS_PER_HC) + port);
3180
3181 mv5_reset_one_hc(hpriv, mmio, hc);
3182 }
3183
3184 return 0;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003185}
3186
Jeff Garzik101ffae2005-11-12 22:17:49 -05003187#undef ZERO
3188#define ZERO(reg) writel(0, mmio + (reg))
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003189static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003190{
Mark Lord02a121d2007-12-01 13:07:22 -05003191 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003192 u32 tmp;
3193
Mark Lordcae5a292009-04-06 16:43:45 -04003194 tmp = readl(mmio + MV_PCI_MODE);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003195 tmp &= 0xff00ffff;
Mark Lordcae5a292009-04-06 16:43:45 -04003196 writel(tmp, mmio + MV_PCI_MODE);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003197
3198 ZERO(MV_PCI_DISC_TIMER);
3199 ZERO(MV_PCI_MSI_TRIGGER);
Mark Lordcae5a292009-04-06 16:43:45 -04003200 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003201 ZERO(MV_PCI_SERR_MASK);
Mark Lordcae5a292009-04-06 16:43:45 -04003202 ZERO(hpriv->irq_cause_offset);
3203 ZERO(hpriv->irq_mask_offset);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003204 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3205 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3206 ZERO(MV_PCI_ERR_ATTRIBUTE);
3207 ZERO(MV_PCI_ERR_COMMAND);
3208}
3209#undef ZERO
3210
3211static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3212{
3213 u32 tmp;
3214
3215 mv5_reset_flash(hpriv, mmio);
3216
Mark Lordcae5a292009-04-06 16:43:45 -04003217 tmp = readl(mmio + GPIO_PORT_CTL);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003218 tmp &= 0x3;
3219 tmp |= (1 << 5) | (1 << 6);
Mark Lordcae5a292009-04-06 16:43:45 -04003220 writel(tmp, mmio + GPIO_PORT_CTL);
Jeff Garzik101ffae2005-11-12 22:17:49 -05003221}
3222
3223/**
3224 * mv6_reset_hc - Perform the 6xxx global soft reset
3225 * @mmio: base address of the HBA
3226 *
3227 * This routine only applies to 6xxx parts.
3228 *
3229 * LOCKING:
3230 * Inherited from caller.
3231 */
Jeff Garzikc9d39132005-11-13 17:47:51 -05003232static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3233 unsigned int n_hc)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003234{
Mark Lordcae5a292009-04-06 16:43:45 -04003235 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003236 int i, rc = 0;
3237 u32 t;
3238
3239 /* Following procedure defined in PCI "main command and status
3240 * register" table.
3241 */
3242 t = readl(reg);
3243 writel(t | STOP_PCI_MASTER, reg);
3244
3245 for (i = 0; i < 1000; i++) {
3246 udelay(1);
3247 t = readl(reg);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04003248 if (PCI_MASTER_EMPTY & t)
Jeff Garzik101ffae2005-11-12 22:17:49 -05003249 break;
Jeff Garzik101ffae2005-11-12 22:17:49 -05003250 }
3251 if (!(PCI_MASTER_EMPTY & t)) {
3252 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3253 rc = 1;
3254 goto done;
3255 }
3256
3257 /* set reset */
3258 i = 5;
3259 do {
3260 writel(t | GLOB_SFT_RST, reg);
3261 t = readl(reg);
3262 udelay(1);
3263 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3264
3265 if (!(GLOB_SFT_RST & t)) {
3266 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3267 rc = 1;
3268 goto done;
3269 }
3270
3271 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3272 i = 5;
3273 do {
3274 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3275 t = readl(reg);
3276 udelay(1);
3277 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3278
3279 if (GLOB_SFT_RST & t) {
3280 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3281 rc = 1;
3282 }
3283done:
3284 return rc;
3285}
3286
Jeff Garzik47c2b672005-11-12 21:13:17 -05003287static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003288 void __iomem *mmio)
3289{
3290 void __iomem *port_mmio;
3291 u32 tmp;
3292
Mark Lordcae5a292009-04-06 16:43:45 -04003293 tmp = readl(mmio + RESET_CFG);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003294 if ((tmp & (1 << 0)) == 0) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003295 hpriv->signal[idx].amps = 0x7 << 8;
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003296 hpriv->signal[idx].pre = 0x1 << 5;
3297 return;
3298 }
3299
3300 port_mmio = mv_port_base(mmio, idx);
3301 tmp = readl(port_mmio + PHY_MODE2);
3302
3303 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3304 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3305}
3306
Jeff Garzik47c2b672005-11-12 21:13:17 -05003307static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003308{
Mark Lordcae5a292009-04-06 16:43:45 -04003309 writel(0x00000060, mmio + GPIO_PORT_CTL);
Jeff Garzikba3fe8f2005-11-12 19:08:48 -05003310}
3311
Jeff Garzikc9d39132005-11-13 17:47:51 -05003312static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003313 unsigned int port)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003314{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003315 void __iomem *port_mmio = mv_port_base(mmio, port);
3316
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003317 u32 hp_flags = hpriv->hp_flags;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003318 int fix_phy_mode2 =
3319 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003320 int fix_phy_mode4 =
Jeff Garzik47c2b672005-11-12 21:13:17 -05003321 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
Mark Lord8c30a8b2008-05-27 17:56:31 -04003322 u32 m2, m3;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003323
3324 if (fix_phy_mode2) {
3325 m2 = readl(port_mmio + PHY_MODE2);
3326 m2 &= ~(1 << 16);
3327 m2 |= (1 << 31);
3328 writel(m2, port_mmio + PHY_MODE2);
3329
3330 udelay(200);
3331
3332 m2 = readl(port_mmio + PHY_MODE2);
3333 m2 &= ~((1 << 16) | (1 << 31));
3334 writel(m2, port_mmio + PHY_MODE2);
3335
3336 udelay(200);
3337 }
3338
Mark Lord8c30a8b2008-05-27 17:56:31 -04003339 /*
3340 * Gen-II/IIe PHY_MODE3 errata RM#2:
3341 * Achieves better receiver noise performance than the h/w default:
3342 */
3343 m3 = readl(port_mmio + PHY_MODE3);
3344 m3 = (m3 & 0x1f) | (0x5555601 << 5);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003345
Mark Lord0388a8c2008-05-28 13:41:52 -04003346 /* Guideline 88F5182 (GL# SATA-S11) */
3347 if (IS_SOC(hpriv))
3348 m3 &= ~0x1c;
3349
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003350 if (fix_phy_mode4) {
Mark Lordba069e32008-05-31 16:46:34 -04003351 u32 m4 = readl(port_mmio + PHY_MODE4);
3352 /*
3353 * Enforce reserved-bit restrictions on GenIIe devices only.
3354 * For earlier chipsets, force only the internal config field
3355 * (workaround for errata FEr SATA#10 part 1).
3356 */
Mark Lord8c30a8b2008-05-27 17:56:31 -04003357 if (IS_GEN_IIE(hpriv))
Mark Lordba069e32008-05-31 16:46:34 -04003358 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3359 else
3360 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
Mark Lord8c30a8b2008-05-27 17:56:31 -04003361 writel(m4, port_mmio + PHY_MODE4);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003362 }
Mark Lordb406c7a2008-05-28 12:01:12 -04003363 /*
3364 * Workaround for 60x1-B2 errata SATA#13:
3365 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3366 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
Mark Lordba684602009-04-06 15:25:39 -04003367 * Or ensure we use writelfl() when writing PHY_MODE4.
Mark Lordb406c7a2008-05-28 12:01:12 -04003368 */
3369 writel(m3, port_mmio + PHY_MODE3);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003370
3371 /* Revert values of pre-emphasis and signal amps to the saved ones */
3372 m2 = readl(port_mmio + PHY_MODE2);
3373
3374 m2 &= ~MV_M2_PREAMP_MASK;
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003375 m2 |= hpriv->signal[port].amps;
3376 m2 |= hpriv->signal[port].pre;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003377 m2 &= ~(1 << 16);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003378
Jeff Garzike4e7b892006-01-31 12:18:41 -05003379 /* according to mvSata 3.6.1, some IIE values are fixed */
3380 if (IS_GEN_IIE(hpriv)) {
3381 m2 &= ~0xC30FF01F;
3382 m2 |= 0x0000900F;
3383 }
3384
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003385 writel(m2, port_mmio + PHY_MODE2);
3386}
3387
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003388/* TODO: use the generic LED interface to configure the SATA Presence */
3389/* & Acitivy LEDs on the board */
3390static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3391 void __iomem *mmio)
3392{
3393 return;
3394}
3395
3396static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3397 void __iomem *mmio)
3398{
3399 void __iomem *port_mmio;
3400 u32 tmp;
3401
3402 port_mmio = mv_port_base(mmio, idx);
3403 tmp = readl(port_mmio + PHY_MODE2);
3404
3405 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3406 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3407}
3408
3409#undef ZERO
3410#define ZERO(reg) writel(0, port_mmio + (reg))
3411static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3412 void __iomem *mmio, unsigned int port)
3413{
3414 void __iomem *port_mmio = mv_port_base(mmio, port);
3415
Mark Lorde12bef52008-03-31 19:33:56 -04003416 mv_reset_channel(hpriv, mmio, port);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003417
3418 ZERO(0x028); /* command */
Mark Lordcae5a292009-04-06 16:43:45 -04003419 writel(0x101f, port_mmio + EDMA_CFG);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003420 ZERO(0x004); /* timer */
3421 ZERO(0x008); /* irq err cause */
3422 ZERO(0x00c); /* irq err mask */
3423 ZERO(0x010); /* rq bah */
3424 ZERO(0x014); /* rq inp */
3425 ZERO(0x018); /* rq outp */
3426 ZERO(0x01c); /* respq bah */
3427 ZERO(0x024); /* respq outp */
3428 ZERO(0x020); /* respq inp */
3429 ZERO(0x02c); /* test control */
Saeed Bisharad7b0c142009-12-06 18:26:17 +02003430 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003431}
3432
3433#undef ZERO
3434
3435#define ZERO(reg) writel(0, hc_mmio + (reg))
3436static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3437 void __iomem *mmio)
3438{
3439 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3440
3441 ZERO(0x00c);
3442 ZERO(0x010);
3443 ZERO(0x014);
3444
3445}
3446
3447#undef ZERO
3448
3449static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3450 void __iomem *mmio, unsigned int n_hc)
3451{
3452 unsigned int port;
3453
3454 for (port = 0; port < hpriv->n_ports; port++)
3455 mv_soc_reset_hc_port(hpriv, mmio, port);
3456
3457 mv_soc_reset_one_hc(hpriv, mmio);
3458
3459 return 0;
3460}
3461
3462static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3463 void __iomem *mmio)
3464{
3465 return;
3466}
3467
3468static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3469{
3470 return;
3471}
3472
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003473static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3474 void __iomem *mmio, unsigned int port)
3475{
3476 void __iomem *port_mmio = mv_port_base(mmio, port);
3477 u32 reg;
3478
3479 reg = readl(port_mmio + PHY_MODE3);
3480 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3481 reg |= (0x1 << 27);
3482 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3483 reg |= (0x1 << 29);
3484 writel(reg, port_mmio + PHY_MODE3);
3485
3486 reg = readl(port_mmio + PHY_MODE4);
3487 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3488 reg |= (0x1 << 16);
3489 writel(reg, port_mmio + PHY_MODE4);
3490
3491 reg = readl(port_mmio + PHY_MODE9_GEN2);
3492 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3493 reg |= 0x8;
3494 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3495 writel(reg, port_mmio + PHY_MODE9_GEN2);
3496
3497 reg = readl(port_mmio + PHY_MODE9_GEN1);
3498 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3499 reg |= 0x8;
3500 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3501 writel(reg, port_mmio + PHY_MODE9_GEN1);
3502}
3503
3504/**
3505 * soc_is_65 - check if the soc is 65 nano device
3506 *
3507 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3508 * register, this register should contain non-zero value and it exists only
3509 * in the 65 nano devices, when reading it from older devices we get 0.
3510 */
3511static bool soc_is_65n(struct mv_host_priv *hpriv)
3512{
3513 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3514
3515 if (readl(port0_mmio + PHYCFG_OFS))
3516 return true;
3517 return false;
3518}
3519
Mark Lord8e7decd2008-05-02 02:07:51 -04003520static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
Mark Lordb67a1062008-03-31 19:35:13 -04003521{
Mark Lordcae5a292009-04-06 16:43:45 -04003522 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
Mark Lordb67a1062008-03-31 19:35:13 -04003523
Mark Lord8e7decd2008-05-02 02:07:51 -04003524 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
Mark Lordb67a1062008-03-31 19:35:13 -04003525 if (want_gen2i)
Mark Lord8e7decd2008-05-02 02:07:51 -04003526 ifcfg |= (1 << 7); /* enable gen2i speed */
Mark Lordcae5a292009-04-06 16:43:45 -04003527 writelfl(ifcfg, port_mmio + SATA_IFCFG);
Mark Lordb67a1062008-03-31 19:35:13 -04003528}
3529
Mark Lorde12bef52008-03-31 19:33:56 -04003530static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
Jeff Garzikc9d39132005-11-13 17:47:51 -05003531 unsigned int port_no)
Brett Russ20f733e2005-09-01 18:26:17 -04003532{
Jeff Garzikc9d39132005-11-13 17:47:51 -05003533 void __iomem *port_mmio = mv_port_base(mmio, port_no);
Brett Russ20f733e2005-09-01 18:26:17 -04003534
Mark Lord8e7decd2008-05-02 02:07:51 -04003535 /*
3536 * The datasheet warns against setting EDMA_RESET when EDMA is active
3537 * (but doesn't say what the problem might be). So we first try
3538 * to disable the EDMA engine before doing the EDMA_RESET operation.
3539 */
Mark Lord0d8be5c2008-04-16 14:56:12 -04003540 mv_stop_edma_engine(port_mmio);
Mark Lordcae5a292009-04-06 16:43:45 -04003541 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003542
Mark Lordb67a1062008-03-31 19:35:13 -04003543 if (!IS_GEN_I(hpriv)) {
Mark Lord8e7decd2008-05-02 02:07:51 -04003544 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3545 mv_setup_ifcfg(port_mmio, 1);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003546 }
Mark Lordb67a1062008-03-31 19:35:13 -04003547 /*
Mark Lord8e7decd2008-05-02 02:07:51 -04003548 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
Mark Lordb67a1062008-03-31 19:35:13 -04003549 * link, and physical layers. It resets all SATA interface registers
Mark Lordcae5a292009-04-06 16:43:45 -04003550 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
Brett Russ20f733e2005-09-01 18:26:17 -04003551 */
Mark Lordcae5a292009-04-06 16:43:45 -04003552 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
Mark Lordb67a1062008-03-31 19:35:13 -04003553 udelay(25); /* allow reset propagation */
Mark Lordcae5a292009-04-06 16:43:45 -04003554 writelfl(0, port_mmio + EDMA_CMD);
Brett Russ20f733e2005-09-01 18:26:17 -04003555
Jeff Garzikc9d39132005-11-13 17:47:51 -05003556 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3557
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003558 if (IS_GEN_I(hpriv))
Jeff Garzikc9d39132005-11-13 17:47:51 -05003559 mdelay(1);
3560}
3561
Mark Lorde49856d2008-04-16 14:59:07 -04003562static void mv_pmp_select(struct ata_port *ap, int pmp)
Jeff Garzikc9d39132005-11-13 17:47:51 -05003563{
Mark Lorde49856d2008-04-16 14:59:07 -04003564 if (sata_pmp_supported(ap)) {
3565 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordcae5a292009-04-06 16:43:45 -04003566 u32 reg = readl(port_mmio + SATA_IFCTL);
Mark Lorde49856d2008-04-16 14:59:07 -04003567 int old = reg & 0xf;
Jeff Garzikc9d39132005-11-13 17:47:51 -05003568
Mark Lorde49856d2008-04-16 14:59:07 -04003569 if (old != pmp) {
3570 reg = (reg & ~0xf) | pmp;
Mark Lordcae5a292009-04-06 16:43:45 -04003571 writelfl(reg, port_mmio + SATA_IFCTL);
Mark Lorde49856d2008-04-16 14:59:07 -04003572 }
Tejun Heoda3dbb12007-07-16 14:29:40 +09003573 }
Brett Russ20f733e2005-09-01 18:26:17 -04003574}
3575
Mark Lorde49856d2008-04-16 14:59:07 -04003576static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3577 unsigned long deadline)
Jeff Garzik22374672005-11-17 10:59:48 -05003578{
Mark Lorde49856d2008-04-16 14:59:07 -04003579 mv_pmp_select(link->ap, sata_srst_pmp(link));
3580 return sata_std_hardreset(link, class, deadline);
3581}
Jeff Garzik0ea9e172007-07-13 17:06:45 -04003582
Mark Lorde49856d2008-04-16 14:59:07 -04003583static int mv_softreset(struct ata_link *link, unsigned int *class,
3584 unsigned long deadline)
3585{
3586 mv_pmp_select(link->ap, sata_srst_pmp(link));
3587 return ata_sff_softreset(link, class, deadline);
Jeff Garzik22374672005-11-17 10:59:48 -05003588}
3589
Tejun Heocc0680a2007-08-06 18:36:23 +09003590static int mv_hardreset(struct ata_link *link, unsigned int *class,
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003591 unsigned long deadline)
3592{
Tejun Heocc0680a2007-08-06 18:36:23 +09003593 struct ata_port *ap = link->ap;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003594 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordb5624682008-03-31 19:34:40 -04003595 struct mv_port_priv *pp = ap->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003596 void __iomem *mmio = hpriv->base;
Mark Lord0d8be5c2008-04-16 14:56:12 -04003597 int rc, attempts = 0, extra = 0;
3598 u32 sstatus;
3599 bool online;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003600
Mark Lorde12bef52008-03-31 19:33:56 -04003601 mv_reset_channel(hpriv, mmio, ap->port_no);
Mark Lordb5624682008-03-31 19:34:40 -04003602 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
Mark Lordd16ab3f2009-02-25 15:17:43 -05003603 pp->pp_flags &=
3604 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003605
Mark Lord0d8be5c2008-04-16 14:56:12 -04003606 /* Workaround for errata FEr SATA#10 (part 2) */
3607 do {
Mark Lord17c5aab2008-04-16 14:56:51 -04003608 const unsigned long *timing =
3609 sata_ehc_deb_timing(&link->eh_context);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003610
Mark Lord17c5aab2008-04-16 14:56:51 -04003611 rc = sata_link_hardreset(link, timing, deadline + extra,
3612 &online, NULL);
Mark Lord9dcffd92008-05-14 09:18:12 -04003613 rc = online ? -EAGAIN : rc;
Mark Lord17c5aab2008-04-16 14:56:51 -04003614 if (rc)
Mark Lord0d8be5c2008-04-16 14:56:12 -04003615 return rc;
Mark Lord0d8be5c2008-04-16 14:56:12 -04003616 sata_scr_read(link, SCR_STATUS, &sstatus);
3617 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3618 /* Force 1.5gb/s link speed and try again */
Mark Lord8e7decd2008-05-02 02:07:51 -04003619 mv_setup_ifcfg(mv_ap_base(ap), 0);
Mark Lord0d8be5c2008-04-16 14:56:12 -04003620 if (time_after(jiffies + HZ, deadline))
3621 extra = HZ; /* only extend it once, max */
3622 }
3623 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
Mark Lord08da1752009-02-25 15:13:03 -05003624 mv_save_cached_regs(ap);
Mark Lord66e57a22009-01-30 18:52:58 -05003625 mv_edma_cfg(ap, 0, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003626
Mark Lord17c5aab2008-04-16 14:56:51 -04003627 return rc;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003628}
3629
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003630static void mv_eh_freeze(struct ata_port *ap)
Brett Russ20f733e2005-09-01 18:26:17 -04003631{
Mark Lord1cfd19a2008-04-19 15:05:50 -04003632 mv_stop_edma(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04003633 mv_enable_port_irqs(ap, 0);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003634}
3635
3636static void mv_eh_thaw(struct ata_port *ap)
3637{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003638 struct mv_host_priv *hpriv = ap->host->private_data;
Mark Lordc4de5732008-05-17 13:35:21 -04003639 unsigned int port = ap->port_no;
3640 unsigned int hardport = mv_hardport_from_port(port);
Mark Lord1cfd19a2008-04-19 15:05:50 -04003641 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003642 void __iomem *port_mmio = mv_ap_base(ap);
Mark Lordc4de5732008-05-17 13:35:21 -04003643 u32 hc_irq_cause;
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003644
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003645 /* clear EDMA errors on this port */
Mark Lordcae5a292009-04-06 16:43:45 -04003646 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003647
3648 /* clear pending irq events */
Mark Lordcae6edc2009-01-19 18:05:42 -05003649 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
Mark Lordcae5a292009-04-06 16:43:45 -04003650 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
Jeff Garzikbdd4ddd2007-07-12 14:34:26 -04003651
Mark Lord88e675e2008-05-17 13:36:30 -04003652 mv_enable_port_irqs(ap, ERR_IRQ);
Brett Russ31961942005-09-30 01:36:00 -04003653}
3654
Brett Russ05b308e2005-10-05 17:08:53 -04003655/**
3656 * mv_port_init - Perform some early initialization on a single port.
3657 * @port: libata data structure storing shadow register addresses
3658 * @port_mmio: base address of the port
3659 *
3660 * Initialize shadow register mmio addresses, clear outstanding
3661 * interrupts on the port, and unmask interrupts for the future
3662 * start of the port.
3663 *
3664 * LOCKING:
3665 * Inherited from caller.
3666 */
Brett Russ31961942005-09-30 01:36:00 -04003667static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3668{
Mark Lordcae5a292009-04-06 16:43:45 -04003669 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
Brett Russ31961942005-09-30 01:36:00 -04003670
Jeff Garzik8b260242005-11-12 12:32:50 -05003671 /* PIO related setup
Brett Russ31961942005-09-30 01:36:00 -04003672 */
3673 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
Jeff Garzik8b260242005-11-12 12:32:50 -05003674 port->error_addr =
Brett Russ31961942005-09-30 01:36:00 -04003675 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3676 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3677 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3678 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3679 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3680 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
Jeff Garzik8b260242005-11-12 12:32:50 -05003681 port->status_addr =
Brett Russ31961942005-09-30 01:36:00 -04003682 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3683 /* special case: control/altstatus doesn't have ATA_REG_ address */
Mark Lordcae5a292009-04-06 16:43:45 -04003684 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
Brett Russ31961942005-09-30 01:36:00 -04003685
Brett Russ31961942005-09-30 01:36:00 -04003686 /* Clear any currently outstanding port interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003687 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3688 writelfl(readl(serr), serr);
3689 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
Brett Russ31961942005-09-30 01:36:00 -04003690
Mark Lord646a4da2008-01-26 18:30:37 -05003691 /* unmask all non-transient EDMA error interrupts */
Mark Lordcae5a292009-04-06 16:43:45 -04003692 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
Brett Russ20f733e2005-09-01 18:26:17 -04003693
Jeff Garzik8b260242005-11-12 12:32:50 -05003694 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
Mark Lordcae5a292009-04-06 16:43:45 -04003695 readl(port_mmio + EDMA_CFG),
3696 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3697 readl(port_mmio + EDMA_ERR_IRQ_MASK));
Brett Russ20f733e2005-09-01 18:26:17 -04003698}
3699
Mark Lord616d4a92008-05-02 02:08:32 -04003700static unsigned int mv_in_pcix_mode(struct ata_host *host)
3701{
3702 struct mv_host_priv *hpriv = host->private_data;
3703 void __iomem *mmio = hpriv->base;
3704 u32 reg;
3705
Mark Lord1f398472008-05-27 17:54:48 -04003706 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
Mark Lord616d4a92008-05-02 02:08:32 -04003707 return 0; /* not PCI-X capable */
Mark Lordcae5a292009-04-06 16:43:45 -04003708 reg = readl(mmio + MV_PCI_MODE);
Mark Lord616d4a92008-05-02 02:08:32 -04003709 if ((reg & MV_PCI_MODE_MASK) == 0)
3710 return 0; /* conventional PCI mode */
3711 return 1; /* chip is in PCI-X mode */
3712}
3713
3714static int mv_pci_cut_through_okay(struct ata_host *host)
3715{
3716 struct mv_host_priv *hpriv = host->private_data;
3717 void __iomem *mmio = hpriv->base;
3718 u32 reg;
3719
3720 if (!mv_in_pcix_mode(host)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003721 reg = readl(mmio + MV_PCI_COMMAND);
3722 if (reg & MV_PCI_COMMAND_MRDTRIG)
Mark Lord616d4a92008-05-02 02:08:32 -04003723 return 0; /* not okay */
3724 }
3725 return 1; /* okay */
3726}
3727
Mark Lord65ad7fe2009-04-06 15:24:14 -04003728static void mv_60x1b2_errata_pci7(struct ata_host *host)
3729{
3730 struct mv_host_priv *hpriv = host->private_data;
3731 void __iomem *mmio = hpriv->base;
3732
3733 /* workaround for 60x1-B2 errata PCI#7 */
3734 if (mv_in_pcix_mode(host)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003735 u32 reg = readl(mmio + MV_PCI_COMMAND);
3736 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
Mark Lord65ad7fe2009-04-06 15:24:14 -04003737 }
3738}
3739
Tejun Heo4447d352007-04-17 23:44:08 +09003740static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003741{
Tejun Heo4447d352007-04-17 23:44:08 +09003742 struct pci_dev *pdev = to_pci_dev(host->dev);
3743 struct mv_host_priv *hpriv = host->private_data;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003744 u32 hp_flags = hpriv->hp_flags;
3745
Jeff Garzik5796d1c2007-10-26 00:03:37 -04003746 switch (board_idx) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003747 case chip_5080:
3748 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003749 hp_flags |= MV_HP_GEN_I;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003750
Auke Kok44c10132007-06-08 15:46:36 -07003751 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003752 case 0x1:
3753 hp_flags |= MV_HP_ERRATA_50XXB0;
3754 break;
3755 case 0x3:
3756 hp_flags |= MV_HP_ERRATA_50XXB2;
3757 break;
3758 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003759 dev_warn(&pdev->dev,
3760 "Applying 50XXB2 workarounds to unknown rev\n");
Jeff Garzik47c2b672005-11-12 21:13:17 -05003761 hp_flags |= MV_HP_ERRATA_50XXB2;
3762 break;
3763 }
3764 break;
3765
3766 case chip_504x:
3767 case chip_508x:
3768 hpriv->ops = &mv5xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003769 hp_flags |= MV_HP_GEN_I;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003770
Auke Kok44c10132007-06-08 15:46:36 -07003771 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003772 case 0x0:
3773 hp_flags |= MV_HP_ERRATA_50XXB0;
3774 break;
3775 case 0x3:
3776 hp_flags |= MV_HP_ERRATA_50XXB2;
3777 break;
3778 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003779 dev_warn(&pdev->dev,
3780 "Applying B2 workarounds to unknown rev\n");
Jeff Garzik47c2b672005-11-12 21:13:17 -05003781 hp_flags |= MV_HP_ERRATA_50XXB2;
3782 break;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003783 }
3784 break;
3785
3786 case chip_604x:
3787 case chip_608x:
Jeff Garzik47c2b672005-11-12 21:13:17 -05003788 hpriv->ops = &mv6xxx_ops;
Jeff Garzikee9ccdf2007-07-12 15:51:22 -04003789 hp_flags |= MV_HP_GEN_II;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003790
Auke Kok44c10132007-06-08 15:46:36 -07003791 switch (pdev->revision) {
Jeff Garzik47c2b672005-11-12 21:13:17 -05003792 case 0x7:
Mark Lord65ad7fe2009-04-06 15:24:14 -04003793 mv_60x1b2_errata_pci7(host);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003794 hp_flags |= MV_HP_ERRATA_60X1B2;
3795 break;
3796 case 0x9:
3797 hp_flags |= MV_HP_ERRATA_60X1C0;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003798 break;
3799 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003800 dev_warn(&pdev->dev,
3801 "Applying B2 workarounds to unknown rev\n");
Jeff Garzik47c2b672005-11-12 21:13:17 -05003802 hp_flags |= MV_HP_ERRATA_60X1B2;
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003803 break;
3804 }
3805 break;
3806
Jeff Garzike4e7b892006-01-31 12:18:41 -05003807 case chip_7042:
Mark Lord616d4a92008-05-02 02:08:32 -04003808 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
Mark Lord306b30f2007-12-04 14:07:52 -05003809 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3810 (pdev->device == 0x2300 || pdev->device == 0x2310))
3811 {
Mark Lord4e520032007-12-11 12:58:05 -05003812 /*
3813 * Highpoint RocketRAID PCIe 23xx series cards:
3814 *
3815 * Unconfigured drives are treated as "Legacy"
3816 * by the BIOS, and it overwrites sector 8 with
3817 * a "Lgcy" metadata block prior to Linux boot.
3818 *
3819 * Configured drives (RAID or JBOD) leave sector 8
3820 * alone, but instead overwrite a high numbered
3821 * sector for the RAID metadata. This sector can
3822 * be determined exactly, by truncating the physical
3823 * drive capacity to a nice even GB value.
3824 *
3825 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3826 *
3827 * Warn the user, lest they think we're just buggy.
3828 */
3829 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3830 " BIOS CORRUPTS DATA on all attached drives,"
3831 " regardless of if/how they are configured."
3832 " BEWARE!\n");
3833 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3834 " use sectors 8-9 on \"Legacy\" drives,"
3835 " and avoid the final two gigabytes on"
3836 " all RocketRAID BIOS initialized drives.\n");
Mark Lord306b30f2007-12-04 14:07:52 -05003837 }
Mark Lord8e7decd2008-05-02 02:07:51 -04003838 /* drop through */
Jeff Garzike4e7b892006-01-31 12:18:41 -05003839 case chip_6042:
3840 hpriv->ops = &mv6xxx_ops;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003841 hp_flags |= MV_HP_GEN_IIE;
Mark Lord616d4a92008-05-02 02:08:32 -04003842 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3843 hp_flags |= MV_HP_CUT_THROUGH;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003844
Auke Kok44c10132007-06-08 15:46:36 -07003845 switch (pdev->revision) {
Mark Lord5cf73bf2008-05-27 17:58:56 -04003846 case 0x2: /* Rev.B0: the first/only public release */
Jeff Garzike4e7b892006-01-31 12:18:41 -05003847 hp_flags |= MV_HP_ERRATA_60X1C0;
3848 break;
3849 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003850 dev_warn(&pdev->dev,
3851 "Applying 60X1C0 workarounds to unknown rev\n");
Jeff Garzike4e7b892006-01-31 12:18:41 -05003852 hp_flags |= MV_HP_ERRATA_60X1C0;
3853 break;
3854 }
3855 break;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003856 case chip_soc:
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003857 if (soc_is_65n(hpriv))
3858 hpriv->ops = &mv_soc_65n_ops;
3859 else
3860 hpriv->ops = &mv_soc_ops;
Saeed Bisharaeb3a55a2008-08-04 00:52:55 -11003861 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3862 MV_HP_ERRATA_60X1C0;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003863 break;
Jeff Garzike4e7b892006-01-31 12:18:41 -05003864
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003865 default:
Joe Perchesa44fec12011-04-15 15:51:58 -07003866 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003867 return 1;
3868 }
3869
3870 hpriv->hp_flags = hp_flags;
Mark Lord02a121d2007-12-01 13:07:22 -05003871 if (hp_flags & MV_HP_PCIE) {
Mark Lordcae5a292009-04-06 16:43:45 -04003872 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3873 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
Mark Lord02a121d2007-12-01 13:07:22 -05003874 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3875 } else {
Mark Lordcae5a292009-04-06 16:43:45 -04003876 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3877 hpriv->irq_mask_offset = PCI_IRQ_MASK;
Mark Lord02a121d2007-12-01 13:07:22 -05003878 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3879 }
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003880
3881 return 0;
3882}
3883
Brett Russ05b308e2005-10-05 17:08:53 -04003884/**
Jeff Garzik47c2b672005-11-12 21:13:17 -05003885 * mv_init_host - Perform some early initialization of the host.
Tejun Heo4447d352007-04-17 23:44:08 +09003886 * @host: ATA host to initialize
Brett Russ05b308e2005-10-05 17:08:53 -04003887 *
3888 * If possible, do an early global reset of the host. Then do
3889 * our port init and clear/unmask all/relevant host interrupts.
3890 *
3891 * LOCKING:
3892 * Inherited from caller.
3893 */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05003894static int mv_init_host(struct ata_host *host)
Brett Russ20f733e2005-09-01 18:26:17 -04003895{
3896 int rc = 0, n_hc, port, hc;
Tejun Heo4447d352007-04-17 23:44:08 +09003897 struct mv_host_priv *hpriv = host->private_data;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003898 void __iomem *mmio = hpriv->base;
Jeff Garzik47c2b672005-11-12 21:13:17 -05003899
Saeed Bishara1bfeff02009-12-17 01:05:00 -05003900 rc = mv_chip_id(host, hpriv->board_idx);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003901 if (rc)
Mark Lord352fab72008-04-19 14:43:42 -04003902 goto done;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003903
Mark Lord1f398472008-05-27 17:54:48 -04003904 if (IS_SOC(hpriv)) {
Mark Lordcae5a292009-04-06 16:43:45 -04003905 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3906 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
Mark Lord1f398472008-05-27 17:54:48 -04003907 } else {
Mark Lordcae5a292009-04-06 16:43:45 -04003908 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3909 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05003910 }
Mark Lord352fab72008-04-19 14:43:42 -04003911
Thomas Reitmayr5d0fb2e2009-01-24 20:24:58 +01003912 /* initialize shadow irq mask with register's value */
3913 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3914
Mark Lord352fab72008-04-19 14:43:42 -04003915 /* global interrupt mask: 0 == mask everything */
Mark Lordc4de5732008-05-17 13:35:21 -04003916 mv_set_main_irq_mask(host, ~0, 0);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003917
Tejun Heo4447d352007-04-17 23:44:08 +09003918 n_hc = mv_get_hc_count(host->ports[0]->flags);
Jeff Garzikbca1c4e2005-11-12 12:48:15 -05003919
Tejun Heo4447d352007-04-17 23:44:08 +09003920 for (port = 0; port < host->n_ports; port++)
Martin Michlmayr29b7e432009-05-04 20:58:50 +02003921 if (hpriv->ops->read_preamp)
3922 hpriv->ops->read_preamp(hpriv, port, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003923
Jeff Garzikc9d39132005-11-13 17:47:51 -05003924 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003925 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04003926 goto done;
Brett Russ20f733e2005-09-01 18:26:17 -04003927
Jeff Garzik522479f2005-11-12 22:14:02 -05003928 hpriv->ops->reset_flash(hpriv, mmio);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11003929 hpriv->ops->reset_bus(host, mmio);
Jeff Garzik47c2b672005-11-12 21:13:17 -05003930 hpriv->ops->enable_leds(hpriv, mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003931
Tejun Heo4447d352007-04-17 23:44:08 +09003932 for (port = 0; port < host->n_ports; port++) {
Tejun Heocbcdd872007-08-18 13:14:55 +09003933 struct ata_port *ap = host->ports[port];
Jeff Garzik2a47ce02005-11-12 23:05:14 -05003934 void __iomem *port_mmio = mv_port_base(mmio, port);
Tejun Heocbcdd872007-08-18 13:14:55 +09003935
3936 mv_port_init(&ap->ioaddr, port_mmio);
Brett Russ20f733e2005-09-01 18:26:17 -04003937 }
3938
3939 for (hc = 0; hc < n_hc; hc++) {
Brett Russ31961942005-09-30 01:36:00 -04003940 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3941
3942 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3943 "(before clear)=0x%08x\n", hc,
Mark Lordcae5a292009-04-06 16:43:45 -04003944 readl(hc_mmio + HC_CFG),
3945 readl(hc_mmio + HC_IRQ_CAUSE));
Brett Russ31961942005-09-30 01:36:00 -04003946
3947 /* Clear any currently outstanding hc interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003948 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
Brett Russ20f733e2005-09-01 18:26:17 -04003949 }
3950
Mark Lord44c65d12009-04-06 12:29:49 -04003951 if (!IS_SOC(hpriv)) {
3952 /* Clear any currently outstanding host interrupt conditions */
Mark Lordcae5a292009-04-06 16:43:45 -04003953 writelfl(0, mmio + hpriv->irq_cause_offset);
Brett Russ31961942005-09-30 01:36:00 -04003954
Mark Lord44c65d12009-04-06 12:29:49 -04003955 /* and unmask interrupt generation for host regs */
Mark Lordcae5a292009-04-06 16:43:45 -04003956 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
Mark Lord44c65d12009-04-06 12:29:49 -04003957 }
Jeff Garzikfb621e22007-02-25 04:19:45 -05003958
Mark Lord6be96ac2009-02-19 10:38:04 -05003959 /*
3960 * enable only global host interrupts for now.
3961 * The per-port interrupts get done later as ports are set up.
3962 */
3963 mv_set_main_irq_mask(host, 0, PCI_ERR);
Mark Lord2b748a02009-03-10 22:01:17 -04003964 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3965 irq_coalescing_usecs);
Brett Russ31961942005-09-30 01:36:00 -04003966done:
Brett Russ20f733e2005-09-01 18:26:17 -04003967 return rc;
3968}
3969
Byron Bradleyfbf14e22008-02-10 21:17:30 +00003970static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3971{
3972 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3973 MV_CRQB_Q_SZ, 0);
3974 if (!hpriv->crqb_pool)
3975 return -ENOMEM;
3976
3977 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3978 MV_CRPB_Q_SZ, 0);
3979 if (!hpriv->crpb_pool)
3980 return -ENOMEM;
3981
3982 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3983 MV_SG_TBL_SZ, 0);
3984 if (!hpriv->sg_tbl_pool)
3985 return -ENOMEM;
3986
3987 return 0;
3988}
3989
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003990static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
Andrew Lunn63a93322011-12-07 21:48:07 +01003991 const struct mbus_dram_target_info *dram)
Lennert Buytenhek15a32632008-03-27 14:51:39 -04003992{
3993 int i;
3994
3995 for (i = 0; i < 4; i++) {
3996 writel(0, hpriv->base + WINDOW_CTRL(i));
3997 writel(0, hpriv->base + WINDOW_BASE(i));
3998 }
3999
4000 for (i = 0; i < dram->num_cs; i++) {
Andrew Lunn63a93322011-12-07 21:48:07 +01004001 const struct mbus_dram_window *cs = dram->cs + i;
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004002
4003 writel(((cs->size - 1) & 0xffff0000) |
4004 (cs->mbus_attr << 8) |
4005 (dram->mbus_dram_target_id << 4) | 1,
4006 hpriv->base + WINDOW_CTRL(i));
4007 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4008 }
4009}
4010
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004011/**
4012 * mv_platform_probe - handle a positive probe of an soc Marvell
4013 * host
4014 * @pdev: platform device found
4015 *
4016 * LOCKING:
4017 * Inherited from caller.
4018 */
4019static int mv_platform_probe(struct platform_device *pdev)
4020{
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004021 const struct mv_sata_platform_data *mv_platform_data;
Andrew Lunn63a93322011-12-07 21:48:07 +01004022 const struct mbus_dram_target_info *dram;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004023 const struct ata_port_info *ppi[] =
4024 { &mv_port_info[chip_soc], NULL };
4025 struct ata_host *host;
4026 struct mv_host_priv *hpriv;
4027 struct resource *res;
4028 int n_ports, rc;
4029
Joe Perches06296a12011-04-15 15:52:00 -07004030 ata_print_version_once(&pdev->dev, DRV_VERSION);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004031
4032 /*
4033 * Simple resource validation ..
4034 */
4035 if (unlikely(pdev->num_resources != 2)) {
4036 dev_err(&pdev->dev, "invalid number of resources\n");
4037 return -EINVAL;
4038 }
4039
4040 /*
4041 * Get the register base first
4042 */
4043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4044 if (res == NULL)
4045 return -EINVAL;
4046
4047 /* allocate host */
4048 mv_platform_data = pdev->dev.platform_data;
4049 n_ports = mv_platform_data->n_ports;
4050
4051 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4052 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4053
4054 if (!host || !hpriv)
4055 return -ENOMEM;
4056 host->private_data = hpriv;
4057 hpriv->n_ports = n_ports;
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004058 hpriv->board_idx = chip_soc;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004059
4060 host->iomap = NULL;
Saeed Bisharaf1cb0ea2008-02-18 07:42:28 -11004061 hpriv->base = devm_ioremap(&pdev->dev, res->start,
Julia Lawall041b5ea2009-08-06 16:05:08 -07004062 resource_size(res));
Mark Lordcae5a292009-04-06 16:43:45 -04004063 hpriv->base -= SATAHC0_REG_BASE;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004064
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004065#if defined(CONFIG_HAVE_CLK)
4066 hpriv->clk = clk_get(&pdev->dev, NULL);
4067 if (IS_ERR(hpriv->clk))
4068 dev_notice(&pdev->dev, "cannot get clkdev\n");
4069 else
4070 clk_enable(hpriv->clk);
4071#endif
4072
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004073 /*
4074 * (Re-)program MBUS remapping windows if we are asked to.
4075 */
Andrew Lunn63a93322011-12-07 21:48:07 +01004076 dram = mv_mbus_dram_info();
4077 if (dram)
4078 mv_conf_mbus_windows(hpriv, dram);
Lennert Buytenhek15a32632008-03-27 14:51:39 -04004079
Byron Bradleyfbf14e22008-02-10 21:17:30 +00004080 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4081 if (rc)
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004082 goto err;
Byron Bradleyfbf14e22008-02-10 21:17:30 +00004083
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004084 /* initialize adapter */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004085 rc = mv_init_host(host);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004086 if (rc)
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004087 goto err;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004088
Joe Perchesa44fec12011-04-15 15:51:58 -07004089 dev_info(&pdev->dev, "slots %u ports %d\n",
4090 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004091
Sergei Shtylyovc00a4c92011-10-07 19:22:33 +04004092 rc = ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4093 IRQF_SHARED, &mv6_sht);
4094 if (!rc)
4095 return 0;
4096
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004097err:
4098#if defined(CONFIG_HAVE_CLK)
4099 if (!IS_ERR(hpriv->clk)) {
4100 clk_disable(hpriv->clk);
4101 clk_put(hpriv->clk);
4102 }
4103#endif
4104
4105 return rc;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004106}
4107
4108/*
4109 *
4110 * mv_platform_remove - unplug a platform interface
4111 * @pdev: platform device
4112 *
4113 * A platform bus SATA device has been unplugged. Perform the needed
4114 * cleanup. Also called on module unload for any active devices.
4115 */
4116static int __devexit mv_platform_remove(struct platform_device *pdev)
4117{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004118 struct ata_host *host = platform_get_drvdata(pdev);
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004119#if defined(CONFIG_HAVE_CLK)
4120 struct mv_host_priv *hpriv = host->private_data;
4121#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004122 ata_host_detach(host);
Saeed Bisharac77a2f42009-12-06 18:26:18 +02004123
4124#if defined(CONFIG_HAVE_CLK)
4125 if (!IS_ERR(hpriv->clk)) {
4126 clk_disable(hpriv->clk);
4127 clk_put(hpriv->clk);
4128 }
4129#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004130 return 0;
4131}
4132
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004133#ifdef CONFIG_PM
4134static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4135{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004136 struct ata_host *host = platform_get_drvdata(pdev);
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004137 if (host)
4138 return ata_host_suspend(host, state);
4139 else
4140 return 0;
4141}
4142
4143static int mv_platform_resume(struct platform_device *pdev)
4144{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004145 struct ata_host *host = platform_get_drvdata(pdev);
Andrew Lunn63a93322011-12-07 21:48:07 +01004146 const struct mbus_dram_target_info *dram;
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004147 int ret;
4148
4149 if (host) {
4150 struct mv_host_priv *hpriv = host->private_data;
Andrew Lunn63a93322011-12-07 21:48:07 +01004151
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004152 /*
4153 * (Re-)program MBUS remapping windows if we are asked to.
4154 */
Andrew Lunn63a93322011-12-07 21:48:07 +01004155 dram = mv_mbus_dram_info();
4156 if (dram)
4157 mv_conf_mbus_windows(hpriv, dram);
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004158
4159 /* initialize adapter */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004160 ret = mv_init_host(host);
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004161 if (ret) {
4162 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4163 return ret;
4164 }
4165 ata_host_resume(host);
4166 }
4167
4168 return 0;
4169}
4170#else
4171#define mv_platform_suspend NULL
4172#define mv_platform_resume NULL
4173#endif
4174
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004175static struct platform_driver mv_platform_driver = {
4176 .probe = mv_platform_probe,
4177 .remove = __devexit_p(mv_platform_remove),
Saeed Bishara6481f2b2009-12-06 18:26:19 +02004178 .suspend = mv_platform_suspend,
4179 .resume = mv_platform_resume,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004180 .driver = {
4181 .name = DRV_NAME,
4182 .owner = THIS_MODULE,
4183 },
4184};
4185
4186
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004187#ifdef CONFIG_PCI
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004188static int mv_pci_init_one(struct pci_dev *pdev,
4189 const struct pci_device_id *ent);
Saeed Bisharab2dec482009-12-06 18:26:22 +02004190#ifdef CONFIG_PM
4191static int mv_pci_device_resume(struct pci_dev *pdev);
4192#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004193
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004194
4195static struct pci_driver mv_pci_driver = {
4196 .name = DRV_NAME,
4197 .id_table = mv_pci_tbl,
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004198 .probe = mv_pci_init_one,
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004199 .remove = ata_pci_remove_one,
Saeed Bisharab2dec482009-12-06 18:26:22 +02004200#ifdef CONFIG_PM
4201 .suspend = ata_pci_device_suspend,
4202 .resume = mv_pci_device_resume,
4203#endif
4204
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004205};
4206
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004207/* move to PCI layer or libata core? */
4208static int pci_go_64(struct pci_dev *pdev)
4209{
4210 int rc;
4211
Yang Hongyang6a355282009-04-06 19:01:13 -07004212 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4213 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004214 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07004215 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004216 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07004217 dev_err(&pdev->dev,
4218 "64-bit DMA enable failed\n");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004219 return rc;
4220 }
4221 }
4222 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07004223 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004224 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07004225 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004226 return rc;
4227 }
Yang Hongyang284901a2009-04-06 19:01:15 -07004228 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004229 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -07004230 dev_err(&pdev->dev,
4231 "32-bit consistent DMA enable failed\n");
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004232 return rc;
4233 }
4234 }
4235
4236 return rc;
4237}
4238
Brett Russ05b308e2005-10-05 17:08:53 -04004239/**
4240 * mv_print_info - Dump key info to kernel log for perusal.
Tejun Heo4447d352007-04-17 23:44:08 +09004241 * @host: ATA host to print info about
Brett Russ05b308e2005-10-05 17:08:53 -04004242 *
4243 * FIXME: complete this.
4244 *
4245 * LOCKING:
4246 * Inherited from caller.
4247 */
Tejun Heo4447d352007-04-17 23:44:08 +09004248static void mv_print_info(struct ata_host *host)
Brett Russ31961942005-09-30 01:36:00 -04004249{
Tejun Heo4447d352007-04-17 23:44:08 +09004250 struct pci_dev *pdev = to_pci_dev(host->dev);
4251 struct mv_host_priv *hpriv = host->private_data;
Auke Kok44c10132007-06-08 15:46:36 -07004252 u8 scc;
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004253 const char *scc_s, *gen;
Brett Russ31961942005-09-30 01:36:00 -04004254
4255 /* Use this to determine the HW stepping of the chip so we know
4256 * what errata to workaround
4257 */
Brett Russ31961942005-09-30 01:36:00 -04004258 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4259 if (scc == 0)
4260 scc_s = "SCSI";
4261 else if (scc == 0x01)
4262 scc_s = "RAID";
4263 else
Jeff Garzikc1e4fe72007-07-09 12:29:31 -04004264 scc_s = "?";
4265
4266 if (IS_GEN_I(hpriv))
4267 gen = "I";
4268 else if (IS_GEN_II(hpriv))
4269 gen = "II";
4270 else if (IS_GEN_IIE(hpriv))
4271 gen = "IIE";
4272 else
4273 gen = "?";
Brett Russ31961942005-09-30 01:36:00 -04004274
Joe Perchesa44fec12011-04-15 15:51:58 -07004275 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4276 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4277 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
Brett Russ31961942005-09-30 01:36:00 -04004278}
4279
Brett Russ05b308e2005-10-05 17:08:53 -04004280/**
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004281 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
Brett Russ05b308e2005-10-05 17:08:53 -04004282 * @pdev: PCI device found
4283 * @ent: PCI device ID entry for the matched host
4284 *
4285 * LOCKING:
4286 * Inherited from caller.
4287 */
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004288static int mv_pci_init_one(struct pci_dev *pdev,
4289 const struct pci_device_id *ent)
Brett Russ20f733e2005-09-01 18:26:17 -04004290{
Brett Russ20f733e2005-09-01 18:26:17 -04004291 unsigned int board_idx = (unsigned int)ent->driver_data;
Tejun Heo4447d352007-04-17 23:44:08 +09004292 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4293 struct ata_host *host;
4294 struct mv_host_priv *hpriv;
Saeed Bisharac4bc7d72009-12-06 18:26:20 +02004295 int n_ports, port, rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004296
Joe Perches06296a12011-04-15 15:52:00 -07004297 ata_print_version_once(&pdev->dev, DRV_VERSION);
Brett Russ20f733e2005-09-01 18:26:17 -04004298
Tejun Heo4447d352007-04-17 23:44:08 +09004299 /* allocate host */
4300 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4301
4302 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4303 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4304 if (!host || !hpriv)
4305 return -ENOMEM;
4306 host->private_data = hpriv;
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004307 hpriv->n_ports = n_ports;
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004308 hpriv->board_idx = board_idx;
Tejun Heo4447d352007-04-17 23:44:08 +09004309
4310 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09004311 rc = pcim_enable_device(pdev);
4312 if (rc)
Brett Russ20f733e2005-09-01 18:26:17 -04004313 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004314
Tejun Heo0d5ff562007-02-01 15:06:36 +09004315 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4316 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09004317 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09004318 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09004319 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +09004320 host->iomap = pcim_iomap_table(pdev);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004321 hpriv->base = host->iomap[MV_PRIMARY_BAR];
Brett Russ20f733e2005-09-01 18:26:17 -04004322
Jeff Garzikd88184f2007-02-26 01:26:06 -05004323 rc = pci_go_64(pdev);
4324 if (rc)
4325 return rc;
4326
Mark Lordda2fa9b2008-01-26 18:32:45 -05004327 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4328 if (rc)
4329 return rc;
4330
Saeed Bisharac4bc7d72009-12-06 18:26:20 +02004331 for (port = 0; port < host->n_ports; port++) {
4332 struct ata_port *ap = host->ports[port];
4333 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4334 unsigned int offset = port_mmio - hpriv->base;
4335
4336 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4337 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4338 }
4339
Brett Russ20f733e2005-09-01 18:26:17 -04004340 /* initialize adapter */
Saeed Bishara1bfeff02009-12-17 01:05:00 -05004341 rc = mv_init_host(host);
Tejun Heo24dc5f32007-01-20 16:00:28 +09004342 if (rc)
4343 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004344
Mark Lord6d3c30e2009-01-21 10:31:29 -05004345 /* Enable message-switched interrupts, if requested */
4346 if (msi && pci_enable_msi(pdev) == 0)
4347 hpriv->hp_flags |= MV_HP_FLAG_MSI;
Brett Russ20f733e2005-09-01 18:26:17 -04004348
Brett Russ31961942005-09-30 01:36:00 -04004349 mv_dump_pci_cfg(pdev, 0x68);
Tejun Heo4447d352007-04-17 23:44:08 +09004350 mv_print_info(host);
Brett Russ20f733e2005-09-01 18:26:17 -04004351
Tejun Heo4447d352007-04-17 23:44:08 +09004352 pci_set_master(pdev);
Jeff Garzikea8b4db2007-07-17 02:21:50 -04004353 pci_try_set_mwi(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +09004354 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
Jeff Garzikc5d3e452007-07-11 18:30:50 -04004355 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
Brett Russ20f733e2005-09-01 18:26:17 -04004356}
Saeed Bisharab2dec482009-12-06 18:26:22 +02004357
4358#ifdef CONFIG_PM
4359static int mv_pci_device_resume(struct pci_dev *pdev)
4360{
Sergei Shtylyovd8661922011-10-07 19:24:22 +04004361 struct ata_host *host = pci_get_drvdata(pdev);
Saeed Bisharab2dec482009-12-06 18:26:22 +02004362 int rc;
4363
4364 rc = ata_pci_device_do_resume(pdev);
4365 if (rc)
4366 return rc;
4367
4368 /* initialize adapter */
4369 rc = mv_init_host(host);
4370 if (rc)
4371 return rc;
4372
4373 ata_host_resume(host);
4374
4375 return 0;
4376}
4377#endif
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004378#endif
Brett Russ20f733e2005-09-01 18:26:17 -04004379
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004380static int mv_platform_probe(struct platform_device *pdev);
4381static int __devexit mv_platform_remove(struct platform_device *pdev);
4382
Brett Russ20f733e2005-09-01 18:26:17 -04004383static int __init mv_init(void)
4384{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004385 int rc = -ENODEV;
4386#ifdef CONFIG_PCI
4387 rc = pci_register_driver(&mv_pci_driver);
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004388 if (rc < 0)
4389 return rc;
4390#endif
4391 rc = platform_driver_register(&mv_platform_driver);
4392
4393#ifdef CONFIG_PCI
4394 if (rc < 0)
4395 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004396#endif
4397 return rc;
Brett Russ20f733e2005-09-01 18:26:17 -04004398}
4399
4400static void __exit mv_exit(void)
4401{
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004402#ifdef CONFIG_PCI
Brett Russ20f733e2005-09-01 18:26:17 -04004403 pci_unregister_driver(&mv_pci_driver);
Saeed Bishara7bb3c522008-01-30 11:50:45 -11004404#endif
Saeed Bisharaf351b2d2008-02-01 18:08:03 -05004405 platform_driver_unregister(&mv_platform_driver);
Brett Russ20f733e2005-09-01 18:26:17 -04004406}
4407
4408MODULE_AUTHOR("Brett Russ");
4409MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4410MODULE_LICENSE("GPL");
4411MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4412MODULE_VERSION(DRV_VERSION);
Mark Lord17c5aab2008-04-16 14:56:51 -04004413MODULE_ALIAS("platform:" DRV_NAME);
Brett Russ20f733e2005-09-01 18:26:17 -04004414
Brett Russ20f733e2005-09-01 18:26:17 -04004415module_init(mv_init);
4416module_exit(mv_exit);