Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/clk.h> |
| 22 | |
| 23 | #include <asm/clkdev.h> |
| 24 | #include <asm/mach-types.h> |
| 25 | |
| 26 | #include <mach/msm_iomap.h> |
| 27 | #include <mach/clk.h> |
| 28 | #include <mach/rpm-regulator.h> |
| 29 | #include <mach/msm_xo.h> |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 30 | #include <mach/socinfo.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 31 | |
| 32 | #include "clock-local.h" |
| 33 | #include "clock-rpm.h" |
| 34 | #include "clock-voter.h" |
| 35 | #include "clock-dss-8960.h" |
| 36 | #include "devices.h" |
| 37 | |
| 38 | #define REG(off) (MSM_CLK_CTL_BASE + (off)) |
| 39 | #define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off)) |
| 40 | #define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off)) |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 41 | #define REG_GCC(off) (MSM_APCS_GCC_BASE + (off)) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 42 | |
| 43 | /* Peripheral clock registers. */ |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 44 | #define ADM0_PBUS_CLK_CTL_REG REG(0x2208) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 45 | #define CE1_HCLK_CTL_REG REG(0x2720) |
| 46 | #define CE1_CORE_CLK_CTL_REG REG(0x2724) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 47 | #define CE3_HCLK_CTL_REG REG(0x36C4) |
| 48 | #define CE3_CORE_CLK_CTL_REG REG(0x36CC) |
| 49 | #define CE3_CLK_SRC_NS_REG REG(0x36C0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 50 | #define DMA_BAM_HCLK_CTL REG(0x25C0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 51 | #define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 52 | #define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC) |
| 53 | #define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0) |
| 54 | #define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4) |
| 55 | #define CLK_HALT_DFAB_STATE_REG REG(0x2FC8) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 56 | /* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 57 | #define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC) |
| 58 | #define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8) |
Stephen Boyd | 973e4ba | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 59 | #define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 60 | #define CLK_TEST_REG REG(0x2FA0) |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 61 | #define GPn_MD_REG(n) REG(0x2D00+(0x20*(n))) |
| 62 | #define GPn_NS_REG(n) REG(0x2D24+(0x20*(n))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 63 | #define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1))) |
| 64 | #define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1))) |
| 65 | #define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1))) |
| 66 | #define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1))) |
| 67 | #define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1))) |
| 68 | #define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1))) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 69 | #define PDM_CLK_NS_REG REG(0x2CC0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 70 | /* 8064 name BB_PLL_ENA_APCS_REG */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 71 | #define BB_PLL_ENA_SC0_REG REG(0x34C0) |
Tianyi Gou | 59608a7 | 2012-01-31 22:19:30 -0800 | [diff] [blame] | 72 | #define BB_PLL_ENA_RPM_REG REG(0x34A0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 73 | #define BB_PLL0_STATUS_REG REG(0x30D8) |
| 74 | #define BB_PLL5_STATUS_REG REG(0x30F8) |
| 75 | #define BB_PLL6_STATUS_REG REG(0x3118) |
| 76 | #define BB_PLL7_STATUS_REG REG(0x3138) |
| 77 | #define BB_PLL8_L_VAL_REG REG(0x3144) |
| 78 | #define BB_PLL8_M_VAL_REG REG(0x3148) |
| 79 | #define BB_PLL8_MODE_REG REG(0x3140) |
| 80 | #define BB_PLL8_N_VAL_REG REG(0x314C) |
| 81 | #define BB_PLL8_STATUS_REG REG(0x3158) |
| 82 | #define BB_PLL8_CONFIG_REG REG(0x3154) |
| 83 | #define BB_PLL8_TEST_CTL_REG REG(0x3150) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 84 | #define BB_MMCC_PLL2_MODE_REG REG(0x3160) |
| 85 | #define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 86 | #define BB_PLL14_MODE_REG REG(0x31C0) |
| 87 | #define BB_PLL14_L_VAL_REG REG(0x31C4) |
| 88 | #define BB_PLL14_M_VAL_REG REG(0x31C8) |
| 89 | #define BB_PLL14_N_VAL_REG REG(0x31CC) |
| 90 | #define BB_PLL14_TEST_CTL_REG REG(0x31D0) |
| 91 | #define BB_PLL14_CONFIG_REG REG(0x31D4) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 92 | #define BB_PLL14_STATUS_REG REG(0x31D8) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 93 | #define PLLTEST_PAD_CFG_REG REG(0x2FA4) |
| 94 | #define PMEM_ACLK_CTL_REG REG(0x25A0) |
| 95 | #define RINGOSC_NS_REG REG(0x2DC0) |
| 96 | #define RINGOSC_STATUS_REG REG(0x2DCC) |
| 97 | #define RINGOSC_TCXO_CTL_REG REG(0x2DC4) |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 98 | #define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 99 | #define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080) |
| 100 | #define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1))) |
| 101 | #define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1))) |
| 102 | #define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1))) |
| 103 | #define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1))) |
| 104 | #define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628) |
| 105 | #define TSIF_HCLK_CTL_REG REG(0x2700) |
| 106 | #define TSIF_REF_CLK_MD_REG REG(0x270C) |
| 107 | #define TSIF_REF_CLK_NS_REG REG(0x2710) |
| 108 | #define TSSC_CLK_CTL_REG REG(0x2CA0) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 109 | #define SATA_CLK_SRC_NS_REG REG(0x2C08) |
| 110 | #define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C) |
| 111 | #define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10) |
| 112 | #define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14) |
| 113 | #define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 114 | #define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1))) |
| 115 | #define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1))) |
| 116 | #define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1))) |
| 117 | #define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1))) |
| 118 | #define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1))) |
| 119 | #define USB_HS1_HCLK_CTL_REG REG(0x2900) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 120 | #define USB_HS1_HCLK_FS_REG REG(0x2904) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 121 | #define USB_HS1_RESET_REG REG(0x2910) |
| 122 | #define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908) |
| 123 | #define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 124 | #define USB_HS3_HCLK_CTL_REG REG(0x3700) |
| 125 | #define USB_HS3_HCLK_FS_REG REG(0x3704) |
| 126 | #define USB_HS3_RESET_REG REG(0x3710) |
| 127 | #define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708) |
| 128 | #define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C) |
| 129 | #define USB_HS4_HCLK_CTL_REG REG(0x3720) |
| 130 | #define USB_HS4_HCLK_FS_REG REG(0x3724) |
| 131 | #define USB_HS4_RESET_REG REG(0x3730) |
| 132 | #define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728) |
| 133 | #define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 134 | #define USB_HSIC_HCLK_CTL_REG REG(0x2920) |
| 135 | #define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44) |
| 136 | #define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40) |
| 137 | #define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48) |
| 138 | #define USB_HSIC_RESET_REG REG(0x2934) |
| 139 | #define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C) |
| 140 | #define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924) |
| 141 | #define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 142 | #define USB_PHY0_RESET_REG REG(0x2E20) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 143 | #define PCIE_ALT_REF_CLK_NS_REG REG(0x3860) |
| 144 | #define PCIE_HCLK_CTL_REG REG(0x22CC) |
| 145 | #define GPLL1_MODE_REG REG(0x3160) |
| 146 | #define GPLL1_L_VAL_REG REG(0x3164) |
| 147 | #define GPLL1_M_VAL_REG REG(0x3168) |
| 148 | #define GPLL1_N_VAL_REG REG(0x316C) |
| 149 | #define GPLL1_CONFIG_REG REG(0x3174) |
| 150 | #define GPLL1_STATUS_REG REG(0x3178) |
| 151 | #define PXO_SRC_CLK_CTL_REG REG(0x2EA0) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 152 | |
| 153 | /* Multimedia clock registers. */ |
| 154 | #define AHB_EN_REG REG_MM(0x0008) |
| 155 | #define AHB_EN2_REG REG_MM(0x0038) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 156 | #define AHB_EN3_REG REG_MM(0x0248) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 157 | #define AHB_NS_REG REG_MM(0x0004) |
| 158 | #define AXI_NS_REG REG_MM(0x0014) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 159 | #define CAMCLK0_NS_REG REG_MM(0x0148) |
| 160 | #define CAMCLK0_CC_REG REG_MM(0x0140) |
| 161 | #define CAMCLK0_MD_REG REG_MM(0x0144) |
| 162 | #define CAMCLK1_NS_REG REG_MM(0x015C) |
| 163 | #define CAMCLK1_CC_REG REG_MM(0x0154) |
| 164 | #define CAMCLK1_MD_REG REG_MM(0x0158) |
| 165 | #define CAMCLK2_NS_REG REG_MM(0x0228) |
| 166 | #define CAMCLK2_CC_REG REG_MM(0x0220) |
| 167 | #define CAMCLK2_MD_REG REG_MM(0x0224) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 168 | #define CSI0_NS_REG REG_MM(0x0048) |
| 169 | #define CSI0_CC_REG REG_MM(0x0040) |
| 170 | #define CSI0_MD_REG REG_MM(0x0044) |
| 171 | #define CSI1_NS_REG REG_MM(0x0010) |
| 172 | #define CSI1_CC_REG REG_MM(0x0024) |
| 173 | #define CSI1_MD_REG REG_MM(0x0028) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 174 | #define CSI2_NS_REG REG_MM(0x0234) |
| 175 | #define CSI2_CC_REG REG_MM(0x022C) |
| 176 | #define CSI2_MD_REG REG_MM(0x0230) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 177 | #define CSIPHYTIMER_CC_REG REG_MM(0x0160) |
| 178 | #define CSIPHYTIMER_MD_REG REG_MM(0x0164) |
| 179 | #define CSIPHYTIMER_NS_REG REG_MM(0x0168) |
| 180 | #define DSI1_BYTE_NS_REG REG_MM(0x00B0) |
| 181 | #define DSI1_BYTE_CC_REG REG_MM(0x0090) |
| 182 | #define DSI2_BYTE_NS_REG REG_MM(0x00BC) |
| 183 | #define DSI2_BYTE_CC_REG REG_MM(0x00B4) |
| 184 | #define DSI1_ESC_NS_REG REG_MM(0x011C) |
| 185 | #define DSI1_ESC_CC_REG REG_MM(0x00CC) |
| 186 | #define DSI2_ESC_NS_REG REG_MM(0x0150) |
| 187 | #define DSI2_ESC_CC_REG REG_MM(0x013C) |
| 188 | #define DSI_PIXEL_CC_REG REG_MM(0x0130) |
| 189 | #define DSI2_PIXEL_CC_REG REG_MM(0x0094) |
| 190 | #define DBG_BUS_VEC_A_REG REG_MM(0x01C8) |
| 191 | #define DBG_BUS_VEC_B_REG REG_MM(0x01CC) |
| 192 | #define DBG_BUS_VEC_C_REG REG_MM(0x01D0) |
| 193 | #define DBG_BUS_VEC_D_REG REG_MM(0x01D4) |
| 194 | #define DBG_BUS_VEC_E_REG REG_MM(0x01D8) |
| 195 | #define DBG_BUS_VEC_F_REG REG_MM(0x01DC) |
| 196 | #define DBG_BUS_VEC_G_REG REG_MM(0x01E0) |
| 197 | #define DBG_BUS_VEC_H_REG REG_MM(0x01E4) |
| 198 | #define DBG_BUS_VEC_I_REG REG_MM(0x01E8) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 199 | #define DBG_BUS_VEC_J_REG REG_MM(0x0240) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 200 | #define DBG_CFG_REG_HS_REG REG_MM(0x01B4) |
| 201 | #define DBG_CFG_REG_LS_REG REG_MM(0x01B8) |
| 202 | #define GFX2D0_CC_REG REG_MM(0x0060) |
| 203 | #define GFX2D0_MD0_REG REG_MM(0x0064) |
| 204 | #define GFX2D0_MD1_REG REG_MM(0x0068) |
| 205 | #define GFX2D0_NS_REG REG_MM(0x0070) |
| 206 | #define GFX2D1_CC_REG REG_MM(0x0074) |
| 207 | #define GFX2D1_MD0_REG REG_MM(0x0078) |
| 208 | #define GFX2D1_MD1_REG REG_MM(0x006C) |
| 209 | #define GFX2D1_NS_REG REG_MM(0x007C) |
| 210 | #define GFX3D_CC_REG REG_MM(0x0080) |
| 211 | #define GFX3D_MD0_REG REG_MM(0x0084) |
| 212 | #define GFX3D_MD1_REG REG_MM(0x0088) |
| 213 | #define GFX3D_NS_REG REG_MM(0x008C) |
| 214 | #define IJPEG_CC_REG REG_MM(0x0098) |
| 215 | #define IJPEG_MD_REG REG_MM(0x009C) |
| 216 | #define IJPEG_NS_REG REG_MM(0x00A0) |
| 217 | #define JPEGD_CC_REG REG_MM(0x00A4) |
| 218 | #define JPEGD_NS_REG REG_MM(0x00AC) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 219 | #define VCAP_CC_REG REG_MM(0x0178) |
| 220 | #define VCAP_NS_REG REG_MM(0x021C) |
| 221 | #define VCAP_MD0_REG REG_MM(0x01EC) |
| 222 | #define VCAP_MD1_REG REG_MM(0x0218) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 223 | #define MAXI_EN_REG REG_MM(0x0018) |
| 224 | #define MAXI_EN2_REG REG_MM(0x0020) |
| 225 | #define MAXI_EN3_REG REG_MM(0x002C) |
| 226 | #define MAXI_EN4_REG REG_MM(0x0114) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 227 | #define MAXI_EN5_REG REG_MM(0x0244) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 228 | #define MDP_CC_REG REG_MM(0x00C0) |
| 229 | #define MDP_LUT_CC_REG REG_MM(0x016C) |
| 230 | #define MDP_MD0_REG REG_MM(0x00C4) |
| 231 | #define MDP_MD1_REG REG_MM(0x00C8) |
| 232 | #define MDP_NS_REG REG_MM(0x00D0) |
| 233 | #define MISC_CC_REG REG_MM(0x0058) |
| 234 | #define MISC_CC2_REG REG_MM(0x005C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 235 | #define MISC_CC3_REG REG_MM(0x0238) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 236 | #define MM_PLL1_MODE_REG REG_MM(0x031C) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 237 | #define MM_PLL1_L_VAL_REG REG_MM(0x0320) |
| 238 | #define MM_PLL1_M_VAL_REG REG_MM(0x0324) |
| 239 | #define MM_PLL1_N_VAL_REG REG_MM(0x0328) |
| 240 | #define MM_PLL1_CONFIG_REG REG_MM(0x032C) |
| 241 | #define MM_PLL1_TEST_CTL_REG REG_MM(0x0330) |
| 242 | #define MM_PLL1_STATUS_REG REG_MM(0x0334) |
| 243 | #define MM_PLL3_MODE_REG REG_MM(0x0338) |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 244 | #define MM_PLL3_L_VAL_REG REG_MM(0x033C) |
| 245 | #define MM_PLL3_M_VAL_REG REG_MM(0x0340) |
| 246 | #define MM_PLL3_N_VAL_REG REG_MM(0x0344) |
| 247 | #define MM_PLL3_CONFIG_REG REG_MM(0x0348) |
| 248 | #define MM_PLL3_TEST_CTL_REG REG_MM(0x034C) |
| 249 | #define MM_PLL3_STATUS_REG REG_MM(0x0350) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 250 | #define ROT_CC_REG REG_MM(0x00E0) |
| 251 | #define ROT_NS_REG REG_MM(0x00E8) |
| 252 | #define SAXI_EN_REG REG_MM(0x0030) |
| 253 | #define SW_RESET_AHB_REG REG_MM(0x020C) |
| 254 | #define SW_RESET_AHB2_REG REG_MM(0x0200) |
| 255 | #define SW_RESET_ALL_REG REG_MM(0x0204) |
| 256 | #define SW_RESET_AXI_REG REG_MM(0x0208) |
| 257 | #define SW_RESET_CORE_REG REG_MM(0x0210) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 258 | #define SW_RESET_CORE2_REG REG_MM(0x0214) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 259 | #define TV_CC_REG REG_MM(0x00EC) |
| 260 | #define TV_CC2_REG REG_MM(0x0124) |
| 261 | #define TV_MD_REG REG_MM(0x00F0) |
| 262 | #define TV_NS_REG REG_MM(0x00F4) |
| 263 | #define VCODEC_CC_REG REG_MM(0x00F8) |
| 264 | #define VCODEC_MD0_REG REG_MM(0x00FC) |
| 265 | #define VCODEC_MD1_REG REG_MM(0x0128) |
| 266 | #define VCODEC_NS_REG REG_MM(0x0100) |
| 267 | #define VFE_CC_REG REG_MM(0x0104) |
| 268 | #define VFE_MD_REG REG_MM(0x0108) |
| 269 | #define VFE_NS_REG REG_MM(0x010C) |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 270 | #define VFE_CC2_REG REG_MM(0x023C) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 271 | #define VPE_CC_REG REG_MM(0x0110) |
| 272 | #define VPE_NS_REG REG_MM(0x0118) |
| 273 | |
| 274 | /* Low-power Audio clock registers. */ |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 275 | #define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 276 | #define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8) |
| 277 | #define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064) |
| 278 | #define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060) |
| 279 | #define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068) |
| 280 | #define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070) |
| 281 | #define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C) |
| 282 | #define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074) |
| 283 | #define LCC_MI2S_MD_REG REG_LPA(0x004C) |
| 284 | #define LCC_MI2S_NS_REG REG_LPA(0x0048) |
| 285 | #define LCC_MI2S_STATUS_REG REG_LPA(0x0050) |
| 286 | #define LCC_PCM_MD_REG REG_LPA(0x0058) |
| 287 | #define LCC_PCM_NS_REG REG_LPA(0x0054) |
| 288 | #define LCC_PCM_STATUS_REG REG_LPA(0x005C) |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 289 | #define LCC_PLL0_MODE_REG REG_LPA(0x0000) |
| 290 | #define LCC_PLL0_L_VAL_REG REG_LPA(0x0004) |
| 291 | #define LCC_PLL0_M_VAL_REG REG_LPA(0x0008) |
| 292 | #define LCC_PLL0_N_VAL_REG REG_LPA(0x000C) |
| 293 | #define LCC_PLL0_CONFIG_REG REG_LPA(0x0014) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 294 | #define LCC_PLL0_STATUS_REG REG_LPA(0x0018) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 295 | #define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C) |
| 296 | #define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078) |
| 297 | #define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080) |
| 298 | #define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088) |
| 299 | #define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084) |
| 300 | #define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C) |
| 301 | #define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC) |
| 302 | #define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0) |
| 303 | #define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4) |
| 304 | #define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4) |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 305 | #define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 306 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 307 | #define GCC_APCS_CLK_DIAG REG_GCC(0x001C) |
| 308 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 309 | /* MUX source input identifiers. */ |
| 310 | #define pxo_to_bb_mux 0 |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 311 | #define cxo_to_bb_mux 5 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 312 | #define pll0_to_bb_mux 2 |
| 313 | #define pll8_to_bb_mux 3 |
| 314 | #define pll6_to_bb_mux 4 |
| 315 | #define gnd_to_bb_mux 5 |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 316 | #define pll3_to_bb_mux 6 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 317 | #define pxo_to_mm_mux 0 |
| 318 | #define pll1_to_mm_mux 1 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 319 | #define pll2_to_mm_mux 1 /* or MMCC_PLL1 */ |
| 320 | #define pll8_to_mm_mux 2 /* or GCC_PERF */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 321 | #define pll0_to_mm_mux 3 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 322 | #define pll15_to_mm_mux 3 /* or MM_PLL3 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 323 | #define gnd_to_mm_mux 4 |
Stephen Boyd | 7a776cd | 2011-10-20 12:46:04 -0700 | [diff] [blame] | 324 | #define pll3_to_mm_mux 3 /* or MMCC_PLL2 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 325 | #define hdmi_pll_to_mm_mux 3 |
| 326 | #define cxo_to_xo_mux 0 |
| 327 | #define pxo_to_xo_mux 1 |
| 328 | #define gnd_to_xo_mux 3 |
| 329 | #define pxo_to_lpa_mux 0 |
| 330 | #define cxo_to_lpa_mux 1 |
| 331 | #define pll4_to_lpa_mux 2 |
| 332 | #define gnd_to_lpa_mux 6 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 333 | #define pxo_to_pcie_mux 0 |
| 334 | #define pll3_to_pcie_mux 1 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 335 | |
| 336 | /* Test Vector Macros */ |
| 337 | #define TEST_TYPE_PER_LS 1 |
| 338 | #define TEST_TYPE_PER_HS 2 |
| 339 | #define TEST_TYPE_MM_LS 3 |
| 340 | #define TEST_TYPE_MM_HS 4 |
| 341 | #define TEST_TYPE_LPA 5 |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 342 | #define TEST_TYPE_CPUL2 6 |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 343 | #define TEST_TYPE_LPA_HS 7 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 344 | #define TEST_TYPE_SHIFT 24 |
| 345 | #define TEST_CLK_SEL_MASK BM(23, 0) |
| 346 | #define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s))) |
| 347 | #define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS) |
| 348 | #define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS) |
| 349 | #define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS) |
| 350 | #define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS) |
| 351 | #define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA) |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 352 | #define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS) |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 353 | #define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 354 | |
| 355 | #define MN_MODE_DUAL_EDGE 0x2 |
| 356 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 357 | struct pll_rate { |
| 358 | const uint32_t l_val; |
| 359 | const uint32_t m_val; |
| 360 | const uint32_t n_val; |
| 361 | const uint32_t vco; |
| 362 | const uint32_t post_div; |
| 363 | const uint32_t i_bits; |
| 364 | }; |
| 365 | #define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i } |
| 366 | |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 367 | static int rpm_vreg_id_vdd_dig; |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 368 | static int rpm_vreg_id_vdd_sr2_pll; |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 369 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 370 | enum vdd_dig_levels { |
| 371 | VDD_DIG_NONE, |
| 372 | VDD_DIG_LOW, |
| 373 | VDD_DIG_NOMINAL, |
| 374 | VDD_DIG_HIGH |
| 375 | }; |
| 376 | |
| 377 | static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level) |
| 378 | { |
| 379 | static const int vdd_uv[] = { |
| 380 | [VDD_DIG_NONE] = 0, |
| 381 | [VDD_DIG_LOW] = 945000, |
| 382 | [VDD_DIG_NOMINAL] = 1050000, |
| 383 | [VDD_DIG_HIGH] = 1150000 |
| 384 | }; |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 385 | return rpm_vreg_set_voltage(rpm_vreg_id_vdd_dig, RPM_VREG_VOTER3, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 386 | vdd_uv[level], 1150000, 1); |
| 387 | } |
| 388 | |
| 389 | static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig); |
| 390 | |
| 391 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
| 392 | .vdd_class = &vdd_dig, \ |
| 393 | .fmax[VDD_DIG_##l1] = (f1) |
| 394 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
| 395 | .vdd_class = &vdd_dig, \ |
| 396 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 397 | .fmax[VDD_DIG_##l2] = (f2) |
| 398 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
| 399 | .vdd_class = &vdd_dig, \ |
| 400 | .fmax[VDD_DIG_##l1] = (f1), \ |
| 401 | .fmax[VDD_DIG_##l2] = (f2), \ |
| 402 | .fmax[VDD_DIG_##l3] = (f3) |
| 403 | |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 404 | enum vdd_sr2_pll_levels { |
| 405 | VDD_SR2_PLL_OFF, |
| 406 | VDD_SR2_PLL_ON |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 407 | }; |
| 408 | |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 409 | static int set_vdd_sr2_pll(struct clk_vdd_class *vdd_class, int level) |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 410 | { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 411 | int rc = 0; |
| 412 | if (cpu_is_msm8960()) { |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 413 | if (level == VDD_SR2_PLL_OFF) { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 414 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 415 | RPM_VREG_VOTER3, 0, 0, 1); |
| 416 | if (rc) |
| 417 | return rc; |
| 418 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
| 419 | RPM_VREG_VOTER3, 0, 0, 1); |
| 420 | if (rc) |
| 421 | rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 422 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
| 423 | } else { |
| 424 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
| 425 | RPM_VREG_VOTER3, 2200000, 2200000, 1); |
| 426 | if (rc) |
| 427 | return rc; |
| 428 | rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23, |
| 429 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
| 430 | if (rc) |
| 431 | rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8, |
| 432 | RPM_VREG_VOTER3, 0, 0, 1); |
| 433 | } |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 434 | } else { |
| 435 | if (level == VDD_SR2_PLL_OFF) { |
| 436 | rc = rpm_vreg_set_voltage(rpm_vreg_id_vdd_sr2_pll, |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 437 | RPM_VREG_VOTER3, 0, 0, 1); |
| 438 | if (rc) |
| 439 | return rc; |
| 440 | } else { |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 441 | rc = rpm_vreg_set_voltage(rpm_vreg_id_vdd_sr2_pll, |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 442 | RPM_VREG_VOTER3, 1800000, 1800000, 1); |
| 443 | if (rc) |
| 444 | return rc; |
| 445 | } |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | return rc; |
| 449 | } |
| 450 | |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 451 | static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll); |
Matt Wagantall | c57577d | 2011-10-06 17:06:53 -0700 | [diff] [blame] | 452 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 453 | /* |
| 454 | * Clock Descriptions |
| 455 | */ |
| 456 | |
| 457 | static struct msm_xo_voter *xo_pxo, *xo_cxo; |
| 458 | |
| 459 | static int pxo_clk_enable(struct clk *clk) |
| 460 | { |
| 461 | return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON); |
| 462 | } |
| 463 | |
| 464 | static void pxo_clk_disable(struct clk *clk) |
| 465 | { |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 466 | msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static struct clk_ops clk_ops_pxo = { |
| 470 | .enable = pxo_clk_enable, |
| 471 | .disable = pxo_clk_disable, |
| 472 | .get_rate = fixed_clk_get_rate, |
| 473 | .is_local = local_clk_is_local, |
| 474 | }; |
| 475 | |
| 476 | static struct fixed_clk pxo_clk = { |
| 477 | .rate = 27000000, |
| 478 | .c = { |
| 479 | .dbg_name = "pxo_clk", |
| 480 | .ops = &clk_ops_pxo, |
| 481 | CLK_INIT(pxo_clk.c), |
| 482 | }, |
| 483 | }; |
| 484 | |
| 485 | static int cxo_clk_enable(struct clk *clk) |
| 486 | { |
| 487 | return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON); |
| 488 | } |
| 489 | |
| 490 | static void cxo_clk_disable(struct clk *clk) |
| 491 | { |
| 492 | msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF); |
| 493 | } |
| 494 | |
| 495 | static struct clk_ops clk_ops_cxo = { |
| 496 | .enable = cxo_clk_enable, |
| 497 | .disable = cxo_clk_disable, |
| 498 | .get_rate = fixed_clk_get_rate, |
| 499 | .is_local = local_clk_is_local, |
| 500 | }; |
| 501 | |
| 502 | static struct fixed_clk cxo_clk = { |
| 503 | .rate = 19200000, |
| 504 | .c = { |
| 505 | .dbg_name = "cxo_clk", |
| 506 | .ops = &clk_ops_cxo, |
| 507 | CLK_INIT(cxo_clk.c), |
| 508 | }, |
| 509 | }; |
| 510 | |
| 511 | static struct pll_clk pll2_clk = { |
| 512 | .rate = 800000000, |
| 513 | .mode_reg = MM_PLL1_MODE_REG, |
| 514 | .parent = &pxo_clk.c, |
| 515 | .c = { |
| 516 | .dbg_name = "pll2_clk", |
| 517 | .ops = &clk_ops_pll, |
| 518 | CLK_INIT(pll2_clk.c), |
| 519 | }, |
| 520 | }; |
| 521 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 522 | static struct pll_clk pll3_clk = { |
| 523 | .rate = 1200000000, |
| 524 | .mode_reg = BB_MMCC_PLL2_MODE_REG, |
| 525 | .parent = &pxo_clk.c, |
| 526 | .c = { |
| 527 | .dbg_name = "pll3_clk", |
| 528 | .ops = &clk_ops_pll, |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 529 | .vdd_class = &vdd_sr2_pll, |
| 530 | .fmax[VDD_SR2_PLL_ON] = ULONG_MAX, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 531 | CLK_INIT(pll3_clk.c), |
| 532 | }, |
| 533 | }; |
| 534 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 535 | static struct pll_vote_clk pll4_clk = { |
| 536 | .rate = 393216000, |
| 537 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 538 | .en_mask = BIT(4), |
| 539 | .status_reg = LCC_PLL0_STATUS_REG, |
| 540 | .parent = &pxo_clk.c, |
| 541 | .c = { |
| 542 | .dbg_name = "pll4_clk", |
| 543 | .ops = &clk_ops_pll_vote, |
| 544 | CLK_INIT(pll4_clk.c), |
| 545 | }, |
| 546 | }; |
| 547 | |
| 548 | static struct pll_vote_clk pll8_clk = { |
| 549 | .rate = 384000000, |
| 550 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 551 | .en_mask = BIT(8), |
| 552 | .status_reg = BB_PLL8_STATUS_REG, |
| 553 | .parent = &pxo_clk.c, |
| 554 | .c = { |
| 555 | .dbg_name = "pll8_clk", |
| 556 | .ops = &clk_ops_pll_vote, |
| 557 | CLK_INIT(pll8_clk.c), |
| 558 | }, |
| 559 | }; |
| 560 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 561 | static struct pll_vote_clk pll14_clk = { |
| 562 | .rate = 480000000, |
| 563 | .en_reg = BB_PLL_ENA_SC0_REG, |
| 564 | .en_mask = BIT(14), |
| 565 | .status_reg = BB_PLL14_STATUS_REG, |
| 566 | .parent = &pxo_clk.c, |
| 567 | .c = { |
| 568 | .dbg_name = "pll14_clk", |
| 569 | .ops = &clk_ops_pll_vote, |
| 570 | CLK_INIT(pll14_clk.c), |
| 571 | }, |
| 572 | }; |
| 573 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 574 | static struct pll_clk pll15_clk = { |
| 575 | .rate = 975000000, |
| 576 | .mode_reg = MM_PLL3_MODE_REG, |
| 577 | .parent = &pxo_clk.c, |
| 578 | .c = { |
| 579 | .dbg_name = "pll15_clk", |
| 580 | .ops = &clk_ops_pll, |
| 581 | CLK_INIT(pll15_clk.c), |
| 582 | }, |
| 583 | }; |
| 584 | |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 585 | static struct clk_ops clk_ops_rcg_8960 = { |
Matt Wagantall | 0625ea0 | 2011-07-13 18:51:56 -0700 | [diff] [blame] | 586 | .enable = rcg_clk_enable, |
| 587 | .disable = rcg_clk_disable, |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 588 | .enable_hwcg = rcg_clk_enable_hwcg, |
| 589 | .disable_hwcg = rcg_clk_disable_hwcg, |
| 590 | .in_hwcg_mode = rcg_clk_in_hwcg_mode, |
Matt Wagantall | 41af077 | 2011-09-17 12:21:39 -0700 | [diff] [blame] | 591 | .auto_off = rcg_clk_disable, |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 592 | .handoff = rcg_clk_handoff, |
Matt Wagantall | 0625ea0 | 2011-07-13 18:51:56 -0700 | [diff] [blame] | 593 | .set_rate = rcg_clk_set_rate, |
Matt Wagantall | 0625ea0 | 2011-07-13 18:51:56 -0700 | [diff] [blame] | 594 | .get_rate = rcg_clk_get_rate, |
| 595 | .list_rate = rcg_clk_list_rate, |
| 596 | .is_enabled = rcg_clk_is_enabled, |
| 597 | .round_rate = rcg_clk_round_rate, |
Stephen Boyd | 7bf2814 | 2011-12-07 00:30:52 -0800 | [diff] [blame] | 598 | .reset = rcg_clk_reset, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 599 | .is_local = local_clk_is_local, |
Matt Wagantall | 0625ea0 | 2011-07-13 18:51:56 -0700 | [diff] [blame] | 600 | .get_parent = rcg_clk_get_parent, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 601 | .set_flags = rcg_clk_set_flags, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 602 | }; |
| 603 | |
| 604 | static struct clk_ops clk_ops_branch = { |
| 605 | .enable = branch_clk_enable, |
| 606 | .disable = branch_clk_disable, |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 607 | .enable_hwcg = branch_clk_enable_hwcg, |
| 608 | .disable_hwcg = branch_clk_disable_hwcg, |
| 609 | .in_hwcg_mode = branch_clk_in_hwcg_mode, |
Matt Wagantall | 41af077 | 2011-09-17 12:21:39 -0700 | [diff] [blame] | 610 | .auto_off = branch_clk_disable, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 611 | .is_enabled = branch_clk_is_enabled, |
| 612 | .reset = branch_clk_reset, |
| 613 | .is_local = local_clk_is_local, |
| 614 | .get_parent = branch_clk_get_parent, |
| 615 | .set_parent = branch_clk_set_parent, |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 616 | .handoff = branch_clk_handoff, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 617 | .set_flags = branch_clk_set_flags, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 618 | }; |
| 619 | |
| 620 | static struct clk_ops clk_ops_reset = { |
| 621 | .reset = branch_clk_reset, |
| 622 | .is_local = local_clk_is_local, |
| 623 | }; |
| 624 | |
| 625 | /* AXI Interfaces */ |
| 626 | static struct branch_clk gmem_axi_clk = { |
| 627 | .b = { |
| 628 | .ctl_reg = MAXI_EN_REG, |
| 629 | .en_mask = BIT(24), |
| 630 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 631 | .halt_bit = 6, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 632 | .retain_reg = MAXI_EN2_REG, |
| 633 | .retain_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 634 | }, |
| 635 | .c = { |
| 636 | .dbg_name = "gmem_axi_clk", |
| 637 | .ops = &clk_ops_branch, |
| 638 | CLK_INIT(gmem_axi_clk.c), |
| 639 | }, |
| 640 | }; |
| 641 | |
| 642 | static struct branch_clk ijpeg_axi_clk = { |
| 643 | .b = { |
| 644 | .ctl_reg = MAXI_EN_REG, |
| 645 | .en_mask = BIT(21), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 646 | .hwcg_reg = MAXI_EN_REG, |
| 647 | .hwcg_mask = BIT(11), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 648 | .reset_reg = SW_RESET_AXI_REG, |
| 649 | .reset_mask = BIT(14), |
| 650 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 651 | .halt_bit = 4, |
| 652 | }, |
| 653 | .c = { |
| 654 | .dbg_name = "ijpeg_axi_clk", |
| 655 | .ops = &clk_ops_branch, |
| 656 | CLK_INIT(ijpeg_axi_clk.c), |
| 657 | }, |
| 658 | }; |
| 659 | |
| 660 | static struct branch_clk imem_axi_clk = { |
| 661 | .b = { |
| 662 | .ctl_reg = MAXI_EN_REG, |
| 663 | .en_mask = BIT(22), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 664 | .hwcg_reg = MAXI_EN_REG, |
| 665 | .hwcg_mask = BIT(15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 666 | .reset_reg = SW_RESET_CORE_REG, |
| 667 | .reset_mask = BIT(10), |
| 668 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 669 | .halt_bit = 7, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 670 | .retain_reg = MAXI_EN2_REG, |
| 671 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 672 | }, |
| 673 | .c = { |
| 674 | .dbg_name = "imem_axi_clk", |
| 675 | .ops = &clk_ops_branch, |
| 676 | CLK_INIT(imem_axi_clk.c), |
| 677 | }, |
| 678 | }; |
| 679 | |
| 680 | static struct branch_clk jpegd_axi_clk = { |
| 681 | .b = { |
| 682 | .ctl_reg = MAXI_EN_REG, |
| 683 | .en_mask = BIT(25), |
| 684 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 685 | .halt_bit = 5, |
| 686 | }, |
| 687 | .c = { |
| 688 | .dbg_name = "jpegd_axi_clk", |
| 689 | .ops = &clk_ops_branch, |
| 690 | CLK_INIT(jpegd_axi_clk.c), |
| 691 | }, |
| 692 | }; |
| 693 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 694 | static struct branch_clk vcodec_axi_b_clk = { |
| 695 | .b = { |
| 696 | .ctl_reg = MAXI_EN4_REG, |
| 697 | .en_mask = BIT(23), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 698 | .hwcg_reg = MAXI_EN4_REG, |
| 699 | .hwcg_mask = BIT(22), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 700 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 701 | .halt_bit = 25, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 702 | .retain_reg = MAXI_EN4_REG, |
| 703 | .retain_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 704 | }, |
| 705 | .c = { |
| 706 | .dbg_name = "vcodec_axi_b_clk", |
| 707 | .ops = &clk_ops_branch, |
| 708 | CLK_INIT(vcodec_axi_b_clk.c), |
| 709 | }, |
| 710 | }; |
| 711 | |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 712 | static struct branch_clk vcodec_axi_a_clk = { |
| 713 | .b = { |
| 714 | .ctl_reg = MAXI_EN4_REG, |
| 715 | .en_mask = BIT(25), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 716 | .hwcg_reg = MAXI_EN4_REG, |
| 717 | .hwcg_mask = BIT(24), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 718 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 719 | .halt_bit = 26, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 720 | .retain_reg = MAXI_EN4_REG, |
| 721 | .retain_mask = BIT(10), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 722 | }, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 723 | .c = { |
| 724 | .dbg_name = "vcodec_axi_a_clk", |
| 725 | .ops = &clk_ops_branch, |
| 726 | CLK_INIT(vcodec_axi_a_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 727 | .depends = &vcodec_axi_b_clk.c, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 728 | }, |
| 729 | }; |
| 730 | |
| 731 | static struct branch_clk vcodec_axi_clk = { |
| 732 | .b = { |
| 733 | .ctl_reg = MAXI_EN_REG, |
| 734 | .en_mask = BIT(19), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 735 | .hwcg_reg = MAXI_EN_REG, |
| 736 | .hwcg_mask = BIT(13), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 737 | .reset_reg = SW_RESET_AXI_REG, |
Gopikrishnaiah Anandan | 83b6e85 | 2012-01-05 17:47:02 -0800 | [diff] [blame] | 738 | .reset_mask = BIT(4)|BIT(5)|BIT(7), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 739 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 740 | .halt_bit = 3, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 741 | .retain_reg = MAXI_EN2_REG, |
| 742 | .retain_mask = BIT(28), |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 743 | }, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 744 | .c = { |
| 745 | .dbg_name = "vcodec_axi_clk", |
| 746 | .ops = &clk_ops_branch, |
| 747 | CLK_INIT(vcodec_axi_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 748 | .depends = &vcodec_axi_a_clk.c, |
Matt Wagantall | 91f4270 | 2011-07-14 12:01:15 -0700 | [diff] [blame] | 749 | }, |
| 750 | }; |
| 751 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 752 | static struct branch_clk vfe_axi_clk = { |
| 753 | .b = { |
| 754 | .ctl_reg = MAXI_EN_REG, |
| 755 | .en_mask = BIT(18), |
| 756 | .reset_reg = SW_RESET_AXI_REG, |
| 757 | .reset_mask = BIT(9), |
| 758 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 759 | .halt_bit = 0, |
| 760 | }, |
| 761 | .c = { |
| 762 | .dbg_name = "vfe_axi_clk", |
| 763 | .ops = &clk_ops_branch, |
| 764 | CLK_INIT(vfe_axi_clk.c), |
| 765 | }, |
| 766 | }; |
| 767 | |
| 768 | static struct branch_clk mdp_axi_clk = { |
| 769 | .b = { |
| 770 | .ctl_reg = MAXI_EN_REG, |
| 771 | .en_mask = BIT(23), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 772 | .hwcg_reg = MAXI_EN_REG, |
| 773 | .hwcg_mask = BIT(16), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 774 | .reset_reg = SW_RESET_AXI_REG, |
| 775 | .reset_mask = BIT(13), |
| 776 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 777 | .halt_bit = 8, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 778 | .retain_reg = MAXI_EN_REG, |
| 779 | .retain_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 780 | }, |
| 781 | .c = { |
| 782 | .dbg_name = "mdp_axi_clk", |
| 783 | .ops = &clk_ops_branch, |
| 784 | CLK_INIT(mdp_axi_clk.c), |
| 785 | }, |
| 786 | }; |
| 787 | |
| 788 | static struct branch_clk rot_axi_clk = { |
| 789 | .b = { |
| 790 | .ctl_reg = MAXI_EN2_REG, |
| 791 | .en_mask = BIT(24), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 792 | .hwcg_reg = MAXI_EN2_REG, |
| 793 | .hwcg_mask = BIT(25), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 794 | .reset_reg = SW_RESET_AXI_REG, |
| 795 | .reset_mask = BIT(6), |
| 796 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 797 | .halt_bit = 2, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 798 | .retain_reg = MAXI_EN3_REG, |
| 799 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 800 | }, |
| 801 | .c = { |
| 802 | .dbg_name = "rot_axi_clk", |
| 803 | .ops = &clk_ops_branch, |
| 804 | CLK_INIT(rot_axi_clk.c), |
| 805 | }, |
| 806 | }; |
| 807 | |
| 808 | static struct branch_clk vpe_axi_clk = { |
| 809 | .b = { |
| 810 | .ctl_reg = MAXI_EN2_REG, |
| 811 | .en_mask = BIT(26), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 812 | .hwcg_reg = MAXI_EN2_REG, |
| 813 | .hwcg_mask = BIT(27), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 814 | .reset_reg = SW_RESET_AXI_REG, |
| 815 | .reset_mask = BIT(15), |
| 816 | .halt_reg = DBG_BUS_VEC_E_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 817 | .halt_bit = 1, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 818 | .retain_reg = MAXI_EN3_REG, |
| 819 | .retain_mask = BIT(21), |
| 820 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 821 | }, |
| 822 | .c = { |
| 823 | .dbg_name = "vpe_axi_clk", |
| 824 | .ops = &clk_ops_branch, |
| 825 | CLK_INIT(vpe_axi_clk.c), |
| 826 | }, |
| 827 | }; |
| 828 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 829 | static struct branch_clk vcap_axi_clk = { |
| 830 | .b = { |
| 831 | .ctl_reg = MAXI_EN5_REG, |
| 832 | .en_mask = BIT(12), |
| 833 | .reset_reg = SW_RESET_AXI_REG, |
| 834 | .reset_mask = BIT(16), |
| 835 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 836 | .halt_bit = 20, |
| 837 | }, |
| 838 | .c = { |
| 839 | .dbg_name = "vcap_axi_clk", |
| 840 | .ops = &clk_ops_branch, |
| 841 | CLK_INIT(vcap_axi_clk.c), |
| 842 | }, |
| 843 | }; |
| 844 | |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 845 | /* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */ |
| 846 | static struct branch_clk gfx3d_axi_clk = { |
| 847 | .b = { |
| 848 | .ctl_reg = MAXI_EN5_REG, |
| 849 | .en_mask = BIT(25), |
| 850 | .reset_reg = SW_RESET_AXI_REG, |
| 851 | .reset_mask = BIT(17), |
| 852 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 853 | .halt_bit = 30, |
| 854 | }, |
| 855 | .c = { |
| 856 | .dbg_name = "gfx3d_axi_clk", |
| 857 | .ops = &clk_ops_branch, |
| 858 | CLK_INIT(gfx3d_axi_clk.c), |
| 859 | }, |
| 860 | }; |
| 861 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 862 | /* AHB Interfaces */ |
| 863 | static struct branch_clk amp_p_clk = { |
| 864 | .b = { |
| 865 | .ctl_reg = AHB_EN_REG, |
| 866 | .en_mask = BIT(24), |
| 867 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 868 | .halt_bit = 18, |
| 869 | }, |
| 870 | .c = { |
| 871 | .dbg_name = "amp_p_clk", |
| 872 | .ops = &clk_ops_branch, |
| 873 | CLK_INIT(amp_p_clk.c), |
| 874 | }, |
| 875 | }; |
| 876 | |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 877 | static struct branch_clk csi_p_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 878 | .b = { |
| 879 | .ctl_reg = AHB_EN_REG, |
| 880 | .en_mask = BIT(7), |
| 881 | .reset_reg = SW_RESET_AHB_REG, |
| 882 | .reset_mask = BIT(17), |
| 883 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 884 | .halt_bit = 16, |
| 885 | }, |
| 886 | .c = { |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 887 | .dbg_name = "csi_p_clk", |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 888 | .ops = &clk_ops_branch, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 889 | CLK_INIT(csi_p_clk.c), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 890 | }, |
| 891 | }; |
| 892 | |
| 893 | static struct branch_clk dsi1_m_p_clk = { |
| 894 | .b = { |
| 895 | .ctl_reg = AHB_EN_REG, |
| 896 | .en_mask = BIT(9), |
| 897 | .reset_reg = SW_RESET_AHB_REG, |
| 898 | .reset_mask = BIT(6), |
| 899 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 900 | .halt_bit = 19, |
| 901 | }, |
| 902 | .c = { |
| 903 | .dbg_name = "dsi1_m_p_clk", |
| 904 | .ops = &clk_ops_branch, |
| 905 | CLK_INIT(dsi1_m_p_clk.c), |
| 906 | }, |
| 907 | }; |
| 908 | |
| 909 | static struct branch_clk dsi1_s_p_clk = { |
| 910 | .b = { |
| 911 | .ctl_reg = AHB_EN_REG, |
| 912 | .en_mask = BIT(18), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 913 | .hwcg_reg = AHB_EN2_REG, |
| 914 | .hwcg_mask = BIT(20), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 915 | .reset_reg = SW_RESET_AHB_REG, |
| 916 | .reset_mask = BIT(5), |
| 917 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 918 | .halt_bit = 21, |
| 919 | }, |
| 920 | .c = { |
| 921 | .dbg_name = "dsi1_s_p_clk", |
| 922 | .ops = &clk_ops_branch, |
| 923 | CLK_INIT(dsi1_s_p_clk.c), |
| 924 | }, |
| 925 | }; |
| 926 | |
| 927 | static struct branch_clk dsi2_m_p_clk = { |
| 928 | .b = { |
| 929 | .ctl_reg = AHB_EN_REG, |
| 930 | .en_mask = BIT(17), |
| 931 | .reset_reg = SW_RESET_AHB2_REG, |
| 932 | .reset_mask = BIT(1), |
| 933 | .halt_reg = DBG_BUS_VEC_E_REG, |
| 934 | .halt_bit = 18, |
| 935 | }, |
| 936 | .c = { |
| 937 | .dbg_name = "dsi2_m_p_clk", |
| 938 | .ops = &clk_ops_branch, |
| 939 | CLK_INIT(dsi2_m_p_clk.c), |
| 940 | }, |
| 941 | }; |
| 942 | |
| 943 | static struct branch_clk dsi2_s_p_clk = { |
| 944 | .b = { |
| 945 | .ctl_reg = AHB_EN_REG, |
| 946 | .en_mask = BIT(22), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 947 | .hwcg_reg = AHB_EN2_REG, |
| 948 | .hwcg_mask = BIT(15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 949 | .reset_reg = SW_RESET_AHB2_REG, |
| 950 | .reset_mask = BIT(0), |
| 951 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 952 | .halt_bit = 20, |
| 953 | }, |
| 954 | .c = { |
| 955 | .dbg_name = "dsi2_s_p_clk", |
| 956 | .ops = &clk_ops_branch, |
| 957 | CLK_INIT(dsi2_s_p_clk.c), |
| 958 | }, |
| 959 | }; |
| 960 | |
| 961 | static struct branch_clk gfx2d0_p_clk = { |
| 962 | .b = { |
| 963 | .ctl_reg = AHB_EN_REG, |
| 964 | .en_mask = BIT(19), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 965 | .hwcg_reg = AHB_EN2_REG, |
| 966 | .hwcg_mask = BIT(28), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 967 | .reset_reg = SW_RESET_AHB_REG, |
| 968 | .reset_mask = BIT(12), |
| 969 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 970 | .halt_bit = 2, |
| 971 | }, |
| 972 | .c = { |
| 973 | .dbg_name = "gfx2d0_p_clk", |
| 974 | .ops = &clk_ops_branch, |
| 975 | CLK_INIT(gfx2d0_p_clk.c), |
| 976 | }, |
| 977 | }; |
| 978 | |
| 979 | static struct branch_clk gfx2d1_p_clk = { |
| 980 | .b = { |
| 981 | .ctl_reg = AHB_EN_REG, |
| 982 | .en_mask = BIT(2), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 983 | .hwcg_reg = AHB_EN2_REG, |
| 984 | .hwcg_mask = BIT(29), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 985 | .reset_reg = SW_RESET_AHB_REG, |
| 986 | .reset_mask = BIT(11), |
| 987 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 988 | .halt_bit = 3, |
| 989 | }, |
| 990 | .c = { |
| 991 | .dbg_name = "gfx2d1_p_clk", |
| 992 | .ops = &clk_ops_branch, |
| 993 | CLK_INIT(gfx2d1_p_clk.c), |
| 994 | }, |
| 995 | }; |
| 996 | |
| 997 | static struct branch_clk gfx3d_p_clk = { |
| 998 | .b = { |
| 999 | .ctl_reg = AHB_EN_REG, |
| 1000 | .en_mask = BIT(3), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1001 | .hwcg_reg = AHB_EN2_REG, |
| 1002 | .hwcg_mask = BIT(27), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1003 | .reset_reg = SW_RESET_AHB_REG, |
| 1004 | .reset_mask = BIT(10), |
| 1005 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1006 | .halt_bit = 4, |
| 1007 | }, |
| 1008 | .c = { |
| 1009 | .dbg_name = "gfx3d_p_clk", |
| 1010 | .ops = &clk_ops_branch, |
| 1011 | CLK_INIT(gfx3d_p_clk.c), |
| 1012 | }, |
| 1013 | }; |
| 1014 | |
| 1015 | static struct branch_clk hdmi_m_p_clk = { |
| 1016 | .b = { |
| 1017 | .ctl_reg = AHB_EN_REG, |
| 1018 | .en_mask = BIT(14), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1019 | .hwcg_reg = AHB_EN2_REG, |
| 1020 | .hwcg_mask = BIT(21), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1021 | .reset_reg = SW_RESET_AHB_REG, |
| 1022 | .reset_mask = BIT(9), |
| 1023 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1024 | .halt_bit = 5, |
| 1025 | }, |
| 1026 | .c = { |
| 1027 | .dbg_name = "hdmi_m_p_clk", |
| 1028 | .ops = &clk_ops_branch, |
| 1029 | CLK_INIT(hdmi_m_p_clk.c), |
| 1030 | }, |
| 1031 | }; |
| 1032 | |
| 1033 | static struct branch_clk hdmi_s_p_clk = { |
| 1034 | .b = { |
| 1035 | .ctl_reg = AHB_EN_REG, |
| 1036 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1037 | .hwcg_reg = AHB_EN2_REG, |
| 1038 | .hwcg_mask = BIT(22), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1039 | .reset_reg = SW_RESET_AHB_REG, |
| 1040 | .reset_mask = BIT(9), |
| 1041 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1042 | .halt_bit = 6, |
| 1043 | }, |
| 1044 | .c = { |
| 1045 | .dbg_name = "hdmi_s_p_clk", |
| 1046 | .ops = &clk_ops_branch, |
| 1047 | CLK_INIT(hdmi_s_p_clk.c), |
| 1048 | }, |
| 1049 | }; |
| 1050 | |
| 1051 | static struct branch_clk ijpeg_p_clk = { |
| 1052 | .b = { |
| 1053 | .ctl_reg = AHB_EN_REG, |
| 1054 | .en_mask = BIT(5), |
| 1055 | .reset_reg = SW_RESET_AHB_REG, |
| 1056 | .reset_mask = BIT(7), |
| 1057 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1058 | .halt_bit = 9, |
| 1059 | }, |
| 1060 | .c = { |
| 1061 | .dbg_name = "ijpeg_p_clk", |
| 1062 | .ops = &clk_ops_branch, |
| 1063 | CLK_INIT(ijpeg_p_clk.c), |
| 1064 | }, |
| 1065 | }; |
| 1066 | |
| 1067 | static struct branch_clk imem_p_clk = { |
| 1068 | .b = { |
| 1069 | .ctl_reg = AHB_EN_REG, |
| 1070 | .en_mask = BIT(6), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1071 | .hwcg_reg = AHB_EN2_REG, |
| 1072 | .hwcg_mask = BIT(12), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1073 | .reset_reg = SW_RESET_AHB_REG, |
| 1074 | .reset_mask = BIT(8), |
| 1075 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1076 | .halt_bit = 10, |
| 1077 | }, |
| 1078 | .c = { |
| 1079 | .dbg_name = "imem_p_clk", |
| 1080 | .ops = &clk_ops_branch, |
| 1081 | CLK_INIT(imem_p_clk.c), |
| 1082 | }, |
| 1083 | }; |
| 1084 | |
| 1085 | static struct branch_clk jpegd_p_clk = { |
| 1086 | .b = { |
| 1087 | .ctl_reg = AHB_EN_REG, |
| 1088 | .en_mask = BIT(21), |
| 1089 | .reset_reg = SW_RESET_AHB_REG, |
| 1090 | .reset_mask = BIT(4), |
| 1091 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1092 | .halt_bit = 7, |
| 1093 | }, |
| 1094 | .c = { |
| 1095 | .dbg_name = "jpegd_p_clk", |
| 1096 | .ops = &clk_ops_branch, |
| 1097 | CLK_INIT(jpegd_p_clk.c), |
| 1098 | }, |
| 1099 | }; |
| 1100 | |
| 1101 | static struct branch_clk mdp_p_clk = { |
| 1102 | .b = { |
| 1103 | .ctl_reg = AHB_EN_REG, |
| 1104 | .en_mask = BIT(10), |
| 1105 | .reset_reg = SW_RESET_AHB_REG, |
| 1106 | .reset_mask = BIT(3), |
| 1107 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1108 | .halt_bit = 11, |
| 1109 | }, |
| 1110 | .c = { |
| 1111 | .dbg_name = "mdp_p_clk", |
| 1112 | .ops = &clk_ops_branch, |
| 1113 | CLK_INIT(mdp_p_clk.c), |
| 1114 | }, |
| 1115 | }; |
| 1116 | |
| 1117 | static struct branch_clk rot_p_clk = { |
| 1118 | .b = { |
| 1119 | .ctl_reg = AHB_EN_REG, |
| 1120 | .en_mask = BIT(12), |
| 1121 | .reset_reg = SW_RESET_AHB_REG, |
| 1122 | .reset_mask = BIT(2), |
| 1123 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1124 | .halt_bit = 13, |
| 1125 | }, |
| 1126 | .c = { |
| 1127 | .dbg_name = "rot_p_clk", |
| 1128 | .ops = &clk_ops_branch, |
| 1129 | CLK_INIT(rot_p_clk.c), |
| 1130 | }, |
| 1131 | }; |
| 1132 | |
| 1133 | static struct branch_clk smmu_p_clk = { |
| 1134 | .b = { |
| 1135 | .ctl_reg = AHB_EN_REG, |
| 1136 | .en_mask = BIT(15), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1137 | .hwcg_reg = AHB_EN_REG, |
| 1138 | .hwcg_mask = BIT(26), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1139 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1140 | .halt_bit = 22, |
| 1141 | }, |
| 1142 | .c = { |
| 1143 | .dbg_name = "smmu_p_clk", |
| 1144 | .ops = &clk_ops_branch, |
| 1145 | CLK_INIT(smmu_p_clk.c), |
| 1146 | }, |
| 1147 | }; |
| 1148 | |
| 1149 | static struct branch_clk tv_enc_p_clk = { |
| 1150 | .b = { |
| 1151 | .ctl_reg = AHB_EN_REG, |
| 1152 | .en_mask = BIT(25), |
| 1153 | .reset_reg = SW_RESET_AHB_REG, |
| 1154 | .reset_mask = BIT(15), |
| 1155 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1156 | .halt_bit = 23, |
| 1157 | }, |
| 1158 | .c = { |
| 1159 | .dbg_name = "tv_enc_p_clk", |
| 1160 | .ops = &clk_ops_branch, |
| 1161 | CLK_INIT(tv_enc_p_clk.c), |
| 1162 | }, |
| 1163 | }; |
| 1164 | |
| 1165 | static struct branch_clk vcodec_p_clk = { |
| 1166 | .b = { |
| 1167 | .ctl_reg = AHB_EN_REG, |
| 1168 | .en_mask = BIT(11), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1169 | .hwcg_reg = AHB_EN2_REG, |
| 1170 | .hwcg_mask = BIT(26), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1171 | .reset_reg = SW_RESET_AHB_REG, |
| 1172 | .reset_mask = BIT(1), |
| 1173 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1174 | .halt_bit = 12, |
| 1175 | }, |
| 1176 | .c = { |
| 1177 | .dbg_name = "vcodec_p_clk", |
| 1178 | .ops = &clk_ops_branch, |
| 1179 | CLK_INIT(vcodec_p_clk.c), |
| 1180 | }, |
| 1181 | }; |
| 1182 | |
| 1183 | static struct branch_clk vfe_p_clk = { |
| 1184 | .b = { |
| 1185 | .ctl_reg = AHB_EN_REG, |
| 1186 | .en_mask = BIT(13), |
| 1187 | .reset_reg = SW_RESET_AHB_REG, |
| 1188 | .reset_mask = BIT(0), |
| 1189 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1190 | .halt_bit = 14, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 1191 | .retain_reg = AHB_EN2_REG, |
| 1192 | .retain_mask = BIT(0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1193 | }, |
| 1194 | .c = { |
| 1195 | .dbg_name = "vfe_p_clk", |
| 1196 | .ops = &clk_ops_branch, |
| 1197 | CLK_INIT(vfe_p_clk.c), |
| 1198 | }, |
| 1199 | }; |
| 1200 | |
| 1201 | static struct branch_clk vpe_p_clk = { |
| 1202 | .b = { |
| 1203 | .ctl_reg = AHB_EN_REG, |
| 1204 | .en_mask = BIT(16), |
| 1205 | .reset_reg = SW_RESET_AHB_REG, |
| 1206 | .reset_mask = BIT(14), |
| 1207 | .halt_reg = DBG_BUS_VEC_F_REG, |
| 1208 | .halt_bit = 15, |
| 1209 | }, |
| 1210 | .c = { |
| 1211 | .dbg_name = "vpe_p_clk", |
| 1212 | .ops = &clk_ops_branch, |
| 1213 | CLK_INIT(vpe_p_clk.c), |
| 1214 | }, |
| 1215 | }; |
| 1216 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1217 | static struct branch_clk vcap_p_clk = { |
| 1218 | .b = { |
| 1219 | .ctl_reg = AHB_EN3_REG, |
| 1220 | .en_mask = BIT(1), |
| 1221 | .reset_reg = SW_RESET_AHB2_REG, |
| 1222 | .reset_mask = BIT(2), |
| 1223 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 1224 | .halt_bit = 23, |
| 1225 | }, |
| 1226 | .c = { |
| 1227 | .dbg_name = "vcap_p_clk", |
| 1228 | .ops = &clk_ops_branch, |
| 1229 | CLK_INIT(vcap_p_clk.c), |
| 1230 | }, |
| 1231 | }; |
| 1232 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1233 | /* |
| 1234 | * Peripheral Clocks |
| 1235 | */ |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 1236 | #define CLK_GP(i, n, h_r, h_b) \ |
| 1237 | struct rcg_clk i##_clk = { \ |
| 1238 | .b = { \ |
| 1239 | .ctl_reg = GPn_NS_REG(n), \ |
| 1240 | .en_mask = BIT(9), \ |
| 1241 | .halt_reg = h_r, \ |
| 1242 | .halt_bit = h_b, \ |
| 1243 | }, \ |
| 1244 | .ns_reg = GPn_NS_REG(n), \ |
| 1245 | .md_reg = GPn_MD_REG(n), \ |
| 1246 | .root_en_mask = BIT(11), \ |
| 1247 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 1248 | .set_rate = set_rate_mnd, \ |
| 1249 | .freq_tbl = clk_tbl_gp, \ |
| 1250 | .current_freq = &rcg_dummy_freq, \ |
| 1251 | .c = { \ |
| 1252 | .dbg_name = #i "_clk", \ |
| 1253 | .ops = &clk_ops_rcg_8960, \ |
| 1254 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \ |
| 1255 | CLK_INIT(i##_clk.c), \ |
| 1256 | }, \ |
| 1257 | } |
| 1258 | #define F_GP(f, s, d, m, n) \ |
| 1259 | { \ |
| 1260 | .freq_hz = f, \ |
| 1261 | .src_clk = &s##_clk.c, \ |
| 1262 | .md_val = MD8(16, m, 0, n), \ |
| 1263 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1264 | .mnd_en_mask = BIT(8) * !!(n), \ |
| 1265 | } |
| 1266 | static struct clk_freq_tbl clk_tbl_gp[] = { |
| 1267 | F_GP( 0, gnd, 1, 0, 0), |
| 1268 | F_GP( 9600000, cxo, 2, 0, 0), |
| 1269 | F_GP( 13500000, pxo, 2, 0, 0), |
| 1270 | F_GP( 19200000, cxo, 1, 0, 0), |
| 1271 | F_GP( 27000000, pxo, 1, 0, 0), |
| 1272 | F_GP( 64000000, pll8, 2, 1, 3), |
| 1273 | F_GP( 76800000, pll8, 1, 1, 5), |
| 1274 | F_GP( 96000000, pll8, 4, 0, 0), |
| 1275 | F_GP(128000000, pll8, 3, 0, 0), |
| 1276 | F_GP(192000000, pll8, 2, 0, 0), |
| 1277 | F_GP(384000000, pll8, 1, 0, 0), |
| 1278 | F_END |
| 1279 | }; |
| 1280 | |
| 1281 | static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7); |
| 1282 | static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6); |
| 1283 | static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5); |
| 1284 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1285 | #define CLK_GSBI_UART(i, n, h_r, h_b) \ |
| 1286 | struct rcg_clk i##_clk = { \ |
| 1287 | .b = { \ |
| 1288 | .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \ |
| 1289 | .en_mask = BIT(9), \ |
| 1290 | .reset_reg = GSBIn_RESET_REG(n), \ |
| 1291 | .reset_mask = BIT(0), \ |
| 1292 | .halt_reg = h_r, \ |
| 1293 | .halt_bit = h_b, \ |
| 1294 | }, \ |
| 1295 | .ns_reg = GSBIn_UART_APPS_NS_REG(n), \ |
| 1296 | .md_reg = GSBIn_UART_APPS_MD_REG(n), \ |
| 1297 | .root_en_mask = BIT(11), \ |
| 1298 | .ns_mask = (BM(31, 16) | BM(6, 0)), \ |
| 1299 | .set_rate = set_rate_mnd, \ |
| 1300 | .freq_tbl = clk_tbl_gsbi_uart, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1301 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1302 | .c = { \ |
| 1303 | .dbg_name = #i "_clk", \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1304 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1305 | VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1306 | CLK_INIT(i##_clk.c), \ |
| 1307 | }, \ |
| 1308 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1309 | #define F_GSBI_UART(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1310 | { \ |
| 1311 | .freq_hz = f, \ |
| 1312 | .src_clk = &s##_clk.c, \ |
| 1313 | .md_val = MD16(m, n), \ |
| 1314 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1315 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1316 | } |
| 1317 | static struct clk_freq_tbl clk_tbl_gsbi_uart[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1318 | F_GSBI_UART( 0, gnd, 1, 0, 0), |
Matt Wagantall | 9a561f7 | 2012-01-19 16:13:12 -0800 | [diff] [blame] | 1319 | F_GSBI_UART( 1843200, pll8, 2, 6, 625), |
| 1320 | F_GSBI_UART( 3686400, pll8, 2, 12, 625), |
| 1321 | F_GSBI_UART( 7372800, pll8, 2, 24, 625), |
| 1322 | F_GSBI_UART(14745600, pll8, 2, 48, 625), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1323 | F_GSBI_UART(16000000, pll8, 4, 1, 6), |
| 1324 | F_GSBI_UART(24000000, pll8, 4, 1, 4), |
| 1325 | F_GSBI_UART(32000000, pll8, 4, 1, 3), |
| 1326 | F_GSBI_UART(40000000, pll8, 1, 5, 48), |
| 1327 | F_GSBI_UART(46400000, pll8, 1, 29, 240), |
| 1328 | F_GSBI_UART(48000000, pll8, 4, 1, 2), |
| 1329 | F_GSBI_UART(51200000, pll8, 1, 2, 15), |
| 1330 | F_GSBI_UART(56000000, pll8, 1, 7, 48), |
| 1331 | F_GSBI_UART(58982400, pll8, 1, 96, 625), |
| 1332 | F_GSBI_UART(64000000, pll8, 2, 1, 3), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1333 | F_END |
| 1334 | }; |
| 1335 | |
| 1336 | static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10); |
| 1337 | static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6); |
| 1338 | static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2); |
| 1339 | static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26); |
| 1340 | static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22); |
| 1341 | static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18); |
| 1342 | static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14); |
| 1343 | static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10); |
| 1344 | static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6); |
| 1345 | static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2); |
| 1346 | static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17); |
| 1347 | static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13); |
| 1348 | |
| 1349 | #define CLK_GSBI_QUP(i, n, h_r, h_b) \ |
| 1350 | struct rcg_clk i##_clk = { \ |
| 1351 | .b = { \ |
| 1352 | .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \ |
| 1353 | .en_mask = BIT(9), \ |
| 1354 | .reset_reg = GSBIn_RESET_REG(n), \ |
| 1355 | .reset_mask = BIT(0), \ |
| 1356 | .halt_reg = h_r, \ |
| 1357 | .halt_bit = h_b, \ |
| 1358 | }, \ |
| 1359 | .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \ |
| 1360 | .md_reg = GSBIn_QUP_APPS_MD_REG(n), \ |
| 1361 | .root_en_mask = BIT(11), \ |
| 1362 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 1363 | .set_rate = set_rate_mnd, \ |
| 1364 | .freq_tbl = clk_tbl_gsbi_qup, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1365 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1366 | .c = { \ |
| 1367 | .dbg_name = #i "_clk", \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1368 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1369 | VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1370 | CLK_INIT(i##_clk.c), \ |
| 1371 | }, \ |
| 1372 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1373 | #define F_GSBI_QUP(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1374 | { \ |
| 1375 | .freq_hz = f, \ |
| 1376 | .src_clk = &s##_clk.c, \ |
| 1377 | .md_val = MD8(16, m, 0, n), \ |
| 1378 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1379 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1380 | } |
| 1381 | static struct clk_freq_tbl clk_tbl_gsbi_qup[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1382 | F_GSBI_QUP( 0, gnd, 1, 0, 0), |
| 1383 | F_GSBI_QUP( 1100000, pxo, 1, 2, 49), |
| 1384 | F_GSBI_QUP( 5400000, pxo, 1, 1, 5), |
| 1385 | F_GSBI_QUP(10800000, pxo, 1, 2, 5), |
| 1386 | F_GSBI_QUP(15060000, pll8, 1, 2, 51), |
| 1387 | F_GSBI_QUP(24000000, pll8, 4, 1, 4), |
| 1388 | F_GSBI_QUP(25600000, pll8, 1, 1, 15), |
| 1389 | F_GSBI_QUP(27000000, pxo, 1, 0, 0), |
| 1390 | F_GSBI_QUP(48000000, pll8, 4, 1, 2), |
| 1391 | F_GSBI_QUP(51200000, pll8, 1, 2, 15), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1392 | F_END |
| 1393 | }; |
| 1394 | |
| 1395 | static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9); |
| 1396 | static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4); |
| 1397 | static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0); |
| 1398 | static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24); |
| 1399 | static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20); |
| 1400 | static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16); |
| 1401 | static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12); |
| 1402 | static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8); |
| 1403 | static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4); |
| 1404 | static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0); |
| 1405 | static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15); |
| 1406 | static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11); |
| 1407 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1408 | #define F_PDM(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1409 | { \ |
| 1410 | .freq_hz = f, \ |
| 1411 | .src_clk = &s##_clk.c, \ |
| 1412 | .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1413 | } |
| 1414 | static struct clk_freq_tbl clk_tbl_pdm[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1415 | F_PDM( 0, gnd, 1), |
| 1416 | F_PDM(27000000, pxo, 1), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1417 | F_END |
| 1418 | }; |
| 1419 | |
| 1420 | static struct rcg_clk pdm_clk = { |
| 1421 | .b = { |
| 1422 | .ctl_reg = PDM_CLK_NS_REG, |
| 1423 | .en_mask = BIT(9), |
| 1424 | .reset_reg = PDM_CLK_NS_REG, |
| 1425 | .reset_mask = BIT(12), |
| 1426 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1427 | .halt_bit = 3, |
| 1428 | }, |
| 1429 | .ns_reg = PDM_CLK_NS_REG, |
| 1430 | .root_en_mask = BIT(11), |
| 1431 | .ns_mask = BM(1, 0), |
| 1432 | .set_rate = set_rate_nop, |
| 1433 | .freq_tbl = clk_tbl_pdm, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1434 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1435 | .c = { |
| 1436 | .dbg_name = "pdm_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1437 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1438 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1439 | CLK_INIT(pdm_clk.c), |
| 1440 | }, |
| 1441 | }; |
| 1442 | |
| 1443 | static struct branch_clk pmem_clk = { |
| 1444 | .b = { |
| 1445 | .ctl_reg = PMEM_ACLK_CTL_REG, |
| 1446 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1447 | .hwcg_reg = PMEM_ACLK_CTL_REG, |
| 1448 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1449 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 1450 | .halt_bit = 20, |
| 1451 | }, |
| 1452 | .c = { |
| 1453 | .dbg_name = "pmem_clk", |
| 1454 | .ops = &clk_ops_branch, |
| 1455 | CLK_INIT(pmem_clk.c), |
| 1456 | }, |
| 1457 | }; |
| 1458 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1459 | #define F_PRNG(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1460 | { \ |
| 1461 | .freq_hz = f, \ |
| 1462 | .src_clk = &s##_clk.c, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1463 | } |
| 1464 | static struct clk_freq_tbl clk_tbl_prng[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1465 | F_PRNG(64000000, pll8), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1466 | F_END |
| 1467 | }; |
| 1468 | |
| 1469 | static struct rcg_clk prng_clk = { |
| 1470 | .b = { |
| 1471 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 1472 | .en_mask = BIT(10), |
| 1473 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 1474 | .halt_check = HALT_VOTED, |
| 1475 | .halt_bit = 10, |
| 1476 | }, |
| 1477 | .set_rate = set_rate_nop, |
| 1478 | .freq_tbl = clk_tbl_prng, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1479 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1480 | .c = { |
| 1481 | .dbg_name = "prng_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1482 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1483 | VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1484 | CLK_INIT(prng_clk.c), |
| 1485 | }, |
| 1486 | }; |
| 1487 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1488 | #define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1489 | struct rcg_clk name = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1490 | .b = { \ |
| 1491 | .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \ |
| 1492 | .en_mask = BIT(9), \ |
| 1493 | .reset_reg = SDCn_RESET_REG(n), \ |
| 1494 | .reset_mask = BIT(0), \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1495 | .halt_reg = CLK_HALT_DFAB_STATE_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1496 | .halt_bit = h_b, \ |
| 1497 | }, \ |
| 1498 | .ns_reg = SDCn_APPS_CLK_NS_REG(n), \ |
| 1499 | .md_reg = SDCn_APPS_CLK_MD_REG(n), \ |
| 1500 | .root_en_mask = BIT(11), \ |
| 1501 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 1502 | .set_rate = set_rate_mnd, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1503 | .freq_tbl = clk_tbl_sdc, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1504 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1505 | .c = { \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1506 | .dbg_name = #name, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1507 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1508 | VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \ |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1509 | CLK_INIT(name.c), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1510 | }, \ |
| 1511 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1512 | #define F_SDC(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1513 | { \ |
| 1514 | .freq_hz = f, \ |
| 1515 | .src_clk = &s##_clk.c, \ |
| 1516 | .md_val = MD8(16, m, 0, n), \ |
| 1517 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1518 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1519 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1520 | static struct clk_freq_tbl clk_tbl_sdc[] = { |
| 1521 | F_SDC( 0, gnd, 1, 0, 0), |
| 1522 | F_SDC( 144000, pxo, 3, 2, 125), |
| 1523 | F_SDC( 400000, pll8, 4, 1, 240), |
| 1524 | F_SDC( 16000000, pll8, 4, 1, 6), |
| 1525 | F_SDC( 17070000, pll8, 1, 2, 45), |
| 1526 | F_SDC( 20210000, pll8, 1, 1, 19), |
| 1527 | F_SDC( 24000000, pll8, 4, 1, 4), |
| 1528 | F_SDC( 48000000, pll8, 4, 1, 2), |
| 1529 | F_SDC( 64000000, pll8, 3, 1, 2), |
| 1530 | F_SDC( 96000000, pll8, 4, 0, 0), |
Subhash Jadavani | bd238ba | 2011-11-24 15:12:39 +0530 | [diff] [blame] | 1531 | F_SDC(192000000, pll8, 2, 0, 0), |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1532 | F_END |
| 1533 | }; |
| 1534 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1535 | static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000); |
| 1536 | static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000); |
| 1537 | static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000); |
| 1538 | static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000); |
| 1539 | static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000); |
Stephen Boyd | a78a740 | 2011-08-02 11:23:39 -0700 | [diff] [blame] | 1540 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1541 | #define F_TSIF_REF(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1542 | { \ |
| 1543 | .freq_hz = f, \ |
| 1544 | .src_clk = &s##_clk.c, \ |
| 1545 | .md_val = MD16(m, n), \ |
| 1546 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1547 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1548 | } |
| 1549 | static struct clk_freq_tbl clk_tbl_tsif_ref[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1550 | F_TSIF_REF( 0, gnd, 1, 0, 0), |
| 1551 | F_TSIF_REF(105000, pxo, 1, 1, 256), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1552 | F_END |
| 1553 | }; |
| 1554 | |
| 1555 | static struct rcg_clk tsif_ref_clk = { |
| 1556 | .b = { |
| 1557 | .ctl_reg = TSIF_REF_CLK_NS_REG, |
| 1558 | .en_mask = BIT(9), |
| 1559 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1560 | .halt_bit = 5, |
| 1561 | }, |
| 1562 | .ns_reg = TSIF_REF_CLK_NS_REG, |
| 1563 | .md_reg = TSIF_REF_CLK_MD_REG, |
| 1564 | .root_en_mask = BIT(11), |
| 1565 | .ns_mask = (BM(31, 16) | BM(6, 0)), |
| 1566 | .set_rate = set_rate_mnd, |
| 1567 | .freq_tbl = clk_tbl_tsif_ref, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1568 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1569 | .c = { |
| 1570 | .dbg_name = "tsif_ref_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1571 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1572 | VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1573 | CLK_INIT(tsif_ref_clk.c), |
| 1574 | }, |
| 1575 | }; |
| 1576 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1577 | #define F_TSSC(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1578 | { \ |
| 1579 | .freq_hz = f, \ |
| 1580 | .src_clk = &s##_clk.c, \ |
| 1581 | .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1582 | } |
| 1583 | static struct clk_freq_tbl clk_tbl_tssc[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1584 | F_TSSC( 0, gnd), |
| 1585 | F_TSSC(27000000, pxo), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1586 | F_END |
| 1587 | }; |
| 1588 | |
| 1589 | static struct rcg_clk tssc_clk = { |
| 1590 | .b = { |
| 1591 | .ctl_reg = TSSC_CLK_CTL_REG, |
| 1592 | .en_mask = BIT(4), |
| 1593 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1594 | .halt_bit = 4, |
| 1595 | }, |
| 1596 | .ns_reg = TSSC_CLK_CTL_REG, |
| 1597 | .ns_mask = BM(1, 0), |
| 1598 | .set_rate = set_rate_nop, |
| 1599 | .freq_tbl = clk_tbl_tssc, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1600 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1601 | .c = { |
| 1602 | .dbg_name = "tssc_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1603 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1604 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1605 | CLK_INIT(tssc_clk.c), |
| 1606 | }, |
| 1607 | }; |
| 1608 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1609 | #define CLK_USB_HS(name, n, h_b) \ |
| 1610 | static struct rcg_clk name = { \ |
| 1611 | .b = { \ |
| 1612 | .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \ |
| 1613 | .en_mask = BIT(9), \ |
| 1614 | .reset_reg = USB_HS##n##_RESET_REG, \ |
| 1615 | .reset_mask = BIT(0), \ |
| 1616 | .halt_reg = CLK_HALT_DFAB_STATE_REG, \ |
| 1617 | .halt_bit = h_b, \ |
| 1618 | }, \ |
| 1619 | .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \ |
| 1620 | .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \ |
| 1621 | .root_en_mask = BIT(11), \ |
| 1622 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 1623 | .set_rate = set_rate_mnd, \ |
| 1624 | .freq_tbl = clk_tbl_usb, \ |
| 1625 | .current_freq = &rcg_dummy_freq, \ |
| 1626 | .c = { \ |
| 1627 | .dbg_name = #name, \ |
| 1628 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1629 | VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1630 | CLK_INIT(name.c), \ |
| 1631 | }, \ |
| 1632 | } |
| 1633 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1634 | #define F_USB(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1635 | { \ |
| 1636 | .freq_hz = f, \ |
| 1637 | .src_clk = &s##_clk.c, \ |
| 1638 | .md_val = MD8(16, m, 0, n), \ |
| 1639 | .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \ |
| 1640 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1641 | } |
| 1642 | static struct clk_freq_tbl clk_tbl_usb[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1643 | F_USB( 0, gnd, 1, 0, 0), |
| 1644 | F_USB(60000000, pll8, 1, 5, 32), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1645 | F_END |
| 1646 | }; |
| 1647 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1648 | CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0); |
| 1649 | CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30); |
| 1650 | CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1651 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1652 | static struct clk_freq_tbl clk_tbl_usb_hsic[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1653 | F_USB( 0, gnd, 1, 0, 0), |
| 1654 | F_USB(60000000, pll8, 1, 5, 32), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1655 | F_END |
| 1656 | }; |
| 1657 | |
| 1658 | static struct rcg_clk usb_hsic_xcvr_fs_clk = { |
| 1659 | .b = { |
| 1660 | .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG, |
| 1661 | .en_mask = BIT(9), |
| 1662 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1663 | .halt_bit = 26, |
| 1664 | }, |
| 1665 | .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG, |
| 1666 | .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG, |
| 1667 | .root_en_mask = BIT(11), |
| 1668 | .ns_mask = (BM(23, 16) | BM(6, 0)), |
| 1669 | .set_rate = set_rate_mnd, |
| 1670 | .freq_tbl = clk_tbl_usb_hsic, |
| 1671 | .current_freq = &rcg_dummy_freq, |
| 1672 | .c = { |
| 1673 | .dbg_name = "usb_hsic_xcvr_fs_clk", |
| 1674 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1675 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1676 | CLK_INIT(usb_hsic_xcvr_fs_clk.c), |
| 1677 | }, |
| 1678 | }; |
| 1679 | |
| 1680 | static struct branch_clk usb_hsic_system_clk = { |
| 1681 | .b = { |
| 1682 | .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG, |
| 1683 | .en_mask = BIT(4), |
| 1684 | .reset_reg = USB_HSIC_RESET_REG, |
| 1685 | .reset_mask = BIT(0), |
| 1686 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1687 | .halt_bit = 24, |
| 1688 | }, |
| 1689 | .parent = &usb_hsic_xcvr_fs_clk.c, |
| 1690 | .c = { |
| 1691 | .dbg_name = "usb_hsic_system_clk", |
| 1692 | .ops = &clk_ops_branch, |
| 1693 | CLK_INIT(usb_hsic_system_clk.c), |
| 1694 | }, |
| 1695 | }; |
| 1696 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1697 | #define F_USB_HSIC(f, s) \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1698 | { \ |
| 1699 | .freq_hz = f, \ |
| 1700 | .src_clk = &s##_clk.c, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1701 | } |
| 1702 | static struct clk_freq_tbl clk_tbl_usb2_hsic[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1703 | F_USB_HSIC(480000000, pll14), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1704 | F_END |
| 1705 | }; |
| 1706 | |
| 1707 | static struct rcg_clk usb_hsic_hsic_src_clk = { |
| 1708 | .b = { |
| 1709 | .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG, |
| 1710 | .halt_check = NOCHECK, |
| 1711 | }, |
| 1712 | .root_en_mask = BIT(0), |
| 1713 | .set_rate = set_rate_nop, |
| 1714 | .freq_tbl = clk_tbl_usb2_hsic, |
| 1715 | .current_freq = &rcg_dummy_freq, |
| 1716 | .c = { |
| 1717 | .dbg_name = "usb_hsic_hsic_src_clk", |
| 1718 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1719 | VDD_DIG_FMAX_MAP1(LOW, 480000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1720 | CLK_INIT(usb_hsic_hsic_src_clk.c), |
| 1721 | }, |
| 1722 | }; |
| 1723 | |
| 1724 | static struct branch_clk usb_hsic_hsic_clk = { |
| 1725 | .b = { |
| 1726 | .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG, |
| 1727 | .en_mask = BIT(0), |
| 1728 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1729 | .halt_bit = 19, |
| 1730 | }, |
| 1731 | .parent = &usb_hsic_hsic_src_clk.c, |
| 1732 | .c = { |
| 1733 | .dbg_name = "usb_hsic_hsic_clk", |
| 1734 | .ops = &clk_ops_branch, |
| 1735 | CLK_INIT(usb_hsic_hsic_clk.c), |
| 1736 | }, |
| 1737 | }; |
| 1738 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1739 | #define F_USB_HSIO_CAL(f, s) \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1740 | { \ |
| 1741 | .freq_hz = f, \ |
| 1742 | .src_clk = &s##_clk.c, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1743 | } |
| 1744 | static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1745 | F_USB_HSIO_CAL(9000000, pxo), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1746 | F_END |
| 1747 | }; |
| 1748 | |
| 1749 | static struct rcg_clk usb_hsic_hsio_cal_clk = { |
| 1750 | .b = { |
| 1751 | .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG, |
| 1752 | .en_mask = BIT(0), |
| 1753 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1754 | .halt_bit = 23, |
| 1755 | }, |
| 1756 | .set_rate = set_rate_nop, |
| 1757 | .freq_tbl = clk_tbl_usb_hsio_cal, |
| 1758 | .current_freq = &rcg_dummy_freq, |
| 1759 | .c = { |
| 1760 | .dbg_name = "usb_hsic_hsio_cal_clk", |
Stephen Boyd | a0e82ec | 2011-09-19 12:18:45 -0700 | [diff] [blame] | 1761 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1762 | VDD_DIG_FMAX_MAP1(LOW, 10000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 1763 | CLK_INIT(usb_hsic_hsio_cal_clk.c), |
| 1764 | }, |
| 1765 | }; |
| 1766 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1767 | static struct branch_clk usb_phy0_clk = { |
| 1768 | .b = { |
| 1769 | .reset_reg = USB_PHY0_RESET_REG, |
| 1770 | .reset_mask = BIT(0), |
| 1771 | }, |
| 1772 | .c = { |
| 1773 | .dbg_name = "usb_phy0_clk", |
| 1774 | .ops = &clk_ops_reset, |
| 1775 | CLK_INIT(usb_phy0_clk.c), |
| 1776 | }, |
| 1777 | }; |
| 1778 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1779 | #define CLK_USB_FS(i, n, fmax_nom) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1780 | struct rcg_clk i##_clk = { \ |
| 1781 | .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \ |
| 1782 | .b = { \ |
| 1783 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \ |
| 1784 | .halt_check = NOCHECK, \ |
| 1785 | }, \ |
| 1786 | .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \ |
| 1787 | .root_en_mask = BIT(11), \ |
| 1788 | .ns_mask = (BM(23, 16) | BM(6, 0)), \ |
| 1789 | .set_rate = set_rate_mnd, \ |
| 1790 | .freq_tbl = clk_tbl_usb, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1791 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1792 | .c = { \ |
| 1793 | .dbg_name = #i "_clk", \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 1794 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1795 | VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1796 | CLK_INIT(i##_clk.c), \ |
| 1797 | }, \ |
| 1798 | } |
| 1799 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1800 | static CLK_USB_FS(usb_fs1_src, 1, 64000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1801 | static struct branch_clk usb_fs1_xcvr_clk = { |
| 1802 | .b = { |
| 1803 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1), |
| 1804 | .en_mask = BIT(9), |
| 1805 | .reset_reg = USB_FSn_RESET_REG(1), |
| 1806 | .reset_mask = BIT(1), |
| 1807 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1808 | .halt_bit = 15, |
| 1809 | }, |
| 1810 | .parent = &usb_fs1_src_clk.c, |
| 1811 | .c = { |
| 1812 | .dbg_name = "usb_fs1_xcvr_clk", |
| 1813 | .ops = &clk_ops_branch, |
| 1814 | CLK_INIT(usb_fs1_xcvr_clk.c), |
| 1815 | }, |
| 1816 | }; |
| 1817 | |
| 1818 | static struct branch_clk usb_fs1_sys_clk = { |
| 1819 | .b = { |
| 1820 | .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1), |
| 1821 | .en_mask = BIT(4), |
| 1822 | .reset_reg = USB_FSn_RESET_REG(1), |
| 1823 | .reset_mask = BIT(0), |
| 1824 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1825 | .halt_bit = 16, |
| 1826 | }, |
| 1827 | .parent = &usb_fs1_src_clk.c, |
| 1828 | .c = { |
| 1829 | .dbg_name = "usb_fs1_sys_clk", |
| 1830 | .ops = &clk_ops_branch, |
| 1831 | CLK_INIT(usb_fs1_sys_clk.c), |
| 1832 | }, |
| 1833 | }; |
| 1834 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1835 | static CLK_USB_FS(usb_fs2_src, 2, 60000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1836 | static struct branch_clk usb_fs2_xcvr_clk = { |
| 1837 | .b = { |
| 1838 | .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2), |
| 1839 | .en_mask = BIT(9), |
| 1840 | .reset_reg = USB_FSn_RESET_REG(2), |
| 1841 | .reset_mask = BIT(1), |
| 1842 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1843 | .halt_bit = 12, |
| 1844 | }, |
| 1845 | .parent = &usb_fs2_src_clk.c, |
| 1846 | .c = { |
| 1847 | .dbg_name = "usb_fs2_xcvr_clk", |
| 1848 | .ops = &clk_ops_branch, |
| 1849 | CLK_INIT(usb_fs2_xcvr_clk.c), |
| 1850 | }, |
| 1851 | }; |
| 1852 | |
| 1853 | static struct branch_clk usb_fs2_sys_clk = { |
| 1854 | .b = { |
| 1855 | .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2), |
| 1856 | .en_mask = BIT(4), |
| 1857 | .reset_reg = USB_FSn_RESET_REG(2), |
| 1858 | .reset_mask = BIT(0), |
| 1859 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 1860 | .halt_bit = 13, |
| 1861 | }, |
| 1862 | .parent = &usb_fs2_src_clk.c, |
| 1863 | .c = { |
| 1864 | .dbg_name = "usb_fs2_sys_clk", |
| 1865 | .ops = &clk_ops_branch, |
| 1866 | CLK_INIT(usb_fs2_sys_clk.c), |
| 1867 | }, |
| 1868 | }; |
| 1869 | |
| 1870 | /* Fast Peripheral Bus Clocks */ |
| 1871 | static struct branch_clk ce1_core_clk = { |
| 1872 | .b = { |
| 1873 | .ctl_reg = CE1_CORE_CLK_CTL_REG, |
| 1874 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 1875 | .hwcg_reg = CE1_CORE_CLK_CTL_REG, |
| 1876 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1877 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1878 | .halt_bit = 27, |
| 1879 | }, |
| 1880 | .c = { |
| 1881 | .dbg_name = "ce1_core_clk", |
| 1882 | .ops = &clk_ops_branch, |
| 1883 | CLK_INIT(ce1_core_clk.c), |
| 1884 | }, |
| 1885 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1886 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1887 | static struct branch_clk ce1_p_clk = { |
| 1888 | .b = { |
| 1889 | .ctl_reg = CE1_HCLK_CTL_REG, |
| 1890 | .en_mask = BIT(4), |
| 1891 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1892 | .halt_bit = 1, |
| 1893 | }, |
| 1894 | .c = { |
| 1895 | .dbg_name = "ce1_p_clk", |
| 1896 | .ops = &clk_ops_branch, |
| 1897 | CLK_INIT(ce1_p_clk.c), |
| 1898 | }, |
| 1899 | }; |
| 1900 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1901 | #define F_CE3(f, s, d) \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1902 | { \ |
| 1903 | .freq_hz = f, \ |
| 1904 | .src_clk = &s##_clk.c, \ |
| 1905 | .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1906 | } |
| 1907 | |
| 1908 | static struct clk_freq_tbl clk_tbl_ce3[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1909 | F_CE3( 0, gnd, 1), |
| 1910 | F_CE3( 48000000, pll8, 8), |
| 1911 | F_CE3(100000000, pll3, 12), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1912 | F_END |
| 1913 | }; |
| 1914 | |
| 1915 | static struct rcg_clk ce3_src_clk = { |
| 1916 | .b = { |
| 1917 | .ctl_reg = CE3_CLK_SRC_NS_REG, |
| 1918 | .halt_check = NOCHECK, |
| 1919 | }, |
| 1920 | .ns_reg = CE3_CLK_SRC_NS_REG, |
| 1921 | .root_en_mask = BIT(7), |
| 1922 | .ns_mask = BM(6, 0), |
| 1923 | .set_rate = set_rate_nop, |
| 1924 | .freq_tbl = clk_tbl_ce3, |
| 1925 | .current_freq = &rcg_dummy_freq, |
| 1926 | .c = { |
| 1927 | .dbg_name = "ce3_src_clk", |
| 1928 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 1929 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 1930 | CLK_INIT(ce3_src_clk.c), |
| 1931 | }, |
| 1932 | }; |
| 1933 | |
| 1934 | static struct branch_clk ce3_core_clk = { |
| 1935 | .b = { |
| 1936 | .ctl_reg = CE3_CORE_CLK_CTL_REG, |
| 1937 | .en_mask = BIT(4), |
| 1938 | .reset_reg = CE3_CORE_CLK_CTL_REG, |
| 1939 | .reset_mask = BIT(7), |
| 1940 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1941 | .halt_bit = 5, |
| 1942 | }, |
| 1943 | .parent = &ce3_src_clk.c, |
| 1944 | .c = { |
| 1945 | .dbg_name = "ce3_core_clk", |
| 1946 | .ops = &clk_ops_branch, |
| 1947 | CLK_INIT(ce3_core_clk.c), |
| 1948 | } |
| 1949 | }; |
| 1950 | |
| 1951 | static struct branch_clk ce3_p_clk = { |
| 1952 | .b = { |
| 1953 | .ctl_reg = CE3_HCLK_CTL_REG, |
| 1954 | .en_mask = BIT(4), |
| 1955 | .reset_reg = CE3_HCLK_CTL_REG, |
| 1956 | .reset_mask = BIT(7), |
| 1957 | .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG, |
| 1958 | .halt_bit = 16, |
| 1959 | }, |
| 1960 | .parent = &ce3_src_clk.c, |
| 1961 | .c = { |
| 1962 | .dbg_name = "ce3_p_clk", |
| 1963 | .ops = &clk_ops_branch, |
| 1964 | CLK_INIT(ce3_p_clk.c), |
| 1965 | } |
| 1966 | }; |
| 1967 | |
| 1968 | static struct branch_clk sata_phy_ref_clk = { |
| 1969 | .b = { |
| 1970 | .ctl_reg = SATA_PHY_REF_CLK_CTL_REG, |
| 1971 | .en_mask = BIT(4), |
| 1972 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 1973 | .halt_bit = 24, |
| 1974 | }, |
| 1975 | .parent = &pxo_clk.c, |
| 1976 | .c = { |
| 1977 | .dbg_name = "sata_phy_ref_clk", |
| 1978 | .ops = &clk_ops_branch, |
| 1979 | CLK_INIT(sata_phy_ref_clk.c), |
| 1980 | }, |
| 1981 | }; |
| 1982 | |
| 1983 | static struct branch_clk pcie_p_clk = { |
| 1984 | .b = { |
| 1985 | .ctl_reg = PCIE_HCLK_CTL_REG, |
| 1986 | .en_mask = BIT(4), |
| 1987 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 1988 | .halt_bit = 8, |
| 1989 | }, |
| 1990 | .c = { |
| 1991 | .dbg_name = "pcie_p_clk", |
| 1992 | .ops = &clk_ops_branch, |
| 1993 | CLK_INIT(pcie_p_clk.c), |
| 1994 | }, |
| 1995 | }; |
| 1996 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1997 | static struct branch_clk dma_bam_p_clk = { |
| 1998 | .b = { |
| 1999 | .ctl_reg = DMA_BAM_HCLK_CTL, |
| 2000 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2001 | .hwcg_reg = DMA_BAM_HCLK_CTL, |
| 2002 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2003 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2004 | .halt_bit = 12, |
| 2005 | }, |
| 2006 | .c = { |
| 2007 | .dbg_name = "dma_bam_p_clk", |
| 2008 | .ops = &clk_ops_branch, |
| 2009 | CLK_INIT(dma_bam_p_clk.c), |
| 2010 | }, |
| 2011 | }; |
| 2012 | |
| 2013 | static struct branch_clk gsbi1_p_clk = { |
| 2014 | .b = { |
| 2015 | .ctl_reg = GSBIn_HCLK_CTL_REG(1), |
| 2016 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2017 | .hwcg_reg = GSBIn_HCLK_CTL_REG(1), |
| 2018 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2019 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2020 | .halt_bit = 11, |
| 2021 | }, |
| 2022 | .c = { |
| 2023 | .dbg_name = "gsbi1_p_clk", |
| 2024 | .ops = &clk_ops_branch, |
| 2025 | CLK_INIT(gsbi1_p_clk.c), |
| 2026 | }, |
| 2027 | }; |
| 2028 | |
| 2029 | static struct branch_clk gsbi2_p_clk = { |
| 2030 | .b = { |
| 2031 | .ctl_reg = GSBIn_HCLK_CTL_REG(2), |
| 2032 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2033 | .hwcg_reg = GSBIn_HCLK_CTL_REG(2), |
| 2034 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2035 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2036 | .halt_bit = 7, |
| 2037 | }, |
| 2038 | .c = { |
| 2039 | .dbg_name = "gsbi2_p_clk", |
| 2040 | .ops = &clk_ops_branch, |
| 2041 | CLK_INIT(gsbi2_p_clk.c), |
| 2042 | }, |
| 2043 | }; |
| 2044 | |
| 2045 | static struct branch_clk gsbi3_p_clk = { |
| 2046 | .b = { |
| 2047 | .ctl_reg = GSBIn_HCLK_CTL_REG(3), |
| 2048 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2049 | .hwcg_reg = GSBIn_HCLK_CTL_REG(3), |
| 2050 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2051 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2052 | .halt_bit = 3, |
| 2053 | }, |
| 2054 | .c = { |
| 2055 | .dbg_name = "gsbi3_p_clk", |
| 2056 | .ops = &clk_ops_branch, |
| 2057 | CLK_INIT(gsbi3_p_clk.c), |
| 2058 | }, |
| 2059 | }; |
| 2060 | |
| 2061 | static struct branch_clk gsbi4_p_clk = { |
| 2062 | .b = { |
| 2063 | .ctl_reg = GSBIn_HCLK_CTL_REG(4), |
| 2064 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2065 | .hwcg_reg = GSBIn_HCLK_CTL_REG(4), |
| 2066 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2067 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2068 | .halt_bit = 27, |
| 2069 | }, |
| 2070 | .c = { |
| 2071 | .dbg_name = "gsbi4_p_clk", |
| 2072 | .ops = &clk_ops_branch, |
| 2073 | CLK_INIT(gsbi4_p_clk.c), |
| 2074 | }, |
| 2075 | }; |
| 2076 | |
| 2077 | static struct branch_clk gsbi5_p_clk = { |
| 2078 | .b = { |
| 2079 | .ctl_reg = GSBIn_HCLK_CTL_REG(5), |
| 2080 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2081 | .hwcg_reg = GSBIn_HCLK_CTL_REG(5), |
| 2082 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2083 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2084 | .halt_bit = 23, |
| 2085 | }, |
| 2086 | .c = { |
| 2087 | .dbg_name = "gsbi5_p_clk", |
| 2088 | .ops = &clk_ops_branch, |
| 2089 | CLK_INIT(gsbi5_p_clk.c), |
| 2090 | }, |
| 2091 | }; |
| 2092 | |
| 2093 | static struct branch_clk gsbi6_p_clk = { |
| 2094 | .b = { |
| 2095 | .ctl_reg = GSBIn_HCLK_CTL_REG(6), |
| 2096 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2097 | .hwcg_reg = GSBIn_HCLK_CTL_REG(6), |
| 2098 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2099 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2100 | .halt_bit = 19, |
| 2101 | }, |
| 2102 | .c = { |
| 2103 | .dbg_name = "gsbi6_p_clk", |
| 2104 | .ops = &clk_ops_branch, |
| 2105 | CLK_INIT(gsbi6_p_clk.c), |
| 2106 | }, |
| 2107 | }; |
| 2108 | |
| 2109 | static struct branch_clk gsbi7_p_clk = { |
| 2110 | .b = { |
| 2111 | .ctl_reg = GSBIn_HCLK_CTL_REG(7), |
| 2112 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2113 | .hwcg_reg = GSBIn_HCLK_CTL_REG(7), |
| 2114 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2115 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2116 | .halt_bit = 15, |
| 2117 | }, |
| 2118 | .c = { |
| 2119 | .dbg_name = "gsbi7_p_clk", |
| 2120 | .ops = &clk_ops_branch, |
| 2121 | CLK_INIT(gsbi7_p_clk.c), |
| 2122 | }, |
| 2123 | }; |
| 2124 | |
| 2125 | static struct branch_clk gsbi8_p_clk = { |
| 2126 | .b = { |
| 2127 | .ctl_reg = GSBIn_HCLK_CTL_REG(8), |
| 2128 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2129 | .hwcg_reg = GSBIn_HCLK_CTL_REG(8), |
| 2130 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2131 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2132 | .halt_bit = 11, |
| 2133 | }, |
| 2134 | .c = { |
| 2135 | .dbg_name = "gsbi8_p_clk", |
| 2136 | .ops = &clk_ops_branch, |
| 2137 | CLK_INIT(gsbi8_p_clk.c), |
| 2138 | }, |
| 2139 | }; |
| 2140 | |
| 2141 | static struct branch_clk gsbi9_p_clk = { |
| 2142 | .b = { |
| 2143 | .ctl_reg = GSBIn_HCLK_CTL_REG(9), |
| 2144 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2145 | .hwcg_reg = GSBIn_HCLK_CTL_REG(9), |
| 2146 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2147 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2148 | .halt_bit = 7, |
| 2149 | }, |
| 2150 | .c = { |
| 2151 | .dbg_name = "gsbi9_p_clk", |
| 2152 | .ops = &clk_ops_branch, |
| 2153 | CLK_INIT(gsbi9_p_clk.c), |
| 2154 | }, |
| 2155 | }; |
| 2156 | |
| 2157 | static struct branch_clk gsbi10_p_clk = { |
| 2158 | .b = { |
| 2159 | .ctl_reg = GSBIn_HCLK_CTL_REG(10), |
| 2160 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2161 | .hwcg_reg = GSBIn_HCLK_CTL_REG(10), |
| 2162 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2163 | .halt_reg = CLK_HALT_CFPB_STATEB_REG, |
| 2164 | .halt_bit = 3, |
| 2165 | }, |
| 2166 | .c = { |
| 2167 | .dbg_name = "gsbi10_p_clk", |
| 2168 | .ops = &clk_ops_branch, |
| 2169 | CLK_INIT(gsbi10_p_clk.c), |
| 2170 | }, |
| 2171 | }; |
| 2172 | |
| 2173 | static struct branch_clk gsbi11_p_clk = { |
| 2174 | .b = { |
| 2175 | .ctl_reg = GSBIn_HCLK_CTL_REG(11), |
| 2176 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2177 | .hwcg_reg = GSBIn_HCLK_CTL_REG(11), |
| 2178 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2179 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2180 | .halt_bit = 18, |
| 2181 | }, |
| 2182 | .c = { |
| 2183 | .dbg_name = "gsbi11_p_clk", |
| 2184 | .ops = &clk_ops_branch, |
| 2185 | CLK_INIT(gsbi11_p_clk.c), |
| 2186 | }, |
| 2187 | }; |
| 2188 | |
| 2189 | static struct branch_clk gsbi12_p_clk = { |
| 2190 | .b = { |
| 2191 | .ctl_reg = GSBIn_HCLK_CTL_REG(12), |
| 2192 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2193 | .hwcg_reg = GSBIn_HCLK_CTL_REG(12), |
| 2194 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2195 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2196 | .halt_bit = 14, |
| 2197 | }, |
| 2198 | .c = { |
| 2199 | .dbg_name = "gsbi12_p_clk", |
| 2200 | .ops = &clk_ops_branch, |
| 2201 | CLK_INIT(gsbi12_p_clk.c), |
| 2202 | }, |
| 2203 | }; |
| 2204 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2205 | static struct branch_clk sata_phy_cfg_clk = { |
| 2206 | .b = { |
| 2207 | .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG, |
| 2208 | .en_mask = BIT(4), |
| 2209 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2210 | .halt_bit = 12, |
| 2211 | }, |
| 2212 | .c = { |
| 2213 | .dbg_name = "sata_phy_cfg_clk", |
| 2214 | .ops = &clk_ops_branch, |
| 2215 | CLK_INIT(sata_phy_cfg_clk.c), |
Stephen Boyd | 973e4ba | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2216 | }, |
| 2217 | }; |
| 2218 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2219 | static struct branch_clk tsif_p_clk = { |
| 2220 | .b = { |
| 2221 | .ctl_reg = TSIF_HCLK_CTL_REG, |
| 2222 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2223 | .hwcg_reg = TSIF_HCLK_CTL_REG, |
| 2224 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2225 | .halt_reg = CLK_HALT_CFPB_STATEC_REG, |
| 2226 | .halt_bit = 7, |
| 2227 | }, |
| 2228 | .c = { |
| 2229 | .dbg_name = "tsif_p_clk", |
| 2230 | .ops = &clk_ops_branch, |
| 2231 | CLK_INIT(tsif_p_clk.c), |
| 2232 | }, |
| 2233 | }; |
| 2234 | |
| 2235 | static struct branch_clk usb_fs1_p_clk = { |
| 2236 | .b = { |
| 2237 | .ctl_reg = USB_FSn_HCLK_CTL_REG(1), |
| 2238 | .en_mask = BIT(4), |
| 2239 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2240 | .halt_bit = 17, |
| 2241 | }, |
| 2242 | .c = { |
| 2243 | .dbg_name = "usb_fs1_p_clk", |
| 2244 | .ops = &clk_ops_branch, |
| 2245 | CLK_INIT(usb_fs1_p_clk.c), |
| 2246 | }, |
| 2247 | }; |
| 2248 | |
| 2249 | static struct branch_clk usb_fs2_p_clk = { |
| 2250 | .b = { |
| 2251 | .ctl_reg = USB_FSn_HCLK_CTL_REG(2), |
| 2252 | .en_mask = BIT(4), |
| 2253 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2254 | .halt_bit = 14, |
| 2255 | }, |
| 2256 | .c = { |
| 2257 | .dbg_name = "usb_fs2_p_clk", |
| 2258 | .ops = &clk_ops_branch, |
| 2259 | CLK_INIT(usb_fs2_p_clk.c), |
| 2260 | }, |
| 2261 | }; |
| 2262 | |
| 2263 | static struct branch_clk usb_hs1_p_clk = { |
| 2264 | .b = { |
| 2265 | .ctl_reg = USB_HS1_HCLK_CTL_REG, |
| 2266 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2267 | .hwcg_reg = USB_HS1_HCLK_CTL_REG, |
| 2268 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2269 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2270 | .halt_bit = 1, |
| 2271 | }, |
| 2272 | .c = { |
| 2273 | .dbg_name = "usb_hs1_p_clk", |
| 2274 | .ops = &clk_ops_branch, |
| 2275 | CLK_INIT(usb_hs1_p_clk.c), |
| 2276 | }, |
| 2277 | }; |
| 2278 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 2279 | static struct branch_clk usb_hs3_p_clk = { |
| 2280 | .b = { |
| 2281 | .ctl_reg = USB_HS3_HCLK_CTL_REG, |
| 2282 | .en_mask = BIT(4), |
| 2283 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2284 | .halt_bit = 31, |
| 2285 | }, |
| 2286 | .c = { |
| 2287 | .dbg_name = "usb_hs3_p_clk", |
| 2288 | .ops = &clk_ops_branch, |
| 2289 | CLK_INIT(usb_hs3_p_clk.c), |
| 2290 | }, |
| 2291 | }; |
| 2292 | |
| 2293 | static struct branch_clk usb_hs4_p_clk = { |
| 2294 | .b = { |
| 2295 | .ctl_reg = USB_HS4_HCLK_CTL_REG, |
| 2296 | .en_mask = BIT(4), |
| 2297 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2298 | .halt_bit = 7, |
| 2299 | }, |
| 2300 | .c = { |
| 2301 | .dbg_name = "usb_hs4_p_clk", |
| 2302 | .ops = &clk_ops_branch, |
| 2303 | CLK_INIT(usb_hs4_p_clk.c), |
| 2304 | }, |
| 2305 | }; |
| 2306 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2307 | static struct branch_clk usb_hsic_p_clk = { |
| 2308 | .b = { |
| 2309 | .ctl_reg = USB_HSIC_HCLK_CTL_REG, |
| 2310 | .en_mask = BIT(4), |
| 2311 | .halt_reg = CLK_HALT_CFPB_STATEA_REG, |
| 2312 | .halt_bit = 28, |
| 2313 | }, |
| 2314 | .c = { |
| 2315 | .dbg_name = "usb_hsic_p_clk", |
| 2316 | .ops = &clk_ops_branch, |
| 2317 | CLK_INIT(usb_hsic_p_clk.c), |
| 2318 | }, |
| 2319 | }; |
| 2320 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2321 | static struct branch_clk sdc1_p_clk = { |
| 2322 | .b = { |
| 2323 | .ctl_reg = SDCn_HCLK_CTL_REG(1), |
| 2324 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2325 | .hwcg_reg = SDCn_HCLK_CTL_REG(1), |
| 2326 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2327 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2328 | .halt_bit = 11, |
| 2329 | }, |
| 2330 | .c = { |
| 2331 | .dbg_name = "sdc1_p_clk", |
| 2332 | .ops = &clk_ops_branch, |
| 2333 | CLK_INIT(sdc1_p_clk.c), |
| 2334 | }, |
| 2335 | }; |
| 2336 | |
| 2337 | static struct branch_clk sdc2_p_clk = { |
| 2338 | .b = { |
| 2339 | .ctl_reg = SDCn_HCLK_CTL_REG(2), |
| 2340 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2341 | .hwcg_reg = SDCn_HCLK_CTL_REG(2), |
| 2342 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2343 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2344 | .halt_bit = 10, |
| 2345 | }, |
| 2346 | .c = { |
| 2347 | .dbg_name = "sdc2_p_clk", |
| 2348 | .ops = &clk_ops_branch, |
| 2349 | CLK_INIT(sdc2_p_clk.c), |
| 2350 | }, |
| 2351 | }; |
| 2352 | |
| 2353 | static struct branch_clk sdc3_p_clk = { |
| 2354 | .b = { |
| 2355 | .ctl_reg = SDCn_HCLK_CTL_REG(3), |
| 2356 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2357 | .hwcg_reg = SDCn_HCLK_CTL_REG(3), |
| 2358 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2359 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2360 | .halt_bit = 9, |
| 2361 | }, |
| 2362 | .c = { |
| 2363 | .dbg_name = "sdc3_p_clk", |
| 2364 | .ops = &clk_ops_branch, |
| 2365 | CLK_INIT(sdc3_p_clk.c), |
| 2366 | }, |
| 2367 | }; |
| 2368 | |
| 2369 | static struct branch_clk sdc4_p_clk = { |
| 2370 | .b = { |
| 2371 | .ctl_reg = SDCn_HCLK_CTL_REG(4), |
| 2372 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2373 | .hwcg_reg = SDCn_HCLK_CTL_REG(4), |
| 2374 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2375 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2376 | .halt_bit = 8, |
| 2377 | }, |
| 2378 | .c = { |
| 2379 | .dbg_name = "sdc4_p_clk", |
| 2380 | .ops = &clk_ops_branch, |
| 2381 | CLK_INIT(sdc4_p_clk.c), |
| 2382 | }, |
| 2383 | }; |
| 2384 | |
| 2385 | static struct branch_clk sdc5_p_clk = { |
| 2386 | .b = { |
| 2387 | .ctl_reg = SDCn_HCLK_CTL_REG(5), |
| 2388 | .en_mask = BIT(4), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2389 | .hwcg_reg = SDCn_HCLK_CTL_REG(5), |
| 2390 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2391 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
| 2392 | .halt_bit = 7, |
| 2393 | }, |
| 2394 | .c = { |
| 2395 | .dbg_name = "sdc5_p_clk", |
| 2396 | .ops = &clk_ops_branch, |
| 2397 | CLK_INIT(sdc5_p_clk.c), |
| 2398 | }, |
| 2399 | }; |
| 2400 | |
| 2401 | /* HW-Voteable Clocks */ |
| 2402 | static struct branch_clk adm0_clk = { |
| 2403 | .b = { |
| 2404 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2405 | .en_mask = BIT(2), |
| 2406 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2407 | .halt_check = HALT_VOTED, |
| 2408 | .halt_bit = 14, |
| 2409 | }, |
| 2410 | .c = { |
| 2411 | .dbg_name = "adm0_clk", |
| 2412 | .ops = &clk_ops_branch, |
| 2413 | CLK_INIT(adm0_clk.c), |
| 2414 | }, |
| 2415 | }; |
| 2416 | |
| 2417 | static struct branch_clk adm0_p_clk = { |
| 2418 | .b = { |
| 2419 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2420 | .en_mask = BIT(3), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2421 | .hwcg_reg = ADM0_PBUS_CLK_CTL_REG, |
| 2422 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2423 | .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG, |
| 2424 | .halt_check = HALT_VOTED, |
| 2425 | .halt_bit = 13, |
| 2426 | }, |
| 2427 | .c = { |
| 2428 | .dbg_name = "adm0_p_clk", |
| 2429 | .ops = &clk_ops_branch, |
| 2430 | CLK_INIT(adm0_p_clk.c), |
| 2431 | }, |
| 2432 | }; |
| 2433 | |
| 2434 | static struct branch_clk pmic_arb0_p_clk = { |
| 2435 | .b = { |
| 2436 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2437 | .en_mask = BIT(8), |
| 2438 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2439 | .halt_check = HALT_VOTED, |
| 2440 | .halt_bit = 22, |
| 2441 | }, |
| 2442 | .c = { |
| 2443 | .dbg_name = "pmic_arb0_p_clk", |
| 2444 | .ops = &clk_ops_branch, |
| 2445 | CLK_INIT(pmic_arb0_p_clk.c), |
| 2446 | }, |
| 2447 | }; |
| 2448 | |
| 2449 | static struct branch_clk pmic_arb1_p_clk = { |
| 2450 | .b = { |
| 2451 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2452 | .en_mask = BIT(9), |
| 2453 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2454 | .halt_check = HALT_VOTED, |
| 2455 | .halt_bit = 21, |
| 2456 | }, |
| 2457 | .c = { |
| 2458 | .dbg_name = "pmic_arb1_p_clk", |
| 2459 | .ops = &clk_ops_branch, |
| 2460 | CLK_INIT(pmic_arb1_p_clk.c), |
| 2461 | }, |
| 2462 | }; |
| 2463 | |
| 2464 | static struct branch_clk pmic_ssbi2_clk = { |
| 2465 | .b = { |
| 2466 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2467 | .en_mask = BIT(7), |
| 2468 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2469 | .halt_check = HALT_VOTED, |
| 2470 | .halt_bit = 23, |
| 2471 | }, |
| 2472 | .c = { |
| 2473 | .dbg_name = "pmic_ssbi2_clk", |
| 2474 | .ops = &clk_ops_branch, |
| 2475 | CLK_INIT(pmic_ssbi2_clk.c), |
| 2476 | }, |
| 2477 | }; |
| 2478 | |
| 2479 | static struct branch_clk rpm_msg_ram_p_clk = { |
| 2480 | .b = { |
| 2481 | .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG, |
| 2482 | .en_mask = BIT(6), |
Stephen Boyd | a52d7e3 | 2011-11-10 11:59:00 -0800 | [diff] [blame] | 2483 | .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG, |
| 2484 | .hwcg_mask = BIT(6), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2485 | .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG, |
| 2486 | .halt_check = HALT_VOTED, |
| 2487 | .halt_bit = 12, |
| 2488 | }, |
| 2489 | .c = { |
| 2490 | .dbg_name = "rpm_msg_ram_p_clk", |
| 2491 | .ops = &clk_ops_branch, |
| 2492 | CLK_INIT(rpm_msg_ram_p_clk.c), |
| 2493 | }, |
| 2494 | }; |
| 2495 | |
| 2496 | /* |
| 2497 | * Multimedia Clocks |
| 2498 | */ |
| 2499 | |
| 2500 | static struct branch_clk amp_clk = { |
| 2501 | .b = { |
| 2502 | .reset_reg = SW_RESET_CORE_REG, |
| 2503 | .reset_mask = BIT(20), |
| 2504 | }, |
| 2505 | .c = { |
| 2506 | .dbg_name = "amp_clk", |
| 2507 | .ops = &clk_ops_reset, |
| 2508 | CLK_INIT(amp_clk.c), |
| 2509 | }, |
| 2510 | }; |
| 2511 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2512 | #define CLK_CAM(name, n, hb) \ |
| 2513 | struct rcg_clk name = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2514 | .b = { \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2515 | .ctl_reg = CAMCLK##n##_CC_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2516 | .en_mask = BIT(0), \ |
| 2517 | .halt_reg = DBG_BUS_VEC_I_REG, \ |
| 2518 | .halt_bit = hb, \ |
| 2519 | }, \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2520 | .ns_reg = CAMCLK##n##_NS_REG, \ |
| 2521 | .md_reg = CAMCLK##n##_MD_REG, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2522 | .root_en_mask = BIT(2), \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2523 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2524 | .ctl_mask = BM(7, 6), \ |
| 2525 | .set_rate = set_rate_mnd_8, \ |
| 2526 | .freq_tbl = clk_tbl_cam, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2527 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2528 | .c = { \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2529 | .dbg_name = #name, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2530 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2531 | VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \ |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2532 | CLK_INIT(name.c), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2533 | }, \ |
| 2534 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2535 | #define F_CAM(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2536 | { \ |
| 2537 | .freq_hz = f, \ |
| 2538 | .src_clk = &s##_clk.c, \ |
| 2539 | .md_val = MD8(8, m, 0, n), \ |
| 2540 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 2541 | .ctl_val = CC(6, n), \ |
| 2542 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2543 | } |
| 2544 | static struct clk_freq_tbl clk_tbl_cam[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2545 | F_CAM( 0, gnd, 1, 0, 0), |
| 2546 | F_CAM( 6000000, pll8, 4, 1, 16), |
| 2547 | F_CAM( 8000000, pll8, 4, 1, 12), |
| 2548 | F_CAM( 12000000, pll8, 4, 1, 8), |
| 2549 | F_CAM( 16000000, pll8, 4, 1, 6), |
| 2550 | F_CAM( 19200000, pll8, 4, 1, 5), |
| 2551 | F_CAM( 24000000, pll8, 4, 1, 4), |
| 2552 | F_CAM( 32000000, pll8, 4, 1, 3), |
| 2553 | F_CAM( 48000000, pll8, 4, 1, 2), |
| 2554 | F_CAM( 64000000, pll8, 3, 1, 2), |
| 2555 | F_CAM( 96000000, pll8, 4, 0, 0), |
| 2556 | F_CAM(128000000, pll8, 3, 0, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2557 | F_END |
| 2558 | }; |
| 2559 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2560 | static CLK_CAM(cam0_clk, 0, 15); |
| 2561 | static CLK_CAM(cam1_clk, 1, 16); |
| 2562 | static CLK_CAM(cam2_clk, 2, 31); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2563 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2564 | #define F_CSI(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2565 | { \ |
| 2566 | .freq_hz = f, \ |
| 2567 | .src_clk = &s##_clk.c, \ |
| 2568 | .md_val = MD8(8, m, 0, n), \ |
| 2569 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 2570 | .ctl_val = CC(6, n), \ |
| 2571 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2572 | } |
| 2573 | static struct clk_freq_tbl clk_tbl_csi[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2574 | F_CSI( 0, gnd, 1, 0, 0), |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2575 | F_CSI( 27000000, pxo, 1, 0, 0), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2576 | F_CSI( 85330000, pll8, 1, 2, 9), |
| 2577 | F_CSI(177780000, pll2, 1, 2, 9), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2578 | F_END |
| 2579 | }; |
| 2580 | |
| 2581 | static struct rcg_clk csi0_src_clk = { |
| 2582 | .ns_reg = CSI0_NS_REG, |
| 2583 | .b = { |
| 2584 | .ctl_reg = CSI0_CC_REG, |
| 2585 | .halt_check = NOCHECK, |
| 2586 | }, |
| 2587 | .md_reg = CSI0_MD_REG, |
| 2588 | .root_en_mask = BIT(2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2589 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2590 | .ctl_mask = BM(7, 6), |
| 2591 | .set_rate = set_rate_mnd, |
| 2592 | .freq_tbl = clk_tbl_csi, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2593 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2594 | .c = { |
| 2595 | .dbg_name = "csi0_src_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2596 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2597 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2598 | CLK_INIT(csi0_src_clk.c), |
| 2599 | }, |
| 2600 | }; |
| 2601 | |
| 2602 | static struct branch_clk csi0_clk = { |
| 2603 | .b = { |
| 2604 | .ctl_reg = CSI0_CC_REG, |
| 2605 | .en_mask = BIT(0), |
| 2606 | .reset_reg = SW_RESET_CORE_REG, |
| 2607 | .reset_mask = BIT(8), |
| 2608 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2609 | .halt_bit = 13, |
| 2610 | }, |
| 2611 | .parent = &csi0_src_clk.c, |
| 2612 | .c = { |
| 2613 | .dbg_name = "csi0_clk", |
| 2614 | .ops = &clk_ops_branch, |
| 2615 | CLK_INIT(csi0_clk.c), |
| 2616 | }, |
| 2617 | }; |
| 2618 | |
| 2619 | static struct branch_clk csi0_phy_clk = { |
| 2620 | .b = { |
| 2621 | .ctl_reg = CSI0_CC_REG, |
| 2622 | .en_mask = BIT(8), |
| 2623 | .reset_reg = SW_RESET_CORE_REG, |
| 2624 | .reset_mask = BIT(29), |
| 2625 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2626 | .halt_bit = 9, |
| 2627 | }, |
| 2628 | .parent = &csi0_src_clk.c, |
| 2629 | .c = { |
| 2630 | .dbg_name = "csi0_phy_clk", |
| 2631 | .ops = &clk_ops_branch, |
| 2632 | CLK_INIT(csi0_phy_clk.c), |
| 2633 | }, |
| 2634 | }; |
| 2635 | |
| 2636 | static struct rcg_clk csi1_src_clk = { |
| 2637 | .ns_reg = CSI1_NS_REG, |
| 2638 | .b = { |
| 2639 | .ctl_reg = CSI1_CC_REG, |
| 2640 | .halt_check = NOCHECK, |
| 2641 | }, |
| 2642 | .md_reg = CSI1_MD_REG, |
| 2643 | .root_en_mask = BIT(2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2644 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2645 | .ctl_mask = BM(7, 6), |
| 2646 | .set_rate = set_rate_mnd, |
| 2647 | .freq_tbl = clk_tbl_csi, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2648 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2649 | .c = { |
| 2650 | .dbg_name = "csi1_src_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 2651 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2652 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2653 | CLK_INIT(csi1_src_clk.c), |
| 2654 | }, |
| 2655 | }; |
| 2656 | |
| 2657 | static struct branch_clk csi1_clk = { |
| 2658 | .b = { |
| 2659 | .ctl_reg = CSI1_CC_REG, |
| 2660 | .en_mask = BIT(0), |
| 2661 | .reset_reg = SW_RESET_CORE_REG, |
| 2662 | .reset_mask = BIT(18), |
| 2663 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2664 | .halt_bit = 14, |
| 2665 | }, |
| 2666 | .parent = &csi1_src_clk.c, |
| 2667 | .c = { |
| 2668 | .dbg_name = "csi1_clk", |
| 2669 | .ops = &clk_ops_branch, |
| 2670 | CLK_INIT(csi1_clk.c), |
| 2671 | }, |
| 2672 | }; |
| 2673 | |
| 2674 | static struct branch_clk csi1_phy_clk = { |
| 2675 | .b = { |
| 2676 | .ctl_reg = CSI1_CC_REG, |
| 2677 | .en_mask = BIT(8), |
| 2678 | .reset_reg = SW_RESET_CORE_REG, |
| 2679 | .reset_mask = BIT(28), |
| 2680 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2681 | .halt_bit = 10, |
| 2682 | }, |
| 2683 | .parent = &csi1_src_clk.c, |
| 2684 | .c = { |
| 2685 | .dbg_name = "csi1_phy_clk", |
| 2686 | .ops = &clk_ops_branch, |
| 2687 | CLK_INIT(csi1_phy_clk.c), |
| 2688 | }, |
| 2689 | }; |
| 2690 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2691 | static struct rcg_clk csi2_src_clk = { |
| 2692 | .ns_reg = CSI2_NS_REG, |
| 2693 | .b = { |
| 2694 | .ctl_reg = CSI2_CC_REG, |
| 2695 | .halt_check = NOCHECK, |
| 2696 | }, |
| 2697 | .md_reg = CSI2_MD_REG, |
| 2698 | .root_en_mask = BIT(2), |
| 2699 | .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), |
| 2700 | .ctl_mask = BM(7, 6), |
| 2701 | .set_rate = set_rate_mnd, |
| 2702 | .freq_tbl = clk_tbl_csi, |
| 2703 | .current_freq = &rcg_dummy_freq, |
| 2704 | .c = { |
| 2705 | .dbg_name = "csi2_src_clk", |
| 2706 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 2707 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2708 | CLK_INIT(csi2_src_clk.c), |
| 2709 | }, |
| 2710 | }; |
| 2711 | |
| 2712 | static struct branch_clk csi2_clk = { |
| 2713 | .b = { |
| 2714 | .ctl_reg = CSI2_CC_REG, |
| 2715 | .en_mask = BIT(0), |
| 2716 | .reset_reg = SW_RESET_CORE2_REG, |
| 2717 | .reset_mask = BIT(2), |
| 2718 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 2719 | .halt_bit = 29, |
| 2720 | }, |
| 2721 | .parent = &csi2_src_clk.c, |
| 2722 | .c = { |
| 2723 | .dbg_name = "csi2_clk", |
| 2724 | .ops = &clk_ops_branch, |
| 2725 | CLK_INIT(csi2_clk.c), |
| 2726 | }, |
| 2727 | }; |
| 2728 | |
| 2729 | static struct branch_clk csi2_phy_clk = { |
| 2730 | .b = { |
| 2731 | .ctl_reg = CSI2_CC_REG, |
| 2732 | .en_mask = BIT(8), |
| 2733 | .reset_reg = SW_RESET_CORE_REG, |
| 2734 | .reset_mask = BIT(31), |
| 2735 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 2736 | .halt_bit = 29, |
| 2737 | }, |
| 2738 | .parent = &csi2_src_clk.c, |
| 2739 | .c = { |
| 2740 | .dbg_name = "csi2_phy_clk", |
| 2741 | .ops = &clk_ops_branch, |
| 2742 | CLK_INIT(csi2_phy_clk.c), |
| 2743 | }, |
| 2744 | }; |
| 2745 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2746 | static struct clk *pix_rdi_mux_map[] = { |
| 2747 | [0] = &csi0_clk.c, |
| 2748 | [1] = &csi1_clk.c, |
| 2749 | [2] = &csi2_clk.c, |
| 2750 | NULL, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2751 | }; |
| 2752 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2753 | struct pix_rdi_clk { |
| 2754 | bool enabled; |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2755 | unsigned long cur_rate; |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2756 | |
| 2757 | void __iomem *const s_reg; |
| 2758 | u32 s_mask; |
| 2759 | |
| 2760 | void __iomem *const s2_reg; |
| 2761 | u32 s2_mask; |
| 2762 | |
| 2763 | struct branch b; |
| 2764 | struct clk c; |
| 2765 | }; |
| 2766 | |
| 2767 | static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk) |
| 2768 | { |
| 2769 | return container_of(clk, struct pix_rdi_clk, c); |
| 2770 | } |
| 2771 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2772 | static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2773 | { |
| 2774 | int ret, i; |
| 2775 | u32 reg; |
| 2776 | unsigned long flags; |
| 2777 | struct pix_rdi_clk *clk = to_pix_rdi_clk(c); |
| 2778 | struct clk **mux_map = pix_rdi_mux_map; |
| 2779 | |
| 2780 | /* |
| 2781 | * These clocks select three inputs via two muxes. One mux selects |
| 2782 | * between csi0 and csi1 and the second mux selects between that mux's |
| 2783 | * output and csi2. The source and destination selections for each |
| 2784 | * mux must be clocking for the switch to succeed so just turn on |
| 2785 | * all three sources because it's easier than figuring out what source |
| 2786 | * needs to be on at what time. |
| 2787 | */ |
| 2788 | for (i = 0; mux_map[i]; i++) { |
| 2789 | ret = clk_enable(mux_map[i]); |
| 2790 | if (ret) |
| 2791 | goto err; |
| 2792 | } |
| 2793 | if (rate >= i) { |
| 2794 | ret = -EINVAL; |
| 2795 | goto err; |
| 2796 | } |
| 2797 | /* Keep the new source on when switching inputs of an enabled clock */ |
| 2798 | if (clk->enabled) { |
| 2799 | clk_disable(mux_map[clk->cur_rate]); |
| 2800 | clk_enable(mux_map[rate]); |
| 2801 | } |
| 2802 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 2803 | reg = readl_relaxed(clk->s2_reg); |
| 2804 | reg &= ~clk->s2_mask; |
| 2805 | reg |= rate == 2 ? clk->s2_mask : 0; |
| 2806 | writel_relaxed(reg, clk->s2_reg); |
| 2807 | /* |
| 2808 | * Wait at least 6 cycles of slowest clock |
| 2809 | * for the glitch-free MUX to fully switch sources. |
| 2810 | */ |
| 2811 | mb(); |
| 2812 | udelay(1); |
| 2813 | reg = readl_relaxed(clk->s_reg); |
| 2814 | reg &= ~clk->s_mask; |
| 2815 | reg |= rate == 1 ? clk->s_mask : 0; |
| 2816 | writel_relaxed(reg, clk->s_reg); |
| 2817 | /* |
| 2818 | * Wait at least 6 cycles of slowest clock |
| 2819 | * for the glitch-free MUX to fully switch sources. |
| 2820 | */ |
| 2821 | mb(); |
| 2822 | udelay(1); |
| 2823 | clk->cur_rate = rate; |
| 2824 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2825 | err: |
| 2826 | for (i--; i >= 0; i--) |
| 2827 | clk_disable(mux_map[i]); |
| 2828 | |
| 2829 | return 0; |
| 2830 | } |
| 2831 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 2832 | static unsigned long pix_rdi_clk_get_rate(struct clk *c) |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2833 | { |
| 2834 | return to_pix_rdi_clk(c)->cur_rate; |
| 2835 | } |
| 2836 | |
| 2837 | static int pix_rdi_clk_enable(struct clk *c) |
| 2838 | { |
| 2839 | unsigned long flags; |
| 2840 | struct pix_rdi_clk *clk = to_pix_rdi_clk(c); |
| 2841 | |
| 2842 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 2843 | __branch_clk_enable_reg(&clk->b, clk->c.dbg_name); |
| 2844 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2845 | clk->enabled = true; |
| 2846 | |
| 2847 | return 0; |
| 2848 | } |
| 2849 | |
| 2850 | static void pix_rdi_clk_disable(struct clk *c) |
| 2851 | { |
| 2852 | unsigned long flags; |
| 2853 | struct pix_rdi_clk *clk = to_pix_rdi_clk(c); |
| 2854 | |
| 2855 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 2856 | __branch_clk_disable_reg(&clk->b, clk->c.dbg_name); |
| 2857 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2858 | clk->enabled = false; |
| 2859 | } |
| 2860 | |
| 2861 | static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action) |
| 2862 | { |
| 2863 | return branch_reset(&to_pix_rdi_clk(clk)->b, action); |
| 2864 | } |
| 2865 | |
| 2866 | static struct clk *pix_rdi_clk_get_parent(struct clk *c) |
| 2867 | { |
| 2868 | struct pix_rdi_clk *clk = to_pix_rdi_clk(c); |
| 2869 | |
| 2870 | return pix_rdi_mux_map[clk->cur_rate]; |
| 2871 | } |
| 2872 | |
| 2873 | static int pix_rdi_clk_list_rate(struct clk *c, unsigned n) |
| 2874 | { |
| 2875 | if (pix_rdi_mux_map[n]) |
| 2876 | return n; |
| 2877 | return -ENXIO; |
| 2878 | } |
| 2879 | |
| 2880 | static int pix_rdi_clk_handoff(struct clk *c) |
| 2881 | { |
| 2882 | u32 reg; |
| 2883 | struct pix_rdi_clk *clk = to_pix_rdi_clk(c); |
| 2884 | |
| 2885 | reg = readl_relaxed(clk->s_reg); |
| 2886 | clk->cur_rate = reg & clk->s_mask ? 1 : 0; |
| 2887 | reg = readl_relaxed(clk->s2_reg); |
| 2888 | clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate; |
| 2889 | return 0; |
| 2890 | } |
| 2891 | |
| 2892 | static struct clk_ops clk_ops_pix_rdi_8960 = { |
| 2893 | .enable = pix_rdi_clk_enable, |
| 2894 | .disable = pix_rdi_clk_disable, |
| 2895 | .auto_off = pix_rdi_clk_disable, |
| 2896 | .handoff = pix_rdi_clk_handoff, |
| 2897 | .set_rate = pix_rdi_clk_set_rate, |
| 2898 | .get_rate = pix_rdi_clk_get_rate, |
| 2899 | .list_rate = pix_rdi_clk_list_rate, |
| 2900 | .reset = pix_rdi_clk_reset, |
| 2901 | .is_local = local_clk_is_local, |
| 2902 | .get_parent = pix_rdi_clk_get_parent, |
| 2903 | }; |
| 2904 | |
| 2905 | static struct pix_rdi_clk csi_pix_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2906 | .b = { |
| 2907 | .ctl_reg = MISC_CC_REG, |
| 2908 | .en_mask = BIT(26), |
| 2909 | .halt_check = DELAY, |
| 2910 | .reset_reg = SW_RESET_CORE_REG, |
| 2911 | .reset_mask = BIT(26), |
| 2912 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2913 | .s_reg = MISC_CC_REG, |
| 2914 | .s_mask = BIT(25), |
| 2915 | .s2_reg = MISC_CC3_REG, |
| 2916 | .s2_mask = BIT(13), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2917 | .c = { |
| 2918 | .dbg_name = "csi_pix_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2919 | .ops = &clk_ops_pix_rdi_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2920 | CLK_INIT(csi_pix_clk.c), |
| 2921 | }, |
| 2922 | }; |
| 2923 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2924 | static struct pix_rdi_clk csi_pix1_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2925 | .b = { |
| 2926 | .ctl_reg = MISC_CC3_REG, |
| 2927 | .en_mask = BIT(10), |
| 2928 | .halt_check = DELAY, |
| 2929 | .reset_reg = SW_RESET_CORE_REG, |
| 2930 | .reset_mask = BIT(30), |
| 2931 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2932 | .s_reg = MISC_CC3_REG, |
| 2933 | .s_mask = BIT(8), |
| 2934 | .s2_reg = MISC_CC3_REG, |
| 2935 | .s2_mask = BIT(9), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2936 | .c = { |
| 2937 | .dbg_name = "csi_pix1_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2938 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2939 | CLK_INIT(csi_pix1_clk.c), |
| 2940 | }, |
| 2941 | }; |
| 2942 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2943 | static struct pix_rdi_clk csi_rdi_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2944 | .b = { |
| 2945 | .ctl_reg = MISC_CC_REG, |
| 2946 | .en_mask = BIT(13), |
| 2947 | .halt_check = DELAY, |
| 2948 | .reset_reg = SW_RESET_CORE_REG, |
| 2949 | .reset_mask = BIT(27), |
| 2950 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2951 | .s_reg = MISC_CC_REG, |
| 2952 | .s_mask = BIT(12), |
| 2953 | .s2_reg = MISC_CC3_REG, |
| 2954 | .s2_mask = BIT(12), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2955 | .c = { |
| 2956 | .dbg_name = "csi_rdi_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2957 | .ops = &clk_ops_pix_rdi_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2958 | CLK_INIT(csi_rdi_clk.c), |
| 2959 | }, |
| 2960 | }; |
| 2961 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2962 | static struct pix_rdi_clk csi_rdi1_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2963 | .b = { |
| 2964 | .ctl_reg = MISC_CC3_REG, |
| 2965 | .en_mask = BIT(2), |
| 2966 | .halt_check = DELAY, |
| 2967 | .reset_reg = SW_RESET_CORE2_REG, |
| 2968 | .reset_mask = BIT(1), |
| 2969 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2970 | .s_reg = MISC_CC3_REG, |
| 2971 | .s_mask = BIT(0), |
| 2972 | .s2_reg = MISC_CC3_REG, |
| 2973 | .s2_mask = BIT(1), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2974 | .c = { |
| 2975 | .dbg_name = "csi_rdi1_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2976 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2977 | CLK_INIT(csi_rdi1_clk.c), |
| 2978 | }, |
| 2979 | }; |
| 2980 | |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2981 | static struct pix_rdi_clk csi_rdi2_clk = { |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2982 | .b = { |
| 2983 | .ctl_reg = MISC_CC3_REG, |
| 2984 | .en_mask = BIT(6), |
| 2985 | .halt_check = DELAY, |
| 2986 | .reset_reg = SW_RESET_CORE2_REG, |
| 2987 | .reset_mask = BIT(0), |
| 2988 | }, |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2989 | .s_reg = MISC_CC3_REG, |
| 2990 | .s_mask = BIT(4), |
| 2991 | .s2_reg = MISC_CC3_REG, |
| 2992 | .s2_mask = BIT(5), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2993 | .c = { |
| 2994 | .dbg_name = "csi_rdi2_clk", |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 2995 | .ops = &clk_ops_pix_rdi_8960, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 2996 | CLK_INIT(csi_rdi2_clk.c), |
| 2997 | }, |
| 2998 | }; |
| 2999 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3000 | #define F_CSI_PHYTIMER(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3001 | { \ |
| 3002 | .freq_hz = f, \ |
| 3003 | .src_clk = &s##_clk.c, \ |
| 3004 | .md_val = MD8(8, m, 0, n), \ |
| 3005 | .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3006 | .ctl_val = CC(6, n), \ |
| 3007 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3008 | } |
| 3009 | static struct clk_freq_tbl clk_tbl_csi_phytimer[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3010 | F_CSI_PHYTIMER( 0, gnd, 1, 0, 0), |
| 3011 | F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9), |
| 3012 | F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3013 | F_END |
| 3014 | }; |
| 3015 | |
| 3016 | static struct rcg_clk csiphy_timer_src_clk = { |
| 3017 | .ns_reg = CSIPHYTIMER_NS_REG, |
| 3018 | .b = { |
| 3019 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3020 | .halt_check = NOCHECK, |
| 3021 | }, |
| 3022 | .md_reg = CSIPHYTIMER_MD_REG, |
| 3023 | .root_en_mask = BIT(2), |
| 3024 | .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)), |
| 3025 | .ctl_mask = BM(7, 6), |
| 3026 | .set_rate = set_rate_mnd_8, |
| 3027 | .freq_tbl = clk_tbl_csi_phytimer, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3028 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3029 | .c = { |
| 3030 | .dbg_name = "csiphy_timer_src_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3031 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3032 | VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3033 | CLK_INIT(csiphy_timer_src_clk.c), |
| 3034 | }, |
| 3035 | }; |
| 3036 | |
| 3037 | static struct branch_clk csi0phy_timer_clk = { |
| 3038 | .b = { |
| 3039 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3040 | .en_mask = BIT(0), |
| 3041 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3042 | .halt_bit = 17, |
| 3043 | }, |
| 3044 | .parent = &csiphy_timer_src_clk.c, |
| 3045 | .c = { |
| 3046 | .dbg_name = "csi0phy_timer_clk", |
| 3047 | .ops = &clk_ops_branch, |
| 3048 | CLK_INIT(csi0phy_timer_clk.c), |
| 3049 | }, |
| 3050 | }; |
| 3051 | |
| 3052 | static struct branch_clk csi1phy_timer_clk = { |
| 3053 | .b = { |
| 3054 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3055 | .en_mask = BIT(9), |
| 3056 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3057 | .halt_bit = 18, |
| 3058 | }, |
| 3059 | .parent = &csiphy_timer_src_clk.c, |
| 3060 | .c = { |
| 3061 | .dbg_name = "csi1phy_timer_clk", |
| 3062 | .ops = &clk_ops_branch, |
| 3063 | CLK_INIT(csi1phy_timer_clk.c), |
| 3064 | }, |
| 3065 | }; |
| 3066 | |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3067 | static struct branch_clk csi2phy_timer_clk = { |
| 3068 | .b = { |
| 3069 | .ctl_reg = CSIPHYTIMER_CC_REG, |
| 3070 | .en_mask = BIT(11), |
| 3071 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3072 | .halt_bit = 30, |
| 3073 | }, |
| 3074 | .parent = &csiphy_timer_src_clk.c, |
| 3075 | .c = { |
| 3076 | .dbg_name = "csi2phy_timer_clk", |
| 3077 | .ops = &clk_ops_branch, |
| 3078 | CLK_INIT(csi2phy_timer_clk.c), |
| 3079 | }, |
| 3080 | }; |
| 3081 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3082 | #define F_DSI(d) \ |
| 3083 | { \ |
| 3084 | .freq_hz = d, \ |
| 3085 | .ns_val = BVAL(15, 12, (d-1)), \ |
| 3086 | } |
| 3087 | /* |
| 3088 | * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate |
| 3089 | * without this clock driver knowing. So, overload the clk_set_rate() to set |
| 3090 | * the divider (1 to 16) of the clock with respect to the PLL rate. |
| 3091 | */ |
| 3092 | static struct clk_freq_tbl clk_tbl_dsi_byte[] = { |
| 3093 | F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4), |
| 3094 | F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8), |
| 3095 | F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12), |
| 3096 | F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16), |
| 3097 | F_END |
| 3098 | }; |
| 3099 | |
| 3100 | static struct rcg_clk dsi1_byte_clk = { |
| 3101 | .b = { |
| 3102 | .ctl_reg = DSI1_BYTE_CC_REG, |
| 3103 | .en_mask = BIT(0), |
| 3104 | .reset_reg = SW_RESET_CORE_REG, |
| 3105 | .reset_mask = BIT(7), |
| 3106 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3107 | .halt_bit = 21, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3108 | .retain_reg = DSI1_BYTE_CC_REG, |
| 3109 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3110 | }, |
| 3111 | .ns_reg = DSI1_BYTE_NS_REG, |
| 3112 | .root_en_mask = BIT(2), |
| 3113 | .ns_mask = BM(15, 12), |
| 3114 | .set_rate = set_rate_nop, |
| 3115 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3116 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3117 | .c = { |
| 3118 | .dbg_name = "dsi1_byte_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3119 | .ops = &clk_ops_rcg_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3120 | CLK_INIT(dsi1_byte_clk.c), |
| 3121 | }, |
| 3122 | }; |
| 3123 | |
| 3124 | static struct rcg_clk dsi2_byte_clk = { |
| 3125 | .b = { |
| 3126 | .ctl_reg = DSI2_BYTE_CC_REG, |
| 3127 | .en_mask = BIT(0), |
| 3128 | .reset_reg = SW_RESET_CORE_REG, |
| 3129 | .reset_mask = BIT(25), |
| 3130 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3131 | .halt_bit = 20, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3132 | .retain_reg = DSI2_BYTE_CC_REG, |
| 3133 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3134 | }, |
| 3135 | .ns_reg = DSI2_BYTE_NS_REG, |
| 3136 | .root_en_mask = BIT(2), |
| 3137 | .ns_mask = BM(15, 12), |
| 3138 | .set_rate = set_rate_nop, |
| 3139 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3140 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3141 | .c = { |
| 3142 | .dbg_name = "dsi2_byte_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3143 | .ops = &clk_ops_rcg_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3144 | CLK_INIT(dsi2_byte_clk.c), |
| 3145 | }, |
| 3146 | }; |
| 3147 | |
| 3148 | static struct rcg_clk dsi1_esc_clk = { |
| 3149 | .b = { |
| 3150 | .ctl_reg = DSI1_ESC_CC_REG, |
| 3151 | .en_mask = BIT(0), |
| 3152 | .reset_reg = SW_RESET_CORE_REG, |
| 3153 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3154 | .halt_bit = 1, |
| 3155 | }, |
| 3156 | .ns_reg = DSI1_ESC_NS_REG, |
| 3157 | .root_en_mask = BIT(2), |
| 3158 | .ns_mask = BM(15, 12), |
| 3159 | .set_rate = set_rate_nop, |
| 3160 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3161 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3162 | .c = { |
| 3163 | .dbg_name = "dsi1_esc_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3164 | .ops = &clk_ops_rcg_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3165 | CLK_INIT(dsi1_esc_clk.c), |
| 3166 | }, |
| 3167 | }; |
| 3168 | |
| 3169 | static struct rcg_clk dsi2_esc_clk = { |
| 3170 | .b = { |
| 3171 | .ctl_reg = DSI2_ESC_CC_REG, |
| 3172 | .en_mask = BIT(0), |
| 3173 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3174 | .halt_bit = 3, |
| 3175 | }, |
| 3176 | .ns_reg = DSI2_ESC_NS_REG, |
| 3177 | .root_en_mask = BIT(2), |
| 3178 | .ns_mask = BM(15, 12), |
| 3179 | .set_rate = set_rate_nop, |
| 3180 | .freq_tbl = clk_tbl_dsi_byte, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3181 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3182 | .c = { |
| 3183 | .dbg_name = "dsi2_esc_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3184 | .ops = &clk_ops_rcg_8960, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3185 | CLK_INIT(dsi2_esc_clk.c), |
| 3186 | }, |
| 3187 | }; |
| 3188 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3189 | #define F_GFX2D(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3190 | { \ |
| 3191 | .freq_hz = f, \ |
| 3192 | .src_clk = &s##_clk.c, \ |
| 3193 | .md_val = MD4(4, m, 0, n), \ |
| 3194 | .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \ |
| 3195 | .ctl_val = CC_BANKED(9, 6, n), \ |
| 3196 | .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3197 | } |
| 3198 | static struct clk_freq_tbl clk_tbl_gfx2d[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3199 | F_GFX2D( 0, gnd, 0, 0), |
| 3200 | F_GFX2D( 27000000, pxo, 0, 0), |
| 3201 | F_GFX2D( 48000000, pll8, 1, 8), |
| 3202 | F_GFX2D( 54857000, pll8, 1, 7), |
| 3203 | F_GFX2D( 64000000, pll8, 1, 6), |
| 3204 | F_GFX2D( 76800000, pll8, 1, 5), |
| 3205 | F_GFX2D( 96000000, pll8, 1, 4), |
| 3206 | F_GFX2D(128000000, pll8, 1, 3), |
| 3207 | F_GFX2D(145455000, pll2, 2, 11), |
| 3208 | F_GFX2D(160000000, pll2, 1, 5), |
| 3209 | F_GFX2D(177778000, pll2, 2, 9), |
| 3210 | F_GFX2D(200000000, pll2, 1, 4), |
| 3211 | F_GFX2D(228571000, pll2, 2, 7), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3212 | F_END |
| 3213 | }; |
| 3214 | |
| 3215 | static struct bank_masks bmnd_info_gfx2d0 = { |
| 3216 | .bank_sel_mask = BIT(11), |
| 3217 | .bank0_mask = { |
| 3218 | .md_reg = GFX2D0_MD0_REG, |
| 3219 | .ns_mask = BM(23, 20) | BM(5, 3), |
| 3220 | .rst_mask = BIT(25), |
| 3221 | .mnd_en_mask = BIT(8), |
| 3222 | .mode_mask = BM(10, 9), |
| 3223 | }, |
| 3224 | .bank1_mask = { |
| 3225 | .md_reg = GFX2D0_MD1_REG, |
| 3226 | .ns_mask = BM(19, 16) | BM(2, 0), |
| 3227 | .rst_mask = BIT(24), |
| 3228 | .mnd_en_mask = BIT(5), |
| 3229 | .mode_mask = BM(7, 6), |
| 3230 | }, |
| 3231 | }; |
| 3232 | |
| 3233 | static struct rcg_clk gfx2d0_clk = { |
| 3234 | .b = { |
| 3235 | .ctl_reg = GFX2D0_CC_REG, |
| 3236 | .en_mask = BIT(0), |
| 3237 | .reset_reg = SW_RESET_CORE_REG, |
| 3238 | .reset_mask = BIT(14), |
| 3239 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3240 | .halt_bit = 9, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3241 | .retain_reg = GFX2D0_CC_REG, |
| 3242 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3243 | }, |
| 3244 | .ns_reg = GFX2D0_NS_REG, |
| 3245 | .root_en_mask = BIT(2), |
| 3246 | .set_rate = set_rate_mnd_banked, |
| 3247 | .freq_tbl = clk_tbl_gfx2d, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3248 | .bank_info = &bmnd_info_gfx2d0, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3249 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3250 | .c = { |
| 3251 | .dbg_name = "gfx2d0_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3252 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3253 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 3254 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3255 | CLK_INIT(gfx2d0_clk.c), |
| 3256 | }, |
| 3257 | }; |
| 3258 | |
| 3259 | static struct bank_masks bmnd_info_gfx2d1 = { |
| 3260 | .bank_sel_mask = BIT(11), |
| 3261 | .bank0_mask = { |
| 3262 | .md_reg = GFX2D1_MD0_REG, |
| 3263 | .ns_mask = BM(23, 20) | BM(5, 3), |
| 3264 | .rst_mask = BIT(25), |
| 3265 | .mnd_en_mask = BIT(8), |
| 3266 | .mode_mask = BM(10, 9), |
| 3267 | }, |
| 3268 | .bank1_mask = { |
| 3269 | .md_reg = GFX2D1_MD1_REG, |
| 3270 | .ns_mask = BM(19, 16) | BM(2, 0), |
| 3271 | .rst_mask = BIT(24), |
| 3272 | .mnd_en_mask = BIT(5), |
| 3273 | .mode_mask = BM(7, 6), |
| 3274 | }, |
| 3275 | }; |
| 3276 | |
| 3277 | static struct rcg_clk gfx2d1_clk = { |
| 3278 | .b = { |
| 3279 | .ctl_reg = GFX2D1_CC_REG, |
| 3280 | .en_mask = BIT(0), |
| 3281 | .reset_reg = SW_RESET_CORE_REG, |
| 3282 | .reset_mask = BIT(13), |
| 3283 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3284 | .halt_bit = 14, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3285 | .retain_reg = GFX2D1_CC_REG, |
| 3286 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3287 | }, |
| 3288 | .ns_reg = GFX2D1_NS_REG, |
| 3289 | .root_en_mask = BIT(2), |
| 3290 | .set_rate = set_rate_mnd_banked, |
| 3291 | .freq_tbl = clk_tbl_gfx2d, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3292 | .bank_info = &bmnd_info_gfx2d1, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3293 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3294 | .c = { |
| 3295 | .dbg_name = "gfx2d1_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3296 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3297 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 3298 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3299 | CLK_INIT(gfx2d1_clk.c), |
| 3300 | }, |
| 3301 | }; |
| 3302 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3303 | #define F_GFX3D(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3304 | { \ |
| 3305 | .freq_hz = f, \ |
| 3306 | .src_clk = &s##_clk.c, \ |
| 3307 | .md_val = MD4(4, m, 0, n), \ |
| 3308 | .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3309 | .ctl_val = CC_BANKED(9, 6, n), \ |
| 3310 | .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3311 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3312 | |
| 3313 | static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3314 | F_GFX3D( 0, gnd, 0, 0), |
| 3315 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3316 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3317 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3318 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3319 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3320 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3321 | F_GFX3D(128000000, pll8, 1, 3), |
| 3322 | F_GFX3D(145455000, pll2, 2, 11), |
| 3323 | F_GFX3D(160000000, pll2, 1, 5), |
| 3324 | F_GFX3D(177778000, pll2, 2, 9), |
| 3325 | F_GFX3D(200000000, pll2, 1, 4), |
| 3326 | F_GFX3D(228571000, pll2, 2, 7), |
| 3327 | F_GFX3D(266667000, pll2, 1, 3), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3328 | F_GFX3D(300000000, pll3, 1, 4), |
| 3329 | F_GFX3D(320000000, pll2, 2, 5), |
| 3330 | F_GFX3D(400000000, pll2, 1, 2), |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 3331 | F_END |
| 3332 | }; |
| 3333 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3334 | static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3335 | F_GFX3D( 0, gnd, 0, 0), |
| 3336 | F_GFX3D( 27000000, pxo, 0, 0), |
| 3337 | F_GFX3D( 48000000, pll8, 1, 8), |
| 3338 | F_GFX3D( 54857000, pll8, 1, 7), |
| 3339 | F_GFX3D( 64000000, pll8, 1, 6), |
| 3340 | F_GFX3D( 76800000, pll8, 1, 5), |
| 3341 | F_GFX3D( 96000000, pll8, 1, 4), |
| 3342 | F_GFX3D(128000000, pll8, 1, 3), |
| 3343 | F_GFX3D(145455000, pll2, 2, 11), |
| 3344 | F_GFX3D(160000000, pll2, 1, 5), |
| 3345 | F_GFX3D(177778000, pll2, 2, 9), |
| 3346 | F_GFX3D(200000000, pll2, 1, 4), |
| 3347 | F_GFX3D(228571000, pll2, 2, 7), |
| 3348 | F_GFX3D(266667000, pll2, 1, 3), |
Tianyi Gou | 0c50fe3 | 2011-10-19 15:50:35 -0700 | [diff] [blame] | 3349 | F_GFX3D(325000000, pll15, 1, 3), |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3350 | F_GFX3D(400000000, pll2, 1, 2), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3351 | F_END |
| 3352 | }; |
| 3353 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3354 | static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = { |
| 3355 | [VDD_DIG_LOW] = 128000000, |
| 3356 | [VDD_DIG_NOMINAL] = 325000000, |
| 3357 | [VDD_DIG_HIGH] = 400000000 |
| 3358 | }; |
| 3359 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3360 | static struct bank_masks bmnd_info_gfx3d = { |
| 3361 | .bank_sel_mask = BIT(11), |
| 3362 | .bank0_mask = { |
| 3363 | .md_reg = GFX3D_MD0_REG, |
| 3364 | .ns_mask = BM(21, 18) | BM(5, 3), |
| 3365 | .rst_mask = BIT(23), |
| 3366 | .mnd_en_mask = BIT(8), |
| 3367 | .mode_mask = BM(10, 9), |
| 3368 | }, |
| 3369 | .bank1_mask = { |
| 3370 | .md_reg = GFX3D_MD1_REG, |
| 3371 | .ns_mask = BM(17, 14) | BM(2, 0), |
| 3372 | .rst_mask = BIT(22), |
| 3373 | .mnd_en_mask = BIT(5), |
| 3374 | .mode_mask = BM(7, 6), |
| 3375 | }, |
| 3376 | }; |
| 3377 | |
| 3378 | static struct rcg_clk gfx3d_clk = { |
| 3379 | .b = { |
| 3380 | .ctl_reg = GFX3D_CC_REG, |
| 3381 | .en_mask = BIT(0), |
| 3382 | .reset_reg = SW_RESET_CORE_REG, |
| 3383 | .reset_mask = BIT(12), |
| 3384 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3385 | .halt_bit = 4, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3386 | .retain_reg = GFX3D_CC_REG, |
| 3387 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3388 | }, |
| 3389 | .ns_reg = GFX3D_NS_REG, |
| 3390 | .root_en_mask = BIT(2), |
| 3391 | .set_rate = set_rate_mnd_banked, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3392 | .freq_tbl = clk_tbl_gfx3d_8960, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3393 | .bank_info = &bmnd_info_gfx3d, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3394 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3395 | .c = { |
| 3396 | .dbg_name = "gfx3d_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3397 | .ops = &clk_ops_rcg_8960, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 3398 | VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000, |
| 3399 | HIGH, 400000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3400 | CLK_INIT(gfx3d_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3401 | .depends = &gmem_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3402 | }, |
| 3403 | }; |
| 3404 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3405 | #define F_VCAP(f, s, m, n) \ |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3406 | { \ |
| 3407 | .freq_hz = f, \ |
| 3408 | .src_clk = &s##_clk.c, \ |
| 3409 | .md_val = MD4(4, m, 0, n), \ |
| 3410 | .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3411 | .ctl_val = CC_BANKED(9, 6, n), \ |
| 3412 | .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \ |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3413 | } |
| 3414 | |
| 3415 | static struct clk_freq_tbl clk_tbl_vcap[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3416 | F_VCAP( 0, gnd, 0, 0), |
| 3417 | F_VCAP( 27000000, pxo, 0, 0), |
| 3418 | F_VCAP( 54860000, pll8, 1, 7), |
| 3419 | F_VCAP( 64000000, pll8, 1, 6), |
| 3420 | F_VCAP( 76800000, pll8, 1, 5), |
| 3421 | F_VCAP(128000000, pll8, 1, 3), |
| 3422 | F_VCAP(160000000, pll2, 1, 5), |
| 3423 | F_VCAP(200000000, pll2, 1, 4), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3424 | F_END |
| 3425 | }; |
| 3426 | |
| 3427 | static struct bank_masks bmnd_info_vcap = { |
| 3428 | .bank_sel_mask = BIT(11), |
| 3429 | .bank0_mask = { |
| 3430 | .md_reg = VCAP_MD0_REG, |
| 3431 | .ns_mask = BM(21, 18) | BM(5, 3), |
| 3432 | .rst_mask = BIT(23), |
| 3433 | .mnd_en_mask = BIT(8), |
| 3434 | .mode_mask = BM(10, 9), |
| 3435 | }, |
| 3436 | .bank1_mask = { |
| 3437 | .md_reg = VCAP_MD1_REG, |
| 3438 | .ns_mask = BM(17, 14) | BM(2, 0), |
| 3439 | .rst_mask = BIT(22), |
| 3440 | .mnd_en_mask = BIT(5), |
| 3441 | .mode_mask = BM(7, 6), |
| 3442 | }, |
| 3443 | }; |
| 3444 | |
| 3445 | static struct rcg_clk vcap_clk = { |
| 3446 | .b = { |
| 3447 | .ctl_reg = VCAP_CC_REG, |
| 3448 | .en_mask = BIT(0), |
| 3449 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 3450 | .halt_bit = 15, |
| 3451 | }, |
| 3452 | .ns_reg = VCAP_NS_REG, |
| 3453 | .root_en_mask = BIT(2), |
| 3454 | .set_rate = set_rate_mnd_banked, |
| 3455 | .freq_tbl = clk_tbl_vcap, |
| 3456 | .bank_info = &bmnd_info_vcap, |
| 3457 | .current_freq = &rcg_dummy_freq, |
| 3458 | .c = { |
| 3459 | .dbg_name = "vcap_clk", |
| 3460 | .ops = &clk_ops_rcg_8960, |
| 3461 | .depends = &vcap_axi_clk.c, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3462 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3463 | CLK_INIT(vcap_clk.c), |
| 3464 | }, |
| 3465 | }; |
| 3466 | |
| 3467 | static struct branch_clk vcap_npl_clk = { |
| 3468 | .b = { |
| 3469 | .ctl_reg = VCAP_CC_REG, |
| 3470 | .en_mask = BIT(13), |
| 3471 | .halt_reg = DBG_BUS_VEC_J_REG, |
| 3472 | .halt_bit = 25, |
| 3473 | }, |
| 3474 | .parent = &vcap_clk.c, |
| 3475 | .c = { |
| 3476 | .dbg_name = "vcap_npl_clk", |
| 3477 | .ops = &clk_ops_branch, |
| 3478 | CLK_INIT(vcap_npl_clk.c), |
| 3479 | }, |
| 3480 | }; |
| 3481 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3482 | #define F_IJPEG(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3483 | { \ |
| 3484 | .freq_hz = f, \ |
| 3485 | .src_clk = &s##_clk.c, \ |
| 3486 | .md_val = MD8(8, m, 0, n), \ |
| 3487 | .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \ |
| 3488 | .ctl_val = CC(6, n), \ |
| 3489 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3490 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3491 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3492 | static struct clk_freq_tbl clk_tbl_ijpeg[] = { |
| 3493 | F_IJPEG( 0, gnd, 1, 0, 0), |
| 3494 | F_IJPEG( 27000000, pxo, 1, 0, 0), |
| 3495 | F_IJPEG( 36570000, pll8, 1, 2, 21), |
| 3496 | F_IJPEG( 54860000, pll8, 7, 0, 0), |
| 3497 | F_IJPEG( 96000000, pll8, 4, 0, 0), |
| 3498 | F_IJPEG(109710000, pll8, 1, 2, 7), |
| 3499 | F_IJPEG(128000000, pll8, 3, 0, 0), |
| 3500 | F_IJPEG(153600000, pll8, 1, 2, 5), |
| 3501 | F_IJPEG(200000000, pll2, 4, 0, 0), |
| 3502 | F_IJPEG(228571000, pll2, 1, 2, 7), |
| 3503 | F_IJPEG(266667000, pll2, 1, 1, 3), |
| 3504 | F_IJPEG(320000000, pll2, 1, 2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3505 | F_END |
| 3506 | }; |
| 3507 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3508 | static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = { |
| 3509 | [VDD_DIG_LOW] = 128000000, |
| 3510 | [VDD_DIG_NOMINAL] = 266667000, |
| 3511 | [VDD_DIG_HIGH] = 320000000 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 3512 | }; |
| 3513 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3514 | static struct rcg_clk ijpeg_clk = { |
| 3515 | .b = { |
| 3516 | .ctl_reg = IJPEG_CC_REG, |
| 3517 | .en_mask = BIT(0), |
| 3518 | .reset_reg = SW_RESET_CORE_REG, |
| 3519 | .reset_mask = BIT(9), |
| 3520 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3521 | .halt_bit = 24, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3522 | .retain_reg = IJPEG_CC_REG, |
| 3523 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3524 | }, |
| 3525 | .ns_reg = IJPEG_NS_REG, |
| 3526 | .md_reg = IJPEG_MD_REG, |
| 3527 | .root_en_mask = BIT(2), |
| 3528 | .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)), |
| 3529 | .ctl_mask = BM(7, 6), |
| 3530 | .set_rate = set_rate_mnd, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3531 | .freq_tbl = clk_tbl_ijpeg, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3532 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3533 | .c = { |
| 3534 | .dbg_name = "ijpeg_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3535 | .ops = &clk_ops_rcg_8960, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 3536 | VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000, |
| 3537 | HIGH, 320000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3538 | CLK_INIT(ijpeg_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3539 | .depends = &ijpeg_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3540 | }, |
| 3541 | }; |
| 3542 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3543 | #define F_JPEGD(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3544 | { \ |
| 3545 | .freq_hz = f, \ |
| 3546 | .src_clk = &s##_clk.c, \ |
| 3547 | .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3548 | } |
| 3549 | static struct clk_freq_tbl clk_tbl_jpegd[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3550 | F_JPEGD( 0, gnd, 1), |
| 3551 | F_JPEGD( 64000000, pll8, 6), |
| 3552 | F_JPEGD( 76800000, pll8, 5), |
| 3553 | F_JPEGD( 96000000, pll8, 4), |
| 3554 | F_JPEGD(160000000, pll2, 5), |
| 3555 | F_JPEGD(200000000, pll2, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3556 | F_END |
| 3557 | }; |
| 3558 | |
| 3559 | static struct rcg_clk jpegd_clk = { |
| 3560 | .b = { |
| 3561 | .ctl_reg = JPEGD_CC_REG, |
| 3562 | .en_mask = BIT(0), |
| 3563 | .reset_reg = SW_RESET_CORE_REG, |
| 3564 | .reset_mask = BIT(19), |
| 3565 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 3566 | .halt_bit = 19, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3567 | .retain_reg = JPEGD_CC_REG, |
| 3568 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3569 | }, |
| 3570 | .ns_reg = JPEGD_NS_REG, |
| 3571 | .root_en_mask = BIT(2), |
| 3572 | .ns_mask = (BM(15, 12) | BM(2, 0)), |
| 3573 | .set_rate = set_rate_nop, |
| 3574 | .freq_tbl = clk_tbl_jpegd, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3575 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3576 | .c = { |
| 3577 | .dbg_name = "jpegd_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3578 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3579 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3580 | CLK_INIT(jpegd_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3581 | .depends = &jpegd_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3582 | }, |
| 3583 | }; |
| 3584 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3585 | #define F_MDP(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3586 | { \ |
| 3587 | .freq_hz = f, \ |
| 3588 | .src_clk = &s##_clk.c, \ |
| 3589 | .md_val = MD8(8, m, 0, n), \ |
| 3590 | .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \ |
| 3591 | .ctl_val = CC_BANKED(9, 6, n), \ |
| 3592 | .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3593 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3594 | static struct clk_freq_tbl clk_tbl_mdp[] = { |
| 3595 | F_MDP( 0, gnd, 0, 0), |
| 3596 | F_MDP( 9600000, pll8, 1, 40), |
| 3597 | F_MDP( 13710000, pll8, 1, 28), |
| 3598 | F_MDP( 27000000, pxo, 0, 0), |
| 3599 | F_MDP( 29540000, pll8, 1, 13), |
| 3600 | F_MDP( 34910000, pll8, 1, 11), |
| 3601 | F_MDP( 38400000, pll8, 1, 10), |
| 3602 | F_MDP( 59080000, pll8, 2, 13), |
| 3603 | F_MDP( 76800000, pll8, 1, 5), |
| 3604 | F_MDP( 85330000, pll8, 2, 9), |
| 3605 | F_MDP( 96000000, pll8, 1, 4), |
| 3606 | F_MDP(128000000, pll8, 1, 3), |
| 3607 | F_MDP(160000000, pll2, 1, 5), |
| 3608 | F_MDP(177780000, pll2, 2, 9), |
| 3609 | F_MDP(200000000, pll2, 1, 4), |
| 3610 | F_MDP(266667000, pll2, 1, 3), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3611 | F_END |
| 3612 | }; |
| 3613 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3614 | static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = { |
| 3615 | [VDD_DIG_LOW] = 128000000, |
| 3616 | [VDD_DIG_NOMINAL] = 266667000 |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 3617 | }; |
| 3618 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3619 | static struct bank_masks bmnd_info_mdp = { |
| 3620 | .bank_sel_mask = BIT(11), |
| 3621 | .bank0_mask = { |
| 3622 | .md_reg = MDP_MD0_REG, |
| 3623 | .ns_mask = BM(29, 22) | BM(5, 3), |
| 3624 | .rst_mask = BIT(31), |
| 3625 | .mnd_en_mask = BIT(8), |
| 3626 | .mode_mask = BM(10, 9), |
| 3627 | }, |
| 3628 | .bank1_mask = { |
| 3629 | .md_reg = MDP_MD1_REG, |
| 3630 | .ns_mask = BM(21, 14) | BM(2, 0), |
| 3631 | .rst_mask = BIT(30), |
| 3632 | .mnd_en_mask = BIT(5), |
| 3633 | .mode_mask = BM(7, 6), |
| 3634 | }, |
| 3635 | }; |
| 3636 | |
| 3637 | static struct rcg_clk mdp_clk = { |
| 3638 | .b = { |
| 3639 | .ctl_reg = MDP_CC_REG, |
| 3640 | .en_mask = BIT(0), |
| 3641 | .reset_reg = SW_RESET_CORE_REG, |
| 3642 | .reset_mask = BIT(21), |
| 3643 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 3644 | .halt_bit = 10, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3645 | .retain_reg = MDP_CC_REG, |
| 3646 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3647 | }, |
| 3648 | .ns_reg = MDP_NS_REG, |
| 3649 | .root_en_mask = BIT(2), |
| 3650 | .set_rate = set_rate_mnd_banked, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3651 | .freq_tbl = clk_tbl_mdp, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3652 | .bank_info = &bmnd_info_mdp, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3653 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3654 | .c = { |
| 3655 | .dbg_name = "mdp_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3656 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3657 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3658 | CLK_INIT(mdp_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3659 | .depends = &mdp_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3660 | }, |
| 3661 | }; |
| 3662 | |
| 3663 | static struct branch_clk lut_mdp_clk = { |
| 3664 | .b = { |
| 3665 | .ctl_reg = MDP_LUT_CC_REG, |
| 3666 | .en_mask = BIT(0), |
| 3667 | .halt_reg = DBG_BUS_VEC_I_REG, |
| 3668 | .halt_bit = 13, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3669 | .retain_reg = MDP_LUT_CC_REG, |
| 3670 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3671 | }, |
| 3672 | .parent = &mdp_clk.c, |
| 3673 | .c = { |
| 3674 | .dbg_name = "lut_mdp_clk", |
| 3675 | .ops = &clk_ops_branch, |
| 3676 | CLK_INIT(lut_mdp_clk.c), |
| 3677 | }, |
| 3678 | }; |
| 3679 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3680 | #define F_MDP_VSYNC(f, s) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3681 | { \ |
| 3682 | .freq_hz = f, \ |
| 3683 | .src_clk = &s##_clk.c, \ |
| 3684 | .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3685 | } |
| 3686 | static struct clk_freq_tbl clk_tbl_mdp_vsync[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3687 | F_MDP_VSYNC(27000000, pxo), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3688 | F_END |
| 3689 | }; |
| 3690 | |
| 3691 | static struct rcg_clk mdp_vsync_clk = { |
| 3692 | .b = { |
| 3693 | .ctl_reg = MISC_CC_REG, |
| 3694 | .en_mask = BIT(6), |
| 3695 | .reset_reg = SW_RESET_CORE_REG, |
| 3696 | .reset_mask = BIT(3), |
| 3697 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3698 | .halt_bit = 22, |
| 3699 | }, |
| 3700 | .ns_reg = MISC_CC2_REG, |
| 3701 | .ns_mask = BIT(13), |
| 3702 | .set_rate = set_rate_nop, |
| 3703 | .freq_tbl = clk_tbl_mdp_vsync, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3704 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3705 | .c = { |
| 3706 | .dbg_name = "mdp_vsync_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3707 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3708 | VDD_DIG_FMAX_MAP1(LOW, 27000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3709 | CLK_INIT(mdp_vsync_clk.c), |
| 3710 | }, |
| 3711 | }; |
| 3712 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3713 | #define F_ROT(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3714 | { \ |
| 3715 | .freq_hz = f, \ |
| 3716 | .src_clk = &s##_clk.c, \ |
| 3717 | .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \ |
| 3718 | 21, 19, 18, 16, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3719 | } |
| 3720 | static struct clk_freq_tbl clk_tbl_rot[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3721 | F_ROT( 0, gnd, 1), |
| 3722 | F_ROT( 27000000, pxo, 1), |
| 3723 | F_ROT( 29540000, pll8, 13), |
| 3724 | F_ROT( 32000000, pll8, 12), |
| 3725 | F_ROT( 38400000, pll8, 10), |
| 3726 | F_ROT( 48000000, pll8, 8), |
| 3727 | F_ROT( 54860000, pll8, 7), |
| 3728 | F_ROT( 64000000, pll8, 6), |
| 3729 | F_ROT( 76800000, pll8, 5), |
| 3730 | F_ROT( 96000000, pll8, 4), |
| 3731 | F_ROT(100000000, pll2, 8), |
| 3732 | F_ROT(114290000, pll2, 7), |
| 3733 | F_ROT(133330000, pll2, 6), |
| 3734 | F_ROT(160000000, pll2, 5), |
| 3735 | F_ROT(200000000, pll2, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3736 | F_END |
| 3737 | }; |
| 3738 | |
| 3739 | static struct bank_masks bdiv_info_rot = { |
| 3740 | .bank_sel_mask = BIT(30), |
| 3741 | .bank0_mask = { |
| 3742 | .ns_mask = BM(25, 22) | BM(18, 16), |
| 3743 | }, |
| 3744 | .bank1_mask = { |
| 3745 | .ns_mask = BM(29, 26) | BM(21, 19), |
| 3746 | }, |
| 3747 | }; |
| 3748 | |
| 3749 | static struct rcg_clk rot_clk = { |
| 3750 | .b = { |
| 3751 | .ctl_reg = ROT_CC_REG, |
| 3752 | .en_mask = BIT(0), |
| 3753 | .reset_reg = SW_RESET_CORE_REG, |
| 3754 | .reset_mask = BIT(2), |
| 3755 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 3756 | .halt_bit = 15, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3757 | .retain_reg = ROT_CC_REG, |
| 3758 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3759 | }, |
| 3760 | .ns_reg = ROT_NS_REG, |
| 3761 | .root_en_mask = BIT(2), |
| 3762 | .set_rate = set_rate_div_banked, |
| 3763 | .freq_tbl = clk_tbl_rot, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 3764 | .bank_info = &bdiv_info_rot, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3765 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3766 | .c = { |
| 3767 | .dbg_name = "rot_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3768 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3769 | VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3770 | CLK_INIT(rot_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 3771 | .depends = &rot_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3772 | }, |
| 3773 | }; |
| 3774 | |
| 3775 | static int hdmi_pll_clk_enable(struct clk *clk) |
| 3776 | { |
| 3777 | int ret; |
| 3778 | unsigned long flags; |
| 3779 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3780 | ret = hdmi_pll_enable(); |
| 3781 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3782 | return ret; |
| 3783 | } |
| 3784 | |
| 3785 | static void hdmi_pll_clk_disable(struct clk *clk) |
| 3786 | { |
| 3787 | unsigned long flags; |
| 3788 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3789 | hdmi_pll_disable(); |
| 3790 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3791 | } |
| 3792 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 3793 | static unsigned long hdmi_pll_clk_get_rate(struct clk *clk) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3794 | { |
| 3795 | return hdmi_pll_get_rate(); |
| 3796 | } |
| 3797 | |
Stephen Boyd | 5b35dee | 2011-09-21 12:17:38 -0700 | [diff] [blame] | 3798 | static struct clk *hdmi_pll_clk_get_parent(struct clk *clk) |
| 3799 | { |
| 3800 | return &pxo_clk.c; |
| 3801 | } |
| 3802 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3803 | static struct clk_ops clk_ops_hdmi_pll = { |
| 3804 | .enable = hdmi_pll_clk_enable, |
| 3805 | .disable = hdmi_pll_clk_disable, |
| 3806 | .get_rate = hdmi_pll_clk_get_rate, |
| 3807 | .is_local = local_clk_is_local, |
Stephen Boyd | 5b35dee | 2011-09-21 12:17:38 -0700 | [diff] [blame] | 3808 | .get_parent = hdmi_pll_clk_get_parent, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3809 | }; |
| 3810 | |
| 3811 | static struct clk hdmi_pll_clk = { |
| 3812 | .dbg_name = "hdmi_pll_clk", |
| 3813 | .ops = &clk_ops_hdmi_pll, |
| 3814 | CLK_INIT(hdmi_pll_clk), |
| 3815 | }; |
| 3816 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3817 | #define F_TV_GND(f, s, p_r, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3818 | { \ |
| 3819 | .freq_hz = f, \ |
| 3820 | .src_clk = &s##_clk.c, \ |
| 3821 | .md_val = MD8(8, m, 0, n), \ |
| 3822 | .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3823 | .ctl_val = CC(6, n), \ |
| 3824 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3825 | } |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3826 | #define F_TV(f, s, p_r, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3827 | { \ |
| 3828 | .freq_hz = f, \ |
| 3829 | .src_clk = &s##_clk, \ |
| 3830 | .md_val = MD8(8, m, 0, n), \ |
| 3831 | .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \ |
| 3832 | .ctl_val = CC(6, n), \ |
| 3833 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3834 | .extra_freq_data = (void *)p_r, \ |
| 3835 | } |
| 3836 | /* Switching TV freqs requires PLL reconfiguration. */ |
| 3837 | static struct clk_freq_tbl clk_tbl_tv[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3838 | F_TV_GND( 0, gnd, 0, 1, 0, 0), |
| 3839 | F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0), |
| 3840 | F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0), |
| 3841 | F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0), |
| 3842 | F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0), |
| 3843 | F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3844 | F_END |
| 3845 | }; |
| 3846 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3847 | static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = { |
| 3848 | [VDD_DIG_LOW] = 74250000, |
| 3849 | [VDD_DIG_NOMINAL] = 149000000 |
| 3850 | }; |
| 3851 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3852 | /* |
| 3853 | * Unlike other clocks, the TV rate is adjusted through PLL |
| 3854 | * re-programming. It is also routed through an MND divider. |
| 3855 | */ |
| 3856 | void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf) |
| 3857 | { |
| 3858 | unsigned long pll_rate = (unsigned long)nf->extra_freq_data; |
| 3859 | if (pll_rate) |
| 3860 | hdmi_pll_set_rate(pll_rate); |
| 3861 | set_rate_mnd(clk, nf); |
| 3862 | } |
| 3863 | |
| 3864 | static struct rcg_clk tv_src_clk = { |
| 3865 | .ns_reg = TV_NS_REG, |
| 3866 | .b = { |
| 3867 | .ctl_reg = TV_CC_REG, |
| 3868 | .halt_check = NOCHECK, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3869 | .retain_reg = TV_CC_REG, |
| 3870 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3871 | }, |
| 3872 | .md_reg = TV_MD_REG, |
| 3873 | .root_en_mask = BIT(2), |
| 3874 | .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)), |
| 3875 | .ctl_mask = BM(7, 6), |
| 3876 | .set_rate = set_rate_tv, |
| 3877 | .freq_tbl = clk_tbl_tv, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3878 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3879 | .c = { |
| 3880 | .dbg_name = "tv_src_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 3881 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3882 | VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3883 | CLK_INIT(tv_src_clk.c), |
| 3884 | }, |
| 3885 | }; |
| 3886 | |
| 3887 | static struct branch_clk tv_enc_clk = { |
| 3888 | .b = { |
| 3889 | .ctl_reg = TV_CC_REG, |
| 3890 | .en_mask = BIT(8), |
| 3891 | .reset_reg = SW_RESET_CORE_REG, |
| 3892 | .reset_mask = BIT(0), |
| 3893 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 3894 | .halt_bit = 9, |
| 3895 | }, |
| 3896 | .parent = &tv_src_clk.c, |
| 3897 | .c = { |
| 3898 | .dbg_name = "tv_enc_clk", |
| 3899 | .ops = &clk_ops_branch, |
| 3900 | CLK_INIT(tv_enc_clk.c), |
| 3901 | }, |
| 3902 | }; |
| 3903 | |
| 3904 | static struct branch_clk tv_dac_clk = { |
| 3905 | .b = { |
| 3906 | .ctl_reg = TV_CC_REG, |
| 3907 | .en_mask = BIT(10), |
| 3908 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 3909 | .halt_bit = 10, |
| 3910 | }, |
| 3911 | .parent = &tv_src_clk.c, |
| 3912 | .c = { |
| 3913 | .dbg_name = "tv_dac_clk", |
| 3914 | .ops = &clk_ops_branch, |
| 3915 | CLK_INIT(tv_dac_clk.c), |
| 3916 | }, |
| 3917 | }; |
| 3918 | |
| 3919 | static struct branch_clk mdp_tv_clk = { |
| 3920 | .b = { |
| 3921 | .ctl_reg = TV_CC_REG, |
| 3922 | .en_mask = BIT(0), |
| 3923 | .reset_reg = SW_RESET_CORE_REG, |
| 3924 | .reset_mask = BIT(4), |
| 3925 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 3926 | .halt_bit = 12, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 3927 | .retain_reg = TV_CC2_REG, |
| 3928 | .retain_mask = BIT(10), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3929 | }, |
| 3930 | .parent = &tv_src_clk.c, |
| 3931 | .c = { |
| 3932 | .dbg_name = "mdp_tv_clk", |
| 3933 | .ops = &clk_ops_branch, |
| 3934 | CLK_INIT(mdp_tv_clk.c), |
| 3935 | }, |
| 3936 | }; |
| 3937 | |
| 3938 | static struct branch_clk hdmi_tv_clk = { |
| 3939 | .b = { |
| 3940 | .ctl_reg = TV_CC_REG, |
| 3941 | .en_mask = BIT(12), |
| 3942 | .reset_reg = SW_RESET_CORE_REG, |
| 3943 | .reset_mask = BIT(1), |
| 3944 | .halt_reg = DBG_BUS_VEC_D_REG, |
| 3945 | .halt_bit = 11, |
| 3946 | }, |
| 3947 | .parent = &tv_src_clk.c, |
| 3948 | .c = { |
| 3949 | .dbg_name = "hdmi_tv_clk", |
| 3950 | .ops = &clk_ops_branch, |
| 3951 | CLK_INIT(hdmi_tv_clk.c), |
| 3952 | }, |
| 3953 | }; |
| 3954 | |
| 3955 | static struct branch_clk hdmi_app_clk = { |
| 3956 | .b = { |
| 3957 | .ctl_reg = MISC_CC2_REG, |
| 3958 | .en_mask = BIT(11), |
| 3959 | .reset_reg = SW_RESET_CORE_REG, |
| 3960 | .reset_mask = BIT(11), |
| 3961 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 3962 | .halt_bit = 25, |
| 3963 | }, |
| 3964 | .c = { |
| 3965 | .dbg_name = "hdmi_app_clk", |
| 3966 | .ops = &clk_ops_branch, |
| 3967 | CLK_INIT(hdmi_app_clk.c), |
| 3968 | }, |
| 3969 | }; |
| 3970 | |
| 3971 | static struct bank_masks bmnd_info_vcodec = { |
| 3972 | .bank_sel_mask = BIT(13), |
| 3973 | .bank0_mask = { |
| 3974 | .md_reg = VCODEC_MD0_REG, |
| 3975 | .ns_mask = BM(18, 11) | BM(2, 0), |
| 3976 | .rst_mask = BIT(31), |
| 3977 | .mnd_en_mask = BIT(5), |
| 3978 | .mode_mask = BM(7, 6), |
| 3979 | }, |
| 3980 | .bank1_mask = { |
| 3981 | .md_reg = VCODEC_MD1_REG, |
| 3982 | .ns_mask = BM(26, 19) | BM(29, 27), |
| 3983 | .rst_mask = BIT(30), |
| 3984 | .mnd_en_mask = BIT(10), |
| 3985 | .mode_mask = BM(12, 11), |
| 3986 | }, |
| 3987 | }; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3988 | #define F_VCODEC(f, s, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3989 | { \ |
| 3990 | .freq_hz = f, \ |
| 3991 | .src_clk = &s##_clk.c, \ |
| 3992 | .md_val = MD8(8, m, 0, n), \ |
| 3993 | .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \ |
| 3994 | .ctl_val = CC_BANKED(6, 11, n), \ |
| 3995 | .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3996 | } |
| 3997 | static struct clk_freq_tbl clk_tbl_vcodec[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 3998 | F_VCODEC( 0, gnd, 0, 0), |
| 3999 | F_VCODEC( 27000000, pxo, 0, 0), |
| 4000 | F_VCODEC( 32000000, pll8, 1, 12), |
| 4001 | F_VCODEC( 48000000, pll8, 1, 8), |
| 4002 | F_VCODEC( 54860000, pll8, 1, 7), |
| 4003 | F_VCODEC( 96000000, pll8, 1, 4), |
| 4004 | F_VCODEC(133330000, pll2, 1, 6), |
| 4005 | F_VCODEC(200000000, pll2, 1, 4), |
| 4006 | F_VCODEC(228570000, pll2, 2, 7), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4007 | F_END |
| 4008 | }; |
| 4009 | |
| 4010 | static struct rcg_clk vcodec_clk = { |
| 4011 | .b = { |
| 4012 | .ctl_reg = VCODEC_CC_REG, |
| 4013 | .en_mask = BIT(0), |
| 4014 | .reset_reg = SW_RESET_CORE_REG, |
| 4015 | .reset_mask = BIT(6), |
| 4016 | .halt_reg = DBG_BUS_VEC_C_REG, |
| 4017 | .halt_bit = 29, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4018 | .retain_reg = VCODEC_CC_REG, |
| 4019 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4020 | }, |
| 4021 | .ns_reg = VCODEC_NS_REG, |
| 4022 | .root_en_mask = BIT(2), |
| 4023 | .set_rate = set_rate_mnd_banked, |
Stephen Boyd | c78d9a7 | 2011-07-20 00:46:24 -0700 | [diff] [blame] | 4024 | .bank_info = &bmnd_info_vcodec, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4025 | .freq_tbl = clk_tbl_vcodec, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4026 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4027 | .c = { |
| 4028 | .dbg_name = "vcodec_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4029 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4030 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, |
| 4031 | HIGH, 228571000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4032 | CLK_INIT(vcodec_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4033 | .depends = &vcodec_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4034 | }, |
| 4035 | }; |
| 4036 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4037 | #define F_VPE(f, s, d) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4038 | { \ |
| 4039 | .freq_hz = f, \ |
| 4040 | .src_clk = &s##_clk.c, \ |
| 4041 | .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4042 | } |
| 4043 | static struct clk_freq_tbl clk_tbl_vpe[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4044 | F_VPE( 0, gnd, 1), |
| 4045 | F_VPE( 27000000, pxo, 1), |
| 4046 | F_VPE( 34909000, pll8, 11), |
| 4047 | F_VPE( 38400000, pll8, 10), |
| 4048 | F_VPE( 64000000, pll8, 6), |
| 4049 | F_VPE( 76800000, pll8, 5), |
| 4050 | F_VPE( 96000000, pll8, 4), |
| 4051 | F_VPE(100000000, pll2, 8), |
| 4052 | F_VPE(160000000, pll2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4053 | F_END |
| 4054 | }; |
| 4055 | |
| 4056 | static struct rcg_clk vpe_clk = { |
| 4057 | .b = { |
| 4058 | .ctl_reg = VPE_CC_REG, |
| 4059 | .en_mask = BIT(0), |
| 4060 | .reset_reg = SW_RESET_CORE_REG, |
| 4061 | .reset_mask = BIT(17), |
| 4062 | .halt_reg = DBG_BUS_VEC_A_REG, |
| 4063 | .halt_bit = 28, |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4064 | .retain_reg = VPE_CC_REG, |
| 4065 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4066 | }, |
| 4067 | .ns_reg = VPE_NS_REG, |
| 4068 | .root_en_mask = BIT(2), |
| 4069 | .ns_mask = (BM(15, 12) | BM(2, 0)), |
| 4070 | .set_rate = set_rate_nop, |
| 4071 | .freq_tbl = clk_tbl_vpe, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4072 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4073 | .c = { |
| 4074 | .dbg_name = "vpe_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4075 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4076 | VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4077 | CLK_INIT(vpe_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4078 | .depends = &vpe_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4079 | }, |
| 4080 | }; |
| 4081 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4082 | #define F_VFE(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4083 | { \ |
| 4084 | .freq_hz = f, \ |
| 4085 | .src_clk = &s##_clk.c, \ |
| 4086 | .md_val = MD8(8, m, 0, n), \ |
| 4087 | .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \ |
| 4088 | .ctl_val = CC(6, n), \ |
| 4089 | .mnd_en_mask = BIT(5) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4090 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4091 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4092 | static struct clk_freq_tbl clk_tbl_vfe[] = { |
| 4093 | F_VFE( 0, gnd, 1, 0, 0), |
| 4094 | F_VFE( 13960000, pll8, 1, 2, 55), |
| 4095 | F_VFE( 27000000, pxo, 1, 0, 0), |
| 4096 | F_VFE( 36570000, pll8, 1, 2, 21), |
| 4097 | F_VFE( 38400000, pll8, 2, 1, 5), |
| 4098 | F_VFE( 45180000, pll8, 1, 2, 17), |
| 4099 | F_VFE( 48000000, pll8, 2, 1, 4), |
| 4100 | F_VFE( 54860000, pll8, 1, 1, 7), |
| 4101 | F_VFE( 64000000, pll8, 2, 1, 3), |
| 4102 | F_VFE( 76800000, pll8, 1, 1, 5), |
| 4103 | F_VFE( 96000000, pll8, 2, 1, 2), |
| 4104 | F_VFE(109710000, pll8, 1, 2, 7), |
| 4105 | F_VFE(128000000, pll8, 1, 1, 3), |
| 4106 | F_VFE(153600000, pll8, 1, 2, 5), |
| 4107 | F_VFE(200000000, pll2, 2, 1, 2), |
| 4108 | F_VFE(228570000, pll2, 1, 2, 7), |
| 4109 | F_VFE(266667000, pll2, 1, 1, 3), |
| 4110 | F_VFE(320000000, pll2, 1, 2, 5), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4111 | F_END |
| 4112 | }; |
| 4113 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4114 | static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = { |
| 4115 | [VDD_DIG_LOW] = 128000000, |
| 4116 | [VDD_DIG_NOMINAL] = 266667000, |
| 4117 | [VDD_DIG_HIGH] = 320000000 |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4118 | }; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4119 | |
| 4120 | static struct rcg_clk vfe_clk = { |
| 4121 | .b = { |
| 4122 | .ctl_reg = VFE_CC_REG, |
| 4123 | .reset_reg = SW_RESET_CORE_REG, |
| 4124 | .reset_mask = BIT(15), |
| 4125 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4126 | .halt_bit = 6, |
| 4127 | .en_mask = BIT(0), |
Matt Wagantall | 7e0b6c9 | 2012-01-20 18:48:05 -0800 | [diff] [blame] | 4128 | .retain_reg = VFE_CC2_REG, |
| 4129 | .retain_mask = BIT(31), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4130 | }, |
| 4131 | .ns_reg = VFE_NS_REG, |
| 4132 | .md_reg = VFE_MD_REG, |
| 4133 | .root_en_mask = BIT(2), |
| 4134 | .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)), |
| 4135 | .ctl_mask = BM(7, 6), |
| 4136 | .set_rate = set_rate_mnd, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4137 | .freq_tbl = clk_tbl_vfe, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4138 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4139 | .c = { |
| 4140 | .dbg_name = "vfe_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4141 | .ops = &clk_ops_rcg_8960, |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 4142 | VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000, |
| 4143 | HIGH, 320000000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4144 | CLK_INIT(vfe_clk.c), |
Stephen Boyd | 7fa2674 | 2011-08-11 23:22:29 -0700 | [diff] [blame] | 4145 | .depends = &vfe_axi_clk.c, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4146 | }, |
| 4147 | }; |
| 4148 | |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4149 | static struct branch_clk csi_vfe_clk = { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4150 | .b = { |
| 4151 | .ctl_reg = VFE_CC_REG, |
| 4152 | .en_mask = BIT(12), |
| 4153 | .reset_reg = SW_RESET_CORE_REG, |
| 4154 | .reset_mask = BIT(24), |
| 4155 | .halt_reg = DBG_BUS_VEC_B_REG, |
| 4156 | .halt_bit = 8, |
| 4157 | }, |
| 4158 | .parent = &vfe_clk.c, |
| 4159 | .c = { |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4160 | .dbg_name = "csi_vfe_clk", |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4161 | .ops = &clk_ops_branch, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4162 | CLK_INIT(csi_vfe_clk.c), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4163 | }, |
| 4164 | }; |
| 4165 | |
| 4166 | /* |
| 4167 | * Low Power Audio Clocks |
| 4168 | */ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4169 | #define F_AIF_OSR(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4170 | { \ |
| 4171 | .freq_hz = f, \ |
| 4172 | .src_clk = &s##_clk.c, \ |
| 4173 | .md_val = MD8(8, m, 0, n), \ |
| 4174 | .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \ |
| 4175 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4176 | } |
| 4177 | static struct clk_freq_tbl clk_tbl_aif_osr[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4178 | F_AIF_OSR( 0, gnd, 1, 0, 0), |
| 4179 | F_AIF_OSR( 512000, pll4, 4, 1, 192), |
| 4180 | F_AIF_OSR( 768000, pll4, 4, 1, 128), |
| 4181 | F_AIF_OSR( 1024000, pll4, 4, 1, 96), |
| 4182 | F_AIF_OSR( 1536000, pll4, 4, 1, 64), |
| 4183 | F_AIF_OSR( 2048000, pll4, 4, 1, 48), |
| 4184 | F_AIF_OSR( 3072000, pll4, 4, 1, 32), |
| 4185 | F_AIF_OSR( 4096000, pll4, 4, 1, 24), |
| 4186 | F_AIF_OSR( 6144000, pll4, 4, 1, 16), |
| 4187 | F_AIF_OSR( 8192000, pll4, 4, 1, 12), |
| 4188 | F_AIF_OSR(12288000, pll4, 4, 1, 8), |
| 4189 | F_AIF_OSR(24576000, pll4, 4, 1, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4190 | F_END |
| 4191 | }; |
| 4192 | |
| 4193 | #define CLK_AIF_OSR(i, ns, md, h_r) \ |
| 4194 | struct rcg_clk i##_clk = { \ |
| 4195 | .b = { \ |
| 4196 | .ctl_reg = ns, \ |
| 4197 | .en_mask = BIT(17), \ |
| 4198 | .reset_reg = ns, \ |
| 4199 | .reset_mask = BIT(19), \ |
| 4200 | .halt_reg = h_r, \ |
| 4201 | .halt_check = ENABLE, \ |
| 4202 | .halt_bit = 1, \ |
| 4203 | }, \ |
| 4204 | .ns_reg = ns, \ |
| 4205 | .md_reg = md, \ |
| 4206 | .root_en_mask = BIT(9), \ |
| 4207 | .ns_mask = (BM(31, 24) | BM(6, 0)), \ |
| 4208 | .set_rate = set_rate_mnd, \ |
| 4209 | .freq_tbl = clk_tbl_aif_osr, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4210 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4211 | .c = { \ |
| 4212 | .dbg_name = #i "_clk", \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4213 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4214 | VDD_DIG_FMAX_MAP1(LOW, 24576000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4215 | CLK_INIT(i##_clk.c), \ |
| 4216 | }, \ |
| 4217 | } |
| 4218 | #define CLK_AIF_OSR_DIV(i, ns, md, h_r) \ |
| 4219 | struct rcg_clk i##_clk = { \ |
| 4220 | .b = { \ |
| 4221 | .ctl_reg = ns, \ |
| 4222 | .en_mask = BIT(21), \ |
| 4223 | .reset_reg = ns, \ |
| 4224 | .reset_mask = BIT(23), \ |
| 4225 | .halt_reg = h_r, \ |
| 4226 | .halt_check = ENABLE, \ |
| 4227 | .halt_bit = 1, \ |
| 4228 | }, \ |
| 4229 | .ns_reg = ns, \ |
| 4230 | .md_reg = md, \ |
| 4231 | .root_en_mask = BIT(9), \ |
| 4232 | .ns_mask = (BM(31, 24) | BM(6, 0)), \ |
| 4233 | .set_rate = set_rate_mnd, \ |
| 4234 | .freq_tbl = clk_tbl_aif_osr, \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4235 | .current_freq = &rcg_dummy_freq, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4236 | .c = { \ |
| 4237 | .dbg_name = #i "_clk", \ |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4238 | .ops = &clk_ops_rcg_8960, \ |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4239 | VDD_DIG_FMAX_MAP1(LOW, 24576000), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4240 | CLK_INIT(i##_clk.c), \ |
| 4241 | }, \ |
| 4242 | } |
| 4243 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4244 | #define CLK_AIF_BIT(i, ns, h_r) \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4245 | struct cdiv_clk i##_clk = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4246 | .b = { \ |
| 4247 | .ctl_reg = ns, \ |
| 4248 | .en_mask = BIT(15), \ |
| 4249 | .halt_reg = h_r, \ |
| 4250 | .halt_check = DELAY, \ |
| 4251 | }, \ |
| 4252 | .ns_reg = ns, \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4253 | .ext_mask = BIT(14), \ |
| 4254 | .div_offset = 10, \ |
| 4255 | .max_div = 16, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4256 | .c = { \ |
| 4257 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4258 | .ops = &clk_ops_cdiv, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4259 | CLK_INIT(i##_clk.c), \ |
| 4260 | }, \ |
| 4261 | } |
| 4262 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4263 | #define CLK_AIF_BIT_DIV(i, ns, h_r) \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4264 | struct cdiv_clk i##_clk = { \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4265 | .b = { \ |
| 4266 | .ctl_reg = ns, \ |
| 4267 | .en_mask = BIT(19), \ |
| 4268 | .halt_reg = h_r, \ |
Stephen Boyd | 7bb9cf8 | 2012-01-25 18:09:01 -0800 | [diff] [blame] | 4269 | .halt_check = DELAY, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4270 | }, \ |
| 4271 | .ns_reg = ns, \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4272 | .ext_mask = BIT(18), \ |
| 4273 | .div_offset = 10, \ |
| 4274 | .max_div = 256, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4275 | .c = { \ |
| 4276 | .dbg_name = #i "_clk", \ |
Stephen Boyd | 9fd1964 | 2011-11-16 11:11:09 -0800 | [diff] [blame] | 4277 | .ops = &clk_ops_cdiv, \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4278 | CLK_INIT(i##_clk.c), \ |
| 4279 | }, \ |
| 4280 | } |
| 4281 | |
| 4282 | static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG, |
| 4283 | LCC_MI2S_STATUS_REG); |
| 4284 | static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG); |
| 4285 | |
| 4286 | static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG, |
| 4287 | LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG); |
| 4288 | static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG, |
| 4289 | LCC_CODEC_I2S_MIC_STATUS_REG); |
| 4290 | |
| 4291 | static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG, |
| 4292 | LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG); |
| 4293 | static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG, |
| 4294 | LCC_SPARE_I2S_MIC_STATUS_REG); |
| 4295 | |
| 4296 | static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG, |
| 4297 | LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG); |
| 4298 | static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG, |
| 4299 | LCC_CODEC_I2S_SPKR_STATUS_REG); |
| 4300 | |
| 4301 | static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG, |
| 4302 | LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG); |
| 4303 | static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG, |
| 4304 | LCC_SPARE_I2S_SPKR_STATUS_REG); |
| 4305 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4306 | #define F_PCM(f, s, d, m, n) \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4307 | { \ |
| 4308 | .freq_hz = f, \ |
| 4309 | .src_clk = &s##_clk.c, \ |
| 4310 | .md_val = MD16(m, n), \ |
| 4311 | .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \ |
| 4312 | .mnd_en_mask = BIT(8) * !!(n), \ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4313 | } |
| 4314 | static struct clk_freq_tbl clk_tbl_pcm[] = { |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4315 | F_PCM( 0, gnd, 1, 0, 0), |
| 4316 | F_PCM( 512000, pll4, 4, 1, 192), |
| 4317 | F_PCM( 768000, pll4, 4, 1, 128), |
| 4318 | F_PCM( 1024000, pll4, 4, 1, 96), |
| 4319 | F_PCM( 1536000, pll4, 4, 1, 64), |
| 4320 | F_PCM( 2048000, pll4, 4, 1, 48), |
| 4321 | F_PCM( 3072000, pll4, 4, 1, 32), |
| 4322 | F_PCM( 4096000, pll4, 4, 1, 24), |
| 4323 | F_PCM( 6144000, pll4, 4, 1, 16), |
| 4324 | F_PCM( 8192000, pll4, 4, 1, 12), |
| 4325 | F_PCM(12288000, pll4, 4, 1, 8), |
| 4326 | F_PCM(24576000, pll4, 4, 1, 4), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4327 | F_END |
| 4328 | }; |
| 4329 | |
| 4330 | static struct rcg_clk pcm_clk = { |
| 4331 | .b = { |
| 4332 | .ctl_reg = LCC_PCM_NS_REG, |
| 4333 | .en_mask = BIT(11), |
| 4334 | .reset_reg = LCC_PCM_NS_REG, |
| 4335 | .reset_mask = BIT(13), |
| 4336 | .halt_reg = LCC_PCM_STATUS_REG, |
| 4337 | .halt_check = ENABLE, |
| 4338 | .halt_bit = 0, |
| 4339 | }, |
| 4340 | .ns_reg = LCC_PCM_NS_REG, |
| 4341 | .md_reg = LCC_PCM_MD_REG, |
| 4342 | .root_en_mask = BIT(9), |
| 4343 | .ns_mask = (BM(31, 16) | BM(6, 0)), |
| 4344 | .set_rate = set_rate_mnd, |
| 4345 | .freq_tbl = clk_tbl_pcm, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4346 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4347 | .c = { |
| 4348 | .dbg_name = "pcm_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4349 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4350 | VDD_DIG_FMAX_MAP1(LOW, 24576000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4351 | CLK_INIT(pcm_clk.c), |
| 4352 | }, |
| 4353 | }; |
| 4354 | |
| 4355 | static struct rcg_clk audio_slimbus_clk = { |
| 4356 | .b = { |
| 4357 | .ctl_reg = LCC_SLIMBUS_NS_REG, |
| 4358 | .en_mask = BIT(10), |
| 4359 | .reset_reg = LCC_AHBEX_BRANCH_CTL_REG, |
| 4360 | .reset_mask = BIT(5), |
| 4361 | .halt_reg = LCC_SLIMBUS_STATUS_REG, |
| 4362 | .halt_check = ENABLE, |
| 4363 | .halt_bit = 0, |
| 4364 | }, |
| 4365 | .ns_reg = LCC_SLIMBUS_NS_REG, |
| 4366 | .md_reg = LCC_SLIMBUS_MD_REG, |
| 4367 | .root_en_mask = BIT(9), |
| 4368 | .ns_mask = (BM(31, 24) | BM(6, 0)), |
| 4369 | .set_rate = set_rate_mnd, |
| 4370 | .freq_tbl = clk_tbl_aif_osr, |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4371 | .current_freq = &rcg_dummy_freq, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4372 | .c = { |
| 4373 | .dbg_name = "audio_slimbus_clk", |
Matt Wagantall | 84f43fd | 2011-08-16 23:28:38 -0700 | [diff] [blame] | 4374 | .ops = &clk_ops_rcg_8960, |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 4375 | VDD_DIG_FMAX_MAP1(LOW, 24576000), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4376 | CLK_INIT(audio_slimbus_clk.c), |
| 4377 | }, |
| 4378 | }; |
| 4379 | |
| 4380 | static struct branch_clk sps_slimbus_clk = { |
| 4381 | .b = { |
| 4382 | .ctl_reg = LCC_SLIMBUS_NS_REG, |
| 4383 | .en_mask = BIT(12), |
| 4384 | .halt_reg = LCC_SLIMBUS_STATUS_REG, |
| 4385 | .halt_check = ENABLE, |
| 4386 | .halt_bit = 1, |
| 4387 | }, |
| 4388 | .parent = &audio_slimbus_clk.c, |
| 4389 | .c = { |
| 4390 | .dbg_name = "sps_slimbus_clk", |
| 4391 | .ops = &clk_ops_branch, |
| 4392 | CLK_INIT(sps_slimbus_clk.c), |
| 4393 | }, |
| 4394 | }; |
| 4395 | |
| 4396 | static struct branch_clk slimbus_xo_src_clk = { |
| 4397 | .b = { |
| 4398 | .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG, |
| 4399 | .en_mask = BIT(2), |
| 4400 | .halt_reg = CLK_HALT_DFAB_STATE_REG, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4401 | .halt_bit = 28, |
| 4402 | }, |
| 4403 | .parent = &sps_slimbus_clk.c, |
| 4404 | .c = { |
| 4405 | .dbg_name = "slimbus_xo_src_clk", |
| 4406 | .ops = &clk_ops_branch, |
| 4407 | CLK_INIT(slimbus_xo_src_clk.c), |
| 4408 | }, |
| 4409 | }; |
| 4410 | |
Matt Wagantall | 735f01a | 2011-08-12 12:40:28 -0700 | [diff] [blame] | 4411 | DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL); |
| 4412 | DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL); |
| 4413 | DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL); |
| 4414 | DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL); |
| 4415 | DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL); |
| 4416 | DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL); |
| 4417 | DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL); |
| 4418 | DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4419 | |
| 4420 | static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c); |
| 4421 | static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c); |
Manu Gautam | 7483f17 | 2011-11-08 15:22:26 +0530 | [diff] [blame] | 4422 | static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c); |
| 4423 | static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4424 | static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c); |
| 4425 | static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c); |
| 4426 | static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c); |
| 4427 | static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c); |
| 4428 | static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c); |
| 4429 | static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c); |
Stephen Boyd | 1c51a49 | 2011-10-26 12:11:47 -0700 | [diff] [blame] | 4430 | static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c); |
Stephen Boyd | ef5d1c4 | 2011-12-15 20:47:14 -0800 | [diff] [blame] | 4431 | static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4432 | |
| 4433 | static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c); |
Stephen Boyd | 36466ae | 2012-01-18 20:58:27 -0800 | [diff] [blame] | 4434 | static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4435 | |
| 4436 | #ifdef CONFIG_DEBUG_FS |
| 4437 | struct measure_sel { |
| 4438 | u32 test_vector; |
| 4439 | struct clk *clk; |
| 4440 | }; |
| 4441 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4442 | static DEFINE_CLK_MEASURE(l2_m_clk); |
| 4443 | static DEFINE_CLK_MEASURE(krait0_m_clk); |
| 4444 | static DEFINE_CLK_MEASURE(krait1_m_clk); |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 4445 | static DEFINE_CLK_MEASURE(krait2_m_clk); |
| 4446 | static DEFINE_CLK_MEASURE(krait3_m_clk); |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4447 | static DEFINE_CLK_MEASURE(q6sw_clk); |
| 4448 | static DEFINE_CLK_MEASURE(q6fw_clk); |
| 4449 | static DEFINE_CLK_MEASURE(q6_func_clk); |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4450 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4451 | static struct measure_sel measure_mux[] = { |
| 4452 | { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c }, |
| 4453 | { TEST_PER_LS(0x12), &sdc1_p_clk.c }, |
| 4454 | { TEST_PER_LS(0x13), &sdc1_clk.c }, |
| 4455 | { TEST_PER_LS(0x14), &sdc2_p_clk.c }, |
| 4456 | { TEST_PER_LS(0x15), &sdc2_clk.c }, |
| 4457 | { TEST_PER_LS(0x16), &sdc3_p_clk.c }, |
| 4458 | { TEST_PER_LS(0x17), &sdc3_clk.c }, |
| 4459 | { TEST_PER_LS(0x18), &sdc4_p_clk.c }, |
| 4460 | { TEST_PER_LS(0x19), &sdc4_clk.c }, |
| 4461 | { TEST_PER_LS(0x1A), &sdc5_p_clk.c }, |
| 4462 | { TEST_PER_LS(0x1B), &sdc5_clk.c }, |
Matt Wagantall | 7625a4c | 2011-11-01 16:17:53 -0700 | [diff] [blame] | 4463 | { TEST_PER_LS(0x1F), &gp0_clk.c }, |
| 4464 | { TEST_PER_LS(0x20), &gp1_clk.c }, |
| 4465 | { TEST_PER_LS(0x21), &gp2_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4466 | { TEST_PER_LS(0x25), &dfab_clk.c }, |
| 4467 | { TEST_PER_LS(0x25), &dfab_a_clk.c }, |
| 4468 | { TEST_PER_LS(0x26), &pmem_clk.c }, |
| 4469 | { TEST_PER_LS(0x32), &dma_bam_p_clk.c }, |
| 4470 | { TEST_PER_LS(0x33), &cfpb_clk.c }, |
| 4471 | { TEST_PER_LS(0x33), &cfpb_a_clk.c }, |
| 4472 | { TEST_PER_LS(0x3D), &gsbi1_p_clk.c }, |
| 4473 | { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c }, |
| 4474 | { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c }, |
| 4475 | { TEST_PER_LS(0x41), &gsbi2_p_clk.c }, |
| 4476 | { TEST_PER_LS(0x42), &gsbi2_uart_clk.c }, |
| 4477 | { TEST_PER_LS(0x44), &gsbi2_qup_clk.c }, |
| 4478 | { TEST_PER_LS(0x45), &gsbi3_p_clk.c }, |
| 4479 | { TEST_PER_LS(0x46), &gsbi3_uart_clk.c }, |
| 4480 | { TEST_PER_LS(0x48), &gsbi3_qup_clk.c }, |
| 4481 | { TEST_PER_LS(0x49), &gsbi4_p_clk.c }, |
| 4482 | { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c }, |
| 4483 | { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c }, |
| 4484 | { TEST_PER_LS(0x4D), &gsbi5_p_clk.c }, |
| 4485 | { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c }, |
| 4486 | { TEST_PER_LS(0x50), &gsbi5_qup_clk.c }, |
| 4487 | { TEST_PER_LS(0x51), &gsbi6_p_clk.c }, |
| 4488 | { TEST_PER_LS(0x52), &gsbi6_uart_clk.c }, |
| 4489 | { TEST_PER_LS(0x54), &gsbi6_qup_clk.c }, |
| 4490 | { TEST_PER_LS(0x55), &gsbi7_p_clk.c }, |
| 4491 | { TEST_PER_LS(0x56), &gsbi7_uart_clk.c }, |
| 4492 | { TEST_PER_LS(0x58), &gsbi7_qup_clk.c }, |
| 4493 | { TEST_PER_LS(0x59), &gsbi8_p_clk.c }, |
| 4494 | { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c }, |
| 4495 | { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c }, |
| 4496 | { TEST_PER_LS(0x5D), &gsbi9_p_clk.c }, |
| 4497 | { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c }, |
| 4498 | { TEST_PER_LS(0x60), &gsbi9_qup_clk.c }, |
| 4499 | { TEST_PER_LS(0x61), &gsbi10_p_clk.c }, |
| 4500 | { TEST_PER_LS(0x62), &gsbi10_uart_clk.c }, |
| 4501 | { TEST_PER_LS(0x64), &gsbi10_qup_clk.c }, |
| 4502 | { TEST_PER_LS(0x65), &gsbi11_p_clk.c }, |
| 4503 | { TEST_PER_LS(0x66), &gsbi11_uart_clk.c }, |
| 4504 | { TEST_PER_LS(0x68), &gsbi11_qup_clk.c }, |
| 4505 | { TEST_PER_LS(0x69), &gsbi12_p_clk.c }, |
| 4506 | { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c }, |
| 4507 | { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c }, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4508 | { TEST_PER_LS(0x5E), &pcie_p_clk.c }, |
| 4509 | { TEST_PER_LS(0x5F), &ce3_p_clk.c }, |
| 4510 | { TEST_PER_LS(0x60), &ce3_core_clk.c }, |
| 4511 | { TEST_PER_LS(0x63), &usb_hs3_p_clk.c }, |
| 4512 | { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c }, |
| 4513 | { TEST_PER_LS(0x65), &usb_hs4_p_clk.c }, |
| 4514 | { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c }, |
| 4515 | { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c }, |
| 4516 | { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4517 | { TEST_PER_LS(0x78), &sfpb_clk.c }, |
| 4518 | { TEST_PER_LS(0x78), &sfpb_a_clk.c }, |
| 4519 | { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c }, |
| 4520 | { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c }, |
| 4521 | { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c }, |
| 4522 | { TEST_PER_LS(0x7D), &prng_clk.c }, |
| 4523 | { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c }, |
| 4524 | { TEST_PER_LS(0x80), &adm0_p_clk.c }, |
| 4525 | { TEST_PER_LS(0x84), &usb_hs1_p_clk.c }, |
| 4526 | { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4527 | { TEST_PER_LS(0x86), &usb_hsic_p_clk.c }, |
| 4528 | { TEST_PER_LS(0x87), &usb_hsic_system_clk.c }, |
| 4529 | { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4530 | { TEST_PER_LS(0x89), &usb_fs1_p_clk.c }, |
| 4531 | { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c }, |
| 4532 | { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c }, |
| 4533 | { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c }, |
| 4534 | { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c }, |
| 4535 | { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c }, |
| 4536 | { TEST_PER_LS(0x8F), &tsif_p_clk.c }, |
| 4537 | { TEST_PER_LS(0x91), &tsif_ref_clk.c }, |
| 4538 | { TEST_PER_LS(0x92), &ce1_p_clk.c }, |
| 4539 | { TEST_PER_LS(0x94), &tssc_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4540 | { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4541 | { TEST_PER_LS(0xA4), &ce1_core_clk.c }, |
| 4542 | |
| 4543 | { TEST_PER_HS(0x07), &afab_clk.c }, |
| 4544 | { TEST_PER_HS(0x07), &afab_a_clk.c }, |
| 4545 | { TEST_PER_HS(0x18), &sfab_clk.c }, |
| 4546 | { TEST_PER_HS(0x18), &sfab_a_clk.c }, |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4547 | { TEST_PER_HS(0x26), &q6sw_clk }, |
| 4548 | { TEST_PER_HS(0x27), &q6fw_clk }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4549 | { TEST_PER_HS(0x2A), &adm0_clk.c }, |
| 4550 | { TEST_PER_HS(0x34), &ebi1_clk.c }, |
| 4551 | { TEST_PER_HS(0x34), &ebi1_a_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4552 | { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4553 | |
| 4554 | { TEST_MM_LS(0x00), &dsi1_byte_clk.c }, |
| 4555 | { TEST_MM_LS(0x01), &dsi2_byte_clk.c }, |
| 4556 | { TEST_MM_LS(0x02), &cam1_clk.c }, |
| 4557 | { TEST_MM_LS(0x06), &_p_clk.c }, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4558 | { TEST_MM_LS(0x07), &csi_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4559 | { TEST_MM_LS(0x08), &dsi2_s_p_clk.c }, |
| 4560 | { TEST_MM_LS(0x09), &dsi1_m_p_clk.c }, |
| 4561 | { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c }, |
| 4562 | { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c }, |
| 4563 | { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c }, |
| 4564 | { TEST_MM_LS(0x0E), &gfx3d_p_clk.c }, |
| 4565 | { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c }, |
| 4566 | { TEST_MM_LS(0x10), &hdmi_s_p_clk.c }, |
| 4567 | { TEST_MM_LS(0x11), &ijpeg_p_clk.c }, |
| 4568 | { TEST_MM_LS(0x12), &imem_p_clk.c }, |
| 4569 | { TEST_MM_LS(0x13), &jpegd_p_clk.c }, |
| 4570 | { TEST_MM_LS(0x14), &mdp_p_clk.c }, |
| 4571 | { TEST_MM_LS(0x16), &rot_p_clk.c }, |
| 4572 | { TEST_MM_LS(0x17), &dsi1_esc_clk.c }, |
| 4573 | { TEST_MM_LS(0x18), &smmu_p_clk.c }, |
| 4574 | { TEST_MM_LS(0x19), &tv_enc_p_clk.c }, |
| 4575 | { TEST_MM_LS(0x1A), &vcodec_p_clk.c }, |
| 4576 | { TEST_MM_LS(0x1B), &vfe_p_clk.c }, |
| 4577 | { TEST_MM_LS(0x1C), &vpe_p_clk.c }, |
| 4578 | { TEST_MM_LS(0x1D), &cam0_clk.c }, |
| 4579 | { TEST_MM_LS(0x1F), &hdmi_app_clk.c }, |
| 4580 | { TEST_MM_LS(0x20), &mdp_vsync_clk.c }, |
| 4581 | { TEST_MM_LS(0x21), &tv_dac_clk.c }, |
| 4582 | { TEST_MM_LS(0x22), &tv_enc_clk.c }, |
| 4583 | { TEST_MM_LS(0x23), &dsi2_esc_clk.c }, |
| 4584 | { TEST_MM_LS(0x25), &mmfpb_clk.c }, |
| 4585 | { TEST_MM_LS(0x25), &mmfpb_a_clk.c }, |
| 4586 | { TEST_MM_LS(0x26), &dsi2_m_p_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4587 | { TEST_MM_LS(0x27), &cam2_clk.c }, |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4588 | { TEST_MM_LS(0x28), &vcap_p_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4589 | |
| 4590 | { TEST_MM_HS(0x00), &csi0_clk.c }, |
| 4591 | { TEST_MM_HS(0x01), &csi1_clk.c }, |
Matt Wagantall | c23eee9 | 2011-08-16 23:06:52 -0700 | [diff] [blame] | 4592 | { TEST_MM_HS(0x04), &csi_vfe_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4593 | { TEST_MM_HS(0x05), &ijpeg_clk.c }, |
| 4594 | { TEST_MM_HS(0x06), &vfe_clk.c }, |
| 4595 | { TEST_MM_HS(0x07), &gfx2d0_clk.c }, |
| 4596 | { TEST_MM_HS(0x08), &gfx2d1_clk.c }, |
| 4597 | { TEST_MM_HS(0x09), &gfx3d_clk.c }, |
| 4598 | { TEST_MM_HS(0x0A), &jpegd_clk.c }, |
| 4599 | { TEST_MM_HS(0x0B), &vcodec_clk.c }, |
| 4600 | { TEST_MM_HS(0x0F), &mmfab_clk.c }, |
| 4601 | { TEST_MM_HS(0x0F), &mmfab_a_clk.c }, |
| 4602 | { TEST_MM_HS(0x11), &gmem_axi_clk.c }, |
| 4603 | { TEST_MM_HS(0x12), &ijpeg_axi_clk.c }, |
| 4604 | { TEST_MM_HS(0x13), &imem_axi_clk.c }, |
| 4605 | { TEST_MM_HS(0x14), &jpegd_axi_clk.c }, |
| 4606 | { TEST_MM_HS(0x15), &mdp_axi_clk.c }, |
| 4607 | { TEST_MM_HS(0x16), &rot_axi_clk.c }, |
| 4608 | { TEST_MM_HS(0x17), &vcodec_axi_clk.c }, |
| 4609 | { TEST_MM_HS(0x18), &vfe_axi_clk.c }, |
| 4610 | { TEST_MM_HS(0x19), &vpe_axi_clk.c }, |
| 4611 | { TEST_MM_HS(0x1A), &mdp_clk.c }, |
| 4612 | { TEST_MM_HS(0x1B), &rot_clk.c }, |
| 4613 | { TEST_MM_HS(0x1C), &vpe_clk.c }, |
| 4614 | { TEST_MM_HS(0x1E), &hdmi_tv_clk.c }, |
| 4615 | { TEST_MM_HS(0x1F), &mdp_tv_clk.c }, |
| 4616 | { TEST_MM_HS(0x24), &csi0_phy_clk.c }, |
| 4617 | { TEST_MM_HS(0x25), &csi1_phy_clk.c }, |
| 4618 | { TEST_MM_HS(0x26), &csi_pix_clk.c }, |
| 4619 | { TEST_MM_HS(0x27), &csi_rdi_clk.c }, |
| 4620 | { TEST_MM_HS(0x28), &lut_mdp_clk.c }, |
| 4621 | { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c }, |
| 4622 | { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c }, |
| 4623 | { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c }, |
| 4624 | { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c }, |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 4625 | { TEST_MM_HS(0x2D), &csi2_clk.c }, |
| 4626 | { TEST_MM_HS(0x2E), &csi2_phy_clk.c }, |
| 4627 | { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c }, |
| 4628 | { TEST_MM_HS(0x30), &csi_pix1_clk.c }, |
| 4629 | { TEST_MM_HS(0x31), &csi_rdi1_clk.c }, |
| 4630 | { TEST_MM_HS(0x32), &csi_rdi2_clk.c }, |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 4631 | { TEST_MM_HS(0x33), &vcap_clk.c }, |
| 4632 | { TEST_MM_HS(0x34), &vcap_npl_clk.c }, |
Tianyi Gou | 7747a96 | 2012-02-03 15:03:55 -0800 | [diff] [blame] | 4633 | { TEST_MM_HS(0x35), &vcap_axi_clk.c }, |
| 4634 | { TEST_MM_HS(0x38), &gfx3d_axi_clk.c }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4635 | |
| 4636 | { TEST_LPA(0x0F), &mi2s_bit_clk.c }, |
| 4637 | { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c }, |
| 4638 | { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c }, |
| 4639 | { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c }, |
| 4640 | { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c }, |
| 4641 | { TEST_LPA(0x14), &pcm_clk.c }, |
| 4642 | { TEST_LPA(0x1D), &audio_slimbus_clk.c }, |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4643 | |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4644 | { TEST_LPA_HS(0x00), &q6_func_clk }, |
| 4645 | |
Stephen Boyd | 46fdf0d | 2011-11-22 12:25:09 -0800 | [diff] [blame] | 4646 | { TEST_CPUL2(0x2), &l2_m_clk }, |
| 4647 | { TEST_CPUL2(0x0), &krait0_m_clk }, |
| 4648 | { TEST_CPUL2(0x1), &krait1_m_clk }, |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 4649 | { TEST_CPUL2(0x4), &krait2_m_clk }, |
| 4650 | { TEST_CPUL2(0x5), &krait3_m_clk }, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4651 | }; |
| 4652 | |
| 4653 | static struct measure_sel *find_measure_sel(struct clk *clk) |
| 4654 | { |
| 4655 | int i; |
| 4656 | |
| 4657 | for (i = 0; i < ARRAY_SIZE(measure_mux); i++) |
| 4658 | if (measure_mux[i].clk == clk) |
| 4659 | return &measure_mux[i]; |
| 4660 | return NULL; |
| 4661 | } |
| 4662 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4663 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4664 | { |
| 4665 | int ret = 0; |
| 4666 | u32 clk_sel; |
| 4667 | struct measure_sel *p; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4668 | struct measure_clk *clk = to_measure_clk(c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4669 | unsigned long flags; |
| 4670 | |
| 4671 | if (!parent) |
| 4672 | return -EINVAL; |
| 4673 | |
| 4674 | p = find_measure_sel(parent); |
| 4675 | if (!p) |
| 4676 | return -EINVAL; |
| 4677 | |
| 4678 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4679 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4680 | /* |
| 4681 | * Program the test vector, measurement period (sample_ticks) |
| 4682 | * and scaling multiplier. |
| 4683 | */ |
| 4684 | clk->sample_ticks = 0x10000; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4685 | clk_sel = p->test_vector & TEST_CLK_SEL_MASK; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4686 | clk->multiplier = 1; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4687 | switch (p->test_vector >> TEST_TYPE_SHIFT) { |
| 4688 | case TEST_TYPE_PER_LS: |
| 4689 | writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG); |
| 4690 | break; |
| 4691 | case TEST_TYPE_PER_HS: |
| 4692 | writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG); |
| 4693 | break; |
| 4694 | case TEST_TYPE_MM_LS: |
| 4695 | writel_relaxed(0x4030D97, CLK_TEST_REG); |
| 4696 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG); |
| 4697 | break; |
| 4698 | case TEST_TYPE_MM_HS: |
| 4699 | writel_relaxed(0x402B800, CLK_TEST_REG); |
| 4700 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG); |
| 4701 | break; |
| 4702 | case TEST_TYPE_LPA: |
| 4703 | writel_relaxed(0x4030D98, CLK_TEST_REG); |
| 4704 | writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), |
| 4705 | LCC_CLK_LS_DEBUG_CFG_REG); |
| 4706 | break; |
Stephen Boyd | 3939c8d | 2011-08-29 17:36:22 -0700 | [diff] [blame] | 4707 | case TEST_TYPE_LPA_HS: |
| 4708 | writel_relaxed(0x402BC00, CLK_TEST_REG); |
| 4709 | writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0), |
| 4710 | LCC_CLK_HS_DEBUG_CFG_REG); |
| 4711 | break; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4712 | case TEST_TYPE_CPUL2: |
| 4713 | writel_relaxed(0x4030400, CLK_TEST_REG); |
| 4714 | writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG); |
| 4715 | clk->sample_ticks = 0x4000; |
| 4716 | clk->multiplier = 2; |
| 4717 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4718 | default: |
| 4719 | ret = -EPERM; |
| 4720 | } |
| 4721 | /* Make sure test vector is set before starting measurements. */ |
| 4722 | mb(); |
| 4723 | |
| 4724 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 4725 | |
| 4726 | return ret; |
| 4727 | } |
| 4728 | |
| 4729 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 4730 | static u32 run_measurement(unsigned ticks) |
| 4731 | { |
| 4732 | /* Stop counters and set the XO4 counter start value. */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4733 | writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG); |
| 4734 | |
| 4735 | /* Wait for timer to become ready. */ |
| 4736 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0) |
| 4737 | cpu_relax(); |
| 4738 | |
| 4739 | /* Run measurement and wait for completion. */ |
| 4740 | writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG); |
| 4741 | while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0) |
| 4742 | cpu_relax(); |
| 4743 | |
| 4744 | /* Stop counters. */ |
| 4745 | writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG); |
| 4746 | |
| 4747 | /* Return measured ticks. */ |
| 4748 | return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0); |
| 4749 | } |
| 4750 | |
| 4751 | |
| 4752 | /* Perform a hardware rate measurement for a given clock. |
| 4753 | FOR DEBUG USE ONLY: Measurements take ~15 ms! */ |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 4754 | static unsigned long measure_clk_get_rate(struct clk *c) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4755 | { |
| 4756 | unsigned long flags; |
| 4757 | u32 pdm_reg_backup, ringosc_reg_backup; |
| 4758 | u64 raw_count_short, raw_count_full; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4759 | struct measure_clk *clk = to_measure_clk(c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4760 | unsigned ret; |
| 4761 | |
Stephen Boyd | 3a35f0b | 2012-01-11 16:18:26 -0800 | [diff] [blame] | 4762 | ret = clk_enable(&cxo_clk.c); |
| 4763 | if (ret) { |
| 4764 | pr_warning("CXO clock failed to enable. Can't measure\n"); |
| 4765 | return 0; |
| 4766 | } |
| 4767 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4768 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 4769 | |
| 4770 | /* Enable CXO/4 and RINGOSC branch and root. */ |
| 4771 | pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG); |
| 4772 | ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG); |
| 4773 | writel_relaxed(0x2898, PDM_CLK_NS_REG); |
| 4774 | writel_relaxed(0xA00, RINGOSC_NS_REG); |
| 4775 | |
| 4776 | /* |
| 4777 | * The ring oscillator counter will not reset if the measured clock |
| 4778 | * is not running. To detect this, run a short measurement before |
| 4779 | * the full measurement. If the raw results of the two are the same |
| 4780 | * then the clock must be off. |
| 4781 | */ |
| 4782 | |
| 4783 | /* Run a short measurement. (~1 ms) */ |
| 4784 | raw_count_short = run_measurement(0x1000); |
| 4785 | /* Run a full measurement. (~14 ms) */ |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4786 | raw_count_full = run_measurement(clk->sample_ticks); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4787 | |
| 4788 | writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG); |
| 4789 | writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG); |
| 4790 | |
| 4791 | /* Return 0 if the clock is off. */ |
| 4792 | if (raw_count_full == raw_count_short) |
| 4793 | ret = 0; |
| 4794 | else { |
| 4795 | /* Compute rate in Hz. */ |
| 4796 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4797 | do_div(raw_count_full, ((clk->sample_ticks * 10) + 35)); |
| 4798 | ret = (raw_count_full * clk->multiplier); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4799 | } |
| 4800 | |
| 4801 | /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */ |
Stephen Boyd | 69da840 | 2011-07-14 17:45:31 -0700 | [diff] [blame] | 4802 | writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4803 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 4804 | |
Stephen Boyd | 3a35f0b | 2012-01-11 16:18:26 -0800 | [diff] [blame] | 4805 | clk_disable(&cxo_clk.c); |
| 4806 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4807 | return ret; |
| 4808 | } |
| 4809 | #else /* !CONFIG_DEBUG_FS */ |
| 4810 | static int measure_clk_set_parent(struct clk *clk, struct clk *parent) |
| 4811 | { |
| 4812 | return -EINVAL; |
| 4813 | } |
| 4814 | |
Matt Wagantall | 9de3bfb | 2011-11-03 20:13:12 -0700 | [diff] [blame] | 4815 | static unsigned long measure_clk_get_rate(struct clk *clk) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4816 | { |
| 4817 | return 0; |
| 4818 | } |
| 4819 | #endif /* CONFIG_DEBUG_FS */ |
| 4820 | |
| 4821 | static struct clk_ops measure_clk_ops = { |
| 4822 | .set_parent = measure_clk_set_parent, |
| 4823 | .get_rate = measure_clk_get_rate, |
| 4824 | .is_local = local_clk_is_local, |
| 4825 | }; |
| 4826 | |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 4827 | static struct measure_clk measure_clk = { |
| 4828 | .c = { |
| 4829 | .dbg_name = "measure_clk", |
| 4830 | .ops = &measure_clk_ops, |
| 4831 | CLK_INIT(measure_clk.c), |
| 4832 | }, |
| 4833 | .multiplier = 1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 4834 | }; |
| 4835 | |
Tianyi Gou | a8b3cce | 2011-11-08 14:37:26 -0800 | [diff] [blame] | 4836 | static struct clk_lookup msm_clocks_8064[] = { |
Stephen Boyd | 7dd2266 | 2012-01-26 16:09:31 -0800 | [diff] [blame] | 4837 | CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 4838 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 4839 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 4840 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 4841 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 4842 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
| 4843 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 4844 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 4845 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 4846 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4847 | |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 4848 | CLK_DUMMY("bus_clk", AFAB_CLK, "msm_apps_fab", 0), |
| 4849 | CLK_DUMMY("bus_a_clk", AFAB_A_CLK, "msm_apps_fab", 0), |
| 4850 | CLK_DUMMY("bus_clk", SFAB_CLK, "msm_sys_fab", 0), |
| 4851 | CLK_DUMMY("bus_a_clk", SFAB_A_CLK, "msm_sys_fab", 0), |
| 4852 | CLK_DUMMY("bus_clk", SFPB_CLK, "msm_sys_fpb", 0), |
| 4853 | CLK_DUMMY("bus_a_clk", SFPB_A_CLK, "msm_sys_fpb", 0), |
| 4854 | CLK_DUMMY("bus_clk", MMFAB_CLK, "msm_mm_fab", 0), |
| 4855 | CLK_DUMMY("bus_a_clk", MMFAB_A_CLK, "msm_mm_fab", 0), |
| 4856 | CLK_DUMMY("bus_clk", CFPB_CLK, "msm_cpss_fpb", 0), |
| 4857 | CLK_DUMMY("bus_a_clk", CFPB_A_CLK, "msm_cpss_fpb", 0), |
| 4858 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
| 4859 | CLK_DUMMY("mem_a_clk", EBI1_A_CLK, "msm_bus", 0), |
| 4860 | |
| 4861 | CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4862 | CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0), |
| 4863 | CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0), |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 4864 | CLK_DUMMY("bus_clk", MMFPB_CLK, NULL, 0), |
| 4865 | CLK_DUMMY("bus_a_clk", MMFPB_A_CLK, NULL, 0), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4866 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4867 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 4868 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 4869 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
Stepan Moskovchenko | 4b502d5 | 2012-01-31 18:21:25 -0800 | [diff] [blame] | 4870 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4871 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 4872 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 4873 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
| 4874 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""), |
| 4875 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""), |
| 4876 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), |
| 4877 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, ""), |
| 4878 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
| 4879 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, ""), |
| 4880 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, ""), |
| 4881 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""), |
| 4882 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 4883 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 4884 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4885 | CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL), |
Ramesh Masavarapu | f46be1b | 2011-11-03 11:13:41 -0700 | [diff] [blame] | 4886 | CLK_DUMMY("core_clk", PRNG_CLK, "msm_rng.0", OFF), |
Tianyi Gou | 43208a0 | 2011-09-27 15:35:13 -0700 | [diff] [blame] | 4887 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 4888 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 4889 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 4890 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4891 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""), |
| 4892 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 4893 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 4894 | CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"), |
| 4895 | CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4896 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 4897 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 4898 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
| 4899 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, ""), |
| 4900 | CLK_LOOKUP("core_clk", ce1_core_clk.c, ""), |
| 4901 | CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""), |
| 4902 | CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""), |
Ramesh Masavarapu | 2831191 | 2011-10-27 11:04:12 -0700 | [diff] [blame] | 4903 | CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"), |
| 4904 | CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"), |
| 4905 | CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"), |
| 4906 | CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"), |
| 4907 | CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"), |
| 4908 | CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4909 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
Stepan Moskovchenko | 4b502d5 | 2012-01-31 18:21:25 -0800 | [diff] [blame] | 4910 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4911 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
| 4912 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, ""), |
| 4913 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, ""), |
| 4914 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, ""), |
| 4915 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""), |
| 4916 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""), |
| 4917 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
| 4918 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 4919 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
Manu Gautam | 7483f17 | 2011-11-08 15:22:26 +0530 | [diff] [blame] | 4920 | CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"), |
| 4921 | CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"), |
Tianyi Gou | 43208a0 | 2011-09-27 15:35:13 -0700 | [diff] [blame] | 4922 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 4923 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 4924 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 4925 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4926 | CLK_LOOKUP("iface_clk", pcie_p_clk.c, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 4927 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 4928 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4929 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 4930 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 4931 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 4932 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
| 4933 | CLK_LOOKUP("core_clk", amp_clk.c, ""), |
| 4934 | CLK_LOOKUP("cam_clk", cam0_clk.c, ""), |
| 4935 | CLK_LOOKUP("cam_clk", cam1_clk.c, ""), |
| 4936 | CLK_LOOKUP("cam_clk", cam0_clk.c, ""), |
| 4937 | CLK_LOOKUP("cam_clk", cam0_clk.c, ""), |
| 4938 | CLK_LOOKUP("cam_clk", cam0_clk.c, ""), |
| 4939 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, ""), |
| 4940 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, ""), |
| 4941 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, ""), |
| 4942 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, ""), |
| 4943 | CLK_LOOKUP("csi_clk", csi0_clk.c, ""), |
| 4944 | CLK_LOOKUP("csi_clk", csi1_clk.c, ""), |
| 4945 | CLK_LOOKUP("csi_clk", csi1_clk.c, ""), |
| 4946 | CLK_LOOKUP("csi_clk", csi2_clk.c, ""), |
| 4947 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, ""), |
| 4948 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, ""), |
| 4949 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, ""), |
| 4950 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, ""), |
| 4951 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, ""), |
| 4952 | CLK_LOOKUP("csi_pix_clk", csi_pix1_clk.c, ""), |
| 4953 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, ""), |
| 4954 | CLK_LOOKUP("csi_rdi_clk", csi_rdi1_clk.c, ""), |
| 4955 | CLK_LOOKUP("csi_rdi_clk", csi_rdi2_clk.c, ""), |
| 4956 | CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, ""), |
| 4957 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, ""), |
| 4958 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, ""), |
| 4959 | CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, ""), |
| 4960 | CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, ""), |
| 4961 | CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, ""), |
| 4962 | CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, ""), |
| 4963 | CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, ""), |
| 4964 | CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, "", OFF), |
| 4965 | CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, "", OFF), |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 4966 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4967 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
| 4968 | CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4969 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4970 | CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"), |
| 4971 | CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4972 | CLK_LOOKUP("core_clk", vcap_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4973 | CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4974 | CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4975 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4976 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, ""), |
| 4977 | CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4978 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4979 | CLK_LOOKUP("core_clk", jpegd_clk.c, ""), |
| 4980 | CLK_LOOKUP("mdp_clk", mdp_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4981 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4982 | CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, ""), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 4983 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4984 | CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, ""), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 4985 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 4986 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4987 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4988 | CLK_DUMMY("tv_src_clk", TV_SRC_CLK, "", OFF), |
Greg Grisco | fa47b53 | 2011-11-11 10:32:06 -0800 | [diff] [blame] | 4989 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4990 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4991 | CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, "", OFF), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 4992 | CLK_DUMMY("tv_clk", MDP_TV_CLK, "footswitch-8x60.4", OFF), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4993 | CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, "", OFF), |
| 4994 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, ""), |
| 4995 | CLK_LOOKUP("vpe_clk", vpe_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4996 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4997 | CLK_LOOKUP("vfe_clk", vfe_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 4998 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 4999 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5000 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5001 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5002 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5003 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5004 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5005 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5006 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5007 | CLK_LOOKUP("amp_pclk", amp_p_clk.c, ""), |
| 5008 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, ""), |
| 5009 | CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, ""), |
| 5010 | CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, ""), |
| 5011 | CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, ""), |
| 5012 | CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, ""), |
Pu Chen | 86b4be9 | 2011-11-03 17:27:57 -0700 | [diff] [blame] | 5013 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5014 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5015 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, ""), |
| 5016 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, ""), |
| 5017 | CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5018 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5019 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""), |
Matt Wagantall | 5d44ef2 | 2012-01-23 11:01:05 -0800 | [diff] [blame] | 5020 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5021 | CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5022 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame^] | 5023 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5024 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5025 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
Greg Grisco | fa47b53 | 2011-11-11 10:32:06 -0800 | [diff] [blame] | 5026 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5027 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5028 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5029 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5030 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, ""), |
Matt Wagantall | c9a780c | 2011-10-28 12:12:18 -0700 | [diff] [blame] | 5031 | CLK_LOOKUP("iface_pclk", vpe_p_clk.c, "footswitch-8x60.9"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5032 | CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, ""), |
| 5033 | CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, ""), |
| 5034 | CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, ""), |
| 5035 | CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, ""), |
| 5036 | CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, ""), |
| 5037 | CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, ""), |
| 5038 | CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, ""), |
| 5039 | CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, ""), |
| 5040 | CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, ""), |
| 5041 | CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, ""), |
| 5042 | CLK_LOOKUP("pcm_clk", pcm_clk.c, ""), |
| 5043 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""), |
| 5044 | CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, ""), |
| 5045 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""), |
| 5046 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""), |
| 5047 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""), |
| 5048 | CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""), |
| 5049 | CLK_LOOKUP("core_clk", rot_axi_clk.c, ""), |
| 5050 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""), |
| 5051 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""), |
| 5052 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""), |
| 5053 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""), |
| 5054 | CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, ""), |
| 5055 | CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, "", 0), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5056 | CLK_DUMMY("core_clk", DFAB_USB_HS_CLK, "msm_otg", 0), |
| 5057 | CLK_DUMMY("core_clk", DFAB_USB_HS3_CLK, "msm_ehci_host.0", 0), |
| 5058 | CLK_DUMMY("core_clk", DFAB_USB_HS4_CLK, "msm_ehci_host.1", 0), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5059 | CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, "", 0), |
| 5060 | CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, "", 0), |
| 5061 | CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, "", 0), |
| 5062 | CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, "", 0), |
| 5063 | CLK_DUMMY("dfab_clk", DFAB_CLK, "", 0), |
Stephen Boyd | ef5d1c4 | 2011-12-15 20:47:14 -0800 | [diff] [blame] | 5064 | CLK_DUMMY("bus_clk", DFAB_SCM_CLK, "scm", 0), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5065 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5066 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5067 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5068 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5069 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5070 | |
Stepan Moskovchenko | 279b785 | 2012-01-31 20:42:46 -0800 | [diff] [blame^] | 5071 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"), |
| 5072 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5073 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5074 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5075 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5076 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5077 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5078 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5079 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
| 5080 | CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.9"), |
| 5081 | CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"), |
| 5082 | CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"), |
| 5083 | |
Jeff Ohlstein | 8c116c7 | 2011-10-27 17:34:48 -0700 | [diff] [blame] | 5084 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5085 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5086 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5087 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5088 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
Tianyi Gou | 455c13c | 2012-02-02 16:33:24 -0800 | [diff] [blame] | 5089 | CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""), |
| 5090 | CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""), |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5091 | }; |
| 5092 | |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5093 | static struct clk_lookup msm_clocks_8960[] = { |
Stephen Boyd | 7dd2266 | 2012-01-26 16:09:31 -0800 | [diff] [blame] | 5094 | CLK_LOOKUP("xo", cxo_clk.c, "msm_otg"), |
Stephen Boyd | ed630b0 | 2012-01-26 15:26:47 -0800 | [diff] [blame] | 5095 | CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"), |
| 5096 | CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"), |
| 5097 | CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"), |
| 5098 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"), |
| 5099 | CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"), |
| 5100 | CLK_LOOKUP("pll2", pll2_clk.c, NULL), |
| 5101 | CLK_LOOKUP("pll8", pll8_clk.c, NULL), |
| 5102 | CLK_LOOKUP("pll4", pll4_clk.c, NULL), |
| 5103 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5104 | |
Matt Wagantall | b2710b8 | 2011-11-16 19:55:17 -0800 | [diff] [blame] | 5105 | CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"), |
| 5106 | CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"), |
| 5107 | CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"), |
| 5108 | CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"), |
| 5109 | CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"), |
| 5110 | CLK_LOOKUP("bus_a_clk", sfab_a_clk.c, "msm_sys_fab"), |
| 5111 | CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"), |
| 5112 | CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"), |
| 5113 | CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"), |
| 5114 | CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"), |
| 5115 | CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"), |
| 5116 | CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"), |
| 5117 | |
| 5118 | CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL), |
| 5119 | CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL), |
| 5120 | CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL), |
| 5121 | CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL), |
| 5122 | CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"), |
| 5123 | CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5124 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5125 | CLK_LOOKUP("core_clk", gp0_clk.c, ""), |
| 5126 | CLK_LOOKUP("core_clk", gp1_clk.c, ""), |
| 5127 | CLK_LOOKUP("core_clk", gp2_clk.c, ""), |
| 5128 | CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""), |
| 5129 | CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""), |
| 5130 | CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""), |
| 5131 | CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 5132 | CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"), |
| 5133 | CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5134 | CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""), |
| 5135 | CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""), |
| 5136 | CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""), |
| 5137 | CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""), |
| 5138 | CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""), |
| 5139 | CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5140 | CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5141 | CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5142 | CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"), |
| 5143 | CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5144 | CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""), |
| 5145 | CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""), |
| 5146 | CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""), |
| 5147 | CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""), |
| 5148 | CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5149 | CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5150 | CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5151 | CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5152 | CLK_LOOKUP("core_clk", pdm_clk.c, ""), |
Vikram Mulukutla | dd0a237 | 2011-09-19 15:58:21 -0700 | [diff] [blame] | 5153 | CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"), |
Matt Wagantall | c120529 | 2011-08-11 17:19:31 -0700 | [diff] [blame] | 5154 | CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5155 | CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"), |
| 5156 | CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"), |
| 5157 | CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"), |
| 5158 | CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"), |
| 5159 | CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5160 | CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5161 | CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""), |
| 5162 | CLK_LOOKUP("core_clk", tssc_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5163 | CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"), |
| 5164 | CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5165 | CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""), |
| 5166 | CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""), |
| 5167 | CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""), |
| 5168 | CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""), |
| 5169 | CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""), |
| 5170 | CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5171 | CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"), |
| 5172 | CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"), |
| 5173 | CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"), |
| 5174 | CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"), |
| 5175 | CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 5176 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"), |
Matt Wagantall | e0b1145 | 2011-09-13 17:25:33 -0700 | [diff] [blame] | 5177 | CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"), |
Matt Wagantall | c4b3a4d | 2011-08-17 16:58:39 -0700 | [diff] [blame] | 5178 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"), |
Matt Wagantall | e0b1145 | 2011-09-13 17:25:33 -0700 | [diff] [blame] | 5179 | CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5180 | CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5181 | CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5182 | CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5183 | CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"), |
| 5184 | CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"), |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 5185 | CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"), |
| 5186 | CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5187 | CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""), |
| 5188 | CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""), |
| 5189 | CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5190 | CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5191 | CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""), |
Matt Wagantall | ac29485 | 2011-08-17 15:44:58 -0700 | [diff] [blame] | 5192 | CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5193 | CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""), |
| 5194 | CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""), |
| 5195 | CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5196 | CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5197 | CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"), |
| 5198 | CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"), |
| 5199 | CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"), |
| 5200 | CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"), |
| 5201 | CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"), |
Matt Wagantall | e1a8606 | 2011-08-18 17:46:10 -0700 | [diff] [blame] | 5202 | CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"), |
| 5203 | CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5204 | CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""), |
| 5205 | CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""), |
| 5206 | CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""), |
| 5207 | CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""), |
| 5208 | CLK_LOOKUP("core_clk", amp_clk.c, ""), |
Kevin Chan | 09f4e66 | 2011-12-16 08:17:02 -0800 | [diff] [blame] | 5209 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"), |
| 5210 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"), |
| 5211 | CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5212 | CLK_LOOKUP("cam_clk", cam2_clk.c, NULL), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5213 | CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"), |
| 5214 | CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"), |
| 5215 | CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"), |
| 5216 | CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"), |
| 5217 | CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"), |
| 5218 | CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"), |
Kevin Chan | e12c667 | 2011-10-26 11:55:26 -0700 | [diff] [blame] | 5219 | CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"), |
| 5220 | CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"), |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5221 | CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL), |
| 5222 | CLK_LOOKUP("csi_clk", csi2_clk.c, NULL), |
| 5223 | CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"), |
| 5224 | CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"), |
| 5225 | CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"), |
| 5226 | CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL), |
| 5227 | CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL), |
Kevin Chan | f6216f2 | 2011-10-25 18:40:11 -0700 | [diff] [blame] | 5228 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5229 | csiphy_timer_src_clk.c, "msm_csiphy.0"), |
| 5230 | CLK_LOOKUP("csiphy_timer_src_clk", |
| 5231 | csiphy_timer_src_clk.c, "msm_csiphy.1"), |
| 5232 | CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"), |
| 5233 | CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5234 | CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL), |
| 5235 | CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL), |
| 5236 | CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL), |
| 5237 | CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5238 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5239 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5240 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5241 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5242 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5243 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"), |
| 5244 | CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5245 | CLK_LOOKUP("mem_clk", imem_axi_clk.c, ""), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5246 | CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5247 | CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5248 | CLK_LOOKUP("core_clk", jpegd_clk.c, ""), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5249 | CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5250 | CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5251 | CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5252 | CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5253 | CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5254 | CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5255 | CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5256 | CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5257 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5258 | CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5259 | CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL), |
| 5260 | CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL), |
Matt Wagantall | 3f7660b | 2011-08-17 21:25:13 -0700 | [diff] [blame] | 5261 | CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5262 | CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5263 | CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL), |
Matt Wagantall | b82a513 | 2011-12-12 22:26:41 -0800 | [diff] [blame] | 5264 | CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5265 | CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 5266 | CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"), |
Kevin Chan | a085312 | 2011-11-07 19:48:44 -0800 | [diff] [blame] | 5267 | CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5268 | CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5269 | CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5270 | CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5271 | CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5272 | CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"), |
| 5273 | CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"), |
| 5274 | CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"), |
| 5275 | CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"), |
| 5276 | CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"), |
| 5277 | CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"), |
| 5278 | CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5279 | CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL), |
Kevin Chan | c8b52e8 | 2011-10-25 23:20:21 -0700 | [diff] [blame] | 5280 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"), |
| 5281 | CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5282 | CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL), |
| 5283 | CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL), |
| 5284 | CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL), |
| 5285 | CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5286 | CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5287 | CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5288 | CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5289 | CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"), |
Matt Wagantall | 9dc0163 | 2011-08-17 18:55:04 -0700 | [diff] [blame] | 5290 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5291 | CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"), |
Matt Wagantall | 5a4f1ba | 2011-08-18 18:13:03 -0700 | [diff] [blame] | 5292 | CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"), |
| 5293 | CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5294 | CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5295 | CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"), |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5296 | CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""), |
Matt Wagantall | 5d44ef2 | 2012-01-23 11:01:05 -0800 | [diff] [blame] | 5297 | CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5298 | CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5299 | CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 5300 | CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"), |
Matt Wagantall | bb90da9 | 2011-10-25 15:07:52 -0700 | [diff] [blame] | 5301 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5302 | CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5303 | CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL), |
Matt Wagantall | 3f7660b | 2011-08-17 21:25:13 -0700 | [diff] [blame] | 5304 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5305 | CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"), |
Kevin Chan | 5827c55 | 2011-10-28 18:36:32 -0700 | [diff] [blame] | 5306 | CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5307 | CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"), |
Kevin Chan | a085312 | 2011-11-07 19:48:44 -0800 | [diff] [blame] | 5308 | CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"), |
Matt Wagantall | 4972271 | 2011-08-17 18:50:53 -0700 | [diff] [blame] | 5309 | CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5310 | CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL), |
| 5311 | CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL), |
| 5312 | CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL), |
| 5313 | CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL), |
| 5314 | CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL), |
| 5315 | CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL), |
| 5316 | CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL), |
| 5317 | CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL), |
| 5318 | CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL), |
| 5319 | CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL), |
| 5320 | CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL), |
| 5321 | CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL), |
| 5322 | CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL), |
Matt Wagantall | e604d71 | 2011-10-21 15:38:18 -0700 | [diff] [blame] | 5323 | CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"), |
| 5324 | CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"), |
| 5325 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"), |
| 5326 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"), |
| 5327 | CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"), |
| 5328 | CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"), |
| 5329 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"), |
| 5330 | CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"), |
| 5331 | CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"), |
| 5332 | CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"), |
| 5333 | CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"), |
| 5334 | CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"), |
Gopikrishnaiah Anandan | 4d05ed3 | 2012-01-13 11:08:44 -0800 | [diff] [blame] | 5335 | |
| 5336 | CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"), |
| 5337 | CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"), |
| 5338 | CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"), |
| 5339 | CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"), |
| 5340 | CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"), |
| 5341 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5342 | CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL), |
Manu Gautam | 5143b25 | 2012-01-05 19:25:23 -0800 | [diff] [blame] | 5343 | CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"), |
Matt Wagantall | 37ce384 | 2011-08-17 16:00:36 -0700 | [diff] [blame] | 5344 | CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"), |
| 5345 | CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"), |
| 5346 | CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"), |
| 5347 | CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"), |
| 5348 | CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"), |
Yan He | 160633e | 2011-06-30 12:18:56 -0700 | [diff] [blame] | 5349 | CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"), |
Stephen Boyd | 1c51a49 | 2011-10-26 12:11:47 -0700 | [diff] [blame] | 5350 | CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"), |
Stephen Boyd | ef5d1c4 | 2011-12-15 20:47:14 -0800 | [diff] [blame] | 5351 | CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5352 | |
Matt Wagantall | e1a8606 | 2011-08-18 17:46:10 -0700 | [diff] [blame] | 5353 | CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), |
Matt Wagantall | 8b38f94 | 2011-08-02 18:23:18 -0700 | [diff] [blame] | 5354 | |
Matt Wagantall | c00f95d | 2012-01-05 14:22:45 -0800 | [diff] [blame] | 5355 | CLK_LOOKUP("l2_mclk", l2_m_clk, ""), |
| 5356 | CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""), |
| 5357 | CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""), |
| 5358 | CLK_LOOKUP("q6sw_clk", q6sw_clk, ""), |
| 5359 | CLK_LOOKUP("q6fw_clk", q6fw_clk, ""), |
| 5360 | CLK_LOOKUP("q6_func_clk", q6_func_clk, ""), |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5361 | }; |
| 5362 | |
| 5363 | /* |
| 5364 | * Miscellaneous clock register initializations |
| 5365 | */ |
| 5366 | |
| 5367 | /* Read, modify, then write-back a register. */ |
| 5368 | static void __init rmwreg(uint32_t val, void *reg, uint32_t mask) |
| 5369 | { |
| 5370 | uint32_t regval = readl_relaxed(reg); |
| 5371 | regval &= ~mask; |
| 5372 | regval |= val; |
| 5373 | writel_relaxed(regval, reg); |
| 5374 | } |
| 5375 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5376 | static void __init set_fsm_mode(void __iomem *mode_reg) |
| 5377 | { |
| 5378 | u32 regval = readl_relaxed(mode_reg); |
| 5379 | |
| 5380 | /*De-assert reset to FSM */ |
| 5381 | regval &= ~BIT(21); |
| 5382 | writel_relaxed(regval, mode_reg); |
| 5383 | |
| 5384 | /* Program bias count */ |
Tianyi Gou | 358c386 | 2011-10-18 17:03:41 -0700 | [diff] [blame] | 5385 | regval &= ~BM(19, 14); |
| 5386 | regval |= BVAL(19, 14, 0x1); |
| 5387 | writel_relaxed(regval, mode_reg); |
| 5388 | |
| 5389 | /* Program lock count */ |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5390 | regval &= ~BM(13, 8); |
| 5391 | regval |= BVAL(13, 8, 0x8); |
| 5392 | writel_relaxed(regval, mode_reg); |
| 5393 | |
| 5394 | /*Enable PLL FSM voting */ |
| 5395 | regval |= BIT(20); |
| 5396 | writel_relaxed(regval, mode_reg); |
| 5397 | } |
| 5398 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5399 | static void __init reg_init(void) |
| 5400 | { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5401 | void __iomem *imem_reg; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5402 | /* Deassert MM SW_RESET_ALL signal. */ |
| 5403 | writel_relaxed(0, SW_RESET_ALL_REG); |
| 5404 | |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5405 | /* |
| 5406 | * Some bits are only used on either 8960 or 8064 and are marked as |
| 5407 | * reserved bits on the other SoC. Writing to these reserved bits |
| 5408 | * should have no effect. |
| 5409 | */ |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5410 | /* |
| 5411 | * Initialize MM AHB registers: Enable the FPB clock and disable HW |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5412 | * gating on non-8960 for all clocks. Also set VFE_AHB's |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5413 | * FORCE_CORE_ON bit to prevent its memory from being collapsed when |
| 5414 | * the clock is halted. The sleep and wake-up delays are set to safe |
| 5415 | * values. |
| 5416 | */ |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5417 | if (cpu_is_msm8960()) { |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5418 | rmwreg(0x44000000, AHB_EN_REG, 0x6C000103); |
| 5419 | writel_relaxed(0x3C7097F9, AHB_EN2_REG); |
| 5420 | } else { |
| 5421 | rmwreg(0x00000003, AHB_EN_REG, 0x6C000103); |
| 5422 | writel_relaxed(0x000007F9, AHB_EN2_REG); |
| 5423 | } |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5424 | if (cpu_is_apq8064()) |
| 5425 | rmwreg(0x00000000, AHB_EN3_REG, 0x00000001); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5426 | |
| 5427 | /* Deassert all locally-owned MM AHB resets. */ |
| 5428 | rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5429 | rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5430 | |
| 5431 | /* Initialize MM AXI registers: Enable HW gating for all clocks that |
| 5432 | * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up |
| 5433 | * delays to safe values. */ |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5434 | if (cpu_is_msm8960() && |
| 5435 | SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) { |
| 5436 | rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF); |
| 5437 | rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF); |
Gopikrishnaiah Anandan | 83b6e85 | 2012-01-05 17:47:02 -0800 | [diff] [blame] | 5438 | rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF); |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5439 | } else { |
| 5440 | rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF); |
| 5441 | rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF); |
| 5442 | rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF); |
| 5443 | } |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 5444 | rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5445 | if (cpu_is_apq8064()) |
| 5446 | rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF); |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5447 | if (cpu_is_msm8960()) |
Stephen Boyd | d471e7a | 2011-11-19 01:37:39 -0800 | [diff] [blame] | 5448 | rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF); |
| 5449 | else |
| 5450 | rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF); |
| 5451 | |
| 5452 | /* Enable IMEM's clk_on signal */ |
| 5453 | imem_reg = ioremap(0x04b00040, 4); |
| 5454 | if (imem_reg) { |
| 5455 | writel_relaxed(0x3, imem_reg); |
| 5456 | iounmap(imem_reg); |
| 5457 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5458 | |
| 5459 | /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core |
| 5460 | * memories retain state even when not clocked. Also, set sleep and |
| 5461 | * wake-up delays to safe values. */ |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 5462 | rmwreg(0x00000000, CSI0_CC_REG, 0x00000410); |
| 5463 | rmwreg(0x00000000, CSI1_CC_REG, 0x00000410); |
| 5464 | rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010); |
| 5465 | rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010); |
| 5466 | rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010); |
| 5467 | rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010); |
Tarun Karra | 6fbc00a | 2011-12-13 09:23:47 -0700 | [diff] [blame] | 5468 | rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 5469 | rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010); |
| 5470 | rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010); |
| 5471 | rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010); |
| 5472 | rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010); |
| 5473 | rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 5474 | rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF); |
| 5475 | rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010); |
| 5476 | rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010); |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 5477 | rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF); |
Matt Wagantall | 53d968f | 2011-07-19 13:22:53 -0700 | [diff] [blame] | 5478 | rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010); |
Stepan Moskovchenko | 2429f15 | 2011-10-25 14:42:35 -0700 | [diff] [blame] | 5479 | if (cpu_is_msm8960() || cpu_is_msm8930()) { |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5480 | rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010); |
| 5481 | rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010); |
| 5482 | rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010); |
| 5483 | } |
| 5484 | if (cpu_is_apq8064()) { |
| 5485 | rmwreg(0x00000000, TV_CC_REG, 0x00004010); |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 5486 | rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5487 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5488 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5489 | /* |
| 5490 | * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that |
| 5491 | * core remain active during halt state of the clk. Also, set sleep |
| 5492 | * and wake-up value to max. |
| 5493 | */ |
| 5494 | rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F); |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5495 | if (cpu_is_apq8064()) { |
| 5496 | rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F); |
| 5497 | rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F); |
| 5498 | } |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5499 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5500 | /* De-assert MM AXI resets to all hardware blocks. */ |
| 5501 | writel_relaxed(0, SW_RESET_AXI_REG); |
| 5502 | |
| 5503 | /* Deassert all MM core resets. */ |
| 5504 | writel_relaxed(0, SW_RESET_CORE_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5505 | writel_relaxed(0, SW_RESET_CORE2_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5506 | |
| 5507 | /* Reset 3D core once more, with its clock enabled. This can |
| 5508 | * eventually be done as part of the GDFS footswitch driver. */ |
| 5509 | clk_set_rate(&gfx3d_clk.c, 27000000); |
| 5510 | clk_enable(&gfx3d_clk.c); |
| 5511 | writel_relaxed(BIT(12), SW_RESET_CORE_REG); |
| 5512 | mb(); |
| 5513 | udelay(5); |
| 5514 | writel_relaxed(0, SW_RESET_CORE_REG); |
| 5515 | /* Make sure reset is de-asserted before clock is disabled. */ |
| 5516 | mb(); |
| 5517 | clk_disable(&gfx3d_clk.c); |
| 5518 | |
| 5519 | /* Enable TSSC and PDM PXO sources. */ |
| 5520 | writel_relaxed(BIT(11), TSSC_CLK_CTL_REG); |
| 5521 | writel_relaxed(BIT(15), PDM_CLK_NS_REG); |
| 5522 | |
| 5523 | /* Source SLIMBus xo src from slimbus reference clock */ |
Stepan Moskovchenko | 2429f15 | 2011-10-25 14:42:35 -0700 | [diff] [blame] | 5524 | if (cpu_is_msm8960() || cpu_is_msm8930()) |
Tianyi Gou | 8c1a118 | 2011-10-10 14:47:11 -0700 | [diff] [blame] | 5525 | writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5526 | |
| 5527 | /* Source the dsi_byte_clks from the DSI PHY PLLs */ |
| 5528 | rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7); |
| 5529 | rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5530 | |
| 5531 | /* Source the sata_phy_ref_clk from PXO */ |
| 5532 | if (cpu_is_apq8064()) |
| 5533 | rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1); |
| 5534 | |
| 5535 | /* |
| 5536 | * TODO: Programming below PLLs is temporary and needs to be removed |
| 5537 | * after bootloaders program them. |
| 5538 | */ |
| 5539 | if (cpu_is_apq8064()) { |
| 5540 | u32 regval, is_pll_enabled; |
| 5541 | |
| 5542 | /* Program pxo_src_clk to source from PXO */ |
| 5543 | rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7); |
| 5544 | |
| 5545 | /* Check if PLL8 is active */ |
| 5546 | is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16); |
| 5547 | if (!is_pll_enabled) { |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 5548 | /* Ref clk = 27MHz and program pll8 to 384MHz */ |
| 5549 | writel_relaxed(0xE, BB_PLL8_L_VAL_REG); |
| 5550 | writel_relaxed(0x2, BB_PLL8_M_VAL_REG); |
| 5551 | writel_relaxed(0x9, BB_PLL8_N_VAL_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5552 | |
| 5553 | regval = readl_relaxed(BB_PLL8_CONFIG_REG); |
| 5554 | |
| 5555 | /* Enable the main output and the MN accumulator */ |
| 5556 | regval |= BIT(23) | BIT(22); |
| 5557 | |
| 5558 | /* Set pre-divider and post-divider values to 1 and 1 */ |
| 5559 | regval &= ~BIT(19); |
| 5560 | regval &= ~BM(21, 20); |
| 5561 | |
| 5562 | writel_relaxed(regval, BB_PLL8_CONFIG_REG); |
| 5563 | |
| 5564 | /* Set VCO frequency */ |
| 5565 | rmwreg(0x10000, BB_PLL8_CONFIG_REG, 0x30000); |
| 5566 | |
| 5567 | /* Enable AUX output */ |
| 5568 | regval = readl_relaxed(BB_PLL8_TEST_CTL_REG); |
| 5569 | regval |= BIT(12); |
| 5570 | writel_relaxed(regval, BB_PLL8_TEST_CTL_REG); |
| 5571 | |
| 5572 | set_fsm_mode(BB_PLL8_MODE_REG); |
Tianyi Gou | 59608a7 | 2012-01-31 22:19:30 -0800 | [diff] [blame] | 5573 | |
| 5574 | /* Enable PLL8 by voting from RPM */ |
| 5575 | regval = readl_relaxed(BB_PLL_ENA_RPM_REG); |
| 5576 | regval |= BIT(8); |
| 5577 | writel_relaxed(regval, BB_PLL_ENA_RPM_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5578 | } |
| 5579 | /* Check if PLL3 is active */ |
| 5580 | is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16); |
| 5581 | if (!is_pll_enabled) { |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 5582 | /* Ref clk = 27MHz and program pll3 to 1200MHz */ |
| 5583 | writel_relaxed(0x2C, GPLL1_L_VAL_REG); |
| 5584 | writel_relaxed(0x4, GPLL1_M_VAL_REG); |
| 5585 | writel_relaxed(0x9, GPLL1_N_VAL_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5586 | |
| 5587 | regval = readl_relaxed(GPLL1_CONFIG_REG); |
| 5588 | |
| 5589 | /* Set pre-divider and post-divider values to 1 and 1 */ |
| 5590 | regval &= ~BIT(15); |
| 5591 | regval |= BIT(16); |
| 5592 | |
| 5593 | writel_relaxed(regval, GPLL1_CONFIG_REG); |
| 5594 | |
| 5595 | /* Set VCO frequency */ |
| 5596 | rmwreg(0x180, GPLL1_CONFIG_REG, 0x180); |
| 5597 | } |
| 5598 | /* Check if PLL14 is active */ |
| 5599 | is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16); |
| 5600 | if (!is_pll_enabled) { |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 5601 | /* Ref clk = 27MHz and program pll14 to 480MHz */ |
| 5602 | writel_relaxed(0x11, BB_PLL14_L_VAL_REG); |
| 5603 | writel_relaxed(0x7, BB_PLL14_M_VAL_REG); |
| 5604 | writel_relaxed(0x9, BB_PLL14_N_VAL_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5605 | |
| 5606 | regval = readl_relaxed(BB_PLL14_CONFIG_REG); |
| 5607 | |
| 5608 | /* Enable the main output and the MN accumulator */ |
| 5609 | regval |= BIT(23) | BIT(22); |
| 5610 | |
| 5611 | /* Set pre-divider and post-divider values to 1 and 1 */ |
| 5612 | regval &= ~BIT(19); |
| 5613 | regval &= ~BM(21, 20); |
| 5614 | |
| 5615 | writel_relaxed(regval, BB_PLL14_CONFIG_REG); |
| 5616 | |
| 5617 | /* Set VCO frequency */ |
| 5618 | rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000); |
| 5619 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5620 | set_fsm_mode(BB_PLL14_MODE_REG); |
| 5621 | } |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 5622 | /* Program PLL2 to 800MHz with ref clk = 27MHz */ |
| 5623 | writel_relaxed(0x1D, MM_PLL1_L_VAL_REG); |
| 5624 | writel_relaxed(0x11, MM_PLL1_M_VAL_REG); |
| 5625 | writel_relaxed(0x1B, MM_PLL1_N_VAL_REG); |
| 5626 | |
| 5627 | regval = readl_relaxed(MM_PLL1_CONFIG_REG); |
| 5628 | |
| 5629 | /* Enable the main output and the MN accumulator */ |
| 5630 | regval |= BIT(23) | BIT(22); |
| 5631 | |
| 5632 | /* Set pre-divider and post-divider values to 1 and 1 */ |
| 5633 | regval &= ~BIT(19); |
| 5634 | regval &= ~BM(21, 20); |
| 5635 | |
| 5636 | writel_relaxed(regval, MM_PLL1_CONFIG_REG); |
| 5637 | |
| 5638 | /* Set VCO frequency */ |
| 5639 | rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000); |
| 5640 | |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 5641 | /* Program PLL15 to 975MHz with ref clk = 27MHz */ |
| 5642 | writel_relaxed(0x24, MM_PLL3_L_VAL_REG); |
| 5643 | writel_relaxed(0x1, MM_PLL3_M_VAL_REG); |
| 5644 | writel_relaxed(0x9, MM_PLL3_N_VAL_REG); |
| 5645 | |
| 5646 | regval = readl_relaxed(MM_PLL3_CONFIG_REG); |
| 5647 | |
| 5648 | /* Enable the main output and the MN accumulator */ |
| 5649 | regval |= BIT(23) | BIT(22); |
| 5650 | |
| 5651 | /* Set pre-divider and post-divider values to 1 and 1 */ |
| 5652 | regval &= ~BIT(19); |
| 5653 | regval &= ~BM(21, 20); |
| 5654 | |
| 5655 | writel_relaxed(regval, MM_PLL3_CONFIG_REG); |
| 5656 | |
| 5657 | /* Set VCO frequency */ |
| 5658 | rmwreg(0x20000, MM_PLL3_CONFIG_REG, 0x30000); |
| 5659 | |
| 5660 | /* Enable AUX output */ |
| 5661 | regval = readl_relaxed(MM_PLL3_TEST_CTL_REG); |
| 5662 | regval |= BIT(12); |
| 5663 | writel_relaxed(regval, MM_PLL3_TEST_CTL_REG); |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 5664 | |
| 5665 | /* Check if PLL4 is active */ |
| 5666 | is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16); |
| 5667 | if (!is_pll_enabled) { |
Tianyi Gou | df71f2e | 2011-10-24 22:25:04 -0700 | [diff] [blame] | 5668 | /* Ref clk = 27MHz and program pll4 to 393.2160MHz */ |
| 5669 | writel_relaxed(0xE, LCC_PLL0_L_VAL_REG); |
| 5670 | writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG); |
| 5671 | writel_relaxed(0x465, LCC_PLL0_N_VAL_REG); |
Tianyi Gou | c29c324 | 2011-10-12 21:02:15 -0700 | [diff] [blame] | 5672 | |
| 5673 | regval = readl_relaxed(LCC_PLL0_CONFIG_REG); |
| 5674 | |
| 5675 | /* Enable the main output and the MN accumulator */ |
| 5676 | regval |= BIT(23) | BIT(22); |
| 5677 | |
| 5678 | /* Set pre-divider and post-divider values to 1 and 1 */ |
| 5679 | regval &= ~BIT(19); |
| 5680 | regval &= ~BM(21, 20); |
| 5681 | |
| 5682 | /* Set VCO frequency */ |
| 5683 | regval &= ~BM(17, 16); |
| 5684 | writel_relaxed(regval, LCC_PLL0_CONFIG_REG); |
| 5685 | |
| 5686 | set_fsm_mode(LCC_PLL0_MODE_REG); |
| 5687 | } |
| 5688 | |
| 5689 | /* Enable PLL4 source on the LPASS Primary PLL Mux */ |
| 5690 | writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5691 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5692 | } |
| 5693 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5694 | /* Local clock driver initialization. */ |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 5695 | static void __init msm8960_clock_init(void) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5696 | { |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5697 | |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 5698 | if (cpu_is_msm8960()) { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 5699 | rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3; |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 5700 | } else if (cpu_is_apq8064()) { |
| 5701 | rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8921_S3; |
| 5702 | rpm_vreg_id_vdd_sr2_pll = RPM_VREG_ID_PM8921_LVS7; |
| 5703 | } else if (cpu_is_msm8930() || cpu_is_msm8627()) { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 5704 | rpm_vreg_id_vdd_dig = RPM_VREG_ID_PM8038_S1; |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 5705 | rpm_vreg_id_vdd_sr2_pll = RPM_VREG_ID_PM8038_L23; |
| 5706 | } else { |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 5707 | BUG(); |
Tianyi Gou | e1faaf2 | 2012-01-24 16:07:19 -0800 | [diff] [blame] | 5708 | } |
Tianyi Gou | bf3d0b1 | 2012-01-23 14:37:28 -0800 | [diff] [blame] | 5709 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5710 | xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960"); |
| 5711 | if (IS_ERR(xo_pxo)) { |
| 5712 | pr_err("%s: msm_xo_get(PXO) failed.\n", __func__); |
| 5713 | BUG(); |
| 5714 | } |
Matt Wagantall | ed90b00 | 2011-12-12 21:22:43 -0800 | [diff] [blame] | 5715 | xo_cxo = msm_xo_get(MSM_XO_CXO, "clock-8960"); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5716 | if (IS_ERR(xo_cxo)) { |
| 5717 | pr_err("%s: msm_xo_get(CXO) failed.\n", __func__); |
| 5718 | BUG(); |
| 5719 | } |
| 5720 | |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5721 | /* |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 5722 | * Change the freq tables for and voltage requirements for |
| 5723 | * clocks which differ between 8960 and 8064. |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5724 | */ |
| 5725 | if (cpu_is_apq8064()) { |
| 5726 | gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 5727 | |
| 5728 | memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064, |
| 5729 | sizeof(gfx3d_clk.c.fmax)); |
| 5730 | memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064, |
| 5731 | sizeof(ijpeg_clk.c.fmax)); |
| 5732 | memcpy(mdp_clk.c.fmax, fmax_mdp_8064, |
| 5733 | sizeof(ijpeg_clk.c.fmax)); |
| 5734 | memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064, |
| 5735 | sizeof(tv_src_clk.c.fmax)); |
| 5736 | memcpy(vfe_clk.c.fmax, fmax_vfe_8064, |
| 5737 | sizeof(vfe_clk.c.fmax)); |
| 5738 | |
Tianyi Gou | 621f874 | 2011-09-01 21:45:01 -0700 | [diff] [blame] | 5739 | gmem_axi_clk.c.depends = &gfx3d_axi_clk.c; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5740 | } |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 5741 | |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 5742 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5743 | |
Vikram Mulukutla | 489e39e | 2011-08-31 18:04:05 -0700 | [diff] [blame] | 5744 | clk_ops_pll.enable = sr_pll_clk_enable; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5745 | |
| 5746 | /* Initialize clock registers. */ |
| 5747 | reg_init(); |
| 5748 | |
| 5749 | /* Initialize rates for clocks that only support one. */ |
| 5750 | clk_set_rate(&pdm_clk.c, 27000000); |
| 5751 | clk_set_rate(&prng_clk.c, 64000000); |
| 5752 | clk_set_rate(&mdp_vsync_clk.c, 27000000); |
| 5753 | clk_set_rate(&tsif_ref_clk.c, 105000); |
| 5754 | clk_set_rate(&tssc_clk.c, 27000000); |
| 5755 | clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000); |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5756 | if (cpu_is_apq8064()) { |
| 5757 | clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000); |
| 5758 | clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000); |
| 5759 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5760 | clk_set_rate(&usb_fs1_src_clk.c, 60000000); |
Stepan Moskovchenko | 2429f15 | 2011-10-25 14:42:35 -0700 | [diff] [blame] | 5761 | if (cpu_is_msm8960() || cpu_is_msm8930()) |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5762 | clk_set_rate(&usb_fs2_src_clk.c, 60000000); |
Stephen Boyd | 94625ef | 2011-07-12 17:06:01 -0700 | [diff] [blame] | 5763 | clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000); |
| 5764 | clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000); |
| 5765 | clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000); |
Stephen Boyd | 092fd18 | 2011-10-21 15:56:30 -0700 | [diff] [blame] | 5766 | /* |
| 5767 | * Set the CSI rates to a safe default to avoid warnings when |
| 5768 | * switching csi pix and rdi clocks. |
| 5769 | */ |
| 5770 | clk_set_rate(&csi0_src_clk.c, 27000000); |
| 5771 | clk_set_rate(&csi1_src_clk.c, 27000000); |
| 5772 | clk_set_rate(&csi2_src_clk.c, 27000000); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5773 | |
| 5774 | /* |
Stephen Boyd | 60496bb | 2011-10-17 13:51:37 -0700 | [diff] [blame] | 5775 | * The halt status bits for these clocks may be incorrect at boot. |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5776 | * Toggle these clocks on and off to refresh them. |
| 5777 | */ |
Matt Wagantall | 0625ea0 | 2011-07-13 18:51:56 -0700 | [diff] [blame] | 5778 | rcg_clk_enable(&pdm_clk.c); |
| 5779 | rcg_clk_disable(&pdm_clk.c); |
| 5780 | rcg_clk_enable(&tssc_clk.c); |
| 5781 | rcg_clk_disable(&tssc_clk.c); |
Tianyi Gou | 3022dfd | 2012-01-25 15:50:05 -0800 | [diff] [blame] | 5782 | clk_enable(&usb_hsic_hsic_clk.c); |
| 5783 | clk_disable(&usb_hsic_hsic_clk.c); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5784 | } |
| 5785 | |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 5786 | static int __init msm8960_clock_late_init(void) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5787 | { |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 5788 | int rc; |
| 5789 | struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk"); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 5790 | struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk"); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 5791 | |
| 5792 | /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */ |
| 5793 | if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n", |
| 5794 | PTR_ERR(mmfpb_a_clk))) |
| 5795 | return PTR_ERR(mmfpb_a_clk); |
Matt Wagantall | de555f56 | 2011-11-08 14:18:07 -0800 | [diff] [blame] | 5796 | rc = clk_set_rate(mmfpb_a_clk, 76800000); |
Stephen Boyd | a3787f3 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 5797 | if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc)) |
| 5798 | return rc; |
| 5799 | rc = clk_enable(mmfpb_a_clk); |
| 5800 | if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc)) |
| 5801 | return rc; |
| 5802 | |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 5803 | /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */ |
| 5804 | if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n", |
| 5805 | PTR_ERR(cfpb_a_clk))) |
| 5806 | return PTR_ERR(cfpb_a_clk); |
Matt Wagantall | de555f56 | 2011-11-08 14:18:07 -0800 | [diff] [blame] | 5807 | rc = clk_set_rate(cfpb_a_clk, 64000000); |
Stephen Boyd | 8543613 | 2011-09-16 18:55:13 -0700 | [diff] [blame] | 5808 | if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc)) |
| 5809 | return rc; |
| 5810 | rc = clk_enable(cfpb_a_clk); |
| 5811 | if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc)) |
| 5812 | return rc; |
Matt Wagantall | e18bbc8 | 2011-10-06 10:07:28 -0700 | [diff] [blame] | 5813 | |
| 5814 | return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 5815 | } |
Stephen Boyd | bb600ae | 2011-08-02 20:11:40 -0700 | [diff] [blame] | 5816 | |
| 5817 | struct clock_init_data msm8960_clock_init_data __initdata = { |
| 5818 | .table = msm_clocks_8960, |
| 5819 | .size = ARRAY_SIZE(msm_clocks_8960), |
| 5820 | .init = msm8960_clock_init, |
| 5821 | .late_init = msm8960_clock_late_init, |
| 5822 | }; |
Tianyi Gou | 41515e2 | 2011-09-01 19:37:43 -0700 | [diff] [blame] | 5823 | |
| 5824 | struct clock_init_data apq8064_clock_init_data __initdata = { |
| 5825 | .table = msm_clocks_8064, |
| 5826 | .size = ARRAY_SIZE(msm_clocks_8064), |
| 5827 | .init = msm8960_clock_init, |
| 5828 | .late_init = msm8960_clock_late_init, |
| 5829 | }; |