Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge |
| 3 | * |
| 4 | * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file COPYING in the main directory of this archive for |
| 8 | * more details. |
| 9 | * |
| 10 | * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/) |
| 11 | * which is based on the code of neofb. |
| 12 | */ |
| 13 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/string.h> |
| 18 | #include <linux/mm.h> |
| 19 | #include <linux/tty.h> |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/fb.h> |
| 22 | #include <linux/svga.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/pci.h> |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 25 | #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 26 | #include <video/vga.h> |
| 27 | |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 28 | #include <linux/i2c.h> |
| 29 | #include <linux/i2c-algo-bit.h> |
| 30 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 31 | #ifdef CONFIG_MTRR |
| 32 | #include <asm/mtrr.h> |
| 33 | #endif |
| 34 | |
| 35 | struct s3fb_info { |
| 36 | int chip, rev, mclk_freq; |
| 37 | int mtrr_reg; |
| 38 | struct vgastate state; |
| 39 | struct mutex open_lock; |
| 40 | unsigned int ref_count; |
| 41 | u32 pseudo_palette[16]; |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 42 | #ifdef CONFIG_FB_S3_DDC |
| 43 | u8 __iomem *mmio; |
| 44 | bool ddc_registered; |
| 45 | struct i2c_adapter ddc_adapter; |
| 46 | struct i2c_algo_bit_data ddc_algo; |
| 47 | #endif |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | |
| 51 | /* ------------------------------------------------------------------------- */ |
| 52 | |
| 53 | static const struct svga_fb_format s3fb_formats[] = { |
| 54 | { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, |
| 55 | FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
Michal Januszewski | c26d7b2 | 2009-04-13 14:39:49 -0700 | [diff] [blame] | 56 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 57 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
Michal Januszewski | c26d7b2 | 2009-04-13 14:39:49 -0700 | [diff] [blame] | 58 | { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 59 | FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, |
Michal Januszewski | c26d7b2 | 2009-04-13 14:39:49 -0700 | [diff] [blame] | 60 | { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 61 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8}, |
| 62 | {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, |
| 63 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, |
| 64 | {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, |
| 65 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4}, |
| 66 | {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
| 67 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, |
| 68 | {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, |
| 69 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2}, |
| 70 | SVGA_FORMAT_END |
| 71 | }; |
| 72 | |
| 73 | |
| 74 | static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3, |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 75 | 35000, 240000, 14318}; |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 76 | static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4, |
| 77 | 230000, 460000, 14318}; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 78 | |
| 79 | static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512}; |
| 80 | |
| 81 | static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+", |
| 82 | "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX", |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 83 | "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge", |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 84 | "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 85 | "S3 Virge/GX2", "S3 Virge/GX2+", "", |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 86 | "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", |
| 87 | "S3 Trio3D"}; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 88 | |
| 89 | #define CHIP_UNKNOWN 0x00 |
| 90 | #define CHIP_732_TRIO32 0x01 |
| 91 | #define CHIP_764_TRIO64 0x02 |
| 92 | #define CHIP_765_TRIO64VP 0x03 |
| 93 | #define CHIP_767_TRIO64UVP 0x04 |
| 94 | #define CHIP_775_TRIO64V2_DX 0x05 |
| 95 | #define CHIP_785_TRIO64V2_GX 0x06 |
| 96 | #define CHIP_551_PLATO_PX 0x07 |
| 97 | #define CHIP_M65_AURORA64VP 0x08 |
| 98 | #define CHIP_325_VIRGE 0x09 |
| 99 | #define CHIP_988_VIRGE_VX 0x0A |
| 100 | #define CHIP_375_VIRGE_DX 0x0B |
| 101 | #define CHIP_385_VIRGE_GX 0x0C |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 102 | #define CHIP_357_VIRGE_GX2 0x0D |
| 103 | #define CHIP_359_VIRGE_GX2P 0x0E |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 104 | #define CHIP_360_TRIO3D_1X 0x10 |
| 105 | #define CHIP_362_TRIO3D_2X 0x11 |
| 106 | #define CHIP_368_TRIO3D_2X 0x12 |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 107 | #define CHIP_365_TRIO3D 0x13 |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 108 | |
| 109 | #define CHIP_XXX_TRIO 0x80 |
| 110 | #define CHIP_XXX_TRIO64V2_DXGX 0x81 |
| 111 | #define CHIP_XXX_VIRGE_DXGX 0x82 |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 112 | #define CHIP_36X_TRIO3D_1X_2X 0x83 |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 113 | |
| 114 | #define CHIP_UNDECIDED_FLAG 0x80 |
| 115 | #define CHIP_MASK 0xFF |
| 116 | |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 117 | #define MMIO_OFFSET 0x1000000 |
| 118 | #define MMIO_SIZE 0x10000 |
| 119 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 120 | /* CRT timing register sets */ |
| 121 | |
| 122 | static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END}; |
| 123 | static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END}; |
| 124 | static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END}; |
| 125 | static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END}; |
| 126 | static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END}; |
| 127 | static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; |
| 128 | |
| 129 | static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END}; |
| 130 | static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END}; |
| 131 | static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END}; |
| 132 | static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; |
| 133 | static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END}; |
| 134 | static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; |
| 135 | |
| 136 | static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END}; |
Ondrej Zary | 7fe029d | 2011-03-01 19:18:43 +0000 | [diff] [blame] | 137 | static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END}; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 138 | static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */ |
| 139 | |
Ondrej Zary | cb11c04 | 2011-03-01 19:18:35 +0000 | [diff] [blame] | 140 | static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END}; |
| 141 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 142 | static const struct svga_timing_regs s3_timing_regs = { |
| 143 | s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs, |
| 144 | s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs, |
| 145 | s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs, |
| 146 | s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs, |
| 147 | }; |
| 148 | |
| 149 | |
| 150 | /* ------------------------------------------------------------------------- */ |
| 151 | |
| 152 | /* Module parameters */ |
| 153 | |
| 154 | |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 155 | static char *mode_option __devinitdata; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 156 | |
| 157 | #ifdef CONFIG_MTRR |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 158 | static int mtrr __devinitdata = 1; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 159 | #endif |
| 160 | |
| 161 | static int fasttext = 1; |
| 162 | |
| 163 | |
| 164 | MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>"); |
| 165 | MODULE_LICENSE("GPL"); |
| 166 | MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge"); |
| 167 | |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 168 | module_param(mode_option, charp, 0444); |
| 169 | MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); |
| 170 | module_param_named(mode, mode_option, charp, 0444); |
| 171 | MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 172 | |
| 173 | #ifdef CONFIG_MTRR |
| 174 | module_param(mtrr, int, 0444); |
| 175 | MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); |
| 176 | #endif |
| 177 | |
| 178 | module_param(fasttext, int, 0644); |
| 179 | MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)"); |
| 180 | |
| 181 | |
| 182 | /* ------------------------------------------------------------------------- */ |
| 183 | |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 184 | #ifdef CONFIG_FB_S3_DDC |
| 185 | |
| 186 | #define DDC_REG 0xaa /* Trio 3D/1X/2X */ |
| 187 | #define DDC_MMIO_REG 0xff20 /* all other chips */ |
| 188 | #define DDC_SCL_OUT (1 << 0) |
| 189 | #define DDC_SDA_OUT (1 << 1) |
| 190 | #define DDC_SCL_IN (1 << 2) |
| 191 | #define DDC_SDA_IN (1 << 3) |
| 192 | #define DDC_DRIVE_EN (1 << 4) |
| 193 | |
| 194 | static bool s3fb_ddc_needs_mmio(int chip) |
| 195 | { |
| 196 | return !(chip == CHIP_360_TRIO3D_1X || |
| 197 | chip == CHIP_362_TRIO3D_2X || |
| 198 | chip == CHIP_368_TRIO3D_2X); |
| 199 | } |
| 200 | |
| 201 | static u8 s3fb_ddc_read(struct s3fb_info *par) |
| 202 | { |
| 203 | if (s3fb_ddc_needs_mmio(par->chip)) |
| 204 | return readb(par->mmio + DDC_MMIO_REG); |
| 205 | else |
| 206 | return vga_rcrt(par->state.vgabase, DDC_REG); |
| 207 | } |
| 208 | |
| 209 | static void s3fb_ddc_write(struct s3fb_info *par, u8 val) |
| 210 | { |
| 211 | if (s3fb_ddc_needs_mmio(par->chip)) |
| 212 | writeb(val, par->mmio + DDC_MMIO_REG); |
| 213 | else |
| 214 | vga_wcrt(par->state.vgabase, DDC_REG, val); |
| 215 | } |
| 216 | |
| 217 | static void s3fb_ddc_setscl(void *data, int val) |
| 218 | { |
| 219 | struct s3fb_info *par = data; |
| 220 | unsigned char reg; |
| 221 | |
| 222 | reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; |
| 223 | if (val) |
| 224 | reg |= DDC_SCL_OUT; |
| 225 | else |
| 226 | reg &= ~DDC_SCL_OUT; |
| 227 | s3fb_ddc_write(par, reg); |
| 228 | } |
| 229 | |
| 230 | static void s3fb_ddc_setsda(void *data, int val) |
| 231 | { |
| 232 | struct s3fb_info *par = data; |
| 233 | unsigned char reg; |
| 234 | |
| 235 | reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; |
| 236 | if (val) |
| 237 | reg |= DDC_SDA_OUT; |
| 238 | else |
| 239 | reg &= ~DDC_SDA_OUT; |
| 240 | s3fb_ddc_write(par, reg); |
| 241 | } |
| 242 | |
| 243 | static int s3fb_ddc_getscl(void *data) |
| 244 | { |
| 245 | struct s3fb_info *par = data; |
| 246 | |
| 247 | return !!(s3fb_ddc_read(par) & DDC_SCL_IN); |
| 248 | } |
| 249 | |
| 250 | static int s3fb_ddc_getsda(void *data) |
| 251 | { |
| 252 | struct s3fb_info *par = data; |
| 253 | |
| 254 | return !!(s3fb_ddc_read(par) & DDC_SDA_IN); |
| 255 | } |
| 256 | |
| 257 | static int __devinit s3fb_setup_ddc_bus(struct fb_info *info) |
| 258 | { |
| 259 | struct s3fb_info *par = info->par; |
| 260 | |
| 261 | strlcpy(par->ddc_adapter.name, info->fix.id, |
| 262 | sizeof(par->ddc_adapter.name)); |
| 263 | par->ddc_adapter.owner = THIS_MODULE; |
| 264 | par->ddc_adapter.class = I2C_CLASS_DDC; |
| 265 | par->ddc_adapter.algo_data = &par->ddc_algo; |
| 266 | par->ddc_adapter.dev.parent = info->device; |
| 267 | par->ddc_algo.setsda = s3fb_ddc_setsda; |
| 268 | par->ddc_algo.setscl = s3fb_ddc_setscl; |
| 269 | par->ddc_algo.getsda = s3fb_ddc_getsda; |
| 270 | par->ddc_algo.getscl = s3fb_ddc_getscl; |
| 271 | par->ddc_algo.udelay = 10; |
| 272 | par->ddc_algo.timeout = 20; |
| 273 | par->ddc_algo.data = par; |
| 274 | |
| 275 | i2c_set_adapdata(&par->ddc_adapter, par); |
| 276 | |
| 277 | /* |
| 278 | * some Virge cards have external MUX to switch chip I2C bus between |
| 279 | * DDC and extension pins - switch it do DDC |
| 280 | */ |
| 281 | /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ |
| 282 | if (par->chip == CHIP_357_VIRGE_GX2 || |
| 283 | par->chip == CHIP_359_VIRGE_GX2P) |
| 284 | svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); |
| 285 | else |
| 286 | svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); |
| 287 | /* some Virge need this or the DDC is ignored */ |
| 288 | svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); |
| 289 | |
| 290 | return i2c_bit_add_bus(&par->ddc_adapter); |
| 291 | } |
| 292 | #endif /* CONFIG_FB_S3_DDC */ |
| 293 | |
| 294 | |
| 295 | /* ------------------------------------------------------------------------- */ |
| 296 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 297 | /* Set font in S3 fast text mode */ |
| 298 | |
| 299 | static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) |
| 300 | { |
| 301 | const u8 *font = map->data; |
Antonino A. Daplas | 75814d8 | 2007-05-08 00:38:49 -0700 | [diff] [blame] | 302 | u8 __iomem *fb = (u8 __iomem *) info->screen_base; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 303 | int i, c; |
| 304 | |
| 305 | if ((map->width != 8) || (map->height != 16) || |
| 306 | (map->depth != 1) || (map->length != 256)) { |
| 307 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", |
| 308 | info->node, map->width, map->height, map->depth, map->length); |
| 309 | return; |
| 310 | } |
| 311 | |
| 312 | fb += 2; |
| 313 | for (i = 0; i < map->height; i++) { |
| 314 | for (c = 0; c < map->length; c++) { |
Antonino A. Daplas | 75814d8 | 2007-05-08 00:38:49 -0700 | [diff] [blame] | 315 | fb_writeb(font[c * map->height + i], fb + c * 4); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 316 | } |
| 317 | fb += 1024; |
| 318 | } |
| 319 | } |
| 320 | |
David Miller | 55db092 | 2011-01-11 23:52:11 +0000 | [diff] [blame] | 321 | static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) |
| 322 | { |
| 323 | struct s3fb_info *par = info->par; |
| 324 | |
| 325 | svga_tilecursor(par->state.vgabase, info, cursor); |
| 326 | } |
| 327 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 328 | static struct fb_tile_ops s3fb_tile_ops = { |
| 329 | .fb_settile = svga_settile, |
| 330 | .fb_tilecopy = svga_tilecopy, |
| 331 | .fb_tilefill = svga_tilefill, |
| 332 | .fb_tileblit = svga_tileblit, |
David Miller | 55db092 | 2011-01-11 23:52:11 +0000 | [diff] [blame] | 333 | .fb_tilecursor = s3fb_tilecursor, |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 334 | .fb_get_tilemax = svga_get_tilemax, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 335 | }; |
| 336 | |
| 337 | static struct fb_tile_ops s3fb_fast_tile_ops = { |
| 338 | .fb_settile = s3fb_settile_fast, |
| 339 | .fb_tilecopy = svga_tilecopy, |
| 340 | .fb_tilefill = svga_tilefill, |
| 341 | .fb_tileblit = svga_tileblit, |
David Miller | 55db092 | 2011-01-11 23:52:11 +0000 | [diff] [blame] | 342 | .fb_tilecursor = s3fb_tilecursor, |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 343 | .fb_get_tilemax = svga_get_tilemax, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 344 | }; |
| 345 | |
| 346 | |
| 347 | /* ------------------------------------------------------------------------- */ |
| 348 | |
| 349 | /* image data is MSB-first, fb structure is MSB-first too */ |
| 350 | static inline u32 expand_color(u32 c) |
| 351 | { |
| 352 | return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; |
| 353 | } |
| 354 | |
| 355 | /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ |
| 356 | static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) |
| 357 | { |
| 358 | u32 fg = expand_color(image->fg_color); |
| 359 | u32 bg = expand_color(image->bg_color); |
| 360 | const u8 *src1, *src; |
| 361 | u8 __iomem *dst1; |
| 362 | u32 __iomem *dst; |
| 363 | u32 val; |
| 364 | int x, y; |
| 365 | |
| 366 | src1 = image->data; |
| 367 | dst1 = info->screen_base + (image->dy * info->fix.line_length) |
| 368 | + ((image->dx / 8) * 4); |
| 369 | |
| 370 | for (y = 0; y < image->height; y++) { |
| 371 | src = src1; |
| 372 | dst = (u32 __iomem *) dst1; |
| 373 | for (x = 0; x < image->width; x += 8) { |
| 374 | val = *(src++) * 0x01010101; |
| 375 | val = (val & fg) | (~val & bg); |
| 376 | fb_writel(val, dst++); |
| 377 | } |
| 378 | src1 += image->width / 8; |
| 379 | dst1 += info->fix.line_length; |
| 380 | } |
| 381 | |
| 382 | } |
| 383 | |
| 384 | /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ |
| 385 | static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
| 386 | { |
| 387 | u32 fg = expand_color(rect->color); |
| 388 | u8 __iomem *dst1; |
| 389 | u32 __iomem *dst; |
| 390 | int x, y; |
| 391 | |
| 392 | dst1 = info->screen_base + (rect->dy * info->fix.line_length) |
| 393 | + ((rect->dx / 8) * 4); |
| 394 | |
| 395 | for (y = 0; y < rect->height; y++) { |
| 396 | dst = (u32 __iomem *) dst1; |
| 397 | for (x = 0; x < rect->width; x += 8) { |
| 398 | fb_writel(fg, dst++); |
| 399 | } |
| 400 | dst1 += info->fix.line_length; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | |
| 405 | /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ |
| 406 | static inline u32 expand_pixel(u32 c) |
| 407 | { |
| 408 | return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | |
| 409 | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; |
| 410 | } |
| 411 | |
| 412 | /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ |
| 413 | static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) |
| 414 | { |
| 415 | u32 fg = image->fg_color * 0x11111111; |
| 416 | u32 bg = image->bg_color * 0x11111111; |
| 417 | const u8 *src1, *src; |
| 418 | u8 __iomem *dst1; |
| 419 | u32 __iomem *dst; |
| 420 | u32 val; |
| 421 | int x, y; |
| 422 | |
| 423 | src1 = image->data; |
| 424 | dst1 = info->screen_base + (image->dy * info->fix.line_length) |
| 425 | + ((image->dx / 8) * 4); |
| 426 | |
| 427 | for (y = 0; y < image->height; y++) { |
| 428 | src = src1; |
| 429 | dst = (u32 __iomem *) dst1; |
| 430 | for (x = 0; x < image->width; x += 8) { |
| 431 | val = expand_pixel(*(src++)); |
| 432 | val = (val & fg) | (~val & bg); |
| 433 | fb_writel(val, dst++); |
| 434 | } |
| 435 | src1 += image->width / 8; |
| 436 | dst1 += info->fix.line_length; |
| 437 | } |
| 438 | } |
| 439 | |
| 440 | static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image) |
| 441 | { |
| 442 | if ((info->var.bits_per_pixel == 4) && (image->depth == 1) |
| 443 | && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { |
| 444 | if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) |
| 445 | s3fb_iplan_imageblit(info, image); |
| 446 | else |
| 447 | s3fb_cfb4_imageblit(info, image); |
| 448 | } else |
| 449 | cfb_imageblit(info, image); |
| 450 | } |
| 451 | |
| 452 | static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
| 453 | { |
| 454 | if ((info->var.bits_per_pixel == 4) |
| 455 | && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) |
| 456 | && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) |
| 457 | s3fb_iplan_fillrect(info, rect); |
| 458 | else |
| 459 | cfb_fillrect(info, rect); |
| 460 | } |
| 461 | |
| 462 | |
| 463 | |
| 464 | /* ------------------------------------------------------------------------- */ |
| 465 | |
| 466 | |
| 467 | static void s3_set_pixclock(struct fb_info *info, u32 pixclock) |
| 468 | { |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 469 | struct s3fb_info *par = info->par; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 470 | u16 m, n, r; |
| 471 | u8 regval; |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 472 | int rv; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 473 | |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 474 | rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, |
| 475 | 1000000000 / pixclock, &m, &n, &r, info->node); |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 476 | if (rv < 0) { |
| 477 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); |
| 478 | return; |
| 479 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 480 | |
| 481 | /* Set VGA misc register */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 482 | regval = vga_r(par->state.vgabase, VGA_MIS_R); |
| 483 | vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 484 | |
| 485 | /* Set S3 clock registers */ |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 486 | if (par->chip == CHIP_357_VIRGE_GX2 || |
| 487 | par->chip == CHIP_359_VIRGE_GX2P || |
| 488 | par->chip == CHIP_360_TRIO3D_1X || |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 489 | par->chip == CHIP_362_TRIO3D_2X || |
| 490 | par->chip == CHIP_368_TRIO3D_2X) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 491 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ |
| 492 | vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 493 | } else |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 494 | vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); |
| 495 | vga_wseq(par->state.vgabase, 0x13, m - 2); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 496 | |
| 497 | udelay(1000); |
| 498 | |
| 499 | /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 500 | regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ |
| 501 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); |
| 502 | vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); |
| 503 | vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | |
| 507 | /* Open framebuffer */ |
| 508 | |
| 509 | static int s3fb_open(struct fb_info *info, int user) |
| 510 | { |
| 511 | struct s3fb_info *par = info->par; |
| 512 | |
| 513 | mutex_lock(&(par->open_lock)); |
| 514 | if (par->ref_count == 0) { |
David Miller | 3ff259f | 2011-01-11 23:53:53 +0000 | [diff] [blame] | 515 | void __iomem *vgabase = par->state.vgabase; |
| 516 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 517 | memset(&(par->state), 0, sizeof(struct vgastate)); |
David Miller | 3ff259f | 2011-01-11 23:53:53 +0000 | [diff] [blame] | 518 | par->state.vgabase = vgabase; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 519 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; |
| 520 | par->state.num_crtc = 0x70; |
| 521 | par->state.num_seq = 0x20; |
| 522 | save_vga(&(par->state)); |
| 523 | } |
| 524 | |
| 525 | par->ref_count++; |
| 526 | mutex_unlock(&(par->open_lock)); |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | /* Close framebuffer */ |
| 532 | |
| 533 | static int s3fb_release(struct fb_info *info, int user) |
| 534 | { |
| 535 | struct s3fb_info *par = info->par; |
| 536 | |
| 537 | mutex_lock(&(par->open_lock)); |
| 538 | if (par->ref_count == 0) { |
| 539 | mutex_unlock(&(par->open_lock)); |
| 540 | return -EINVAL; |
| 541 | } |
| 542 | |
| 543 | if (par->ref_count == 1) |
| 544 | restore_vga(&(par->state)); |
| 545 | |
| 546 | par->ref_count--; |
| 547 | mutex_unlock(&(par->open_lock)); |
| 548 | |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | /* Validate passed in var */ |
| 553 | |
| 554 | static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
| 555 | { |
| 556 | struct s3fb_info *par = info->par; |
| 557 | int rv, mem, step; |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 558 | u16 m, n, r; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 559 | |
| 560 | /* Find appropriate format */ |
| 561 | rv = svga_match_format (s3fb_formats, var, NULL); |
Ondrej Zajicek | d4b766a | 2007-10-16 01:29:52 -0700 | [diff] [blame] | 562 | |
| 563 | /* 32bpp mode is not supported on VIRGE VX, |
| 564 | 24bpp is not supported on others */ |
| 565 | if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) |
| 566 | rv = -EINVAL; |
| 567 | |
| 568 | if (rv < 0) { |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 569 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); |
| 570 | return rv; |
| 571 | } |
| 572 | |
| 573 | /* Do not allow to have real resoulution larger than virtual */ |
| 574 | if (var->xres > var->xres_virtual) |
| 575 | var->xres_virtual = var->xres; |
| 576 | |
| 577 | if (var->yres > var->yres_virtual) |
| 578 | var->yres_virtual = var->yres; |
| 579 | |
| 580 | /* Round up xres_virtual to have proper alignment of lines */ |
| 581 | step = s3fb_formats[rv].xresstep - 1; |
| 582 | var->xres_virtual = (var->xres_virtual+step) & ~step; |
| 583 | |
| 584 | /* Check whether have enough memory */ |
| 585 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 586 | if (mem > info->screen_size) { |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 587 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", |
| 588 | info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); |
| 589 | return -EINVAL; |
| 590 | } |
| 591 | |
| 592 | rv = svga_check_timings (&s3_timing_regs, var, info->node); |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 593 | if (rv < 0) { |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 594 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); |
| 595 | return rv; |
| 596 | } |
| 597 | |
Krzysztof Helt | c3ca34f | 2007-10-16 01:29:54 -0700 | [diff] [blame] | 598 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, |
| 599 | info->node); |
| 600 | if (rv < 0) { |
| 601 | printk(KERN_ERR "fb%d: invalid pixclock value requested\n", |
| 602 | info->node); |
| 603 | return rv; |
| 604 | } |
| 605 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 606 | return 0; |
| 607 | } |
| 608 | |
| 609 | /* Set video mode from par */ |
| 610 | |
| 611 | static int s3fb_set_par(struct fb_info *info) |
| 612 | { |
| 613 | struct s3fb_info *par = info->par; |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 614 | u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 615 | u32 bpp = info->var.bits_per_pixel; |
Ondrej Zary | cb11c04 | 2011-03-01 19:18:35 +0000 | [diff] [blame] | 616 | u32 htotal, hsstart; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 617 | |
| 618 | if (bpp != 0) { |
| 619 | info->fix.ypanstep = 1; |
| 620 | info->fix.line_length = (info->var.xres_virtual * bpp) / 8; |
| 621 | |
| 622 | info->flags &= ~FBINFO_MISC_TILEBLITTING; |
| 623 | info->tileops = NULL; |
| 624 | |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 625 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ |
| 626 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); |
Antonino A. Daplas | 8db5166 | 2007-05-08 00:39:14 -0700 | [diff] [blame] | 627 | info->pixmap.blit_y = ~(u32)0; |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 628 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 629 | offset_value = (info->var.xres_virtual * bpp) / 64; |
| 630 | screen_size = info->var.yres_virtual * info->fix.line_length; |
| 631 | } else { |
| 632 | info->fix.ypanstep = 16; |
| 633 | info->fix.line_length = 0; |
| 634 | |
| 635 | info->flags |= FBINFO_MISC_TILEBLITTING; |
| 636 | info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; |
Ondrej Zajicek | 34ed25f | 2007-05-08 00:40:00 -0700 | [diff] [blame] | 637 | |
Antonino A. Daplas | 8db5166 | 2007-05-08 00:39:14 -0700 | [diff] [blame] | 638 | /* supports 8x16 tiles only */ |
| 639 | info->pixmap.blit_x = 1 << (8 - 1); |
| 640 | info->pixmap.blit_y = 1 << (16 - 1); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 641 | |
| 642 | offset_value = info->var.xres_virtual / 16; |
| 643 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; |
| 644 | } |
| 645 | |
| 646 | info->var.xoffset = 0; |
| 647 | info->var.yoffset = 0; |
| 648 | info->var.activate = FB_ACTIVATE_NOW; |
| 649 | |
| 650 | /* Unlock registers */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 651 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
| 652 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); |
| 653 | vga_wseq(par->state.vgabase, 0x08, 0x06); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 654 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 655 | |
| 656 | /* Blank screen and turn off sync */ |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 657 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 658 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 659 | |
| 660 | /* Set default values */ |
David Miller | e2fade2 | 2011-01-11 23:50:04 +0000 | [diff] [blame] | 661 | svga_set_default_gfx_regs(par->state.vgabase); |
David Miller | f51a14d | 2011-01-11 23:50:36 +0000 | [diff] [blame] | 662 | svga_set_default_atc_regs(par->state.vgabase); |
David Miller | a4ade83 | 2011-01-11 23:50:54 +0000 | [diff] [blame] | 663 | svga_set_default_seq_regs(par->state.vgabase); |
David Miller | 1d28fca | 2011-01-11 23:51:41 +0000 | [diff] [blame] | 664 | svga_set_default_crt_regs(par->state.vgabase); |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 665 | svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); |
| 666 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 667 | |
| 668 | /* S3 specific initialization */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 669 | svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ |
| 670 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 671 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 672 | /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ |
| 673 | /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ |
| 674 | svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ |
| 675 | svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 676 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 677 | svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 678 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 679 | /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 680 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 681 | /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ |
| 682 | /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 683 | |
| 684 | |
| 685 | /* Set the offset register */ |
| 686 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 687 | svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 688 | |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 689 | if (par->chip != CHIP_357_VIRGE_GX2 && |
| 690 | par->chip != CHIP_359_VIRGE_GX2P && |
| 691 | par->chip != CHIP_360_TRIO3D_1X && |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 692 | par->chip != CHIP_362_TRIO3D_2X && |
| 693 | par->chip != CHIP_368_TRIO3D_2X) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 694 | vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ |
| 695 | vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ |
| 696 | vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ |
| 697 | vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 698 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 699 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 700 | vga_wcrt(par->state.vgabase, 0x3A, 0x35); |
David Miller | f6b0cc4 | 2011-01-11 23:49:18 +0000 | [diff] [blame] | 701 | svga_wattr(par->state.vgabase, 0x33, 0x00); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 702 | |
| 703 | if (info->var.vmode & FB_VMODE_DOUBLE) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 704 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 705 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 706 | svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 707 | |
| 708 | if (info->var.vmode & FB_VMODE_INTERLACED) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 709 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 710 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 711 | svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 712 | |
| 713 | /* Disable hardware graphics cursor */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 714 | svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 715 | /* Disable Streams engine */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 716 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 717 | |
| 718 | mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); |
| 719 | |
| 720 | /* S3 virge DX hack */ |
| 721 | if (par->chip == CHIP_375_VIRGE_DX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 722 | vga_wcrt(par->state.vgabase, 0x86, 0x80); |
| 723 | vga_wcrt(par->state.vgabase, 0x90, 0x00); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | /* S3 virge VX hack */ |
| 727 | if (par->chip == CHIP_988_VIRGE_VX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 728 | vga_wcrt(par->state.vgabase, 0x50, 0x00); |
| 729 | vga_wcrt(par->state.vgabase, 0x67, 0x50); |
Ondrej Zary | 66cde97 | 2011-12-19 23:39:47 +0100 | [diff] [blame^] | 730 | msleep(10); /* screen remains blank sometimes without this */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 731 | vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); |
| 732 | vga_wcrt(par->state.vgabase, 0x66, 0x90); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 733 | } |
| 734 | |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 735 | if (par->chip == CHIP_357_VIRGE_GX2 || |
| 736 | par->chip == CHIP_359_VIRGE_GX2P || |
| 737 | par->chip == CHIP_360_TRIO3D_1X || |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 738 | par->chip == CHIP_362_TRIO3D_2X || |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 739 | par->chip == CHIP_368_TRIO3D_2X || |
Ondrej Zary | cb11c04 | 2011-03-01 19:18:35 +0000 | [diff] [blame] | 740 | par->chip == CHIP_365_TRIO3D || |
| 741 | par->chip == CHIP_375_VIRGE_DX || |
| 742 | par->chip == CHIP_385_VIRGE_GX) { |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 743 | dbytes = info->var.xres * ((bpp+7)/8); |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 744 | vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); |
| 745 | vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 746 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 747 | vga_wcrt(par->state.vgabase, 0x66, 0x81); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 748 | } |
| 749 | |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 750 | if (par->chip == CHIP_357_VIRGE_GX2 || |
Ondrej Zary | cb11c04 | 2011-03-01 19:18:35 +0000 | [diff] [blame] | 751 | par->chip == CHIP_359_VIRGE_GX2P || |
| 752 | par->chip == CHIP_360_TRIO3D_1X || |
| 753 | par->chip == CHIP_362_TRIO3D_2X || |
| 754 | par->chip == CHIP_368_TRIO3D_2X) |
| 755 | vga_wcrt(par->state.vgabase, 0x34, 0x00); |
| 756 | else /* enable Data Transfer Position Control (DTPC) */ |
| 757 | vga_wcrt(par->state.vgabase, 0x34, 0x10); |
| 758 | |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 759 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 760 | multiplex = 0; |
| 761 | hmul = 1; |
| 762 | |
| 763 | /* Set mode-specific register values */ |
| 764 | switch (mode) { |
| 765 | case 0: |
| 766 | pr_debug("fb%d: text mode\n", info->node); |
David Miller | 9c96394 | 2011-01-11 23:51:56 +0000 | [diff] [blame] | 767 | svga_set_textmode_vga_regs(par->state.vgabase); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 768 | |
| 769 | /* Set additional registers like in 8-bit mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 770 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
| 771 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 772 | |
| 773 | /* Disable enhanced mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 774 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 775 | |
| 776 | if (fasttext) { |
| 777 | pr_debug("fb%d: high speed text mode set\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 778 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 779 | } |
| 780 | break; |
| 781 | case 1: |
| 782 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 783 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 784 | |
| 785 | /* Set additional registers like in 8-bit mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 786 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
| 787 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 788 | |
| 789 | /* disable enhanced mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 790 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 791 | break; |
| 792 | case 2: |
| 793 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); |
| 794 | |
| 795 | /* Set additional registers like in 8-bit mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 796 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
| 797 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 798 | |
| 799 | /* disable enhanced mode */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 800 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 801 | break; |
| 802 | case 3: |
| 803 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 804 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 805 | if (info->var.pixclock > 20000 || |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 806 | par->chip == CHIP_357_VIRGE_GX2 || |
| 807 | par->chip == CHIP_359_VIRGE_GX2P || |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 808 | par->chip == CHIP_360_TRIO3D_1X || |
| 809 | par->chip == CHIP_362_TRIO3D_2X || |
| 810 | par->chip == CHIP_368_TRIO3D_2X) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 811 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 812 | else { |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 813 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 814 | multiplex = 1; |
| 815 | } |
| 816 | break; |
| 817 | case 4: |
| 818 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); |
| 819 | if (par->chip == CHIP_988_VIRGE_VX) { |
| 820 | if (info->var.pixclock > 20000) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 821 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 822 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 823 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
Ondrej Zary | 3827d10 | 2011-03-01 19:18:27 +0000 | [diff] [blame] | 824 | } else if (par->chip == CHIP_365_TRIO3D) { |
| 825 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
| 826 | if (info->var.pixclock > 8695) { |
| 827 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
| 828 | hmul = 2; |
| 829 | } else { |
| 830 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); |
| 831 | multiplex = 1; |
| 832 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 833 | } else { |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 834 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
| 835 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 836 | if (par->chip != CHIP_357_VIRGE_GX2 && |
| 837 | par->chip != CHIP_359_VIRGE_GX2P && |
| 838 | par->chip != CHIP_360_TRIO3D_1X && |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 839 | par->chip != CHIP_362_TRIO3D_2X && |
| 840 | par->chip != CHIP_368_TRIO3D_2X) |
| 841 | hmul = 2; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 842 | } |
| 843 | break; |
| 844 | case 5: |
| 845 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); |
| 846 | if (par->chip == CHIP_988_VIRGE_VX) { |
| 847 | if (info->var.pixclock > 20000) |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 848 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 849 | else |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 850 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
Ondrej Zary | 3827d10 | 2011-03-01 19:18:27 +0000 | [diff] [blame] | 851 | } else if (par->chip == CHIP_365_TRIO3D) { |
| 852 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
| 853 | if (info->var.pixclock > 8695) { |
| 854 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
| 855 | hmul = 2; |
| 856 | } else { |
| 857 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); |
| 858 | multiplex = 1; |
| 859 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 860 | } else { |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 861 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); |
| 862 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 863 | if (par->chip != CHIP_357_VIRGE_GX2 && |
| 864 | par->chip != CHIP_359_VIRGE_GX2P && |
| 865 | par->chip != CHIP_360_TRIO3D_1X && |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 866 | par->chip != CHIP_362_TRIO3D_2X && |
| 867 | par->chip != CHIP_368_TRIO3D_2X) |
| 868 | hmul = 2; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 869 | } |
| 870 | break; |
| 871 | case 6: |
| 872 | /* VIRGE VX case */ |
| 873 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 874 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 875 | break; |
| 876 | case 7: |
| 877 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 878 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); |
| 879 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 880 | break; |
| 881 | default: |
| 882 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); |
| 883 | return -EINVAL; |
| 884 | } |
| 885 | |
| 886 | if (par->chip != CHIP_988_VIRGE_VX) { |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 887 | svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); |
| 888 | svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 889 | } |
| 890 | |
| 891 | s3_set_pixclock(info, info->var.pixclock); |
David Miller | 38d2620 | 2011-01-11 23:52:25 +0000 | [diff] [blame] | 892 | svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 893 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, |
| 894 | (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, |
| 895 | hmul, info->node); |
| 896 | |
| 897 | /* Set interlaced mode start/end register */ |
Ondrej Zary | cb11c04 | 2011-03-01 19:18:35 +0000 | [diff] [blame] | 898 | htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; |
| 899 | htotal = ((htotal * hmul) / 8) - 5; |
| 900 | vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); |
| 901 | |
| 902 | /* Set Data Transfer Position */ |
| 903 | hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8; |
Ondrej Zary | 66cde97 | 2011-12-19 23:39:47 +0100 | [diff] [blame^] | 904 | /* + 2 is needed for Virge/VX, does no harm on other cards */ |
| 905 | value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1); |
Ondrej Zary | cb11c04 | 2011-03-01 19:18:35 +0000 | [diff] [blame] | 906 | svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 907 | |
Antonino A. Daplas | 75814d8 | 2007-05-08 00:38:49 -0700 | [diff] [blame] | 908 | memset_io(info->screen_base, 0x00, screen_size); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 909 | /* Device and screen back on */ |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 910 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 911 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 912 | |
| 913 | return 0; |
| 914 | } |
| 915 | |
| 916 | /* Set a colour register */ |
| 917 | |
| 918 | static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
| 919 | u_int transp, struct fb_info *fb) |
| 920 | { |
| 921 | switch (fb->var.bits_per_pixel) { |
| 922 | case 0: |
| 923 | case 4: |
| 924 | if (regno >= 16) |
| 925 | return -EINVAL; |
| 926 | |
| 927 | if ((fb->var.bits_per_pixel == 4) && |
| 928 | (fb->var.nonstd == 0)) { |
| 929 | outb(0xF0, VGA_PEL_MSK); |
| 930 | outb(regno*16, VGA_PEL_IW); |
| 931 | } else { |
| 932 | outb(0x0F, VGA_PEL_MSK); |
| 933 | outb(regno, VGA_PEL_IW); |
| 934 | } |
| 935 | outb(red >> 10, VGA_PEL_D); |
| 936 | outb(green >> 10, VGA_PEL_D); |
| 937 | outb(blue >> 10, VGA_PEL_D); |
| 938 | break; |
| 939 | case 8: |
| 940 | if (regno >= 256) |
| 941 | return -EINVAL; |
| 942 | |
| 943 | outb(0xFF, VGA_PEL_MSK); |
| 944 | outb(regno, VGA_PEL_IW); |
| 945 | outb(red >> 10, VGA_PEL_D); |
| 946 | outb(green >> 10, VGA_PEL_D); |
| 947 | outb(blue >> 10, VGA_PEL_D); |
| 948 | break; |
| 949 | case 16: |
| 950 | if (regno >= 16) |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 951 | return 0; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 952 | |
| 953 | if (fb->var.green.length == 5) |
| 954 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | |
| 955 | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); |
| 956 | else if (fb->var.green.length == 6) |
| 957 | ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | |
| 958 | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); |
| 959 | else return -EINVAL; |
| 960 | break; |
| 961 | case 24: |
| 962 | case 32: |
| 963 | if (regno >= 16) |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 964 | return 0; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 965 | |
Ondrej Zajicek | 249bdbb | 2007-05-08 00:39:24 -0700 | [diff] [blame] | 966 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 967 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); |
| 968 | break; |
| 969 | default: |
| 970 | return -EINVAL; |
| 971 | } |
| 972 | |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | |
| 977 | /* Set the display blanking state */ |
| 978 | |
| 979 | static int s3fb_blank(int blank_mode, struct fb_info *info) |
| 980 | { |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 981 | struct s3fb_info *par = info->par; |
| 982 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 983 | switch (blank_mode) { |
| 984 | case FB_BLANK_UNBLANK: |
| 985 | pr_debug("fb%d: unblank\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 986 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 987 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 988 | break; |
| 989 | case FB_BLANK_NORMAL: |
| 990 | pr_debug("fb%d: blank\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 991 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 992 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 993 | break; |
| 994 | case FB_BLANK_HSYNC_SUSPEND: |
| 995 | pr_debug("fb%d: hsync\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 996 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 997 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 998 | break; |
| 999 | case FB_BLANK_VSYNC_SUSPEND: |
| 1000 | pr_debug("fb%d: vsync\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 1001 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 1002 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1003 | break; |
| 1004 | case FB_BLANK_POWERDOWN: |
| 1005 | pr_debug("fb%d: sync down\n", info->node); |
David Miller | ea77078 | 2011-01-11 23:51:26 +0000 | [diff] [blame] | 1006 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); |
David Miller | d907ec0 | 2011-01-11 23:51:08 +0000 | [diff] [blame] | 1007 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1008 | break; |
| 1009 | } |
| 1010 | |
| 1011 | return 0; |
| 1012 | } |
| 1013 | |
| 1014 | |
| 1015 | /* Pan the display */ |
| 1016 | |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 1017 | static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
| 1018 | { |
| 1019 | struct s3fb_info *par = info->par; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1020 | unsigned int offset; |
| 1021 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1022 | /* Calculate the offset */ |
Laurent Pinchart | a4aadc9 | 2011-06-14 09:24:58 +0000 | [diff] [blame] | 1023 | if (info->var.bits_per_pixel == 0) { |
| 1024 | offset = (var->yoffset / 16) * (info->var.xres_virtual / 2) |
| 1025 | + (var->xoffset / 2); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1026 | offset = offset >> 2; |
| 1027 | } else { |
| 1028 | offset = (var->yoffset * info->fix.line_length) + |
Laurent Pinchart | a4aadc9 | 2011-06-14 09:24:58 +0000 | [diff] [blame] | 1029 | (var->xoffset * info->var.bits_per_pixel / 8); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1030 | offset = offset >> 2; |
| 1031 | } |
| 1032 | |
| 1033 | /* Set the offset */ |
David Miller | 21da386 | 2011-01-11 23:49:34 +0000 | [diff] [blame] | 1034 | svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1035 | |
| 1036 | return 0; |
| 1037 | } |
| 1038 | |
| 1039 | /* ------------------------------------------------------------------------- */ |
| 1040 | |
| 1041 | /* Frame buffer operations */ |
| 1042 | |
| 1043 | static struct fb_ops s3fb_ops = { |
| 1044 | .owner = THIS_MODULE, |
| 1045 | .fb_open = s3fb_open, |
| 1046 | .fb_release = s3fb_release, |
| 1047 | .fb_check_var = s3fb_check_var, |
| 1048 | .fb_set_par = s3fb_set_par, |
| 1049 | .fb_setcolreg = s3fb_setcolreg, |
| 1050 | .fb_blank = s3fb_blank, |
| 1051 | .fb_pan_display = s3fb_pan_display, |
| 1052 | .fb_fillrect = s3fb_fillrect, |
| 1053 | .fb_copyarea = cfb_copyarea, |
| 1054 | .fb_imageblit = s3fb_imageblit, |
Antonino A. Daplas | 5a87ede | 2007-05-09 02:35:32 -0700 | [diff] [blame] | 1055 | .fb_get_caps = svga_get_caps, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1056 | }; |
| 1057 | |
| 1058 | /* ------------------------------------------------------------------------- */ |
| 1059 | |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1060 | static int __devinit s3_identification(struct s3fb_info *par) |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1061 | { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1062 | int chip = par->chip; |
| 1063 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1064 | if (chip == CHIP_XXX_TRIO) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1065 | u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); |
| 1066 | u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); |
| 1067 | u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1068 | |
| 1069 | if ((cr30 == 0xE0) || (cr30 == 0xE1)) { |
| 1070 | if (cr2e == 0x10) |
| 1071 | return CHIP_732_TRIO32; |
| 1072 | if (cr2e == 0x11) { |
| 1073 | if (! (cr2f & 0x40)) |
| 1074 | return CHIP_764_TRIO64; |
| 1075 | else |
| 1076 | return CHIP_765_TRIO64VP; |
| 1077 | } |
| 1078 | } |
| 1079 | } |
| 1080 | |
| 1081 | if (chip == CHIP_XXX_TRIO64V2_DXGX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1082 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1083 | |
| 1084 | if (! (cr6f & 0x01)) |
| 1085 | return CHIP_775_TRIO64V2_DX; |
| 1086 | else |
| 1087 | return CHIP_785_TRIO64V2_GX; |
| 1088 | } |
| 1089 | |
| 1090 | if (chip == CHIP_XXX_VIRGE_DXGX) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1091 | u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1092 | |
| 1093 | if (! (cr6f & 0x01)) |
| 1094 | return CHIP_375_VIRGE_DX; |
| 1095 | else |
| 1096 | return CHIP_385_VIRGE_GX; |
| 1097 | } |
| 1098 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1099 | if (chip == CHIP_36X_TRIO3D_1X_2X) { |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1100 | switch (vga_rcrt(par->state.vgabase, 0x2f)) { |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1101 | case 0x00: |
| 1102 | return CHIP_360_TRIO3D_1X; |
| 1103 | case 0x01: |
| 1104 | return CHIP_362_TRIO3D_2X; |
| 1105 | case 0x02: |
| 1106 | return CHIP_368_TRIO3D_2X; |
| 1107 | } |
| 1108 | } |
| 1109 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1110 | return CHIP_UNKNOWN; |
| 1111 | } |
| 1112 | |
| 1113 | |
| 1114 | /* PCI probe */ |
| 1115 | |
| 1116 | static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
| 1117 | { |
David Miller | 94c322c | 2011-01-11 23:54:21 +0000 | [diff] [blame] | 1118 | struct pci_bus_region bus_reg; |
| 1119 | struct resource vga_res; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1120 | struct fb_info *info; |
| 1121 | struct s3fb_info *par; |
| 1122 | int rc; |
| 1123 | u8 regval, cr38, cr39; |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 1124 | bool found = false; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1125 | |
| 1126 | /* Ignore secondary VGA device because there is no VGA arbitration */ |
| 1127 | if (! svga_primary_device(dev)) { |
| 1128 | dev_info(&(dev->dev), "ignoring secondary device\n"); |
| 1129 | return -ENODEV; |
| 1130 | } |
| 1131 | |
| 1132 | /* Allocate and fill driver data structure */ |
Ondrej Zajicek | 20e061f | 2008-04-28 02:15:18 -0700 | [diff] [blame] | 1133 | info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1134 | if (!info) { |
| 1135 | dev_err(&(dev->dev), "cannot allocate memory\n"); |
| 1136 | return -ENOMEM; |
| 1137 | } |
| 1138 | |
| 1139 | par = info->par; |
| 1140 | mutex_init(&par->open_lock); |
| 1141 | |
| 1142 | info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; |
| 1143 | info->fbops = &s3fb_ops; |
| 1144 | |
| 1145 | /* Prepare PCI device */ |
| 1146 | rc = pci_enable_device(dev); |
| 1147 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1148 | dev_err(info->device, "cannot enable PCI device\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1149 | goto err_enable_device; |
| 1150 | } |
| 1151 | |
| 1152 | rc = pci_request_regions(dev, "s3fb"); |
| 1153 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1154 | dev_err(info->device, "cannot reserve framebuffer region\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1155 | goto err_request_regions; |
| 1156 | } |
| 1157 | |
| 1158 | |
| 1159 | info->fix.smem_start = pci_resource_start(dev, 0); |
| 1160 | info->fix.smem_len = pci_resource_len(dev, 0); |
| 1161 | |
| 1162 | /* Map physical IO memory address into kernel space */ |
| 1163 | info->screen_base = pci_iomap(dev, 0, 0); |
| 1164 | if (! info->screen_base) { |
| 1165 | rc = -ENOMEM; |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1166 | dev_err(info->device, "iomap for framebuffer failed\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1167 | goto err_iomap; |
| 1168 | } |
| 1169 | |
David Miller | 94c322c | 2011-01-11 23:54:21 +0000 | [diff] [blame] | 1170 | bus_reg.start = 0; |
| 1171 | bus_reg.end = 64 * 1024; |
| 1172 | |
| 1173 | vga_res.flags = IORESOURCE_IO; |
| 1174 | |
| 1175 | pcibios_bus_to_resource(dev, &vga_res, &bus_reg); |
| 1176 | |
| 1177 | par->state.vgabase = (void __iomem *) vga_res.start; |
| 1178 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1179 | /* Unlock regs */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1180 | cr38 = vga_rcrt(par->state.vgabase, 0x38); |
| 1181 | cr39 = vga_rcrt(par->state.vgabase, 0x39); |
| 1182 | vga_wseq(par->state.vgabase, 0x08, 0x06); |
| 1183 | vga_wcrt(par->state.vgabase, 0x38, 0x48); |
| 1184 | vga_wcrt(par->state.vgabase, 0x39, 0xA5); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1185 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1186 | /* Identify chip type */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1187 | par->chip = id->driver_data & CHIP_MASK; |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1188 | par->rev = vga_rcrt(par->state.vgabase, 0x2f); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1189 | if (par->chip & CHIP_UNDECIDED_FLAG) |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1190 | par->chip = s3_identification(par); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1191 | |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1192 | /* Find how many physical memory there is on card */ |
| 1193 | /* 0x36 register is accessible even if other registers are locked */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1194 | regval = vga_rcrt(par->state.vgabase, 0x36); |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1195 | if (par->chip == CHIP_360_TRIO3D_1X || |
| 1196 | par->chip == CHIP_362_TRIO3D_2X || |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 1197 | par->chip == CHIP_368_TRIO3D_2X || |
| 1198 | par->chip == CHIP_365_TRIO3D) { |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1199 | switch ((regval & 0xE0) >> 5) { |
| 1200 | case 0: /* 8MB -- only 4MB usable for display */ |
| 1201 | case 1: /* 4MB with 32-bit bus */ |
| 1202 | case 2: /* 4MB */ |
| 1203 | info->screen_size = 4 << 20; |
| 1204 | break; |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 1205 | case 4: /* 2MB on 365 Trio3D */ |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1206 | case 6: /* 2MB */ |
| 1207 | info->screen_size = 2 << 20; |
| 1208 | break; |
| 1209 | } |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 1210 | } else if (par->chip == CHIP_357_VIRGE_GX2 || |
| 1211 | par->chip == CHIP_359_VIRGE_GX2P) { |
| 1212 | switch ((regval & 0xC0) >> 6) { |
| 1213 | case 1: /* 4MB */ |
| 1214 | info->screen_size = 4 << 20; |
| 1215 | break; |
| 1216 | case 3: /* 2MB */ |
| 1217 | info->screen_size = 2 << 20; |
| 1218 | break; |
| 1219 | } |
Ondrej Zary | 66cde97 | 2011-12-19 23:39:47 +0100 | [diff] [blame^] | 1220 | } else if (par->chip == CHIP_988_VIRGE_VX) { |
| 1221 | switch ((regval & 0x60) >> 5) { |
| 1222 | case 0: /* 2MB */ |
| 1223 | info->screen_size = 2 << 20; |
| 1224 | break; |
| 1225 | case 1: /* 4MB */ |
| 1226 | info->screen_size = 4 << 20; |
| 1227 | break; |
| 1228 | case 2: /* 6MB */ |
| 1229 | info->screen_size = 6 << 20; |
| 1230 | break; |
| 1231 | case 3: /* 8MB */ |
| 1232 | info->screen_size = 8 << 20; |
| 1233 | break; |
| 1234 | } |
| 1235 | /* off-screen memory */ |
| 1236 | regval = vga_rcrt(par->state.vgabase, 0x37); |
| 1237 | switch ((regval & 0x60) >> 5) { |
| 1238 | case 1: /* 4MB */ |
| 1239 | info->screen_size -= 4 << 20; |
| 1240 | break; |
| 1241 | case 2: /* 2MB */ |
| 1242 | info->screen_size -= 2 << 20; |
| 1243 | break; |
| 1244 | } |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1245 | } else |
| 1246 | info->screen_size = s3_memsizes[regval >> 5] << 10; |
| 1247 | info->fix.smem_len = info->screen_size; |
| 1248 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1249 | /* Find MCLK frequency */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1250 | regval = vga_rseq(par->state.vgabase, 0x10); |
| 1251 | par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1252 | par->mclk_freq = par->mclk_freq >> (regval >> 5); |
| 1253 | |
| 1254 | /* Restore locks */ |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1255 | vga_wcrt(par->state.vgabase, 0x38, cr38); |
| 1256 | vga_wcrt(par->state.vgabase, 0x39, cr39); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1257 | |
| 1258 | strcpy(info->fix.id, s3_names [par->chip]); |
| 1259 | info->fix.mmio_start = 0; |
| 1260 | info->fix.mmio_len = 0; |
| 1261 | info->fix.type = FB_TYPE_PACKED_PIXELS; |
| 1262 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
| 1263 | info->fix.ypanstep = 0; |
| 1264 | info->fix.accel = FB_ACCEL_NONE; |
| 1265 | info->pseudo_palette = (void*) (par->pseudo_palette); |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 1266 | info->var.bits_per_pixel = 8; |
| 1267 | |
| 1268 | #ifdef CONFIG_FB_S3_DDC |
| 1269 | /* Enable MMIO if needed */ |
| 1270 | if (s3fb_ddc_needs_mmio(par->chip)) { |
| 1271 | par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); |
| 1272 | if (par->mmio) |
| 1273 | svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ |
| 1274 | else |
| 1275 | dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC", |
| 1276 | info->fix.smem_start + MMIO_OFFSET); |
| 1277 | } |
| 1278 | if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) |
| 1279 | if (s3fb_setup_ddc_bus(info) == 0) { |
| 1280 | u8 *edid = fb_ddc_read(&par->ddc_adapter); |
| 1281 | par->ddc_registered = true; |
| 1282 | if (edid) { |
| 1283 | fb_edid_to_monspecs(edid, &info->monspecs); |
| 1284 | kfree(edid); |
| 1285 | if (!info->monspecs.modedb) |
| 1286 | dev_err(info->device, "error getting mode database\n"); |
| 1287 | else { |
| 1288 | const struct fb_videomode *m; |
| 1289 | |
| 1290 | fb_videomode_to_modelist(info->monspecs.modedb, |
| 1291 | info->monspecs.modedb_len, |
| 1292 | &info->modelist); |
| 1293 | m = fb_find_best_display(&info->monspecs, &info->modelist); |
| 1294 | if (m) { |
| 1295 | fb_videomode_to_var(&info->var, m); |
| 1296 | /* fill all other info->var's fields */ |
| 1297 | if (s3fb_check_var(&info->var, info) == 0) |
| 1298 | found = true; |
| 1299 | } |
| 1300 | } |
| 1301 | } |
| 1302 | } |
| 1303 | #endif |
| 1304 | if (!mode_option && !found) |
| 1305 | mode_option = "640x480-8@60"; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1306 | |
| 1307 | /* Prepare startup mode */ |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 1308 | if (mode_option) { |
| 1309 | rc = fb_find_mode(&info->var, info, mode_option, |
| 1310 | info->monspecs.modedb, info->monspecs.modedb_len, |
| 1311 | NULL, info->var.bits_per_pixel); |
| 1312 | if (!rc || rc == 4) { |
| 1313 | rc = -EINVAL; |
| 1314 | dev_err(info->device, "mode %s not found\n", mode_option); |
| 1315 | fb_destroy_modedb(info->monspecs.modedb); |
| 1316 | info->monspecs.modedb = NULL; |
| 1317 | goto err_find_mode; |
| 1318 | } |
| 1319 | } |
| 1320 | |
| 1321 | fb_destroy_modedb(info->monspecs.modedb); |
| 1322 | info->monspecs.modedb = NULL; |
| 1323 | |
| 1324 | /* maximize virtual vertical size for fast scrolling */ |
| 1325 | info->var.yres_virtual = info->fix.smem_len * 8 / |
| 1326 | (info->var.bits_per_pixel * info->var.xres_virtual); |
| 1327 | if (info->var.yres_virtual < info->var.yres) { |
| 1328 | dev_err(info->device, "virtual vertical size smaller than real\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1329 | goto err_find_mode; |
| 1330 | } |
| 1331 | |
Ondrej Zary | 99d054d | 2011-03-01 19:18:08 +0000 | [diff] [blame] | 1332 | /* maximize virtual vertical size for fast scrolling */ |
| 1333 | info->var.yres_virtual = info->fix.smem_len * 8 / |
| 1334 | (info->var.bits_per_pixel * info->var.xres_virtual); |
| 1335 | if (info->var.yres_virtual < info->var.yres) { |
| 1336 | dev_err(info->device, "virtual vertical size smaller than real\n"); |
| 1337 | goto err_find_mode; |
| 1338 | } |
| 1339 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1340 | rc = fb_alloc_cmap(&info->cmap, 256, 0); |
| 1341 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1342 | dev_err(info->device, "cannot allocate colormap\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1343 | goto err_alloc_cmap; |
| 1344 | } |
| 1345 | |
| 1346 | rc = register_framebuffer(info); |
| 1347 | if (rc < 0) { |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1348 | dev_err(info->device, "cannot register framebuffer\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1349 | goto err_reg_fb; |
| 1350 | } |
| 1351 | |
| 1352 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, |
| 1353 | pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); |
| 1354 | |
| 1355 | if (par->chip == CHIP_UNKNOWN) |
| 1356 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", |
David Miller | f864593 | 2011-01-11 23:52:57 +0000 | [diff] [blame] | 1357 | info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), |
| 1358 | vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1359 | |
| 1360 | /* Record a reference to the driver data */ |
| 1361 | pci_set_drvdata(dev, info); |
| 1362 | |
| 1363 | #ifdef CONFIG_MTRR |
| 1364 | if (mtrr) { |
| 1365 | par->mtrr_reg = -1; |
| 1366 | par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); |
| 1367 | } |
| 1368 | #endif |
| 1369 | |
| 1370 | return 0; |
| 1371 | |
| 1372 | /* Error handling */ |
| 1373 | err_reg_fb: |
| 1374 | fb_dealloc_cmap(&info->cmap); |
| 1375 | err_alloc_cmap: |
| 1376 | err_find_mode: |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 1377 | #ifdef CONFIG_FB_S3_DDC |
| 1378 | if (par->ddc_registered) |
| 1379 | i2c_del_adapter(&par->ddc_adapter); |
| 1380 | if (par->mmio) |
| 1381 | iounmap(par->mmio); |
| 1382 | #endif |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1383 | pci_iounmap(dev, info->screen_base); |
| 1384 | err_iomap: |
| 1385 | pci_release_regions(dev); |
| 1386 | err_request_regions: |
| 1387 | /* pci_disable_device(dev); */ |
| 1388 | err_enable_device: |
| 1389 | framebuffer_release(info); |
| 1390 | return rc; |
| 1391 | } |
| 1392 | |
| 1393 | |
| 1394 | /* PCI remove */ |
| 1395 | |
| 1396 | static void __devexit s3_pci_remove(struct pci_dev *dev) |
| 1397 | { |
| 1398 | struct fb_info *info = pci_get_drvdata(dev); |
Paul Mundt | 4f2970b | 2011-04-20 18:20:26 +0900 | [diff] [blame] | 1399 | struct s3fb_info __maybe_unused *par = info->par; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1400 | |
| 1401 | if (info) { |
| 1402 | |
| 1403 | #ifdef CONFIG_MTRR |
| 1404 | if (par->mtrr_reg >= 0) { |
| 1405 | mtrr_del(par->mtrr_reg, 0, 0); |
| 1406 | par->mtrr_reg = -1; |
| 1407 | } |
| 1408 | #endif |
| 1409 | |
| 1410 | unregister_framebuffer(info); |
| 1411 | fb_dealloc_cmap(&info->cmap); |
| 1412 | |
Ondrej Zary | 86c0f043 | 2011-04-18 10:14:57 +0000 | [diff] [blame] | 1413 | #ifdef CONFIG_FB_S3_DDC |
| 1414 | if (par->ddc_registered) |
| 1415 | i2c_del_adapter(&par->ddc_adapter); |
| 1416 | if (par->mmio) |
| 1417 | iounmap(par->mmio); |
| 1418 | #endif |
| 1419 | |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1420 | pci_iounmap(dev, info->screen_base); |
| 1421 | pci_release_regions(dev); |
| 1422 | /* pci_disable_device(dev); */ |
| 1423 | |
| 1424 | pci_set_drvdata(dev, NULL); |
| 1425 | framebuffer_release(info); |
| 1426 | } |
| 1427 | } |
| 1428 | |
| 1429 | /* PCI suspend */ |
| 1430 | |
| 1431 | static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state) |
| 1432 | { |
| 1433 | struct fb_info *info = pci_get_drvdata(dev); |
| 1434 | struct s3fb_info *par = info->par; |
| 1435 | |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1436 | dev_info(info->device, "suspend\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1437 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1438 | console_lock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1439 | mutex_lock(&(par->open_lock)); |
| 1440 | |
| 1441 | if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { |
| 1442 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1443 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | fb_set_suspend(info, 1); |
| 1448 | |
| 1449 | pci_save_state(dev); |
| 1450 | pci_disable_device(dev); |
| 1451 | pci_set_power_state(dev, pci_choose_state(dev, state)); |
| 1452 | |
| 1453 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1454 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1455 | |
| 1456 | return 0; |
| 1457 | } |
| 1458 | |
| 1459 | |
| 1460 | /* PCI resume */ |
| 1461 | |
| 1462 | static int s3_pci_resume(struct pci_dev* dev) |
| 1463 | { |
| 1464 | struct fb_info *info = pci_get_drvdata(dev); |
| 1465 | struct s3fb_info *par = info->par; |
Randy Dunlap | 6314db4 | 2007-05-08 00:38:11 -0700 | [diff] [blame] | 1466 | int err; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1467 | |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1468 | dev_info(info->device, "resume\n"); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1469 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1470 | console_lock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1471 | mutex_lock(&(par->open_lock)); |
| 1472 | |
| 1473 | if (par->ref_count == 0) { |
| 1474 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1475 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1476 | return 0; |
| 1477 | } |
| 1478 | |
| 1479 | pci_set_power_state(dev, PCI_D0); |
| 1480 | pci_restore_state(dev); |
Randy Dunlap | 6314db4 | 2007-05-08 00:38:11 -0700 | [diff] [blame] | 1481 | err = pci_enable_device(dev); |
| 1482 | if (err) { |
| 1483 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1484 | console_unlock(); |
Ondrej Zajicek | 594a881 | 2008-08-05 13:01:06 -0700 | [diff] [blame] | 1485 | dev_err(info->device, "error %d enabling device for resume\n", err); |
Randy Dunlap | 6314db4 | 2007-05-08 00:38:11 -0700 | [diff] [blame] | 1486 | return err; |
| 1487 | } |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1488 | pci_set_master(dev); |
| 1489 | |
| 1490 | s3fb_set_par(info); |
| 1491 | fb_set_suspend(info, 0); |
| 1492 | |
| 1493 | mutex_unlock(&(par->open_lock)); |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 1494 | console_unlock(); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1495 | |
| 1496 | return 0; |
| 1497 | } |
| 1498 | |
| 1499 | |
| 1500 | /* List of boards that we are trying to support */ |
| 1501 | |
| 1502 | static struct pci_device_id s3_devices[] __devinitdata = { |
| 1503 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO}, |
| 1504 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO}, |
| 1505 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP}, |
| 1506 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP}, |
| 1507 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX}, |
| 1508 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX}, |
| 1509 | |
| 1510 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE}, |
| 1511 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX}, |
| 1512 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX}, |
Ondrej Zary | 94e948e | 2011-03-29 19:07:08 +0000 | [diff] [blame] | 1513 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2}, |
| 1514 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P}, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1515 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, |
Ondrej Zary | 9966c4f | 2010-05-26 14:42:27 -0700 | [diff] [blame] | 1516 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, |
Ondrej Zary | 5694f9c | 2011-03-01 19:18:17 +0000 | [diff] [blame] | 1517 | {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D}, |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1518 | |
| 1519 | {0, 0, 0, 0, 0, 0, 0} |
| 1520 | }; |
| 1521 | |
| 1522 | |
| 1523 | MODULE_DEVICE_TABLE(pci, s3_devices); |
| 1524 | |
| 1525 | static struct pci_driver s3fb_pci_driver = { |
| 1526 | .name = "s3fb", |
| 1527 | .id_table = s3_devices, |
| 1528 | .probe = s3_pci_probe, |
| 1529 | .remove = __devexit_p(s3_pci_remove), |
| 1530 | .suspend = s3_pci_suspend, |
| 1531 | .resume = s3_pci_resume, |
| 1532 | }; |
| 1533 | |
Joe Perches | 75e1b6a | 2011-06-23 22:35:19 +0000 | [diff] [blame] | 1534 | /* Parse user specified options */ |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1535 | |
| 1536 | #ifndef MODULE |
| 1537 | static int __init s3fb_setup(char *options) |
| 1538 | { |
| 1539 | char *opt; |
| 1540 | |
| 1541 | if (!options || !*options) |
| 1542 | return 0; |
| 1543 | |
| 1544 | while ((opt = strsep(&options, ",")) != NULL) { |
| 1545 | |
| 1546 | if (!*opt) |
| 1547 | continue; |
| 1548 | #ifdef CONFIG_MTRR |
Ondrej Zajicek | 62fa4dc | 2007-02-22 17:00:41 +0100 | [diff] [blame] | 1549 | else if (!strncmp(opt, "mtrr:", 5)) |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1550 | mtrr = simple_strtoul(opt + 5, NULL, 0); |
| 1551 | #endif |
Ondrej Zajicek | 62fa4dc | 2007-02-22 17:00:41 +0100 | [diff] [blame] | 1552 | else if (!strncmp(opt, "fasttext:", 9)) |
| 1553 | fasttext = simple_strtoul(opt + 9, NULL, 0); |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1554 | else |
Krzysztof Helt | a814054 | 2008-04-28 02:15:09 -0700 | [diff] [blame] | 1555 | mode_option = opt; |
Ondrej Zajicek | a268422 | 2007-02-12 00:54:49 -0800 | [diff] [blame] | 1556 | } |
| 1557 | |
| 1558 | return 0; |
| 1559 | } |
| 1560 | #endif |
| 1561 | |
| 1562 | /* Cleanup */ |
| 1563 | |
| 1564 | static void __exit s3fb_cleanup(void) |
| 1565 | { |
| 1566 | pr_debug("s3fb: cleaning up\n"); |
| 1567 | pci_unregister_driver(&s3fb_pci_driver); |
| 1568 | } |
| 1569 | |
| 1570 | /* Driver Initialisation */ |
| 1571 | |
| 1572 | static int __init s3fb_init(void) |
| 1573 | { |
| 1574 | |
| 1575 | #ifndef MODULE |
| 1576 | char *option = NULL; |
| 1577 | |
| 1578 | if (fb_get_options("s3fb", &option)) |
| 1579 | return -ENODEV; |
| 1580 | s3fb_setup(option); |
| 1581 | #endif |
| 1582 | |
| 1583 | pr_debug("s3fb: initializing\n"); |
| 1584 | return pci_register_driver(&s3fb_pci_driver); |
| 1585 | } |
| 1586 | |
| 1587 | /* ------------------------------------------------------------------------- */ |
| 1588 | |
| 1589 | /* Modularization */ |
| 1590 | |
| 1591 | module_init(s3fb_init); |
| 1592 | module_exit(s3fb_cleanup); |