Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006, Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along with |
| 14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple |
| 15 | * Place - Suite 330, Boston, MA 02111-1307 USA. |
| 16 | * |
mark gross | 98bcef5 | 2008-02-23 15:23:35 -0800 | [diff] [blame] | 17 | * Copyright (C) 2006-2008 Intel Corporation |
| 18 | * Author: Ashok Raj <ashok.raj@intel.com> |
| 19 | * Author: Shaohua Li <shaohua.li@intel.com> |
| 20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 21 | * Author: Fenghua Yu <fenghua.yu@intel.com> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/bitmap.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 26 | #include <linux/debugfs.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 27 | #include <linux/slab.h> |
| 28 | #include <linux/irq.h> |
| 29 | #include <linux/interrupt.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 30 | #include <linux/spinlock.h> |
| 31 | #include <linux/pci.h> |
| 32 | #include <linux/dmar.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/mempool.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 35 | #include <linux/timer.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 36 | #include <linux/iova.h> |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 37 | #include <linux/iommu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 38 | #include <linux/intel-iommu.h> |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 39 | #include <linux/sysdev.h> |
Shane Wang | 69575d3 | 2009-09-01 18:25:07 -0700 | [diff] [blame^] | 40 | #include <linux/tboot.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 41 | #include <asm/cacheflush.h> |
FUJITA Tomonori | 46a7fa2 | 2008-07-11 10:23:42 +0900 | [diff] [blame] | 42 | #include <asm/iommu.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 43 | #include "pci.h" |
| 44 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 45 | #define ROOT_SIZE VTD_PAGE_SIZE |
| 46 | #define CONTEXT_SIZE VTD_PAGE_SIZE |
| 47 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 48 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
| 49 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
| 50 | |
| 51 | #define IOAPIC_RANGE_START (0xfee00000) |
| 52 | #define IOAPIC_RANGE_END (0xfeefffff) |
| 53 | #define IOVA_START_ADDR (0x1000) |
| 54 | |
| 55 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 |
| 56 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 57 | #define MAX_AGAW_WIDTH 64 |
| 58 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 59 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 60 | #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 61 | |
Mark McLoughlin | f27be03 | 2008-11-20 15:49:43 +0000 | [diff] [blame] | 62 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 63 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 64 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 65 | |
David Woodhouse | fd18de5 | 2009-05-10 23:57:41 +0100 | [diff] [blame] | 66 | |
David Woodhouse | dd4e831 | 2009-06-27 16:21:20 +0100 | [diff] [blame] | 67 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
| 68 | are never going to work. */ |
| 69 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) |
| 70 | { |
| 71 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 72 | } |
| 73 | |
| 74 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) |
| 75 | { |
| 76 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 77 | } |
| 78 | static inline unsigned long page_to_dma_pfn(struct page *pg) |
| 79 | { |
| 80 | return mm_to_dma_pfn(page_to_pfn(pg)); |
| 81 | } |
| 82 | static inline unsigned long virt_to_dma_pfn(void *p) |
| 83 | { |
| 84 | return page_to_dma_pfn(virt_to_page(p)); |
| 85 | } |
| 86 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 87 | /* global iommu list, set NULL for ignored DMAR units */ |
| 88 | static struct intel_iommu **g_iommus; |
| 89 | |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 90 | static int rwbf_quirk; |
| 91 | |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 92 | /* |
| 93 | * 0: Present |
| 94 | * 1-11: Reserved |
| 95 | * 12-63: Context Ptr (12 - (haw-1)) |
| 96 | * 64-127: Reserved |
| 97 | */ |
| 98 | struct root_entry { |
| 99 | u64 val; |
| 100 | u64 rsvd1; |
| 101 | }; |
| 102 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) |
| 103 | static inline bool root_present(struct root_entry *root) |
| 104 | { |
| 105 | return (root->val & 1); |
| 106 | } |
| 107 | static inline void set_root_present(struct root_entry *root) |
| 108 | { |
| 109 | root->val |= 1; |
| 110 | } |
| 111 | static inline void set_root_value(struct root_entry *root, unsigned long value) |
| 112 | { |
| 113 | root->val |= value & VTD_PAGE_MASK; |
| 114 | } |
| 115 | |
| 116 | static inline struct context_entry * |
| 117 | get_context_addr_from_root(struct root_entry *root) |
| 118 | { |
| 119 | return (struct context_entry *) |
| 120 | (root_present(root)?phys_to_virt( |
| 121 | root->val & VTD_PAGE_MASK) : |
| 122 | NULL); |
| 123 | } |
| 124 | |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 125 | /* |
| 126 | * low 64 bits: |
| 127 | * 0: present |
| 128 | * 1: fault processing disable |
| 129 | * 2-3: translation type |
| 130 | * 12-63: address space root |
| 131 | * high 64 bits: |
| 132 | * 0-2: address width |
| 133 | * 3-6: aval |
| 134 | * 8-23: domain id |
| 135 | */ |
| 136 | struct context_entry { |
| 137 | u64 lo; |
| 138 | u64 hi; |
| 139 | }; |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 140 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 141 | static inline bool context_present(struct context_entry *context) |
| 142 | { |
| 143 | return (context->lo & 1); |
| 144 | } |
| 145 | static inline void context_set_present(struct context_entry *context) |
| 146 | { |
| 147 | context->lo |= 1; |
| 148 | } |
| 149 | |
| 150 | static inline void context_set_fault_enable(struct context_entry *context) |
| 151 | { |
| 152 | context->lo &= (((u64)-1) << 2) | 1; |
| 153 | } |
| 154 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 155 | static inline void context_set_translation_type(struct context_entry *context, |
| 156 | unsigned long value) |
| 157 | { |
| 158 | context->lo &= (((u64)-1) << 4) | 3; |
| 159 | context->lo |= (value & 3) << 2; |
| 160 | } |
| 161 | |
| 162 | static inline void context_set_address_root(struct context_entry *context, |
| 163 | unsigned long value) |
| 164 | { |
| 165 | context->lo |= value & VTD_PAGE_MASK; |
| 166 | } |
| 167 | |
| 168 | static inline void context_set_address_width(struct context_entry *context, |
| 169 | unsigned long value) |
| 170 | { |
| 171 | context->hi |= value & 7; |
| 172 | } |
| 173 | |
| 174 | static inline void context_set_domain_id(struct context_entry *context, |
| 175 | unsigned long value) |
| 176 | { |
| 177 | context->hi |= (value & ((1 << 16) - 1)) << 8; |
| 178 | } |
| 179 | |
| 180 | static inline void context_clear_entry(struct context_entry *context) |
| 181 | { |
| 182 | context->lo = 0; |
| 183 | context->hi = 0; |
| 184 | } |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 185 | |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 186 | /* |
| 187 | * 0: readable |
| 188 | * 1: writable |
| 189 | * 2-6: reserved |
| 190 | * 7: super page |
Sheng Yang | 9cf0669 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 191 | * 8-10: available |
| 192 | * 11: snoop behavior |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 193 | * 12-63: Host physcial address |
| 194 | */ |
| 195 | struct dma_pte { |
| 196 | u64 val; |
| 197 | }; |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 198 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 199 | static inline void dma_clear_pte(struct dma_pte *pte) |
| 200 | { |
| 201 | pte->val = 0; |
| 202 | } |
| 203 | |
| 204 | static inline void dma_set_pte_readable(struct dma_pte *pte) |
| 205 | { |
| 206 | pte->val |= DMA_PTE_READ; |
| 207 | } |
| 208 | |
| 209 | static inline void dma_set_pte_writable(struct dma_pte *pte) |
| 210 | { |
| 211 | pte->val |= DMA_PTE_WRITE; |
| 212 | } |
| 213 | |
Sheng Yang | 9cf0669 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 214 | static inline void dma_set_pte_snp(struct dma_pte *pte) |
| 215 | { |
| 216 | pte->val |= DMA_PTE_SNP; |
| 217 | } |
| 218 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 219 | static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot) |
| 220 | { |
| 221 | pte->val = (pte->val & ~3) | (prot & 3); |
| 222 | } |
| 223 | |
| 224 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
| 225 | { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 226 | #ifdef CONFIG_64BIT |
| 227 | return pte->val & VTD_PAGE_MASK; |
| 228 | #else |
| 229 | /* Must have a full atomic 64-bit read */ |
| 230 | return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK; |
| 231 | #endif |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 232 | } |
| 233 | |
David Woodhouse | dd4e831 | 2009-06-27 16:21:20 +0100 | [diff] [blame] | 234 | static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn) |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 235 | { |
David Woodhouse | dd4e831 | 2009-06-27 16:21:20 +0100 | [diff] [blame] | 236 | pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT; |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | static inline bool dma_pte_present(struct dma_pte *pte) |
| 240 | { |
| 241 | return (pte->val & 3) != 0; |
| 242 | } |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 243 | |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 244 | static inline int first_pte_in_page(struct dma_pte *pte) |
| 245 | { |
| 246 | return !((unsigned long)pte & ~VTD_PAGE_MASK); |
| 247 | } |
| 248 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 249 | /* |
| 250 | * This domain is a statically identity mapping domain. |
| 251 | * 1. This domain creats a static 1:1 mapping to all usable memory. |
| 252 | * 2. It maps to each iommu if successful. |
| 253 | * 3. Each iommu mapps to this domain if successful. |
| 254 | */ |
| 255 | struct dmar_domain *si_domain; |
| 256 | |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 257 | /* devices under the same p2p bridge are owned in one domain */ |
Mike Day | cdc7b83 | 2008-12-12 17:16:30 +0100 | [diff] [blame] | 258 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 259 | |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 260 | /* domain represents a virtual machine, more than one devices |
| 261 | * across iommus may be owned in one domain, e.g. kvm guest. |
| 262 | */ |
| 263 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) |
| 264 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 265 | /* si_domain contains mulitple devices */ |
| 266 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) |
| 267 | |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 268 | struct dmar_domain { |
| 269 | int id; /* domain id */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 270 | unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 271 | |
| 272 | struct list_head devices; /* all devices' list */ |
| 273 | struct iova_domain iovad; /* iova's that belong to this domain */ |
| 274 | |
| 275 | struct dma_pte *pgd; /* virtual address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 276 | int gaw; /* max guest address width */ |
| 277 | |
| 278 | /* adjusted guest address width, 0 is level 2 30-bit */ |
| 279 | int agaw; |
| 280 | |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 281 | int flags; /* flags to find out type of domain */ |
Weidong Han | 8e60409 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 282 | |
| 283 | int iommu_coherency;/* indicate coherency of iommu access */ |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 284 | int iommu_snooping; /* indicate snooping control feature*/ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 285 | int iommu_count; /* reference count of iommu */ |
| 286 | spinlock_t iommu_lock; /* protect iommu set in domain */ |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 287 | u64 max_addr; /* maximum mapped address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 288 | }; |
| 289 | |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 290 | /* PCI domain-device relationship */ |
| 291 | struct device_domain_info { |
| 292 | struct list_head link; /* link to domain siblings */ |
| 293 | struct list_head global; /* link to global list */ |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 294 | int segment; /* PCI domain */ |
| 295 | u8 bus; /* PCI bus number */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 296 | u8 devfn; /* PCI devfn number */ |
| 297 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 298 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 299 | struct dmar_domain *domain; /* pointer to domain */ |
| 300 | }; |
| 301 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 302 | static void flush_unmaps_timeout(unsigned long data); |
| 303 | |
| 304 | DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
| 305 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 306 | #define HIGH_WATER_MARK 250 |
| 307 | struct deferred_flush_tables { |
| 308 | int next; |
| 309 | struct iova *iova[HIGH_WATER_MARK]; |
| 310 | struct dmar_domain *domain[HIGH_WATER_MARK]; |
| 311 | }; |
| 312 | |
| 313 | static struct deferred_flush_tables *deferred_flush; |
| 314 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 315 | /* bitmap for indexing intel_iommus */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 316 | static int g_num_of_iommus; |
| 317 | |
| 318 | static DEFINE_SPINLOCK(async_umap_flush_lock); |
| 319 | static LIST_HEAD(unmaps_to_do); |
| 320 | |
| 321 | static int timer_on; |
| 322 | static long list_size; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 323 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 324 | static void domain_remove_dev_info(struct dmar_domain *domain); |
| 325 | |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 326 | #ifdef CONFIG_DMAR_DEFAULT_ON |
| 327 | int dmar_disabled = 0; |
| 328 | #else |
| 329 | int dmar_disabled = 1; |
| 330 | #endif /*CONFIG_DMAR_DEFAULT_ON*/ |
| 331 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 332 | static int __initdata dmar_map_gfx = 1; |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 333 | static int dmar_forcedac; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 334 | static int intel_iommu_strict; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 335 | |
| 336 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
| 337 | static DEFINE_SPINLOCK(device_domain_lock); |
| 338 | static LIST_HEAD(device_domain_list); |
| 339 | |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 340 | static struct iommu_ops intel_iommu_ops; |
| 341 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 342 | static int __init intel_iommu_setup(char *str) |
| 343 | { |
| 344 | if (!str) |
| 345 | return -EINVAL; |
| 346 | while (*str) { |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 347 | if (!strncmp(str, "on", 2)) { |
| 348 | dmar_disabled = 0; |
| 349 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); |
| 350 | } else if (!strncmp(str, "off", 3)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 351 | dmar_disabled = 1; |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 352 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 353 | } else if (!strncmp(str, "igfx_off", 8)) { |
| 354 | dmar_map_gfx = 0; |
| 355 | printk(KERN_INFO |
| 356 | "Intel-IOMMU: disable GFX device mapping\n"); |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 357 | } else if (!strncmp(str, "forcedac", 8)) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 358 | printk(KERN_INFO |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 359 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
| 360 | dmar_forcedac = 1; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 361 | } else if (!strncmp(str, "strict", 6)) { |
| 362 | printk(KERN_INFO |
| 363 | "Intel-IOMMU: disable batched IOTLB flush\n"); |
| 364 | intel_iommu_strict = 1; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | str += strcspn(str, ","); |
| 368 | while (*str == ',') |
| 369 | str++; |
| 370 | } |
| 371 | return 0; |
| 372 | } |
| 373 | __setup("intel_iommu=", intel_iommu_setup); |
| 374 | |
| 375 | static struct kmem_cache *iommu_domain_cache; |
| 376 | static struct kmem_cache *iommu_devinfo_cache; |
| 377 | static struct kmem_cache *iommu_iova_cache; |
| 378 | |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 379 | static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep) |
| 380 | { |
| 381 | unsigned int flags; |
| 382 | void *vaddr; |
| 383 | |
| 384 | /* trying to avoid low memory issues */ |
| 385 | flags = current->flags & PF_MEMALLOC; |
| 386 | current->flags |= PF_MEMALLOC; |
| 387 | vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC); |
| 388 | current->flags &= (~PF_MEMALLOC | flags); |
| 389 | return vaddr; |
| 390 | } |
| 391 | |
| 392 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 393 | static inline void *alloc_pgtable_page(void) |
| 394 | { |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 395 | unsigned int flags; |
| 396 | void *vaddr; |
| 397 | |
| 398 | /* trying to avoid low memory issues */ |
| 399 | flags = current->flags & PF_MEMALLOC; |
| 400 | current->flags |= PF_MEMALLOC; |
| 401 | vaddr = (void *)get_zeroed_page(GFP_ATOMIC); |
| 402 | current->flags &= (~PF_MEMALLOC | flags); |
| 403 | return vaddr; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | static inline void free_pgtable_page(void *vaddr) |
| 407 | { |
| 408 | free_page((unsigned long)vaddr); |
| 409 | } |
| 410 | |
| 411 | static inline void *alloc_domain_mem(void) |
| 412 | { |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 413 | return iommu_kmem_cache_alloc(iommu_domain_cache); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 414 | } |
| 415 | |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 416 | static void free_domain_mem(void *vaddr) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 417 | { |
| 418 | kmem_cache_free(iommu_domain_cache, vaddr); |
| 419 | } |
| 420 | |
| 421 | static inline void * alloc_devinfo_mem(void) |
| 422 | { |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 423 | return iommu_kmem_cache_alloc(iommu_devinfo_cache); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | static inline void free_devinfo_mem(void *vaddr) |
| 427 | { |
| 428 | kmem_cache_free(iommu_devinfo_cache, vaddr); |
| 429 | } |
| 430 | |
| 431 | struct iova *alloc_iova_mem(void) |
| 432 | { |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 433 | return iommu_kmem_cache_alloc(iommu_iova_cache); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 434 | } |
| 435 | |
| 436 | void free_iova_mem(struct iova *iova) |
| 437 | { |
| 438 | kmem_cache_free(iommu_iova_cache, iova); |
| 439 | } |
| 440 | |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 441 | |
| 442 | static inline int width_to_agaw(int width); |
| 443 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 444 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 445 | { |
| 446 | unsigned long sagaw; |
| 447 | int agaw = -1; |
| 448 | |
| 449 | sagaw = cap_sagaw(iommu->cap); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 450 | for (agaw = width_to_agaw(max_gaw); |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 451 | agaw >= 0; agaw--) { |
| 452 | if (test_bit(agaw, &sagaw)) |
| 453 | break; |
| 454 | } |
| 455 | |
| 456 | return agaw; |
| 457 | } |
| 458 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 459 | /* |
| 460 | * Calculate max SAGAW for each iommu. |
| 461 | */ |
| 462 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) |
| 463 | { |
| 464 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); |
| 465 | } |
| 466 | |
| 467 | /* |
| 468 | * calculate agaw for each iommu. |
| 469 | * "SAGAW" may be different across iommus, use a default agaw, and |
| 470 | * get a supported less agaw for iommus that don't support the default agaw. |
| 471 | */ |
| 472 | int iommu_calculate_agaw(struct intel_iommu *iommu) |
| 473 | { |
| 474 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 475 | } |
| 476 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 477 | /* This functionin only returns single iommu in a domain */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 478 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
| 479 | { |
| 480 | int iommu_id; |
| 481 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 482 | /* si_domain and vm domain should not get here. */ |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 483 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 484 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 485 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 486 | iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
| 487 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
| 488 | return NULL; |
| 489 | |
| 490 | return g_iommus[iommu_id]; |
| 491 | } |
| 492 | |
Weidong Han | 8e60409 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 493 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
| 494 | { |
| 495 | int i; |
| 496 | |
| 497 | domain->iommu_coherency = 1; |
| 498 | |
| 499 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
| 500 | for (; i < g_num_of_iommus; ) { |
| 501 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
| 502 | domain->iommu_coherency = 0; |
| 503 | break; |
| 504 | } |
| 505 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); |
| 506 | } |
| 507 | } |
| 508 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 509 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
| 510 | { |
| 511 | int i; |
| 512 | |
| 513 | domain->iommu_snooping = 1; |
| 514 | |
| 515 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
| 516 | for (; i < g_num_of_iommus; ) { |
| 517 | if (!ecap_sc_support(g_iommus[i]->ecap)) { |
| 518 | domain->iommu_snooping = 0; |
| 519 | break; |
| 520 | } |
| 521 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | /* Some capabilities may be different across iommus */ |
| 526 | static void domain_update_iommu_cap(struct dmar_domain *domain) |
| 527 | { |
| 528 | domain_update_iommu_coherency(domain); |
| 529 | domain_update_iommu_snooping(domain); |
| 530 | } |
| 531 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 532 | static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 533 | { |
| 534 | struct dmar_drhd_unit *drhd = NULL; |
| 535 | int i; |
| 536 | |
| 537 | for_each_drhd_unit(drhd) { |
| 538 | if (drhd->ignored) |
| 539 | continue; |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 540 | if (segment != drhd->segment) |
| 541 | continue; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 542 | |
David Woodhouse | 924b623 | 2009-04-04 00:39:25 +0100 | [diff] [blame] | 543 | for (i = 0; i < drhd->devices_cnt; i++) { |
Dirk Hohndel | 288e487 | 2009-01-11 15:33:51 +0000 | [diff] [blame] | 544 | if (drhd->devices[i] && |
| 545 | drhd->devices[i]->bus->number == bus && |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 546 | drhd->devices[i]->devfn == devfn) |
| 547 | return drhd->iommu; |
David Woodhouse | 4958c5d | 2009-04-06 13:30:01 -0700 | [diff] [blame] | 548 | if (drhd->devices[i] && |
| 549 | drhd->devices[i]->subordinate && |
David Woodhouse | 924b623 | 2009-04-04 00:39:25 +0100 | [diff] [blame] | 550 | drhd->devices[i]->subordinate->number <= bus && |
| 551 | drhd->devices[i]->subordinate->subordinate >= bus) |
| 552 | return drhd->iommu; |
| 553 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 554 | |
| 555 | if (drhd->include_all) |
| 556 | return drhd->iommu; |
| 557 | } |
| 558 | |
| 559 | return NULL; |
| 560 | } |
| 561 | |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 562 | static void domain_flush_cache(struct dmar_domain *domain, |
| 563 | void *addr, int size) |
| 564 | { |
| 565 | if (!domain->iommu_coherency) |
| 566 | clflush_cache_range(addr, size); |
| 567 | } |
| 568 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 569 | /* Gets context entry for a given bus and devfn */ |
| 570 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, |
| 571 | u8 bus, u8 devfn) |
| 572 | { |
| 573 | struct root_entry *root; |
| 574 | struct context_entry *context; |
| 575 | unsigned long phy_addr; |
| 576 | unsigned long flags; |
| 577 | |
| 578 | spin_lock_irqsave(&iommu->lock, flags); |
| 579 | root = &iommu->root_entry[bus]; |
| 580 | context = get_context_addr_from_root(root); |
| 581 | if (!context) { |
| 582 | context = (struct context_entry *)alloc_pgtable_page(); |
| 583 | if (!context) { |
| 584 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 585 | return NULL; |
| 586 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 587 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 588 | phy_addr = virt_to_phys((void *)context); |
| 589 | set_root_value(root, phy_addr); |
| 590 | set_root_present(root); |
| 591 | __iommu_flush_cache(iommu, root, sizeof(*root)); |
| 592 | } |
| 593 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 594 | return &context[devfn]; |
| 595 | } |
| 596 | |
| 597 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 598 | { |
| 599 | struct root_entry *root; |
| 600 | struct context_entry *context; |
| 601 | int ret; |
| 602 | unsigned long flags; |
| 603 | |
| 604 | spin_lock_irqsave(&iommu->lock, flags); |
| 605 | root = &iommu->root_entry[bus]; |
| 606 | context = get_context_addr_from_root(root); |
| 607 | if (!context) { |
| 608 | ret = 0; |
| 609 | goto out; |
| 610 | } |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 611 | ret = context_present(&context[devfn]); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 612 | out: |
| 613 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 614 | return ret; |
| 615 | } |
| 616 | |
| 617 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 618 | { |
| 619 | struct root_entry *root; |
| 620 | struct context_entry *context; |
| 621 | unsigned long flags; |
| 622 | |
| 623 | spin_lock_irqsave(&iommu->lock, flags); |
| 624 | root = &iommu->root_entry[bus]; |
| 625 | context = get_context_addr_from_root(root); |
| 626 | if (context) { |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 627 | context_clear_entry(&context[devfn]); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 628 | __iommu_flush_cache(iommu, &context[devfn], \ |
| 629 | sizeof(*context)); |
| 630 | } |
| 631 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 632 | } |
| 633 | |
| 634 | static void free_context_table(struct intel_iommu *iommu) |
| 635 | { |
| 636 | struct root_entry *root; |
| 637 | int i; |
| 638 | unsigned long flags; |
| 639 | struct context_entry *context; |
| 640 | |
| 641 | spin_lock_irqsave(&iommu->lock, flags); |
| 642 | if (!iommu->root_entry) { |
| 643 | goto out; |
| 644 | } |
| 645 | for (i = 0; i < ROOT_ENTRY_NR; i++) { |
| 646 | root = &iommu->root_entry[i]; |
| 647 | context = get_context_addr_from_root(root); |
| 648 | if (context) |
| 649 | free_pgtable_page(context); |
| 650 | } |
| 651 | free_pgtable_page(iommu->root_entry); |
| 652 | iommu->root_entry = NULL; |
| 653 | out: |
| 654 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 655 | } |
| 656 | |
| 657 | /* page table handling */ |
| 658 | #define LEVEL_STRIDE (9) |
| 659 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) |
| 660 | |
| 661 | static inline int agaw_to_level(int agaw) |
| 662 | { |
| 663 | return agaw + 2; |
| 664 | } |
| 665 | |
| 666 | static inline int agaw_to_width(int agaw) |
| 667 | { |
| 668 | return 30 + agaw * LEVEL_STRIDE; |
| 669 | |
| 670 | } |
| 671 | |
| 672 | static inline int width_to_agaw(int width) |
| 673 | { |
| 674 | return (width - 30) / LEVEL_STRIDE; |
| 675 | } |
| 676 | |
| 677 | static inline unsigned int level_to_offset_bits(int level) |
| 678 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 679 | return (level - 1) * LEVEL_STRIDE; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 680 | } |
| 681 | |
David Woodhouse | 77dfa56 | 2009-06-27 16:40:08 +0100 | [diff] [blame] | 682 | static inline int pfn_level_offset(unsigned long pfn, int level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 683 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 684 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 685 | } |
| 686 | |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 687 | static inline unsigned long level_mask(int level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 688 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 689 | return -1UL << level_to_offset_bits(level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 690 | } |
| 691 | |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 692 | static inline unsigned long level_size(int level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 693 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 694 | return 1UL << level_to_offset_bits(level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 695 | } |
| 696 | |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 697 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 698 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 699 | return (pfn + level_size(level) - 1) & level_mask(level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 700 | } |
| 701 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 702 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
| 703 | unsigned long pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 704 | { |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 705 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 706 | struct dma_pte *parent, *pte = NULL; |
| 707 | int level = agaw_to_level(domain->agaw); |
| 708 | int offset; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 709 | |
| 710 | BUG_ON(!domain->pgd); |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 711 | BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 712 | parent = domain->pgd; |
| 713 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 714 | while (level > 0) { |
| 715 | void *tmp_page; |
| 716 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 717 | offset = pfn_level_offset(pfn, level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 718 | pte = &parent[offset]; |
| 719 | if (level == 1) |
| 720 | break; |
| 721 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 722 | if (!dma_pte_present(pte)) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 723 | uint64_t pteval; |
| 724 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 725 | tmp_page = alloc_pgtable_page(); |
| 726 | |
David Woodhouse | 206a73c | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 727 | if (!tmp_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 728 | return NULL; |
David Woodhouse | 206a73c | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 729 | |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 730 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
| 731 | pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
| 732 | if (cmpxchg64(&pte->val, 0ULL, pteval)) { |
| 733 | /* Someone else set it while we were thinking; use theirs. */ |
| 734 | free_pgtable_page(tmp_page); |
| 735 | } else { |
| 736 | dma_pte_addr(pte); |
| 737 | domain_flush_cache(domain, pte, sizeof(*pte)); |
| 738 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 739 | } |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 740 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 741 | level--; |
| 742 | } |
| 743 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 744 | return pte; |
| 745 | } |
| 746 | |
| 747 | /* return address's pte at specific level */ |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 748 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
| 749 | unsigned long pfn, |
| 750 | int level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 751 | { |
| 752 | struct dma_pte *parent, *pte = NULL; |
| 753 | int total = agaw_to_level(domain->agaw); |
| 754 | int offset; |
| 755 | |
| 756 | parent = domain->pgd; |
| 757 | while (level <= total) { |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 758 | offset = pfn_level_offset(pfn, total); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 759 | pte = &parent[offset]; |
| 760 | if (level == total) |
| 761 | return pte; |
| 762 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 763 | if (!dma_pte_present(pte)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 764 | break; |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 765 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 766 | total--; |
| 767 | } |
| 768 | return NULL; |
| 769 | } |
| 770 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 771 | /* clear last level pte, a tlb flush should be followed */ |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 772 | static void dma_pte_clear_range(struct dmar_domain *domain, |
| 773 | unsigned long start_pfn, |
| 774 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 775 | { |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 776 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 777 | struct dma_pte *first_pte, *pte; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 778 | |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 779 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 780 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
David Woodhouse | 66eae84 | 2009-06-27 19:00:32 +0100 | [diff] [blame] | 781 | |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 782 | /* we don't need lock here; nobody else touches the iova range */ |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 783 | while (start_pfn <= last_pfn) { |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 784 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1); |
| 785 | if (!pte) { |
| 786 | start_pfn = align_to_level(start_pfn + 1, 2); |
| 787 | continue; |
| 788 | } |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 789 | do { |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 790 | dma_clear_pte(pte); |
| 791 | start_pfn++; |
| 792 | pte++; |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 793 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
| 794 | |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 795 | domain_flush_cache(domain, first_pte, |
| 796 | (void *)pte - (void *)first_pte); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 797 | } |
| 798 | } |
| 799 | |
| 800 | /* free page table pages. last level pte should already be cleared */ |
| 801 | static void dma_pte_free_pagetable(struct dmar_domain *domain, |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 802 | unsigned long start_pfn, |
| 803 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 804 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 805 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 806 | struct dma_pte *first_pte, *pte; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 807 | int total = agaw_to_level(domain->agaw); |
| 808 | int level; |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 809 | unsigned long tmp; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 810 | |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 811 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
| 812 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 813 | |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 814 | /* We don't need lock here; nobody else touches the iova range */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 815 | level = 2; |
| 816 | while (level <= total) { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 817 | tmp = align_to_level(start_pfn, level); |
| 818 | |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 819 | /* If we can't even clear one PTE at this level, we're done */ |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 820 | if (tmp + level_size(level) - 1 > last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 821 | return; |
| 822 | |
David Woodhouse | 3d7b0e4 | 2009-06-30 03:38:09 +0100 | [diff] [blame] | 823 | while (tmp + level_size(level) - 1 <= last_pfn) { |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 824 | first_pte = pte = dma_pfn_level_pte(domain, tmp, level); |
| 825 | if (!pte) { |
| 826 | tmp = align_to_level(tmp + 1, level + 1); |
| 827 | continue; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 828 | } |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 829 | do { |
David Woodhouse | 6a43e57 | 2009-07-02 12:02:34 +0100 | [diff] [blame] | 830 | if (dma_pte_present(pte)) { |
| 831 | free_pgtable_page(phys_to_virt(dma_pte_addr(pte))); |
| 832 | dma_clear_pte(pte); |
| 833 | } |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 834 | pte++; |
| 835 | tmp += level_size(level); |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 836 | } while (!first_pte_in_page(pte) && |
| 837 | tmp + level_size(level) - 1 <= last_pfn); |
| 838 | |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 839 | domain_flush_cache(domain, first_pte, |
| 840 | (void *)pte - (void *)first_pte); |
| 841 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 842 | } |
| 843 | level++; |
| 844 | } |
| 845 | /* free pgd */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 846 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 847 | free_pgtable_page(domain->pgd); |
| 848 | domain->pgd = NULL; |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | /* iommu handling */ |
| 853 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) |
| 854 | { |
| 855 | struct root_entry *root; |
| 856 | unsigned long flags; |
| 857 | |
| 858 | root = (struct root_entry *)alloc_pgtable_page(); |
| 859 | if (!root) |
| 860 | return -ENOMEM; |
| 861 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 862 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 863 | |
| 864 | spin_lock_irqsave(&iommu->lock, flags); |
| 865 | iommu->root_entry = root; |
| 866 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 871 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
| 872 | { |
| 873 | void *addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 874 | u32 sts; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 875 | unsigned long flag; |
| 876 | |
| 877 | addr = iommu->root_entry; |
| 878 | |
| 879 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 880 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
| 881 | |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 882 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 883 | |
| 884 | /* Make sure hardware complete it */ |
| 885 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 886 | readl, (sts & DMA_GSTS_RTPS), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 887 | |
| 888 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 889 | } |
| 890 | |
| 891 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) |
| 892 | { |
| 893 | u32 val; |
| 894 | unsigned long flag; |
| 895 | |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 896 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 897 | return; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 898 | |
| 899 | spin_lock_irqsave(&iommu->register_lock, flag); |
David Woodhouse | 462b60f | 2009-05-10 20:18:18 +0100 | [diff] [blame] | 900 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 901 | |
| 902 | /* Make sure hardware complete it */ |
| 903 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 904 | readl, (!(val & DMA_GSTS_WBFS)), val); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 905 | |
| 906 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 907 | } |
| 908 | |
| 909 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 910 | static void __iommu_flush_context(struct intel_iommu *iommu, |
| 911 | u16 did, u16 source_id, u8 function_mask, |
| 912 | u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 913 | { |
| 914 | u64 val = 0; |
| 915 | unsigned long flag; |
| 916 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 917 | switch (type) { |
| 918 | case DMA_CCMD_GLOBAL_INVL: |
| 919 | val = DMA_CCMD_GLOBAL_INVL; |
| 920 | break; |
| 921 | case DMA_CCMD_DOMAIN_INVL: |
| 922 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); |
| 923 | break; |
| 924 | case DMA_CCMD_DEVICE_INVL: |
| 925 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) |
| 926 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); |
| 927 | break; |
| 928 | default: |
| 929 | BUG(); |
| 930 | } |
| 931 | val |= DMA_CCMD_ICC; |
| 932 | |
| 933 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 934 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
| 935 | |
| 936 | /* Make sure hardware complete it */ |
| 937 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, |
| 938 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); |
| 939 | |
| 940 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 941 | } |
| 942 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 943 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 944 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
| 945 | u64 addr, unsigned int size_order, u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 946 | { |
| 947 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); |
| 948 | u64 val = 0, val_iva = 0; |
| 949 | unsigned long flag; |
| 950 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 951 | switch (type) { |
| 952 | case DMA_TLB_GLOBAL_FLUSH: |
| 953 | /* global flush doesn't need set IVA_REG */ |
| 954 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; |
| 955 | break; |
| 956 | case DMA_TLB_DSI_FLUSH: |
| 957 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
| 958 | break; |
| 959 | case DMA_TLB_PSI_FLUSH: |
| 960 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
| 961 | /* Note: always flush non-leaf currently */ |
| 962 | val_iva = size_order | addr; |
| 963 | break; |
| 964 | default: |
| 965 | BUG(); |
| 966 | } |
| 967 | /* Note: set drain read/write */ |
| 968 | #if 0 |
| 969 | /* |
| 970 | * This is probably to be super secure.. Looks like we can |
| 971 | * ignore it without any impact. |
| 972 | */ |
| 973 | if (cap_read_drain(iommu->cap)) |
| 974 | val |= DMA_TLB_READ_DRAIN; |
| 975 | #endif |
| 976 | if (cap_write_drain(iommu->cap)) |
| 977 | val |= DMA_TLB_WRITE_DRAIN; |
| 978 | |
| 979 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 980 | /* Note: Only uses first TLB reg currently */ |
| 981 | if (val_iva) |
| 982 | dmar_writeq(iommu->reg + tlb_offset, val_iva); |
| 983 | dmar_writeq(iommu->reg + tlb_offset + 8, val); |
| 984 | |
| 985 | /* Make sure hardware complete it */ |
| 986 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, |
| 987 | dmar_readq, (!(val & DMA_TLB_IVT)), val); |
| 988 | |
| 989 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 990 | |
| 991 | /* check IOTLB invalidation granularity */ |
| 992 | if (DMA_TLB_IAIG(val) == 0) |
| 993 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); |
| 994 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) |
| 995 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 996 | (unsigned long long)DMA_TLB_IIRG(type), |
| 997 | (unsigned long long)DMA_TLB_IAIG(val)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 998 | } |
| 999 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1000 | static struct device_domain_info *iommu_support_dev_iotlb( |
| 1001 | struct dmar_domain *domain, int segment, u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1002 | { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1003 | int found = 0; |
| 1004 | unsigned long flags; |
| 1005 | struct device_domain_info *info; |
| 1006 | struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn); |
| 1007 | |
| 1008 | if (!ecap_dev_iotlb_support(iommu->ecap)) |
| 1009 | return NULL; |
| 1010 | |
| 1011 | if (!iommu->qi) |
| 1012 | return NULL; |
| 1013 | |
| 1014 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1015 | list_for_each_entry(info, &domain->devices, link) |
| 1016 | if (info->bus == bus && info->devfn == devfn) { |
| 1017 | found = 1; |
| 1018 | break; |
| 1019 | } |
| 1020 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1021 | |
| 1022 | if (!found || !info->dev) |
| 1023 | return NULL; |
| 1024 | |
| 1025 | if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS)) |
| 1026 | return NULL; |
| 1027 | |
| 1028 | if (!dmar_find_matched_atsr_unit(info->dev)) |
| 1029 | return NULL; |
| 1030 | |
| 1031 | info->iommu = iommu; |
| 1032 | |
| 1033 | return info; |
| 1034 | } |
| 1035 | |
| 1036 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) |
| 1037 | { |
| 1038 | if (!info) |
| 1039 | return; |
| 1040 | |
| 1041 | pci_enable_ats(info->dev, VTD_PAGE_SHIFT); |
| 1042 | } |
| 1043 | |
| 1044 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) |
| 1045 | { |
| 1046 | if (!info->dev || !pci_ats_enabled(info->dev)) |
| 1047 | return; |
| 1048 | |
| 1049 | pci_disable_ats(info->dev); |
| 1050 | } |
| 1051 | |
| 1052 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, |
| 1053 | u64 addr, unsigned mask) |
| 1054 | { |
| 1055 | u16 sid, qdep; |
| 1056 | unsigned long flags; |
| 1057 | struct device_domain_info *info; |
| 1058 | |
| 1059 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1060 | list_for_each_entry(info, &domain->devices, link) { |
| 1061 | if (!info->dev || !pci_ats_enabled(info->dev)) |
| 1062 | continue; |
| 1063 | |
| 1064 | sid = info->bus << 8 | info->devfn; |
| 1065 | qdep = pci_ats_queue_depth(info->dev); |
| 1066 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
| 1067 | } |
| 1068 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1069 | } |
| 1070 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1071 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 1072 | unsigned long pfn, unsigned int pages) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1073 | { |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1074 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 1075 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1076 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1077 | BUG_ON(pages == 0); |
| 1078 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1079 | /* |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1080 | * Fallback to domain selective flush if no PSI support or the size is |
| 1081 | * too big. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1082 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
| 1083 | * aligned to the size |
| 1084 | */ |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1085 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
| 1086 | iommu->flush.flush_iotlb(iommu, did, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1087 | DMA_TLB_DSI_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1088 | else |
| 1089 | iommu->flush.flush_iotlb(iommu, did, addr, mask, |
| 1090 | DMA_TLB_PSI_FLUSH); |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1091 | |
| 1092 | /* |
| 1093 | * In caching mode, domain ID 0 is reserved for non-present to present |
| 1094 | * mapping flush. Device IOTLB doesn't need to be flushed in this case. |
| 1095 | */ |
| 1096 | if (!cap_caching_mode(iommu->cap) || did) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1097 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1098 | } |
| 1099 | |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1100 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
| 1101 | { |
| 1102 | u32 pmen; |
| 1103 | unsigned long flags; |
| 1104 | |
| 1105 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 1106 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
| 1107 | pmen &= ~DMA_PMEN_EPM; |
| 1108 | writel(pmen, iommu->reg + DMAR_PMEN_REG); |
| 1109 | |
| 1110 | /* wait for the protected region status bit to clear */ |
| 1111 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, |
| 1112 | readl, !(pmen & DMA_PMEN_PRS), pmen); |
| 1113 | |
| 1114 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 1115 | } |
| 1116 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1117 | static int iommu_enable_translation(struct intel_iommu *iommu) |
| 1118 | { |
| 1119 | u32 sts; |
| 1120 | unsigned long flags; |
| 1121 | |
| 1122 | spin_lock_irqsave(&iommu->register_lock, flags); |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1123 | iommu->gcmd |= DMA_GCMD_TE; |
| 1124 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1125 | |
| 1126 | /* Make sure hardware complete it */ |
| 1127 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1128 | readl, (sts & DMA_GSTS_TES), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1129 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1130 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 1131 | return 0; |
| 1132 | } |
| 1133 | |
| 1134 | static int iommu_disable_translation(struct intel_iommu *iommu) |
| 1135 | { |
| 1136 | u32 sts; |
| 1137 | unsigned long flag; |
| 1138 | |
| 1139 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 1140 | iommu->gcmd &= ~DMA_GCMD_TE; |
| 1141 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 1142 | |
| 1143 | /* Make sure hardware complete it */ |
| 1144 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1145 | readl, (!(sts & DMA_GSTS_TES)), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1146 | |
| 1147 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 1148 | return 0; |
| 1149 | } |
| 1150 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 1151 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1152 | static int iommu_init_domains(struct intel_iommu *iommu) |
| 1153 | { |
| 1154 | unsigned long ndomains; |
| 1155 | unsigned long nlongs; |
| 1156 | |
| 1157 | ndomains = cap_ndoms(iommu->cap); |
| 1158 | pr_debug("Number of Domains supportd <%ld>\n", ndomains); |
| 1159 | nlongs = BITS_TO_LONGS(ndomains); |
| 1160 | |
| 1161 | /* TBD: there might be 64K domains, |
| 1162 | * consider other allocation for future chip |
| 1163 | */ |
| 1164 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); |
| 1165 | if (!iommu->domain_ids) { |
| 1166 | printk(KERN_ERR "Allocating domain id array failed\n"); |
| 1167 | return -ENOMEM; |
| 1168 | } |
| 1169 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), |
| 1170 | GFP_KERNEL); |
| 1171 | if (!iommu->domains) { |
| 1172 | printk(KERN_ERR "Allocating domain array failed\n"); |
| 1173 | kfree(iommu->domain_ids); |
| 1174 | return -ENOMEM; |
| 1175 | } |
| 1176 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 1177 | spin_lock_init(&iommu->lock); |
| 1178 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1179 | /* |
| 1180 | * if Caching mode is set, then invalid translations are tagged |
| 1181 | * with domainid 0. Hence we need to pre-allocate it. |
| 1182 | */ |
| 1183 | if (cap_caching_mode(iommu->cap)) |
| 1184 | set_bit(0, iommu->domain_ids); |
| 1185 | return 0; |
| 1186 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1187 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1188 | |
| 1189 | static void domain_exit(struct dmar_domain *domain); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 1190 | static void vm_domain_exit(struct dmar_domain *domain); |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 1191 | |
| 1192 | void free_dmar_iommu(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1193 | { |
| 1194 | struct dmar_domain *domain; |
| 1195 | int i; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1196 | unsigned long flags; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1197 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1198 | i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap)); |
| 1199 | for (; i < cap_ndoms(iommu->cap); ) { |
| 1200 | domain = iommu->domains[i]; |
| 1201 | clear_bit(i, iommu->domain_ids); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1202 | |
| 1203 | spin_lock_irqsave(&domain->iommu_lock, flags); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 1204 | if (--domain->iommu_count == 0) { |
| 1205 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) |
| 1206 | vm_domain_exit(domain); |
| 1207 | else |
| 1208 | domain_exit(domain); |
| 1209 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1210 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
| 1211 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1212 | i = find_next_bit(iommu->domain_ids, |
| 1213 | cap_ndoms(iommu->cap), i+1); |
| 1214 | } |
| 1215 | |
| 1216 | if (iommu->gcmd & DMA_GCMD_TE) |
| 1217 | iommu_disable_translation(iommu); |
| 1218 | |
| 1219 | if (iommu->irq) { |
| 1220 | set_irq_data(iommu->irq, NULL); |
| 1221 | /* This will mask the irq */ |
| 1222 | free_irq(iommu->irq, iommu); |
| 1223 | destroy_irq(iommu->irq); |
| 1224 | } |
| 1225 | |
| 1226 | kfree(iommu->domains); |
| 1227 | kfree(iommu->domain_ids); |
| 1228 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 1229 | g_iommus[iommu->seq_id] = NULL; |
| 1230 | |
| 1231 | /* if all iommus are freed, free g_iommus */ |
| 1232 | for (i = 0; i < g_num_of_iommus; i++) { |
| 1233 | if (g_iommus[i]) |
| 1234 | break; |
| 1235 | } |
| 1236 | |
| 1237 | if (i == g_num_of_iommus) |
| 1238 | kfree(g_iommus); |
| 1239 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1240 | /* free context mapping */ |
| 1241 | free_context_table(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1242 | } |
| 1243 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1244 | static struct dmar_domain *alloc_domain(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1245 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1246 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1247 | |
| 1248 | domain = alloc_domain_mem(); |
| 1249 | if (!domain) |
| 1250 | return NULL; |
| 1251 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1252 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); |
Weidong Han | d71a2f3 | 2008-12-07 21:13:41 +0800 | [diff] [blame] | 1253 | domain->flags = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1254 | |
| 1255 | return domain; |
| 1256 | } |
| 1257 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1258 | static int iommu_attach_domain(struct dmar_domain *domain, |
| 1259 | struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1260 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1261 | int num; |
| 1262 | unsigned long ndomains; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1263 | unsigned long flags; |
| 1264 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1265 | ndomains = cap_ndoms(iommu->cap); |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1266 | |
| 1267 | spin_lock_irqsave(&iommu->lock, flags); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1268 | |
| 1269 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
| 1270 | if (num >= ndomains) { |
| 1271 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1272 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
| 1273 | return -ENOMEM; |
| 1274 | } |
| 1275 | |
| 1276 | domain->id = num; |
| 1277 | set_bit(num, iommu->domain_ids); |
| 1278 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
| 1279 | iommu->domains[num] = domain; |
| 1280 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1281 | |
| 1282 | return 0; |
| 1283 | } |
| 1284 | |
| 1285 | static void iommu_detach_domain(struct dmar_domain *domain, |
| 1286 | struct intel_iommu *iommu) |
| 1287 | { |
| 1288 | unsigned long flags; |
| 1289 | int num, ndomains; |
| 1290 | int found = 0; |
| 1291 | |
| 1292 | spin_lock_irqsave(&iommu->lock, flags); |
| 1293 | ndomains = cap_ndoms(iommu->cap); |
| 1294 | num = find_first_bit(iommu->domain_ids, ndomains); |
| 1295 | for (; num < ndomains; ) { |
| 1296 | if (iommu->domains[num] == domain) { |
| 1297 | found = 1; |
| 1298 | break; |
| 1299 | } |
| 1300 | num = find_next_bit(iommu->domain_ids, |
| 1301 | cap_ndoms(iommu->cap), num+1); |
| 1302 | } |
| 1303 | |
| 1304 | if (found) { |
| 1305 | clear_bit(num, iommu->domain_ids); |
| 1306 | clear_bit(iommu->seq_id, &domain->iommu_bmp); |
| 1307 | iommu->domains[num] = NULL; |
| 1308 | } |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1309 | spin_unlock_irqrestore(&iommu->lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1310 | } |
| 1311 | |
| 1312 | static struct iova_domain reserved_iova_list; |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1313 | static struct lock_class_key reserved_alloc_key; |
| 1314 | static struct lock_class_key reserved_rbtree_key; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1315 | |
| 1316 | static void dmar_init_reserved_ranges(void) |
| 1317 | { |
| 1318 | struct pci_dev *pdev = NULL; |
| 1319 | struct iova *iova; |
| 1320 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1321 | |
David Miller | f661197 | 2008-02-06 01:36:23 -0800 | [diff] [blame] | 1322 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1323 | |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1324 | lockdep_set_class(&reserved_iova_list.iova_alloc_lock, |
| 1325 | &reserved_alloc_key); |
| 1326 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
| 1327 | &reserved_rbtree_key); |
| 1328 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1329 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
| 1330 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), |
| 1331 | IOVA_PFN(IOAPIC_RANGE_END)); |
| 1332 | if (!iova) |
| 1333 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); |
| 1334 | |
| 1335 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ |
| 1336 | for_each_pci_dev(pdev) { |
| 1337 | struct resource *r; |
| 1338 | |
| 1339 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 1340 | r = &pdev->resource[i]; |
| 1341 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) |
| 1342 | continue; |
David Woodhouse | 1a4a455 | 2009-06-28 16:00:42 +0100 | [diff] [blame] | 1343 | iova = reserve_iova(&reserved_iova_list, |
| 1344 | IOVA_PFN(r->start), |
| 1345 | IOVA_PFN(r->end)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1346 | if (!iova) |
| 1347 | printk(KERN_ERR "Reserve iova failed\n"); |
| 1348 | } |
| 1349 | } |
| 1350 | |
| 1351 | } |
| 1352 | |
| 1353 | static void domain_reserve_special_ranges(struct dmar_domain *domain) |
| 1354 | { |
| 1355 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); |
| 1356 | } |
| 1357 | |
| 1358 | static inline int guestwidth_to_adjustwidth(int gaw) |
| 1359 | { |
| 1360 | int agaw; |
| 1361 | int r = (gaw - 12) % 9; |
| 1362 | |
| 1363 | if (r == 0) |
| 1364 | agaw = gaw; |
| 1365 | else |
| 1366 | agaw = gaw + 9 - r; |
| 1367 | if (agaw > 64) |
| 1368 | agaw = 64; |
| 1369 | return agaw; |
| 1370 | } |
| 1371 | |
| 1372 | static int domain_init(struct dmar_domain *domain, int guest_width) |
| 1373 | { |
| 1374 | struct intel_iommu *iommu; |
| 1375 | int adjust_width, agaw; |
| 1376 | unsigned long sagaw; |
| 1377 | |
David Miller | f661197 | 2008-02-06 01:36:23 -0800 | [diff] [blame] | 1378 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1379 | spin_lock_init(&domain->iommu_lock); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1380 | |
| 1381 | domain_reserve_special_ranges(domain); |
| 1382 | |
| 1383 | /* calculate AGAW */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1384 | iommu = domain_get_iommu(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1385 | if (guest_width > cap_mgaw(iommu->cap)) |
| 1386 | guest_width = cap_mgaw(iommu->cap); |
| 1387 | domain->gaw = guest_width; |
| 1388 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 1389 | agaw = width_to_agaw(adjust_width); |
| 1390 | sagaw = cap_sagaw(iommu->cap); |
| 1391 | if (!test_bit(agaw, &sagaw)) { |
| 1392 | /* hardware doesn't support it, choose a bigger one */ |
| 1393 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); |
| 1394 | agaw = find_next_bit(&sagaw, 5, agaw); |
| 1395 | if (agaw >= 5) |
| 1396 | return -ENODEV; |
| 1397 | } |
| 1398 | domain->agaw = agaw; |
| 1399 | INIT_LIST_HEAD(&domain->devices); |
| 1400 | |
Weidong Han | 8e60409 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 1401 | if (ecap_coherent(iommu->ecap)) |
| 1402 | domain->iommu_coherency = 1; |
| 1403 | else |
| 1404 | domain->iommu_coherency = 0; |
| 1405 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 1406 | if (ecap_sc_support(iommu->ecap)) |
| 1407 | domain->iommu_snooping = 1; |
| 1408 | else |
| 1409 | domain->iommu_snooping = 0; |
| 1410 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1411 | domain->iommu_count = 1; |
| 1412 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1413 | /* always allocate the top pgd */ |
| 1414 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); |
| 1415 | if (!domain->pgd) |
| 1416 | return -ENOMEM; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1417 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1418 | return 0; |
| 1419 | } |
| 1420 | |
| 1421 | static void domain_exit(struct dmar_domain *domain) |
| 1422 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1423 | struct dmar_drhd_unit *drhd; |
| 1424 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1425 | |
| 1426 | /* Domain 0 is reserved, so dont process it */ |
| 1427 | if (!domain) |
| 1428 | return; |
| 1429 | |
| 1430 | domain_remove_dev_info(domain); |
| 1431 | /* destroy iovas */ |
| 1432 | put_iova_domain(&domain->iovad); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1433 | |
| 1434 | /* clear ptes */ |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 1435 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1436 | |
| 1437 | /* free page tables */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 1438 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1439 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1440 | for_each_active_iommu(iommu, drhd) |
| 1441 | if (test_bit(iommu->seq_id, &domain->iommu_bmp)) |
| 1442 | iommu_detach_domain(domain, iommu); |
| 1443 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1444 | free_domain_mem(domain); |
| 1445 | } |
| 1446 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1447 | static int domain_context_mapping_one(struct dmar_domain *domain, int segment, |
| 1448 | u8 bus, u8 devfn, int translation) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1449 | { |
| 1450 | struct context_entry *context; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1451 | unsigned long flags; |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1452 | struct intel_iommu *iommu; |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1453 | struct dma_pte *pgd; |
| 1454 | unsigned long num; |
| 1455 | unsigned long ndomains; |
| 1456 | int id; |
| 1457 | int agaw; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1458 | struct device_domain_info *info = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1459 | |
| 1460 | pr_debug("Set context mapping for %02x:%02x.%d\n", |
| 1461 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1462 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1463 | BUG_ON(!domain->pgd); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1464 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
| 1465 | translation != CONTEXT_TT_MULTI_LEVEL); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1466 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1467 | iommu = device_to_iommu(segment, bus, devfn); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1468 | if (!iommu) |
| 1469 | return -ENODEV; |
| 1470 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1471 | context = device_to_context_entry(iommu, bus, devfn); |
| 1472 | if (!context) |
| 1473 | return -ENOMEM; |
| 1474 | spin_lock_irqsave(&iommu->lock, flags); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 1475 | if (context_present(context)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1476 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1480 | id = domain->id; |
| 1481 | pgd = domain->pgd; |
| 1482 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1483 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
| 1484 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1485 | int found = 0; |
| 1486 | |
| 1487 | /* find an available domain id for this device in iommu */ |
| 1488 | ndomains = cap_ndoms(iommu->cap); |
| 1489 | num = find_first_bit(iommu->domain_ids, ndomains); |
| 1490 | for (; num < ndomains; ) { |
| 1491 | if (iommu->domains[num] == domain) { |
| 1492 | id = num; |
| 1493 | found = 1; |
| 1494 | break; |
| 1495 | } |
| 1496 | num = find_next_bit(iommu->domain_ids, |
| 1497 | cap_ndoms(iommu->cap), num+1); |
| 1498 | } |
| 1499 | |
| 1500 | if (found == 0) { |
| 1501 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
| 1502 | if (num >= ndomains) { |
| 1503 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1504 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
| 1505 | return -EFAULT; |
| 1506 | } |
| 1507 | |
| 1508 | set_bit(num, iommu->domain_ids); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1509 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1510 | iommu->domains[num] = domain; |
| 1511 | id = num; |
| 1512 | } |
| 1513 | |
| 1514 | /* Skip top levels of page tables for |
| 1515 | * iommu which has less agaw than default. |
| 1516 | */ |
| 1517 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { |
| 1518 | pgd = phys_to_virt(dma_pte_addr(pgd)); |
| 1519 | if (!dma_pte_present(pgd)) { |
| 1520 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1521 | return -ENOMEM; |
| 1522 | } |
| 1523 | } |
| 1524 | } |
| 1525 | |
| 1526 | context_set_domain_id(context, id); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1527 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1528 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
| 1529 | info = iommu_support_dev_iotlb(domain, segment, bus, devfn); |
| 1530 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
| 1531 | CONTEXT_TT_MULTI_LEVEL; |
| 1532 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1533 | /* |
| 1534 | * In pass through mode, AW must be programmed to indicate the largest |
| 1535 | * AGAW value supported by hardware. And ASR is ignored by hardware. |
| 1536 | */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1537 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1538 | context_set_address_width(context, iommu->msagaw); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1539 | else { |
| 1540 | context_set_address_root(context, virt_to_phys(pgd)); |
| 1541 | context_set_address_width(context, iommu->agaw); |
| 1542 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1543 | |
| 1544 | context_set_translation_type(context, translation); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 1545 | context_set_fault_enable(context); |
| 1546 | context_set_present(context); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1547 | domain_flush_cache(domain, context, sizeof(*context)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1548 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1549 | /* |
| 1550 | * It's a non-present to present mapping. If hardware doesn't cache |
| 1551 | * non-present entry we only need to flush the write-buffer. If the |
| 1552 | * _does_ cache non-present entries, then it does so in the special |
| 1553 | * domain #0, which we have to flush: |
| 1554 | */ |
| 1555 | if (cap_caching_mode(iommu->cap)) { |
| 1556 | iommu->flush.flush_context(iommu, 0, |
| 1557 | (((u16)bus) << 8) | devfn, |
| 1558 | DMA_CCMD_MASK_NOBIT, |
| 1559 | DMA_CCMD_DEVICE_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1560 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1561 | } else { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1562 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1563 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1564 | iommu_enable_dev_iotlb(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1565 | spin_unlock_irqrestore(&iommu->lock, flags); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1566 | |
| 1567 | spin_lock_irqsave(&domain->iommu_lock, flags); |
| 1568 | if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) { |
| 1569 | domain->iommu_count++; |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 1570 | domain_update_iommu_cap(domain); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1571 | } |
| 1572 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1573 | return 0; |
| 1574 | } |
| 1575 | |
| 1576 | static int |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1577 | domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, |
| 1578 | int translation) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1579 | { |
| 1580 | int ret; |
| 1581 | struct pci_dev *tmp, *parent; |
| 1582 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1583 | ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus), |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1584 | pdev->bus->number, pdev->devfn, |
| 1585 | translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1586 | if (ret) |
| 1587 | return ret; |
| 1588 | |
| 1589 | /* dependent device mapping */ |
| 1590 | tmp = pci_find_upstream_pcie_bridge(pdev); |
| 1591 | if (!tmp) |
| 1592 | return 0; |
| 1593 | /* Secondary interface's bus number and devfn 0 */ |
| 1594 | parent = pdev->bus->self; |
| 1595 | while (parent != tmp) { |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1596 | ret = domain_context_mapping_one(domain, |
| 1597 | pci_domain_nr(parent->bus), |
| 1598 | parent->bus->number, |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1599 | parent->devfn, translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1600 | if (ret) |
| 1601 | return ret; |
| 1602 | parent = parent->bus->self; |
| 1603 | } |
| 1604 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ |
| 1605 | return domain_context_mapping_one(domain, |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1606 | pci_domain_nr(tmp->subordinate), |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1607 | tmp->subordinate->number, 0, |
| 1608 | translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1609 | else /* this is a legacy PCI bridge */ |
| 1610 | return domain_context_mapping_one(domain, |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1611 | pci_domain_nr(tmp->bus), |
| 1612 | tmp->bus->number, |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1613 | tmp->devfn, |
| 1614 | translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1615 | } |
| 1616 | |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1617 | static int domain_context_mapped(struct pci_dev *pdev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1618 | { |
| 1619 | int ret; |
| 1620 | struct pci_dev *tmp, *parent; |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1621 | struct intel_iommu *iommu; |
| 1622 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1623 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
| 1624 | pdev->devfn); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1625 | if (!iommu) |
| 1626 | return -ENODEV; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1627 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1628 | ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1629 | if (!ret) |
| 1630 | return ret; |
| 1631 | /* dependent device mapping */ |
| 1632 | tmp = pci_find_upstream_pcie_bridge(pdev); |
| 1633 | if (!tmp) |
| 1634 | return ret; |
| 1635 | /* Secondary interface's bus number and devfn 0 */ |
| 1636 | parent = pdev->bus->self; |
| 1637 | while (parent != tmp) { |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1638 | ret = device_context_mapped(iommu, parent->bus->number, |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1639 | parent->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1640 | if (!ret) |
| 1641 | return ret; |
| 1642 | parent = parent->bus->self; |
| 1643 | } |
| 1644 | if (tmp->is_pcie) |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1645 | return device_context_mapped(iommu, tmp->subordinate->number, |
| 1646 | 0); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1647 | else |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1648 | return device_context_mapped(iommu, tmp->bus->number, |
| 1649 | tmp->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1650 | } |
| 1651 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1652 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 1653 | struct scatterlist *sg, unsigned long phys_pfn, |
| 1654 | unsigned long nr_pages, int prot) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1655 | { |
| 1656 | struct dma_pte *first_pte = NULL, *pte = NULL; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1657 | phys_addr_t uninitialized_var(pteval); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1658 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1659 | unsigned long sg_res; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1660 | |
| 1661 | BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); |
| 1662 | |
| 1663 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) |
| 1664 | return -EINVAL; |
| 1665 | |
| 1666 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; |
| 1667 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1668 | if (sg) |
| 1669 | sg_res = 0; |
| 1670 | else { |
| 1671 | sg_res = nr_pages + 1; |
| 1672 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; |
| 1673 | } |
| 1674 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1675 | while (nr_pages--) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1676 | uint64_t tmp; |
| 1677 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1678 | if (!sg_res) { |
| 1679 | sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT; |
| 1680 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
| 1681 | sg->dma_length = sg->length; |
| 1682 | pteval = page_to_phys(sg_page(sg)) | prot; |
| 1683 | } |
| 1684 | if (!pte) { |
| 1685 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn); |
| 1686 | if (!pte) |
| 1687 | return -ENOMEM; |
| 1688 | } |
| 1689 | /* We don't need lock here, nobody else |
| 1690 | * touches the iova range |
| 1691 | */ |
David Woodhouse | 7766a3f | 2009-07-01 20:27:03 +0100 | [diff] [blame] | 1692 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1693 | if (tmp) { |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 1694 | static int dumps = 5; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1695 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
| 1696 | iov_pfn, tmp, (unsigned long long)pteval); |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 1697 | if (dumps) { |
| 1698 | dumps--; |
| 1699 | debug_dma_dump_mappings(NULL); |
| 1700 | } |
| 1701 | WARN_ON(1); |
| 1702 | } |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1703 | pte++; |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 1704 | if (!nr_pages || first_pte_in_page(pte)) { |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1705 | domain_flush_cache(domain, first_pte, |
| 1706 | (void *)pte - (void *)first_pte); |
| 1707 | pte = NULL; |
| 1708 | } |
| 1709 | iov_pfn++; |
| 1710 | pteval += VTD_PAGE_SIZE; |
| 1711 | sg_res--; |
| 1712 | if (!sg_res) |
| 1713 | sg = sg_next(sg); |
| 1714 | } |
| 1715 | return 0; |
| 1716 | } |
| 1717 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1718 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 1719 | struct scatterlist *sg, unsigned long nr_pages, |
| 1720 | int prot) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1721 | { |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1722 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
| 1723 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1724 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1725 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 1726 | unsigned long phys_pfn, unsigned long nr_pages, |
| 1727 | int prot) |
| 1728 | { |
| 1729 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1730 | } |
| 1731 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1732 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1733 | { |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1734 | if (!iommu) |
| 1735 | return; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1736 | |
| 1737 | clear_context_table(iommu, bus, devfn); |
| 1738 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1739 | DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1740 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1741 | } |
| 1742 | |
| 1743 | static void domain_remove_dev_info(struct dmar_domain *domain) |
| 1744 | { |
| 1745 | struct device_domain_info *info; |
| 1746 | unsigned long flags; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1747 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1748 | |
| 1749 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1750 | while (!list_empty(&domain->devices)) { |
| 1751 | info = list_entry(domain->devices.next, |
| 1752 | struct device_domain_info, link); |
| 1753 | list_del(&info->link); |
| 1754 | list_del(&info->global); |
| 1755 | if (info->dev) |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 1756 | info->dev->dev.archdata.iommu = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1757 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1758 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1759 | iommu_disable_dev_iotlb(info); |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1760 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1761 | iommu_detach_dev(iommu, info->bus, info->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1762 | free_devinfo_mem(info); |
| 1763 | |
| 1764 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1765 | } |
| 1766 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1767 | } |
| 1768 | |
| 1769 | /* |
| 1770 | * find_domain |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 1771 | * Note: we use struct pci_dev->dev.archdata.iommu stores the info |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1772 | */ |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 1773 | static struct dmar_domain * |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1774 | find_domain(struct pci_dev *pdev) |
| 1775 | { |
| 1776 | struct device_domain_info *info; |
| 1777 | |
| 1778 | /* No lock here, assumes no domain exit in normal case */ |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 1779 | info = pdev->dev.archdata.iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1780 | if (info) |
| 1781 | return info->domain; |
| 1782 | return NULL; |
| 1783 | } |
| 1784 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1785 | /* domain is initialized */ |
| 1786 | static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw) |
| 1787 | { |
| 1788 | struct dmar_domain *domain, *found = NULL; |
| 1789 | struct intel_iommu *iommu; |
| 1790 | struct dmar_drhd_unit *drhd; |
| 1791 | struct device_domain_info *info, *tmp; |
| 1792 | struct pci_dev *dev_tmp; |
| 1793 | unsigned long flags; |
| 1794 | int bus = 0, devfn = 0; |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1795 | int segment; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1796 | int ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1797 | |
| 1798 | domain = find_domain(pdev); |
| 1799 | if (domain) |
| 1800 | return domain; |
| 1801 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1802 | segment = pci_domain_nr(pdev->bus); |
| 1803 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1804 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); |
| 1805 | if (dev_tmp) { |
| 1806 | if (dev_tmp->is_pcie) { |
| 1807 | bus = dev_tmp->subordinate->number; |
| 1808 | devfn = 0; |
| 1809 | } else { |
| 1810 | bus = dev_tmp->bus->number; |
| 1811 | devfn = dev_tmp->devfn; |
| 1812 | } |
| 1813 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1814 | list_for_each_entry(info, &device_domain_list, global) { |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1815 | if (info->segment == segment && |
| 1816 | info->bus == bus && info->devfn == devfn) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1817 | found = info->domain; |
| 1818 | break; |
| 1819 | } |
| 1820 | } |
| 1821 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1822 | /* pcie-pci bridge already has a domain, uses it */ |
| 1823 | if (found) { |
| 1824 | domain = found; |
| 1825 | goto found_domain; |
| 1826 | } |
| 1827 | } |
| 1828 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1829 | domain = alloc_domain(); |
| 1830 | if (!domain) |
| 1831 | goto error; |
| 1832 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1833 | /* Allocate new domain for the device */ |
| 1834 | drhd = dmar_find_matched_drhd_unit(pdev); |
| 1835 | if (!drhd) { |
| 1836 | printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n", |
| 1837 | pci_name(pdev)); |
| 1838 | return NULL; |
| 1839 | } |
| 1840 | iommu = drhd->iommu; |
| 1841 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1842 | ret = iommu_attach_domain(domain, iommu); |
| 1843 | if (ret) { |
| 1844 | domain_exit(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1845 | goto error; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1846 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1847 | |
| 1848 | if (domain_init(domain, gaw)) { |
| 1849 | domain_exit(domain); |
| 1850 | goto error; |
| 1851 | } |
| 1852 | |
| 1853 | /* register pcie-to-pci device */ |
| 1854 | if (dev_tmp) { |
| 1855 | info = alloc_devinfo_mem(); |
| 1856 | if (!info) { |
| 1857 | domain_exit(domain); |
| 1858 | goto error; |
| 1859 | } |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1860 | info->segment = segment; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1861 | info->bus = bus; |
| 1862 | info->devfn = devfn; |
| 1863 | info->dev = NULL; |
| 1864 | info->domain = domain; |
| 1865 | /* This domain is shared by devices under p2p bridge */ |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 1866 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1867 | |
| 1868 | /* pcie-to-pci bridge already has a domain, uses it */ |
| 1869 | found = NULL; |
| 1870 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1871 | list_for_each_entry(tmp, &device_domain_list, global) { |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1872 | if (tmp->segment == segment && |
| 1873 | tmp->bus == bus && tmp->devfn == devfn) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1874 | found = tmp->domain; |
| 1875 | break; |
| 1876 | } |
| 1877 | } |
| 1878 | if (found) { |
| 1879 | free_devinfo_mem(info); |
| 1880 | domain_exit(domain); |
| 1881 | domain = found; |
| 1882 | } else { |
| 1883 | list_add(&info->link, &domain->devices); |
| 1884 | list_add(&info->global, &device_domain_list); |
| 1885 | } |
| 1886 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1887 | } |
| 1888 | |
| 1889 | found_domain: |
| 1890 | info = alloc_devinfo_mem(); |
| 1891 | if (!info) |
| 1892 | goto error; |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1893 | info->segment = segment; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1894 | info->bus = pdev->bus->number; |
| 1895 | info->devfn = pdev->devfn; |
| 1896 | info->dev = pdev; |
| 1897 | info->domain = domain; |
| 1898 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1899 | /* somebody is fast */ |
| 1900 | found = find_domain(pdev); |
| 1901 | if (found != NULL) { |
| 1902 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1903 | if (found != domain) { |
| 1904 | domain_exit(domain); |
| 1905 | domain = found; |
| 1906 | } |
| 1907 | free_devinfo_mem(info); |
| 1908 | return domain; |
| 1909 | } |
| 1910 | list_add(&info->link, &domain->devices); |
| 1911 | list_add(&info->global, &device_domain_list); |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 1912 | pdev->dev.archdata.iommu = info; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1913 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1914 | return domain; |
| 1915 | error: |
| 1916 | /* recheck it here, maybe others set it */ |
| 1917 | return find_domain(pdev); |
| 1918 | } |
| 1919 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1920 | static int iommu_identity_mapping; |
| 1921 | |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 1922 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
| 1923 | unsigned long long start, |
| 1924 | unsigned long long end) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1925 | { |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 1926 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
| 1927 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1928 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 1929 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), |
| 1930 | dma_to_mm_pfn(last_vpfn))) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1931 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 1932 | return -ENOMEM; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1933 | } |
| 1934 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 1935 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
| 1936 | start, end, domain->id); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1937 | /* |
| 1938 | * RMRR range might have overlap with physical memory range, |
| 1939 | * clear it first |
| 1940 | */ |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 1941 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1942 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 1943 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
| 1944 | last_vpfn - first_vpfn + 1, |
David Woodhouse | 61df744 | 2009-06-28 11:55:58 +0100 | [diff] [blame] | 1945 | DMA_PTE_READ|DMA_PTE_WRITE); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 1946 | } |
| 1947 | |
| 1948 | static int iommu_prepare_identity_map(struct pci_dev *pdev, |
| 1949 | unsigned long long start, |
| 1950 | unsigned long long end) |
| 1951 | { |
| 1952 | struct dmar_domain *domain; |
| 1953 | int ret; |
| 1954 | |
| 1955 | printk(KERN_INFO |
| 1956 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", |
| 1957 | pci_name(pdev), start, end); |
| 1958 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 1959 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 1960 | if (!domain) |
| 1961 | return -ENOMEM; |
| 1962 | |
| 1963 | ret = iommu_domain_identity_map(domain, start, end); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1964 | if (ret) |
| 1965 | goto error; |
| 1966 | |
| 1967 | /* context entry init */ |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1968 | ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 1969 | if (ret) |
| 1970 | goto error; |
| 1971 | |
| 1972 | return 0; |
| 1973 | |
| 1974 | error: |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1975 | domain_exit(domain); |
| 1976 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1977 | } |
| 1978 | |
| 1979 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, |
| 1980 | struct pci_dev *pdev) |
| 1981 | { |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 1982 | if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1983 | return 0; |
| 1984 | return iommu_prepare_identity_map(pdev, rmrr->base_address, |
| 1985 | rmrr->end_address + 1); |
| 1986 | } |
| 1987 | |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 1988 | #ifdef CONFIG_DMAR_FLOPPY_WA |
| 1989 | static inline void iommu_prepare_isa(void) |
| 1990 | { |
| 1991 | struct pci_dev *pdev; |
| 1992 | int ret; |
| 1993 | |
| 1994 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 1995 | if (!pdev) |
| 1996 | return; |
| 1997 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 1998 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 1999 | ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024); |
| 2000 | |
| 2001 | if (ret) |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2002 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
| 2003 | "floppy might not work\n"); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2004 | |
| 2005 | } |
| 2006 | #else |
| 2007 | static inline void iommu_prepare_isa(void) |
| 2008 | { |
| 2009 | return; |
| 2010 | } |
| 2011 | #endif /* !CONFIG_DMAR_FLPY_WA */ |
| 2012 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2013 | /* Initialize each context entry as pass through.*/ |
| 2014 | static int __init init_context_pass_through(void) |
| 2015 | { |
| 2016 | struct pci_dev *pdev = NULL; |
| 2017 | struct dmar_domain *domain; |
| 2018 | int ret; |
| 2019 | |
| 2020 | for_each_pci_dev(pdev) { |
| 2021 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 2022 | ret = domain_context_mapping(domain, pdev, |
| 2023 | CONTEXT_TT_PASS_THROUGH); |
| 2024 | if (ret) |
| 2025 | return ret; |
| 2026 | } |
| 2027 | return 0; |
| 2028 | } |
| 2029 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2030 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2031 | |
| 2032 | static int __init si_domain_work_fn(unsigned long start_pfn, |
| 2033 | unsigned long end_pfn, void *datax) |
| 2034 | { |
| 2035 | int *ret = datax; |
| 2036 | |
| 2037 | *ret = iommu_domain_identity_map(si_domain, |
| 2038 | (uint64_t)start_pfn << PAGE_SHIFT, |
| 2039 | (uint64_t)end_pfn << PAGE_SHIFT); |
| 2040 | return *ret; |
| 2041 | |
| 2042 | } |
| 2043 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2044 | static int si_domain_init(void) |
| 2045 | { |
| 2046 | struct dmar_drhd_unit *drhd; |
| 2047 | struct intel_iommu *iommu; |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2048 | int nid, ret = 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2049 | |
| 2050 | si_domain = alloc_domain(); |
| 2051 | if (!si_domain) |
| 2052 | return -EFAULT; |
| 2053 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2054 | pr_debug("Identity mapping domain is domain %d\n", si_domain->id); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2055 | |
| 2056 | for_each_active_iommu(iommu, drhd) { |
| 2057 | ret = iommu_attach_domain(si_domain, iommu); |
| 2058 | if (ret) { |
| 2059 | domain_exit(si_domain); |
| 2060 | return -EFAULT; |
| 2061 | } |
| 2062 | } |
| 2063 | |
| 2064 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
| 2065 | domain_exit(si_domain); |
| 2066 | return -EFAULT; |
| 2067 | } |
| 2068 | |
| 2069 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; |
| 2070 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2071 | for_each_online_node(nid) { |
| 2072 | work_with_active_regions(nid, si_domain_work_fn, &ret); |
| 2073 | if (ret) |
| 2074 | return ret; |
| 2075 | } |
| 2076 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2077 | return 0; |
| 2078 | } |
| 2079 | |
| 2080 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
| 2081 | struct pci_dev *pdev); |
| 2082 | static int identity_mapping(struct pci_dev *pdev) |
| 2083 | { |
| 2084 | struct device_domain_info *info; |
| 2085 | |
| 2086 | if (likely(!iommu_identity_mapping)) |
| 2087 | return 0; |
| 2088 | |
| 2089 | |
| 2090 | list_for_each_entry(info, &si_domain->devices, link) |
| 2091 | if (info->dev == pdev) |
| 2092 | return 1; |
| 2093 | return 0; |
| 2094 | } |
| 2095 | |
| 2096 | static int domain_add_dev_info(struct dmar_domain *domain, |
| 2097 | struct pci_dev *pdev) |
| 2098 | { |
| 2099 | struct device_domain_info *info; |
| 2100 | unsigned long flags; |
| 2101 | |
| 2102 | info = alloc_devinfo_mem(); |
| 2103 | if (!info) |
| 2104 | return -ENOMEM; |
| 2105 | |
| 2106 | info->segment = pci_domain_nr(pdev->bus); |
| 2107 | info->bus = pdev->bus->number; |
| 2108 | info->devfn = pdev->devfn; |
| 2109 | info->dev = pdev; |
| 2110 | info->domain = domain; |
| 2111 | |
| 2112 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2113 | list_add(&info->link, &domain->devices); |
| 2114 | list_add(&info->global, &device_domain_list); |
| 2115 | pdev->dev.archdata.iommu = info; |
| 2116 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2117 | |
| 2118 | return 0; |
| 2119 | } |
| 2120 | |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2121 | static int iommu_should_identity_map(struct pci_dev *pdev, int startup) |
| 2122 | { |
| 2123 | if (iommu_identity_mapping == 2) |
| 2124 | return IS_GFX_DEVICE(pdev); |
| 2125 | |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2126 | /* |
| 2127 | * We want to start off with all devices in the 1:1 domain, and |
| 2128 | * take them out later if we find they can't access all of memory. |
| 2129 | * |
| 2130 | * However, we can't do this for PCI devices behind bridges, |
| 2131 | * because all PCI devices behind the same bridge will end up |
| 2132 | * with the same source-id on their transactions. |
| 2133 | * |
| 2134 | * Practically speaking, we can't change things around for these |
| 2135 | * devices at run-time, because we can't be sure there'll be no |
| 2136 | * DMA transactions in flight for any of their siblings. |
| 2137 | * |
| 2138 | * So PCI devices (unless they're on the root bus) as well as |
| 2139 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of |
| 2140 | * the 1:1 domain, just in _case_ one of their siblings turns out |
| 2141 | * not to be able to map all of memory. |
| 2142 | */ |
| 2143 | if (!pdev->is_pcie) { |
| 2144 | if (!pci_is_root_bus(pdev->bus)) |
| 2145 | return 0; |
| 2146 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) |
| 2147 | return 0; |
| 2148 | } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) |
| 2149 | return 0; |
| 2150 | |
| 2151 | /* |
| 2152 | * At boot time, we don't yet know if devices will be 64-bit capable. |
| 2153 | * Assume that they will -- if they turn out not to be, then we can |
| 2154 | * take them out of the 1:1 domain later. |
| 2155 | */ |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2156 | if (!startup) |
| 2157 | return pdev->dma_mask > DMA_BIT_MASK(32); |
| 2158 | |
| 2159 | return 1; |
| 2160 | } |
| 2161 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2162 | static int iommu_prepare_static_identity_mapping(void) |
| 2163 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2164 | struct pci_dev *pdev = NULL; |
| 2165 | int ret; |
| 2166 | |
| 2167 | ret = si_domain_init(); |
| 2168 | if (ret) |
| 2169 | return -EFAULT; |
| 2170 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2171 | for_each_pci_dev(pdev) { |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2172 | if (iommu_should_identity_map(pdev, 1)) { |
David Woodhouse | 62edf5d | 2009-07-04 10:59:46 +0100 | [diff] [blame] | 2173 | printk(KERN_INFO "IOMMU: identity mapping for device %s\n", |
| 2174 | pci_name(pdev)); |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2175 | |
David Woodhouse | 62edf5d | 2009-07-04 10:59:46 +0100 | [diff] [blame] | 2176 | ret = domain_context_mapping(si_domain, pdev, |
| 2177 | CONTEXT_TT_MULTI_LEVEL); |
| 2178 | if (ret) |
| 2179 | return ret; |
| 2180 | ret = domain_add_dev_info(si_domain, pdev); |
| 2181 | if (ret) |
| 2182 | return ret; |
| 2183 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2184 | } |
| 2185 | |
| 2186 | return 0; |
| 2187 | } |
| 2188 | |
| 2189 | int __init init_dmars(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2190 | { |
| 2191 | struct dmar_drhd_unit *drhd; |
| 2192 | struct dmar_rmrr_unit *rmrr; |
| 2193 | struct pci_dev *pdev; |
| 2194 | struct intel_iommu *iommu; |
Suresh Siddha | 9d783ba | 2009-03-16 17:04:55 -0700 | [diff] [blame] | 2195 | int i, ret; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2196 | int pass_through = 1; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2197 | |
| 2198 | /* |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2199 | * In case pass through can not be enabled, iommu tries to use identity |
| 2200 | * mapping. |
| 2201 | */ |
| 2202 | if (iommu_pass_through) |
| 2203 | iommu_identity_mapping = 1; |
| 2204 | |
| 2205 | /* |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2206 | * for each drhd |
| 2207 | * allocate root |
| 2208 | * initialize and program root entry to not present |
| 2209 | * endfor |
| 2210 | */ |
| 2211 | for_each_drhd_unit(drhd) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2212 | g_num_of_iommus++; |
| 2213 | /* |
| 2214 | * lock not needed as this is only incremented in the single |
| 2215 | * threaded kernel __init code path all other access are read |
| 2216 | * only |
| 2217 | */ |
| 2218 | } |
| 2219 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2220 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
| 2221 | GFP_KERNEL); |
| 2222 | if (!g_iommus) { |
| 2223 | printk(KERN_ERR "Allocating global iommu array failed\n"); |
| 2224 | ret = -ENOMEM; |
| 2225 | goto error; |
| 2226 | } |
| 2227 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2228 | deferred_flush = kzalloc(g_num_of_iommus * |
| 2229 | sizeof(struct deferred_flush_tables), GFP_KERNEL); |
| 2230 | if (!deferred_flush) { |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2231 | kfree(g_iommus); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2232 | ret = -ENOMEM; |
| 2233 | goto error; |
| 2234 | } |
| 2235 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2236 | for_each_drhd_unit(drhd) { |
| 2237 | if (drhd->ignored) |
| 2238 | continue; |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 2239 | |
| 2240 | iommu = drhd->iommu; |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2241 | g_iommus[iommu->seq_id] = iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2242 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 2243 | ret = iommu_init_domains(iommu); |
| 2244 | if (ret) |
| 2245 | goto error; |
| 2246 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2247 | /* |
| 2248 | * TBD: |
| 2249 | * we could share the same root & context tables |
| 2250 | * amoung all IOMMU's. Need to Split it later. |
| 2251 | */ |
| 2252 | ret = iommu_alloc_root_entry(iommu); |
| 2253 | if (ret) { |
| 2254 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); |
| 2255 | goto error; |
| 2256 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2257 | if (!ecap_pass_through(iommu->ecap)) |
| 2258 | pass_through = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2259 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2260 | if (iommu_pass_through) |
| 2261 | if (!pass_through) { |
| 2262 | printk(KERN_INFO |
| 2263 | "Pass Through is not supported by hardware.\n"); |
| 2264 | iommu_pass_through = 0; |
| 2265 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2266 | |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 2267 | /* |
| 2268 | * Start from the sane iommu hardware state. |
| 2269 | */ |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2270 | for_each_drhd_unit(drhd) { |
| 2271 | if (drhd->ignored) |
| 2272 | continue; |
| 2273 | |
| 2274 | iommu = drhd->iommu; |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 2275 | |
| 2276 | /* |
| 2277 | * If the queued invalidation is already initialized by us |
| 2278 | * (for example, while enabling interrupt-remapping) then |
| 2279 | * we got the things already rolling from a sane state. |
| 2280 | */ |
| 2281 | if (iommu->qi) |
| 2282 | continue; |
| 2283 | |
| 2284 | /* |
| 2285 | * Clear any previous faults. |
| 2286 | */ |
| 2287 | dmar_fault(-1, iommu); |
| 2288 | /* |
| 2289 | * Disable queued invalidation if supported and already enabled |
| 2290 | * before OS handover. |
| 2291 | */ |
| 2292 | dmar_disable_qi(iommu); |
| 2293 | } |
| 2294 | |
| 2295 | for_each_drhd_unit(drhd) { |
| 2296 | if (drhd->ignored) |
| 2297 | continue; |
| 2298 | |
| 2299 | iommu = drhd->iommu; |
| 2300 | |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2301 | if (dmar_enable_qi(iommu)) { |
| 2302 | /* |
| 2303 | * Queued Invalidate not enabled, use Register Based |
| 2304 | * Invalidate |
| 2305 | */ |
| 2306 | iommu->flush.flush_context = __iommu_flush_context; |
| 2307 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; |
| 2308 | printk(KERN_INFO "IOMMU 0x%Lx: using Register based " |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2309 | "invalidation\n", |
| 2310 | (unsigned long long)drhd->reg_base_addr); |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2311 | } else { |
| 2312 | iommu->flush.flush_context = qi_flush_context; |
| 2313 | iommu->flush.flush_iotlb = qi_flush_iotlb; |
| 2314 | printk(KERN_INFO "IOMMU 0x%Lx: using Queued " |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2315 | "invalidation\n", |
| 2316 | (unsigned long long)drhd->reg_base_addr); |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2317 | } |
| 2318 | } |
| 2319 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2320 | /* |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2321 | * If pass through is set and enabled, context entries of all pci |
| 2322 | * devices are intialized by pass through translation type. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2323 | */ |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2324 | if (iommu_pass_through) { |
| 2325 | ret = init_context_pass_through(); |
| 2326 | if (ret) { |
| 2327 | printk(KERN_ERR "IOMMU: Pass through init failed.\n"); |
| 2328 | iommu_pass_through = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2329 | } |
| 2330 | } |
| 2331 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2332 | /* |
| 2333 | * If pass through is not set or not enabled, setup context entries for |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2334 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
| 2335 | * identity mapping if iommu_identity_mapping is set. |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2336 | */ |
| 2337 | if (!iommu_pass_through) { |
David Woodhouse | 62edf5d | 2009-07-04 10:59:46 +0100 | [diff] [blame] | 2338 | #ifdef CONFIG_DMAR_BROKEN_GFX_WA |
| 2339 | if (!iommu_identity_mapping) |
| 2340 | iommu_identity_mapping = 2; |
| 2341 | #endif |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2342 | if (iommu_identity_mapping) |
| 2343 | iommu_prepare_static_identity_mapping(); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2344 | /* |
| 2345 | * For each rmrr |
| 2346 | * for each dev attached to rmrr |
| 2347 | * do |
| 2348 | * locate drhd for dev, alloc domain for dev |
| 2349 | * allocate free domain |
| 2350 | * allocate page table entries for rmrr |
| 2351 | * if context not allocated for bus |
| 2352 | * allocate and init context |
| 2353 | * set present in root table for this bus |
| 2354 | * init context with domain, translation etc |
| 2355 | * endfor |
| 2356 | * endfor |
| 2357 | */ |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2358 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2359 | for_each_rmrr_units(rmrr) { |
| 2360 | for (i = 0; i < rmrr->devices_cnt; i++) { |
| 2361 | pdev = rmrr->devices[i]; |
| 2362 | /* |
| 2363 | * some BIOS lists non-exist devices in DMAR |
| 2364 | * table. |
| 2365 | */ |
| 2366 | if (!pdev) |
| 2367 | continue; |
| 2368 | ret = iommu_prepare_rmrr_dev(rmrr, pdev); |
| 2369 | if (ret) |
| 2370 | printk(KERN_ERR |
| 2371 | "IOMMU: mapping reserved region failed\n"); |
| 2372 | } |
| 2373 | } |
Keshavamurthy, Anil S | e820482 | 2007-10-21 16:41:55 -0700 | [diff] [blame] | 2374 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2375 | iommu_prepare_isa(); |
| 2376 | } |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2377 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2378 | /* |
| 2379 | * for each drhd |
| 2380 | * enable fault log |
| 2381 | * global invalidate context cache |
| 2382 | * global invalidate iotlb |
| 2383 | * enable translation |
| 2384 | */ |
| 2385 | for_each_drhd_unit(drhd) { |
| 2386 | if (drhd->ignored) |
| 2387 | continue; |
| 2388 | iommu = drhd->iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2389 | |
| 2390 | iommu_flush_write_buffer(iommu); |
| 2391 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 2392 | ret = dmar_set_interrupt(iommu); |
| 2393 | if (ret) |
| 2394 | goto error; |
| 2395 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2396 | iommu_set_root_entry(iommu); |
| 2397 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2398 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2399 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 2400 | iommu_disable_protect_mem_regions(iommu); |
| 2401 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2402 | ret = iommu_enable_translation(iommu); |
| 2403 | if (ret) |
| 2404 | goto error; |
| 2405 | } |
| 2406 | |
| 2407 | return 0; |
| 2408 | error: |
| 2409 | for_each_drhd_unit(drhd) { |
| 2410 | if (drhd->ignored) |
| 2411 | continue; |
| 2412 | iommu = drhd->iommu; |
| 2413 | free_iommu(iommu); |
| 2414 | } |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2415 | kfree(g_iommus); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2416 | return ret; |
| 2417 | } |
| 2418 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2419 | /* Returns a number of VTD pages, but aligned to MM page size */ |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 2420 | static inline unsigned long aligned_nrpages(unsigned long host_addr, |
| 2421 | size_t size) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2422 | { |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 2423 | host_addr &= ~PAGE_MASK; |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2424 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2425 | } |
| 2426 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2427 | /* This takes a number of _MM_ pages, not VTD pages */ |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2428 | static struct iova *intel_alloc_iova(struct device *dev, |
| 2429 | struct dmar_domain *domain, |
| 2430 | unsigned long nrpages, uint64_t dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2431 | { |
| 2432 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2433 | struct iova *iova = NULL; |
| 2434 | |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2435 | /* Restrict dma_mask to the width that the iommu can handle */ |
| 2436 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); |
| 2437 | |
| 2438 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2439 | /* |
| 2440 | * First try to allocate an io virtual address in |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 2441 | * DMA_BIT_MASK(32) and if that fails then try allocating |
Joe Perches | 3609801 | 2007-12-17 11:40:11 -0800 | [diff] [blame] | 2442 | * from higher range |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2443 | */ |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2444 | iova = alloc_iova(&domain->iovad, nrpages, |
| 2445 | IOVA_PFN(DMA_BIT_MASK(32)), 1); |
| 2446 | if (iova) |
| 2447 | return iova; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2448 | } |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2449 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); |
| 2450 | if (unlikely(!iova)) { |
| 2451 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", |
| 2452 | nrpages, pci_name(pdev)); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2453 | return NULL; |
| 2454 | } |
| 2455 | |
| 2456 | return iova; |
| 2457 | } |
| 2458 | |
| 2459 | static struct dmar_domain * |
| 2460 | get_valid_domain_for_dev(struct pci_dev *pdev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2461 | { |
| 2462 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2463 | int ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2464 | |
| 2465 | domain = get_domain_for_dev(pdev, |
| 2466 | DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 2467 | if (!domain) { |
| 2468 | printk(KERN_ERR |
| 2469 | "Allocating domain for %s failed", pci_name(pdev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 2470 | return NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2471 | } |
| 2472 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2473 | /* make sure context mapping is ok */ |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2474 | if (unlikely(!domain_context_mapped(pdev))) { |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2475 | ret = domain_context_mapping(domain, pdev, |
| 2476 | CONTEXT_TT_MULTI_LEVEL); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2477 | if (ret) { |
| 2478 | printk(KERN_ERR |
| 2479 | "Domain context map for %s failed", |
| 2480 | pci_name(pdev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 2481 | return NULL; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2482 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2483 | } |
| 2484 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2485 | return domain; |
| 2486 | } |
| 2487 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2488 | static int iommu_dummy(struct pci_dev *pdev) |
| 2489 | { |
| 2490 | return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
| 2491 | } |
| 2492 | |
| 2493 | /* Check if the pdev needs to go through non-identity map and unmap process.*/ |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2494 | static int iommu_no_mapping(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2495 | { |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2496 | struct pci_dev *pdev; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2497 | int found; |
| 2498 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2499 | if (unlikely(dev->bus != &pci_bus_type)) |
| 2500 | return 1; |
| 2501 | |
| 2502 | pdev = to_pci_dev(dev); |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2503 | if (iommu_dummy(pdev)) |
| 2504 | return 1; |
| 2505 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2506 | if (!iommu_identity_mapping) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2507 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2508 | |
| 2509 | found = identity_mapping(pdev); |
| 2510 | if (found) { |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2511 | if (iommu_should_identity_map(pdev, 0)) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2512 | return 1; |
| 2513 | else { |
| 2514 | /* |
| 2515 | * 32 bit DMA is removed from si_domain and fall back |
| 2516 | * to non-identity mapping. |
| 2517 | */ |
| 2518 | domain_remove_one_dev_info(si_domain, pdev); |
| 2519 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", |
| 2520 | pci_name(pdev)); |
| 2521 | return 0; |
| 2522 | } |
| 2523 | } else { |
| 2524 | /* |
| 2525 | * In case of a detached 64 bit DMA device from vm, the device |
| 2526 | * is put into si_domain for identity mapping. |
| 2527 | */ |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2528 | if (iommu_should_identity_map(pdev, 0)) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2529 | int ret; |
| 2530 | ret = domain_add_dev_info(si_domain, pdev); |
David Woodhouse | 1b7bc0a | 2009-07-04 10:49:46 +0100 | [diff] [blame] | 2531 | if (ret) |
| 2532 | return 0; |
| 2533 | ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2534 | if (!ret) { |
| 2535 | printk(KERN_INFO "64bit %s uses identity mapping\n", |
| 2536 | pci_name(pdev)); |
| 2537 | return 1; |
| 2538 | } |
| 2539 | } |
| 2540 | } |
| 2541 | |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2542 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2543 | } |
| 2544 | |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 2545 | static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr, |
| 2546 | size_t size, int dir, u64 dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2547 | { |
| 2548 | struct pci_dev *pdev = to_pci_dev(hwdev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2549 | struct dmar_domain *domain; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2550 | phys_addr_t start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2551 | struct iova *iova; |
| 2552 | int prot = 0; |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2553 | int ret; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2554 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2555 | |
| 2556 | BUG_ON(dir == DMA_NONE); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2557 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2558 | if (iommu_no_mapping(hwdev)) |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2559 | return paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2560 | |
| 2561 | domain = get_valid_domain_for_dev(pdev); |
| 2562 | if (!domain) |
| 2563 | return 0; |
| 2564 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2565 | iommu = domain_get_iommu(domain); |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 2566 | size = aligned_nrpages(paddr, size); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2567 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2568 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), |
| 2569 | pdev->dma_mask); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2570 | if (!iova) |
| 2571 | goto error; |
| 2572 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2573 | /* |
| 2574 | * Check if DMAR supports zero-length reads on write only |
| 2575 | * mappings.. |
| 2576 | */ |
| 2577 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2578 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2579 | prot |= DMA_PTE_READ; |
| 2580 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 2581 | prot |= DMA_PTE_WRITE; |
| 2582 | /* |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2583 | * paddr - (paddr + size) might be partial page, we should map the whole |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2584 | * page. Note: if two part of one page are separately mapped, we |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2585 | * might have two guest_addr mapping to the same host paddr, but this |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2586 | * is not a big problem |
| 2587 | */ |
David Woodhouse | 0ab36de | 2009-06-28 14:01:43 +0100 | [diff] [blame] | 2588 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
| 2589 | paddr >> VTD_PAGE_SHIFT, size, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2590 | if (ret) |
| 2591 | goto error; |
| 2592 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2593 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 2594 | if (cap_caching_mode(iommu->cap)) |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 2595 | iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2596 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2597 | iommu_flush_write_buffer(iommu); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2598 | |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 2599 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
| 2600 | start_paddr += paddr & ~PAGE_MASK; |
| 2601 | return start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2602 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2603 | error: |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2604 | if (iova) |
| 2605 | __free_iova(&domain->iovad, iova); |
David Woodhouse | 4cf2e75 | 2009-02-11 17:23:43 +0000 | [diff] [blame] | 2606 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2607 | pci_name(pdev), size, (unsigned long long)paddr, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2608 | return 0; |
| 2609 | } |
| 2610 | |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 2611 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
| 2612 | unsigned long offset, size_t size, |
| 2613 | enum dma_data_direction dir, |
| 2614 | struct dma_attrs *attrs) |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 2615 | { |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 2616 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
| 2617 | dir, to_pci_dev(dev)->dma_mask); |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 2618 | } |
| 2619 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2620 | static void flush_unmaps(void) |
| 2621 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2622 | int i, j; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2623 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2624 | timer_on = 0; |
| 2625 | |
| 2626 | /* just flush them all */ |
| 2627 | for (i = 0; i < g_num_of_iommus; i++) { |
Weidong Han | a2bb845 | 2008-12-08 11:24:12 +0800 | [diff] [blame] | 2628 | struct intel_iommu *iommu = g_iommus[i]; |
| 2629 | if (!iommu) |
| 2630 | continue; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 2631 | |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 2632 | if (!deferred_flush[i].next) |
| 2633 | continue; |
| 2634 | |
| 2635 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2636 | DMA_TLB_GLOBAL_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 2637 | for (j = 0; j < deferred_flush[i].next; j++) { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2638 | unsigned long mask; |
| 2639 | struct iova *iova = deferred_flush[i].iova[j]; |
| 2640 | |
| 2641 | mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT; |
| 2642 | mask = ilog2(mask >> VTD_PAGE_SHIFT); |
| 2643 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], |
| 2644 | iova->pfn_lo << PAGE_SHIFT, mask); |
| 2645 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2646 | } |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 2647 | deferred_flush[i].next = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2648 | } |
| 2649 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2650 | list_size = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2651 | } |
| 2652 | |
| 2653 | static void flush_unmaps_timeout(unsigned long data) |
| 2654 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2655 | unsigned long flags; |
| 2656 | |
| 2657 | spin_lock_irqsave(&async_umap_flush_lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2658 | flush_unmaps(); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2659 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2660 | } |
| 2661 | |
| 2662 | static void add_unmap(struct dmar_domain *dom, struct iova *iova) |
| 2663 | { |
| 2664 | unsigned long flags; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2665 | int next, iommu_id; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2666 | struct intel_iommu *iommu; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2667 | |
| 2668 | spin_lock_irqsave(&async_umap_flush_lock, flags); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2669 | if (list_size == HIGH_WATER_MARK) |
| 2670 | flush_unmaps(); |
| 2671 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2672 | iommu = domain_get_iommu(dom); |
| 2673 | iommu_id = iommu->seq_id; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 2674 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2675 | next = deferred_flush[iommu_id].next; |
| 2676 | deferred_flush[iommu_id].domain[next] = dom; |
| 2677 | deferred_flush[iommu_id].iova[next] = iova; |
| 2678 | deferred_flush[iommu_id].next++; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2679 | |
| 2680 | if (!timer_on) { |
| 2681 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); |
| 2682 | timer_on = 1; |
| 2683 | } |
| 2684 | list_size++; |
| 2685 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
| 2686 | } |
| 2687 | |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 2688 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
| 2689 | size_t size, enum dma_data_direction dir, |
| 2690 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2691 | { |
| 2692 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2693 | struct dmar_domain *domain; |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2694 | unsigned long start_pfn, last_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2695 | struct iova *iova; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2696 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2697 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2698 | if (iommu_no_mapping(dev)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2699 | return; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2700 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2701 | domain = find_domain(pdev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2702 | BUG_ON(!domain); |
| 2703 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2704 | iommu = domain_get_iommu(domain); |
| 2705 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2706 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
David Woodhouse | 85b9827 | 2009-07-01 19:27:53 +0100 | [diff] [blame] | 2707 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
| 2708 | (unsigned long long)dev_addr)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2709 | return; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2710 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2711 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
| 2712 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2713 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2714 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
| 2715 | pci_name(pdev), start_pfn, last_pfn); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2716 | |
| 2717 | /* clear the whole page */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2718 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
| 2719 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2720 | /* free page tables */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2721 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
| 2722 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2723 | if (intel_iommu_strict) { |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 2724 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2725 | last_pfn - start_pfn + 1); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2726 | /* free iova */ |
| 2727 | __free_iova(&domain->iovad, iova); |
| 2728 | } else { |
| 2729 | add_unmap(domain, iova); |
| 2730 | /* |
| 2731 | * queue up the release of the unmap to save the 1/6th of the |
| 2732 | * cpu used up by the iotlb flush operation... |
| 2733 | */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2734 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2735 | } |
| 2736 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 2737 | static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size, |
| 2738 | int dir) |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 2739 | { |
| 2740 | intel_unmap_page(dev, dev_addr, size, dir, NULL); |
| 2741 | } |
| 2742 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 2743 | static void *intel_alloc_coherent(struct device *hwdev, size_t size, |
| 2744 | dma_addr_t *dma_handle, gfp_t flags) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2745 | { |
| 2746 | void *vaddr; |
| 2747 | int order; |
| 2748 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2749 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2750 | order = get_order(size); |
| 2751 | flags &= ~(GFP_DMA | GFP_DMA32); |
| 2752 | |
| 2753 | vaddr = (void *)__get_free_pages(flags, order); |
| 2754 | if (!vaddr) |
| 2755 | return NULL; |
| 2756 | memset(vaddr, 0, size); |
| 2757 | |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 2758 | *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size, |
| 2759 | DMA_BIDIRECTIONAL, |
| 2760 | hwdev->coherent_dma_mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2761 | if (*dma_handle) |
| 2762 | return vaddr; |
| 2763 | free_pages((unsigned long)vaddr, order); |
| 2764 | return NULL; |
| 2765 | } |
| 2766 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 2767 | static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, |
| 2768 | dma_addr_t dma_handle) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2769 | { |
| 2770 | int order; |
| 2771 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2772 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2773 | order = get_order(size); |
| 2774 | |
| 2775 | intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL); |
| 2776 | free_pages((unsigned long)vaddr, order); |
| 2777 | } |
| 2778 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 2779 | static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, |
| 2780 | int nelems, enum dma_data_direction dir, |
| 2781 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2782 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2783 | struct pci_dev *pdev = to_pci_dev(hwdev); |
| 2784 | struct dmar_domain *domain; |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2785 | unsigned long start_pfn, last_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2786 | struct iova *iova; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2787 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2788 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2789 | if (iommu_no_mapping(hwdev)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2790 | return; |
| 2791 | |
| 2792 | domain = find_domain(pdev); |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2793 | BUG_ON(!domain); |
| 2794 | |
| 2795 | iommu = domain_get_iommu(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2796 | |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2797 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
David Woodhouse | 85b9827 | 2009-07-01 19:27:53 +0100 | [diff] [blame] | 2798 | if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n", |
| 2799 | (unsigned long long)sglist[0].dma_address)) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2800 | return; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2801 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2802 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
| 2803 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2804 | |
| 2805 | /* clear the whole page */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2806 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2807 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2808 | /* free page tables */ |
| 2809 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
| 2810 | |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 2811 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 2812 | (last_pfn - start_pfn + 1)); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2813 | |
| 2814 | /* free iova */ |
| 2815 | __free_iova(&domain->iovad, iova); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2816 | } |
| 2817 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2818 | static int intel_nontranslate_map_sg(struct device *hddev, |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2819 | struct scatterlist *sglist, int nelems, int dir) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2820 | { |
| 2821 | int i; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2822 | struct scatterlist *sg; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2823 | |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2824 | for_each_sg(sglist, sg, nelems, i) { |
FUJITA Tomonori | 12d4d40 | 2007-10-23 09:32:25 +0200 | [diff] [blame] | 2825 | BUG_ON(!sg_page(sg)); |
David Woodhouse | 4cf2e75 | 2009-02-11 17:23:43 +0000 | [diff] [blame] | 2826 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2827 | sg->dma_length = sg->length; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2828 | } |
| 2829 | return nelems; |
| 2830 | } |
| 2831 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 2832 | static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems, |
| 2833 | enum dma_data_direction dir, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2834 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2835 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2836 | struct pci_dev *pdev = to_pci_dev(hwdev); |
| 2837 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2838 | size_t size = 0; |
| 2839 | int prot = 0; |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 2840 | size_t offset_pfn = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2841 | struct iova *iova = NULL; |
| 2842 | int ret; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2843 | struct scatterlist *sg; |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 2844 | unsigned long start_vpfn; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2845 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2846 | |
| 2847 | BUG_ON(dir == DMA_NONE); |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2848 | if (iommu_no_mapping(hwdev)) |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2849 | return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2850 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2851 | domain = get_valid_domain_for_dev(pdev); |
| 2852 | if (!domain) |
| 2853 | return 0; |
| 2854 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2855 | iommu = domain_get_iommu(domain); |
| 2856 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 2857 | for_each_sg(sglist, sg, nelems, i) |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 2858 | size += aligned_nrpages(sg->offset, sg->length); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2859 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2860 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), |
| 2861 | pdev->dma_mask); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2862 | if (!iova) { |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 2863 | sglist->dma_length = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2864 | return 0; |
| 2865 | } |
| 2866 | |
| 2867 | /* |
| 2868 | * Check if DMAR supports zero-length reads on write only |
| 2869 | * mappings.. |
| 2870 | */ |
| 2871 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2872 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2873 | prot |= DMA_PTE_READ; |
| 2874 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 2875 | prot |= DMA_PTE_WRITE; |
| 2876 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 2877 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2878 | |
| 2879 | ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot); |
| 2880 | if (unlikely(ret)) { |
| 2881 | /* clear the page */ |
| 2882 | dma_pte_clear_range(domain, start_vpfn, |
| 2883 | start_vpfn + size - 1); |
| 2884 | /* free page tables */ |
| 2885 | dma_pte_free_pagetable(domain, start_vpfn, |
| 2886 | start_vpfn + size - 1); |
| 2887 | /* free iova */ |
| 2888 | __free_iova(&domain->iovad, iova); |
| 2889 | return 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2890 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2891 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2892 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 2893 | if (cap_caching_mode(iommu->cap)) |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 2894 | iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2895 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2896 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2897 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2898 | return nelems; |
| 2899 | } |
| 2900 | |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 2901 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
| 2902 | { |
| 2903 | return !dma_addr; |
| 2904 | } |
| 2905 | |
FUJITA Tomonori | 160c1d8 | 2009-01-05 23:59:02 +0900 | [diff] [blame] | 2906 | struct dma_map_ops intel_dma_ops = { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2907 | .alloc_coherent = intel_alloc_coherent, |
| 2908 | .free_coherent = intel_free_coherent, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2909 | .map_sg = intel_map_sg, |
| 2910 | .unmap_sg = intel_unmap_sg, |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 2911 | .map_page = intel_map_page, |
| 2912 | .unmap_page = intel_unmap_page, |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 2913 | .mapping_error = intel_mapping_error, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2914 | }; |
| 2915 | |
| 2916 | static inline int iommu_domain_cache_init(void) |
| 2917 | { |
| 2918 | int ret = 0; |
| 2919 | |
| 2920 | iommu_domain_cache = kmem_cache_create("iommu_domain", |
| 2921 | sizeof(struct dmar_domain), |
| 2922 | 0, |
| 2923 | SLAB_HWCACHE_ALIGN, |
| 2924 | |
| 2925 | NULL); |
| 2926 | if (!iommu_domain_cache) { |
| 2927 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); |
| 2928 | ret = -ENOMEM; |
| 2929 | } |
| 2930 | |
| 2931 | return ret; |
| 2932 | } |
| 2933 | |
| 2934 | static inline int iommu_devinfo_cache_init(void) |
| 2935 | { |
| 2936 | int ret = 0; |
| 2937 | |
| 2938 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", |
| 2939 | sizeof(struct device_domain_info), |
| 2940 | 0, |
| 2941 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2942 | NULL); |
| 2943 | if (!iommu_devinfo_cache) { |
| 2944 | printk(KERN_ERR "Couldn't create devinfo cache\n"); |
| 2945 | ret = -ENOMEM; |
| 2946 | } |
| 2947 | |
| 2948 | return ret; |
| 2949 | } |
| 2950 | |
| 2951 | static inline int iommu_iova_cache_init(void) |
| 2952 | { |
| 2953 | int ret = 0; |
| 2954 | |
| 2955 | iommu_iova_cache = kmem_cache_create("iommu_iova", |
| 2956 | sizeof(struct iova), |
| 2957 | 0, |
| 2958 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2959 | NULL); |
| 2960 | if (!iommu_iova_cache) { |
| 2961 | printk(KERN_ERR "Couldn't create iova cache\n"); |
| 2962 | ret = -ENOMEM; |
| 2963 | } |
| 2964 | |
| 2965 | return ret; |
| 2966 | } |
| 2967 | |
| 2968 | static int __init iommu_init_mempool(void) |
| 2969 | { |
| 2970 | int ret; |
| 2971 | ret = iommu_iova_cache_init(); |
| 2972 | if (ret) |
| 2973 | return ret; |
| 2974 | |
| 2975 | ret = iommu_domain_cache_init(); |
| 2976 | if (ret) |
| 2977 | goto domain_error; |
| 2978 | |
| 2979 | ret = iommu_devinfo_cache_init(); |
| 2980 | if (!ret) |
| 2981 | return ret; |
| 2982 | |
| 2983 | kmem_cache_destroy(iommu_domain_cache); |
| 2984 | domain_error: |
| 2985 | kmem_cache_destroy(iommu_iova_cache); |
| 2986 | |
| 2987 | return -ENOMEM; |
| 2988 | } |
| 2989 | |
| 2990 | static void __init iommu_exit_mempool(void) |
| 2991 | { |
| 2992 | kmem_cache_destroy(iommu_devinfo_cache); |
| 2993 | kmem_cache_destroy(iommu_domain_cache); |
| 2994 | kmem_cache_destroy(iommu_iova_cache); |
| 2995 | |
| 2996 | } |
| 2997 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2998 | static void __init init_no_remapping_devices(void) |
| 2999 | { |
| 3000 | struct dmar_drhd_unit *drhd; |
| 3001 | |
| 3002 | for_each_drhd_unit(drhd) { |
| 3003 | if (!drhd->include_all) { |
| 3004 | int i; |
| 3005 | for (i = 0; i < drhd->devices_cnt; i++) |
| 3006 | if (drhd->devices[i] != NULL) |
| 3007 | break; |
| 3008 | /* ignore DMAR unit if no pci devices exist */ |
| 3009 | if (i == drhd->devices_cnt) |
| 3010 | drhd->ignored = 1; |
| 3011 | } |
| 3012 | } |
| 3013 | |
| 3014 | if (dmar_map_gfx) |
| 3015 | return; |
| 3016 | |
| 3017 | for_each_drhd_unit(drhd) { |
| 3018 | int i; |
| 3019 | if (drhd->ignored || drhd->include_all) |
| 3020 | continue; |
| 3021 | |
| 3022 | for (i = 0; i < drhd->devices_cnt; i++) |
| 3023 | if (drhd->devices[i] && |
| 3024 | !IS_GFX_DEVICE(drhd->devices[i])) |
| 3025 | break; |
| 3026 | |
| 3027 | if (i < drhd->devices_cnt) |
| 3028 | continue; |
| 3029 | |
| 3030 | /* bypass IOMMU if it is just for gfx devices */ |
| 3031 | drhd->ignored = 1; |
| 3032 | for (i = 0; i < drhd->devices_cnt; i++) { |
| 3033 | if (!drhd->devices[i]) |
| 3034 | continue; |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 3035 | drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3036 | } |
| 3037 | } |
| 3038 | } |
| 3039 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3040 | #ifdef CONFIG_SUSPEND |
| 3041 | static int init_iommu_hw(void) |
| 3042 | { |
| 3043 | struct dmar_drhd_unit *drhd; |
| 3044 | struct intel_iommu *iommu = NULL; |
| 3045 | |
| 3046 | for_each_active_iommu(iommu, drhd) |
| 3047 | if (iommu->qi) |
| 3048 | dmar_reenable_qi(iommu); |
| 3049 | |
| 3050 | for_each_active_iommu(iommu, drhd) { |
| 3051 | iommu_flush_write_buffer(iommu); |
| 3052 | |
| 3053 | iommu_set_root_entry(iommu); |
| 3054 | |
| 3055 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3056 | DMA_CCMD_GLOBAL_INVL); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3057 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3058 | DMA_TLB_GLOBAL_FLUSH); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3059 | iommu_disable_protect_mem_regions(iommu); |
| 3060 | iommu_enable_translation(iommu); |
| 3061 | } |
| 3062 | |
| 3063 | return 0; |
| 3064 | } |
| 3065 | |
| 3066 | static void iommu_flush_all(void) |
| 3067 | { |
| 3068 | struct dmar_drhd_unit *drhd; |
| 3069 | struct intel_iommu *iommu; |
| 3070 | |
| 3071 | for_each_active_iommu(iommu, drhd) { |
| 3072 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3073 | DMA_CCMD_GLOBAL_INVL); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3074 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3075 | DMA_TLB_GLOBAL_FLUSH); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3076 | } |
| 3077 | } |
| 3078 | |
| 3079 | static int iommu_suspend(struct sys_device *dev, pm_message_t state) |
| 3080 | { |
| 3081 | struct dmar_drhd_unit *drhd; |
| 3082 | struct intel_iommu *iommu = NULL; |
| 3083 | unsigned long flag; |
| 3084 | |
| 3085 | for_each_active_iommu(iommu, drhd) { |
| 3086 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, |
| 3087 | GFP_ATOMIC); |
| 3088 | if (!iommu->iommu_state) |
| 3089 | goto nomem; |
| 3090 | } |
| 3091 | |
| 3092 | iommu_flush_all(); |
| 3093 | |
| 3094 | for_each_active_iommu(iommu, drhd) { |
| 3095 | iommu_disable_translation(iommu); |
| 3096 | |
| 3097 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 3098 | |
| 3099 | iommu->iommu_state[SR_DMAR_FECTL_REG] = |
| 3100 | readl(iommu->reg + DMAR_FECTL_REG); |
| 3101 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = |
| 3102 | readl(iommu->reg + DMAR_FEDATA_REG); |
| 3103 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = |
| 3104 | readl(iommu->reg + DMAR_FEADDR_REG); |
| 3105 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = |
| 3106 | readl(iommu->reg + DMAR_FEUADDR_REG); |
| 3107 | |
| 3108 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 3109 | } |
| 3110 | return 0; |
| 3111 | |
| 3112 | nomem: |
| 3113 | for_each_active_iommu(iommu, drhd) |
| 3114 | kfree(iommu->iommu_state); |
| 3115 | |
| 3116 | return -ENOMEM; |
| 3117 | } |
| 3118 | |
| 3119 | static int iommu_resume(struct sys_device *dev) |
| 3120 | { |
| 3121 | struct dmar_drhd_unit *drhd; |
| 3122 | struct intel_iommu *iommu = NULL; |
| 3123 | unsigned long flag; |
| 3124 | |
| 3125 | if (init_iommu_hw()) { |
| 3126 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); |
| 3127 | return -EIO; |
| 3128 | } |
| 3129 | |
| 3130 | for_each_active_iommu(iommu, drhd) { |
| 3131 | |
| 3132 | spin_lock_irqsave(&iommu->register_lock, flag); |
| 3133 | |
| 3134 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], |
| 3135 | iommu->reg + DMAR_FECTL_REG); |
| 3136 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], |
| 3137 | iommu->reg + DMAR_FEDATA_REG); |
| 3138 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], |
| 3139 | iommu->reg + DMAR_FEADDR_REG); |
| 3140 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], |
| 3141 | iommu->reg + DMAR_FEUADDR_REG); |
| 3142 | |
| 3143 | spin_unlock_irqrestore(&iommu->register_lock, flag); |
| 3144 | } |
| 3145 | |
| 3146 | for_each_active_iommu(iommu, drhd) |
| 3147 | kfree(iommu->iommu_state); |
| 3148 | |
| 3149 | return 0; |
| 3150 | } |
| 3151 | |
| 3152 | static struct sysdev_class iommu_sysclass = { |
| 3153 | .name = "iommu", |
| 3154 | .resume = iommu_resume, |
| 3155 | .suspend = iommu_suspend, |
| 3156 | }; |
| 3157 | |
| 3158 | static struct sys_device device_iommu = { |
| 3159 | .cls = &iommu_sysclass, |
| 3160 | }; |
| 3161 | |
| 3162 | static int __init init_iommu_sysfs(void) |
| 3163 | { |
| 3164 | int error; |
| 3165 | |
| 3166 | error = sysdev_class_register(&iommu_sysclass); |
| 3167 | if (error) |
| 3168 | return error; |
| 3169 | |
| 3170 | error = sysdev_register(&device_iommu); |
| 3171 | if (error) |
| 3172 | sysdev_class_unregister(&iommu_sysclass); |
| 3173 | |
| 3174 | return error; |
| 3175 | } |
| 3176 | |
| 3177 | #else |
| 3178 | static int __init init_iommu_sysfs(void) |
| 3179 | { |
| 3180 | return 0; |
| 3181 | } |
| 3182 | #endif /* CONFIG_PM */ |
| 3183 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3184 | int __init intel_iommu_init(void) |
| 3185 | { |
| 3186 | int ret = 0; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3187 | int force_on = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3188 | |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3189 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
| 3190 | force_on = tboot_force_iommu(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3191 | |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3192 | if (dmar_table_init()) { |
| 3193 | if (force_on) |
| 3194 | panic("tboot: Failed to initialize DMAR table\n"); |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 3195 | return -ENODEV; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3196 | } |
| 3197 | |
| 3198 | if (dmar_dev_scope_init()) { |
| 3199 | if (force_on) |
| 3200 | panic("tboot: Failed to initialize DMAR device scope\n"); |
| 3201 | return -ENODEV; |
| 3202 | } |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 3203 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 3204 | /* |
| 3205 | * Check the need for DMA-remapping initialization now. |
| 3206 | * Above initialization will also be used by Interrupt-remapping. |
| 3207 | */ |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3208 | if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled) |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 3209 | return -ENODEV; |
| 3210 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3211 | iommu_init_mempool(); |
| 3212 | dmar_init_reserved_ranges(); |
| 3213 | |
| 3214 | init_no_remapping_devices(); |
| 3215 | |
| 3216 | ret = init_dmars(); |
| 3217 | if (ret) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3218 | if (force_on) |
| 3219 | panic("tboot: Failed to initialize DMARs\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3220 | printk(KERN_ERR "IOMMU: dmar init failed\n"); |
| 3221 | put_iova_domain(&reserved_iova_list); |
| 3222 | iommu_exit_mempool(); |
| 3223 | return ret; |
| 3224 | } |
| 3225 | printk(KERN_INFO |
| 3226 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); |
| 3227 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3228 | init_timer(&unmap_timer); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3229 | force_iommu = 1; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3230 | |
| 3231 | if (!iommu_pass_through) { |
| 3232 | printk(KERN_INFO |
| 3233 | "Multi-level page-table translation for DMAR.\n"); |
| 3234 | dma_ops = &intel_dma_ops; |
| 3235 | } else |
| 3236 | printk(KERN_INFO |
| 3237 | "DMAR: Pass through translation for DMAR.\n"); |
| 3238 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3239 | init_iommu_sysfs(); |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 3240 | |
| 3241 | register_iommu(&intel_iommu_ops); |
| 3242 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3243 | return 0; |
| 3244 | } |
Keshavamurthy, Anil S | e820482 | 2007-10-21 16:41:55 -0700 | [diff] [blame] | 3245 | |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 3246 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
| 3247 | struct pci_dev *pdev) |
| 3248 | { |
| 3249 | struct pci_dev *tmp, *parent; |
| 3250 | |
| 3251 | if (!iommu || !pdev) |
| 3252 | return; |
| 3253 | |
| 3254 | /* dependent device detach */ |
| 3255 | tmp = pci_find_upstream_pcie_bridge(pdev); |
| 3256 | /* Secondary interface's bus number and devfn 0 */ |
| 3257 | if (tmp) { |
| 3258 | parent = pdev->bus->self; |
| 3259 | while (parent != tmp) { |
| 3260 | iommu_detach_dev(iommu, parent->bus->number, |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3261 | parent->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 3262 | parent = parent->bus->self; |
| 3263 | } |
| 3264 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ |
| 3265 | iommu_detach_dev(iommu, |
| 3266 | tmp->subordinate->number, 0); |
| 3267 | else /* this is a legacy PCI bridge */ |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3268 | iommu_detach_dev(iommu, tmp->bus->number, |
| 3269 | tmp->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 3270 | } |
| 3271 | } |
| 3272 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3273 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3274 | struct pci_dev *pdev) |
| 3275 | { |
| 3276 | struct device_domain_info *info; |
| 3277 | struct intel_iommu *iommu; |
| 3278 | unsigned long flags; |
| 3279 | int found = 0; |
| 3280 | struct list_head *entry, *tmp; |
| 3281 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3282 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
| 3283 | pdev->devfn); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3284 | if (!iommu) |
| 3285 | return; |
| 3286 | |
| 3287 | spin_lock_irqsave(&device_domain_lock, flags); |
| 3288 | list_for_each_safe(entry, tmp, &domain->devices) { |
| 3289 | info = list_entry(entry, struct device_domain_info, link); |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3290 | /* No need to compare PCI domain; it has to be the same */ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3291 | if (info->bus == pdev->bus->number && |
| 3292 | info->devfn == pdev->devfn) { |
| 3293 | list_del(&info->link); |
| 3294 | list_del(&info->global); |
| 3295 | if (info->dev) |
| 3296 | info->dev->dev.archdata.iommu = NULL; |
| 3297 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 3298 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3299 | iommu_disable_dev_iotlb(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3300 | iommu_detach_dev(iommu, info->bus, info->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 3301 | iommu_detach_dependent_devices(iommu, pdev); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3302 | free_devinfo_mem(info); |
| 3303 | |
| 3304 | spin_lock_irqsave(&device_domain_lock, flags); |
| 3305 | |
| 3306 | if (found) |
| 3307 | break; |
| 3308 | else |
| 3309 | continue; |
| 3310 | } |
| 3311 | |
| 3312 | /* if there is no other devices under the same iommu |
| 3313 | * owned by this domain, clear this iommu in iommu_bmp |
| 3314 | * update iommu count and coherency |
| 3315 | */ |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3316 | if (iommu == device_to_iommu(info->segment, info->bus, |
| 3317 | info->devfn)) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3318 | found = 1; |
| 3319 | } |
| 3320 | |
| 3321 | if (found == 0) { |
| 3322 | unsigned long tmp_flags; |
| 3323 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); |
| 3324 | clear_bit(iommu->seq_id, &domain->iommu_bmp); |
| 3325 | domain->iommu_count--; |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 3326 | domain_update_iommu_cap(domain); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3327 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
| 3328 | } |
| 3329 | |
| 3330 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 3331 | } |
| 3332 | |
| 3333 | static void vm_domain_remove_all_dev_info(struct dmar_domain *domain) |
| 3334 | { |
| 3335 | struct device_domain_info *info; |
| 3336 | struct intel_iommu *iommu; |
| 3337 | unsigned long flags1, flags2; |
| 3338 | |
| 3339 | spin_lock_irqsave(&device_domain_lock, flags1); |
| 3340 | while (!list_empty(&domain->devices)) { |
| 3341 | info = list_entry(domain->devices.next, |
| 3342 | struct device_domain_info, link); |
| 3343 | list_del(&info->link); |
| 3344 | list_del(&info->global); |
| 3345 | if (info->dev) |
| 3346 | info->dev->dev.archdata.iommu = NULL; |
| 3347 | |
| 3348 | spin_unlock_irqrestore(&device_domain_lock, flags1); |
| 3349 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3350 | iommu_disable_dev_iotlb(info); |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3351 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3352 | iommu_detach_dev(iommu, info->bus, info->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 3353 | iommu_detach_dependent_devices(iommu, info->dev); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3354 | |
| 3355 | /* clear this iommu in iommu_bmp, update iommu count |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 3356 | * and capabilities |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3357 | */ |
| 3358 | spin_lock_irqsave(&domain->iommu_lock, flags2); |
| 3359 | if (test_and_clear_bit(iommu->seq_id, |
| 3360 | &domain->iommu_bmp)) { |
| 3361 | domain->iommu_count--; |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 3362 | domain_update_iommu_cap(domain); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 3363 | } |
| 3364 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); |
| 3365 | |
| 3366 | free_devinfo_mem(info); |
| 3367 | spin_lock_irqsave(&device_domain_lock, flags1); |
| 3368 | } |
| 3369 | spin_unlock_irqrestore(&device_domain_lock, flags1); |
| 3370 | } |
| 3371 | |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3372 | /* domain id for virtual machine, it won't be set in context */ |
| 3373 | static unsigned long vm_domid; |
| 3374 | |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3375 | static int vm_domain_min_agaw(struct dmar_domain *domain) |
| 3376 | { |
| 3377 | int i; |
| 3378 | int min_agaw = domain->agaw; |
| 3379 | |
| 3380 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
| 3381 | for (; i < g_num_of_iommus; ) { |
| 3382 | if (min_agaw > g_iommus[i]->agaw) |
| 3383 | min_agaw = g_iommus[i]->agaw; |
| 3384 | |
| 3385 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); |
| 3386 | } |
| 3387 | |
| 3388 | return min_agaw; |
| 3389 | } |
| 3390 | |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3391 | static struct dmar_domain *iommu_alloc_vm_domain(void) |
| 3392 | { |
| 3393 | struct dmar_domain *domain; |
| 3394 | |
| 3395 | domain = alloc_domain_mem(); |
| 3396 | if (!domain) |
| 3397 | return NULL; |
| 3398 | |
| 3399 | domain->id = vm_domid++; |
| 3400 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); |
| 3401 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; |
| 3402 | |
| 3403 | return domain; |
| 3404 | } |
| 3405 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3406 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3407 | { |
| 3408 | int adjust_width; |
| 3409 | |
| 3410 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3411 | spin_lock_init(&domain->iommu_lock); |
| 3412 | |
| 3413 | domain_reserve_special_ranges(domain); |
| 3414 | |
| 3415 | /* calculate AGAW */ |
| 3416 | domain->gaw = guest_width; |
| 3417 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 3418 | domain->agaw = width_to_agaw(adjust_width); |
| 3419 | |
| 3420 | INIT_LIST_HEAD(&domain->devices); |
| 3421 | |
| 3422 | domain->iommu_count = 0; |
| 3423 | domain->iommu_coherency = 0; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3424 | domain->max_addr = 0; |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3425 | |
| 3426 | /* always allocate the top pgd */ |
| 3427 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); |
| 3428 | if (!domain->pgd) |
| 3429 | return -ENOMEM; |
| 3430 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); |
| 3431 | return 0; |
| 3432 | } |
| 3433 | |
| 3434 | static void iommu_free_vm_domain(struct dmar_domain *domain) |
| 3435 | { |
| 3436 | unsigned long flags; |
| 3437 | struct dmar_drhd_unit *drhd; |
| 3438 | struct intel_iommu *iommu; |
| 3439 | unsigned long i; |
| 3440 | unsigned long ndomains; |
| 3441 | |
| 3442 | for_each_drhd_unit(drhd) { |
| 3443 | if (drhd->ignored) |
| 3444 | continue; |
| 3445 | iommu = drhd->iommu; |
| 3446 | |
| 3447 | ndomains = cap_ndoms(iommu->cap); |
| 3448 | i = find_first_bit(iommu->domain_ids, ndomains); |
| 3449 | for (; i < ndomains; ) { |
| 3450 | if (iommu->domains[i] == domain) { |
| 3451 | spin_lock_irqsave(&iommu->lock, flags); |
| 3452 | clear_bit(i, iommu->domain_ids); |
| 3453 | iommu->domains[i] = NULL; |
| 3454 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 3455 | break; |
| 3456 | } |
| 3457 | i = find_next_bit(iommu->domain_ids, ndomains, i+1); |
| 3458 | } |
| 3459 | } |
| 3460 | } |
| 3461 | |
| 3462 | static void vm_domain_exit(struct dmar_domain *domain) |
| 3463 | { |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3464 | /* Domain 0 is reserved, so dont process it */ |
| 3465 | if (!domain) |
| 3466 | return; |
| 3467 | |
| 3468 | vm_domain_remove_all_dev_info(domain); |
| 3469 | /* destroy iovas */ |
| 3470 | put_iova_domain(&domain->iovad); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3471 | |
| 3472 | /* clear ptes */ |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 3473 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3474 | |
| 3475 | /* free page tables */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3476 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 3477 | |
| 3478 | iommu_free_vm_domain(domain); |
| 3479 | free_domain_mem(domain); |
| 3480 | } |
| 3481 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3482 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3483 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3484 | struct dmar_domain *dmar_domain; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3485 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3486 | dmar_domain = iommu_alloc_vm_domain(); |
| 3487 | if (!dmar_domain) { |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3488 | printk(KERN_ERR |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3489 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
| 3490 | return -ENOMEM; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3491 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3492 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3493 | printk(KERN_ERR |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3494 | "intel_iommu_domain_init() failed\n"); |
| 3495 | vm_domain_exit(dmar_domain); |
| 3496 | return -ENOMEM; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3497 | } |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3498 | domain->priv = dmar_domain; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3499 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3500 | return 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3501 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3502 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3503 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3504 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 3505 | struct dmar_domain *dmar_domain = domain->priv; |
| 3506 | |
| 3507 | domain->priv = NULL; |
| 3508 | vm_domain_exit(dmar_domain); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3509 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3510 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 3511 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
| 3512 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3513 | { |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 3514 | struct dmar_domain *dmar_domain = domain->priv; |
| 3515 | struct pci_dev *pdev = to_pci_dev(dev); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3516 | struct intel_iommu *iommu; |
| 3517 | int addr_width; |
| 3518 | u64 end; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3519 | int ret; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3520 | |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3521 | /* normally pdev is not mapped */ |
| 3522 | if (unlikely(domain_context_mapped(pdev))) { |
| 3523 | struct dmar_domain *old_domain; |
| 3524 | |
| 3525 | old_domain = find_domain(pdev); |
| 3526 | if (old_domain) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3527 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
| 3528 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) |
| 3529 | domain_remove_one_dev_info(old_domain, pdev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3530 | else |
| 3531 | domain_remove_dev_info(old_domain); |
| 3532 | } |
| 3533 | } |
| 3534 | |
David Woodhouse | 276dbf9 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 3535 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
| 3536 | pdev->devfn); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3537 | if (!iommu) |
| 3538 | return -ENODEV; |
| 3539 | |
| 3540 | /* check if this iommu agaw is sufficient for max mapped address */ |
| 3541 | addr_width = agaw_to_width(iommu->agaw); |
| 3542 | end = DOMAIN_MAX_ADDR(addr_width); |
| 3543 | end = end & VTD_PAGE_MASK; |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 3544 | if (end < dmar_domain->max_addr) { |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3545 | printk(KERN_ERR "%s: iommu agaw (%d) is not " |
| 3546 | "sufficient for the mapped address (%llx)\n", |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 3547 | __func__, iommu->agaw, dmar_domain->max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3548 | return -EFAULT; |
| 3549 | } |
| 3550 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3551 | ret = domain_add_dev_info(dmar_domain, pdev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3552 | if (ret) |
| 3553 | return ret; |
| 3554 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3555 | ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3556 | return ret; |
| 3557 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3558 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 3559 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
| 3560 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3561 | { |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 3562 | struct dmar_domain *dmar_domain = domain->priv; |
| 3563 | struct pci_dev *pdev = to_pci_dev(dev); |
| 3564 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3565 | domain_remove_one_dev_info(dmar_domain, pdev); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3566 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3567 | |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3568 | static int intel_iommu_map_range(struct iommu_domain *domain, |
| 3569 | unsigned long iova, phys_addr_t hpa, |
| 3570 | size_t size, int iommu_prot) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3571 | { |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3572 | struct dmar_domain *dmar_domain = domain->priv; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3573 | u64 max_addr; |
| 3574 | int addr_width; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3575 | int prot = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3576 | int ret; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3577 | |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3578 | if (iommu_prot & IOMMU_READ) |
| 3579 | prot |= DMA_PTE_READ; |
| 3580 | if (iommu_prot & IOMMU_WRITE) |
| 3581 | prot |= DMA_PTE_WRITE; |
Sheng Yang | 9cf0669 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 3582 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
| 3583 | prot |= DMA_PTE_SNP; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3584 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 3585 | max_addr = iova + size; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3586 | if (dmar_domain->max_addr < max_addr) { |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3587 | int min_agaw; |
| 3588 | u64 end; |
| 3589 | |
| 3590 | /* check if minimum agaw is sufficient for mapped address */ |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3591 | min_agaw = vm_domain_min_agaw(dmar_domain); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3592 | addr_width = agaw_to_width(min_agaw); |
| 3593 | end = DOMAIN_MAX_ADDR(addr_width); |
| 3594 | end = end & VTD_PAGE_MASK; |
| 3595 | if (end < max_addr) { |
| 3596 | printk(KERN_ERR "%s: iommu agaw (%d) is not " |
| 3597 | "sufficient for the mapped address (%llx)\n", |
| 3598 | __func__, min_agaw, max_addr); |
| 3599 | return -EFAULT; |
| 3600 | } |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3601 | dmar_domain->max_addr = max_addr; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3602 | } |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 3603 | /* Round up size to next multiple of PAGE_SIZE, if it and |
| 3604 | the low bits of hpa would take us onto the next page */ |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 3605 | size = aligned_nrpages(hpa, size); |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 3606 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
| 3607 | hpa >> VTD_PAGE_SHIFT, size, prot); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3608 | return ret; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3609 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3610 | |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3611 | static void intel_iommu_unmap_range(struct iommu_domain *domain, |
| 3612 | unsigned long iova, size_t size) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3613 | { |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 3614 | struct dmar_domain *dmar_domain = domain->priv; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3615 | |
Sheng Yang | 4b99d35 | 2009-07-08 11:52:52 +0100 | [diff] [blame] | 3616 | if (!size) |
| 3617 | return; |
| 3618 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 3619 | dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT, |
| 3620 | (iova + size - 1) >> VTD_PAGE_SHIFT); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 3621 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 3622 | if (dmar_domain->max_addr == iova + size) |
| 3623 | dmar_domain->max_addr = iova; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3624 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3625 | |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 3626 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
| 3627 | unsigned long iova) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3628 | { |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 3629 | struct dmar_domain *dmar_domain = domain->priv; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3630 | struct dma_pte *pte; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3631 | u64 phys = 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3632 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 3633 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3634 | if (pte) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3635 | phys = dma_pte_addr(pte); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3636 | |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 3637 | return phys; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 3638 | } |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 3639 | |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 3640 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
| 3641 | unsigned long cap) |
| 3642 | { |
| 3643 | struct dmar_domain *dmar_domain = domain->priv; |
| 3644 | |
| 3645 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
| 3646 | return dmar_domain->iommu_snooping; |
| 3647 | |
| 3648 | return 0; |
| 3649 | } |
| 3650 | |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 3651 | static struct iommu_ops intel_iommu_ops = { |
| 3652 | .domain_init = intel_iommu_domain_init, |
| 3653 | .domain_destroy = intel_iommu_domain_destroy, |
| 3654 | .attach_dev = intel_iommu_attach_device, |
| 3655 | .detach_dev = intel_iommu_detach_device, |
| 3656 | .map = intel_iommu_map_range, |
| 3657 | .unmap = intel_iommu_unmap_range, |
| 3658 | .iova_to_phys = intel_iommu_iova_to_phys, |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 3659 | .domain_has_cap = intel_iommu_domain_has_cap, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 3660 | }; |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 3661 | |
| 3662 | static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) |
| 3663 | { |
| 3664 | /* |
| 3665 | * Mobile 4 Series Chipset neglects to set RWBF capability, |
| 3666 | * but needs it: |
| 3667 | */ |
| 3668 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); |
| 3669 | rwbf_quirk = 1; |
| 3670 | } |
| 3671 | |
| 3672 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |