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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
Paul Walmsleyd8a94452009-12-08 16:21:29 -07004 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
Tony Lindgrence491cf2009-10-20 09:40:47 -070019#include <plat/clock.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020020
Paul Walmsley88b8ba92008-07-03 12:24:46 +030021/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23
Russell Kingc0bf3132009-02-19 13:29:22 +000024/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25#define CORE_CLK_SRC_32K 0x0
26#define CORE_CLK_SRC_DPLL 0x1
27#define CORE_CLK_SRC_DPLL_X2 0x2
28
29/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
30#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
31#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
32#define OMAP2XXX_EN_DPLL_LOCKED 0x3
33
34/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
35#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37#define OMAP3XXX_EN_DPLL_LOCKED 0x7
38
Rajendra Nayak16975a72009-12-08 18:47:16 -070039/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
40#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
41#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
42#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
43#define OMAP4XXX_EN_DPLL_LOCKED 0x7
44
Rajendra Nayaka1391d22009-12-08 18:47:16 -070045/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
46#define DPLL_LOW_POWER_STOP 0x1
47#define DPLL_LOW_POWER_BYPASS 0x5
48#define DPLL_LOCKED 0x7
49
Tony Lindgren646e3ed2008-10-06 15:49:36 +030050int omap2_clk_init(void);
Paul Walmsley543d9372008-03-18 10:22:06 +020051int omap2_clk_enable(struct clk *clk);
52void omap2_clk_disable(struct clk *clk);
53long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
54int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
55int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
Paul Walmsleyfecb4942009-01-27 19:12:50 -070056int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
Paul Walmsley88b8ba92008-07-03 12:24:46 +030057long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
Rajendra Nayaka1391d22009-12-08 18:47:16 -070058unsigned long omap3_dpll_recalc(struct clk *clk);
59unsigned long omap3_clkoutx2_recalc(struct clk *clk);
60void omap3_dpll_allow_idle(struct clk *clk);
61void omap3_dpll_deny_idle(struct clk *clk);
62u32 omap3_dpll_autoidle_read(struct clk *clk);
63int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
64int omap3_noncore_dpll_enable(struct clk *clk);
65void omap3_noncore_dpll_disable(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020066
67#ifdef CONFIG_OMAP_RESET_CLOCKS
68void omap2_clk_disable_unused(struct clk *clk);
69#else
70#define omap2_clk_disable_unused NULL
71#endif
72
Russell King8b9dbc12009-02-12 10:12:59 +000073unsigned long omap2_clksel_recalc(struct clk *clk);
Paul Walmsley333943b2008-08-19 11:08:45 +030074void omap2_init_clk_clkdm(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020075void omap2_init_clksel_parent(struct clk *clk);
76u32 omap2_clksel_get_divisor(struct clk *clk);
77u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
78 u32 *new_div);
79u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
80u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
Paul Walmsley543d9372008-03-18 10:22:06 +020081long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
82int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
Paul Walmsleydf791b32010-01-26 20:13:04 -070083int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
Paul Walmsley543d9372008-03-18 10:22:06 +020084u32 omap2_get_dpll_rate(struct clk *clk);
Rajendra Nayak911bd732009-12-08 18:47:17 -070085void omap2_init_dpll_parent(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020086int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
Tony Lindgrenff00fcc2008-07-03 12:24:44 +030087void omap2_clk_prepare_for_reboot(void);
Paul Walmsley72350b22009-07-24 19:44:03 -060088int omap2_dflt_clk_enable(struct clk *clk);
89void omap2_dflt_clk_disable(struct clk *clk);
90void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
91 u8 *other_bit);
92void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
93 u8 *idlest_bit);
Paul Walmsleydf791b32010-01-26 20:13:04 -070094void omap2xxx_clk_commit(struct clk *clk);
Paul Walmsley543d9372008-03-18 10:22:06 +020095
Paul Walmsleyd8a94452009-12-08 16:21:29 -070096extern u8 cpu_mask;
97
Russell Kingb36ee722008-11-04 17:59:52 +000098extern const struct clkops clkops_omap2_dflt_wait;
Russell Kingbc51da42008-11-04 18:59:32 +000099extern const struct clkops clkops_omap2_dflt;
Russell Kingb36ee722008-11-04 17:59:52 +0000100
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700101extern struct clk_functions omap2_clk_functions;
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700102extern struct clk *vclk, *sclk;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700103
Paul Walmsleyd8a94452009-12-08 16:21:29 -0700104extern const struct clksel_rate gpt_32k_rates[];
105extern const struct clksel_rate gpt_sys_rates[];
106extern const struct clksel_rate gfx_l3_rates[];
Paul Walmsley543d9372008-03-18 10:22:06 +0200107
Paul Walmsley69ecefc2010-01-26 20:13:04 -0700108#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_CPU_FREQ)
109extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
110extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
111#else
112#define omap2_clk_init_cpufreq_table 0
113#define omap2_clk_exit_cpufreq_table 0
114#endif
Paul Walmsley543d9372008-03-18 10:22:06 +0200115
116#endif