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Daniel Walkerda6df072010-04-23 16:04:20 -07001/* include/linux/msm_mdp.h
2 *
3 * Copyright (C) 2007 Google Incorporated
Ken Zhang420dd202013-01-08 14:28:20 -05004 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
Daniel Walkerda6df072010-04-23 16:04:20 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MSM_MDP_H_
16#define _MSM_MDP_H_
17
18#include <linux/types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/fb.h>
Daniel Walkerda6df072010-04-23 16:04:20 -070020
21#define MSMFB_IOCTL_MAGIC 'm'
22#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
23#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070024#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
25#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
26#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
27#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
Carl Vanderlipba093a22011-11-22 13:59:59 -080028#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029/* new ioctls's for set/get ccs matrix */
30#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
31#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
32#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
33 struct mdp_overlay)
34#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080035
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
37 struct msmfb_overlay_data)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080038#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
39
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
41 struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
43 struct mdp_page_protection)
44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
45 struct mdp_overlay)
46#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
47#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
48 struct msmfb_overlay_blt)
49#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Carl Vanderlipba093a22011-11-22 13:59:59 -080050#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
51 struct mdp_histogram_start_req)
52#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070053#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054
55#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
56 struct msmfb_overlay_3d)
57
kuogee hsieh405dc302011-07-21 15:06:59 -070058#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
59 struct msmfb_mixer_info_req)
Nagamalleswararao Ganji0737d652011-10-14 02:02:33 -070060#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
61 struct msmfb_overlay_data)
Vinay Kalia27020d12011-10-14 17:50:29 -070062#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
Vinay Kaliae1ba2702011-12-21 16:24:52 -080063#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
64#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Vinay Kalia27020d12011-10-14 17:50:29 -070065#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
66 struct msmfb_data)
67#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
68 struct msmfb_data)
69#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Pravin Tamkhane02a40682011-11-29 14:17:01 -080070#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
Padmanabhan Komanduruf3b0c232012-07-27 20:46:06 +053071#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
72#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053073#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Kalyan Thota9284a272012-11-02 20:55:30 +053074#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053075#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \
Ken Zhang4e83b932012-12-02 21:15:47 -050076 struct mdp_display_commit)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053077#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
Ken Zhang420dd202013-01-08 14:28:20 -050078#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
Deva Ramasubramanian166b0982013-01-25 20:11:41 -080079#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
80 unsigned int)
Terence Hampson3e636aa2013-05-08 19:01:51 -040081#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
Kuogee Hsieha77eca62012-09-13 13:22:04 -070082
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070083#define FB_TYPE_3D_PANEL 0x10101010
84#define MDP_IMGTYPE2_START 0x10000
85#define MSMFB_DRIVER_VERSION 0xF9E8D701
Daniel Walkerda6df072010-04-23 16:04:20 -070086
87enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070088 NOTIFY_UPDATE_START,
89 NOTIFY_UPDATE_STOP,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -070090 NOTIFY_UPDATE_POWER_OFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070091};
92
93enum {
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070094 NOTIFY_TYPE_NO_UPDATE,
95 NOTIFY_TYPE_SUSPEND,
96 NOTIFY_TYPE_UPDATE,
97};
98
99enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700100 MDP_RGB_565, /* RGB 565 planer */
101 MDP_XRGB_8888, /* RGB 888 padded */
102 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
Padmanabhan Komandurud9f38b02012-02-02 18:57:03 +0530103 MDP_Y_CBCR_H2V2_ADRENO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104 MDP_ARGB_8888, /* ARGB 888 */
105 MDP_RGB_888, /* RGB 888 planer */
106 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
107 MDP_YCRYCB_H2V1, /* YCrYCb interleave */
Pawan Kumar42acdef2013-03-21 19:55:49 +0530108 MDP_CBYCRY_H2V1, /* CbYCrY interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700109 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
110 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700111 MDP_Y_CRCB_H1V2,
112 MDP_Y_CBCR_H1V2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700113 MDP_RGBA_8888, /* ARGB 888 */
114 MDP_BGRA_8888, /* ABGR 888 */
115 MDP_RGBX_8888, /* RGBX 888 */
116 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
117 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
118 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
Pradeep Jilagam9b4a6be2011-10-03 17:19:20 +0530119 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700120 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
121 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
122 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
Adrian Salido-Moreno2b410482011-08-15 10:40:40 -0700123 MDP_YCRCB_H1V1, /* YCrCb interleave */
124 MDP_YCBCR_H1V1, /* YCbCr interleave */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700125 MDP_BGR_565, /* BGR 565 planer */
Adrian Salido-Morenod559ef12012-07-12 20:16:14 -0700126 MDP_BGR_888, /* BGR 888 */
Adrian Salido-Moreno330c0bf2012-08-22 14:15:33 -0700127 MDP_Y_CBCR_H2V2_VENUS,
Pawan Kumar79854382013-02-14 15:27:12 +0530128 MDP_BGRX_8888, /* BGRX 8888 */
Shalabh Jainbea586a2013-08-23 12:30:48 -0700129 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */
130 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */
131 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */
132 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */
133 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */
134 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */
135 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */
136 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */
Ramkumar Radhakrishnan97180fa2013-08-06 20:50:52 -0700137 MDP_YCBYCR_H2V1, /* YCbYCr interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700138 MDP_IMGTYPE_LIMIT,
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800139 MDP_RGB_BORDERFILL, /* border fill pipe */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700140 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
Daniel Walkerda6df072010-04-23 16:04:20 -0700142};
143
144enum {
145 PMEM_IMG,
146 FB_IMG,
147};
148
Liyuan Lid9736632011-11-11 13:47:59 -0800149enum {
150 HSIC_HUE = 0,
151 HSIC_SAT,
152 HSIC_INT,
153 HSIC_CON,
154 NUM_HSIC_PARAM,
155};
156
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700157#define MDSS_MDP_ROT_ONLY 0x80
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700158#define MDSS_MDP_RIGHT_MIXER 0x100
Adrian Salido-Moreno6afd7802013-08-05 14:03:25 -0700159#define MDSS_MDP_DUAL_PIPE 0x200
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700160
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700161/* mdp_blit_req flag values */
162#define MDP_ROT_NOP 0
163#define MDP_FLIP_LR 0x1
164#define MDP_FLIP_UD 0x2
165#define MDP_ROT_90 0x4
166#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
167#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
168#define MDP_DITHER 0x8
169#define MDP_BLUR 0x10
170#define MDP_BLEND_FG_PREMULT 0x20000
Padmanabhan Komandurudd10bf12012-10-17 20:27:33 +0530171#define MDP_IS_FG 0x40000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700172#define MDP_DEINTERLACE 0x80000000
173#define MDP_SHARPENING 0x40000000
174#define MDP_NO_DMA_BARRIER_START 0x20000000
175#define MDP_NO_DMA_BARRIER_END 0x10000000
176#define MDP_NO_BLIT 0x08000000
177#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
178#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
179 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
180#define MDP_BLIT_SRC_GEM 0x04000000
181#define MDP_BLIT_DST_GEM 0x02000000
182#define MDP_BLIT_NON_CACHED 0x01000000
183#define MDP_OV_PIPE_SHARE 0x00800000
184#define MDP_DEINTERLACE_ODD 0x00400000
185#define MDP_OV_PLAY_NOWAIT 0x00200000
186#define MDP_SOURCE_ROTATED_90 0x00100000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700187#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Ajay Singh Parmar4c7ccb32012-02-21 12:56:04 +0530188#define MDP_BACKEND_COMPOSITION 0x00040000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800189#define MDP_BORDERFILL_SUPPORTED 0x00010000
190#define MDP_SECURE_OVERLAY_SESSION 0x00008000
Arun Kumar K.R9ce1fd62013-09-24 11:35:08 -0700191#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000
Adrian Salido-Moreno9a8485c2013-02-06 14:08:28 -0800192#define MDP_OV_PIPE_FORCE_DMA 0x00004000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800193#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Sree Sesha Aravind Vadrevu35143132013-03-12 02:32:06 -0700194#define MDP_BWC_EN 0x00000400
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700195#define MDP_DECIMATION_EN 0x00000800
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700196#define MDP_TRANSP_NOP 0xffffffff
197#define MDP_ALPHA_NOP 0xff
198
199#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
200#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
201#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
202#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
203#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
204/* Sentinel: Don't use! */
205#define MDP_FB_PAGE_PROTECTION_INVALID (5)
206/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
207#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Daniel Walkerda6df072010-04-23 16:04:20 -0700208
209struct mdp_rect {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700210 uint32_t x;
211 uint32_t y;
212 uint32_t w;
213 uint32_t h;
Daniel Walkerda6df072010-04-23 16:04:20 -0700214};
215
216struct mdp_img {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700217 uint32_t width;
218 uint32_t height;
219 uint32_t format;
220 uint32_t offset;
Daniel Walkerda6df072010-04-23 16:04:20 -0700221 int memory_id; /* the file descriptor */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700222 uint32_t priv;
Daniel Walkerda6df072010-04-23 16:04:20 -0700223};
224
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700225/*
226 * {3x3} + {3} ccs matrix
227 */
228
229#define MDP_CCS_RGB2YUV 0
230#define MDP_CCS_YUV2RGB 1
231
232#define MDP_CCS_SIZE 9
233#define MDP_BV_SIZE 3
234
235struct mdp_ccs {
236 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
237 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
238 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
239};
240
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800241struct mdp_csc {
242 int id;
243 uint32_t csc_mv[9];
244 uint32_t csc_pre_bv[3];
245 uint32_t csc_post_bv[3];
246 uint32_t csc_pre_lv[6];
247 uint32_t csc_post_lv[6];
248};
249
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700250/* The version of the mdp_blit_req structure so that
251 * user applications can selectively decide which functionality
252 * to include
253 */
254
255#define MDP_BLIT_REQ_VERSION 2
256
Daniel Walkerda6df072010-04-23 16:04:20 -0700257struct mdp_blit_req {
258 struct mdp_img src;
259 struct mdp_img dst;
260 struct mdp_rect src_rect;
261 struct mdp_rect dst_rect;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700262 uint32_t alpha;
263 uint32_t transp_mask;
264 uint32_t flags;
265 int sharpening_strength; /* -127 <--> 127, default 64 */
Daniel Walkerda6df072010-04-23 16:04:20 -0700266};
267
268struct mdp_blit_req_list {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700269 uint32_t count;
Daniel Walkerda6df072010-04-23 16:04:20 -0700270 struct mdp_blit_req req[];
271};
272
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700273#define MSMFB_DATA_VERSION 2
274
275struct msmfb_data {
276 uint32_t offset;
277 int memory_id;
278 int id;
279 uint32_t flags;
280 uint32_t priv;
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800281 uint32_t iova;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700282};
283
284#define MSMFB_NEW_REQUEST -1
285
286struct msmfb_overlay_data {
287 uint32_t id;
288 struct msmfb_data data;
289 uint32_t version_key;
290 struct msmfb_data plane1_data;
291 struct msmfb_data plane2_data;
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700292 struct msmfb_data dst_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700293};
294
295struct msmfb_img {
296 uint32_t width;
297 uint32_t height;
298 uint32_t format;
299};
300
Vinay Kalia27020d12011-10-14 17:50:29 -0700301#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
302struct msmfb_writeback_data {
303 struct msmfb_data buf_info;
304 struct msmfb_img img;
305};
306
Ken Zhang77ce0192012-08-10 11:27:19 -0400307#define MDP_PP_OPS_ENABLE 0x1
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700308#define MDP_PP_OPS_READ 0x2
309#define MDP_PP_OPS_WRITE 0x4
Ken Zhang77ce0192012-08-10 11:27:19 -0400310#define MDP_PP_OPS_DISABLE 0x8
Ken Zhang824758e2012-08-15 11:02:21 -0400311#define MDP_PP_IGC_FLAG_ROM0 0x10
312#define MDP_PP_IGC_FLAG_ROM1 0x20
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700313
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700314#define MDSS_PP_DSPP_CFG 0x000
315#define MDSS_PP_SSPP_CFG 0x100
316#define MDSS_PP_LM_CFG 0x200
317#define MDSS_PP_WB_CFG 0x300
Ping Li8231ae42013-01-09 20:39:25 -0500318
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700319#define MDSS_PP_ARG_MASK 0x3C00
320#define MDSS_PP_ARG_NUM 4
Carl Vanderlip793aa582013-03-18 10:18:47 -0700321#define MDSS_PP_ARG_SHIFT 10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700322#define MDSS_PP_LOCATION_MASK 0x0300
323#define MDSS_PP_LOGICAL_MASK 0x00FF
Ping Li8231ae42013-01-09 20:39:25 -0500324
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700325#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
326#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
Ping Li8231ae42013-01-09 20:39:25 -0500327#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
328#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
329
330
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700331struct mdp_qseed_cfg {
332 uint32_t table_num;
333 uint32_t ops;
334 uint32_t len;
335 uint32_t *data;
336};
337
Ping Li87cca832013-01-30 18:27:52 -0500338struct mdp_sharp_cfg {
339 uint32_t flags;
340 uint32_t strength;
341 uint32_t edge_thr;
342 uint32_t smooth_thr;
343 uint32_t noise_thr;
344};
345
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700346struct mdp_qseed_cfg_data {
347 uint32_t block;
348 struct mdp_qseed_cfg qseed_data;
349};
350
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800351#define MDP_OVERLAY_PP_CSC_CFG 0x1
352#define MDP_OVERLAY_PP_QSEED_CFG 0x2
353#define MDP_OVERLAY_PP_PA_CFG 0x4
354#define MDP_OVERLAY_PP_IGC_CFG 0x8
Ping Li87cca832013-01-30 18:27:52 -0500355#define MDP_OVERLAY_PP_SHARP_CFG 0x10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700356#define MDP_OVERLAY_PP_HIST_CFG 0x20
Carl Vanderlip57027132013-03-18 13:53:16 -0700357#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700358
359#define MDP_CSC_FLAG_ENABLE 0x1
360#define MDP_CSC_FLAG_YUV_IN 0x2
361#define MDP_CSC_FLAG_YUV_OUT 0x4
362
363struct mdp_csc_cfg {
364 /* flags for enable CSC, toggling RGB,YUV input/output */
365 uint32_t flags;
366 uint32_t csc_mv[9];
367 uint32_t csc_pre_bv[3];
368 uint32_t csc_post_bv[3];
369 uint32_t csc_pre_lv[6];
370 uint32_t csc_post_lv[6];
371};
372
373struct mdp_csc_cfg_data {
374 uint32_t block;
375 struct mdp_csc_cfg csc_data;
376};
377
Ping Li58229242012-11-30 14:05:43 -0500378struct mdp_pa_cfg {
379 uint32_t flags;
380 uint32_t hue_adj;
381 uint32_t sat_adj;
382 uint32_t val_adj;
383 uint32_t cont_adj;
384};
385
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800386struct mdp_igc_lut_data {
387 uint32_t block;
388 uint32_t len, ops;
389 uint32_t *c0_c1_data;
390 uint32_t *c2_data;
391};
392
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700393struct mdp_histogram_cfg {
394 uint32_t ops;
395 uint32_t block;
396 uint8_t frame_cnt;
397 uint8_t bit_mask;
398 uint16_t num_bins;
399};
400
Carl Vanderlip57027132013-03-18 13:53:16 -0700401struct mdp_hist_lut_data {
402 uint32_t block;
403 uint32_t ops;
404 uint32_t len;
405 uint32_t *data;
406};
407
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700408struct mdp_overlay_pp_params {
409 uint32_t config_ops;
410 struct mdp_csc_cfg csc_cfg;
411 struct mdp_qseed_cfg qseed_cfg[2];
Ping Li58229242012-11-30 14:05:43 -0500412 struct mdp_pa_cfg pa_cfg;
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800413 struct mdp_igc_lut_data igc_cfg;
Ping Li87cca832013-01-30 18:27:52 -0500414 struct mdp_sharp_cfg sharp_cfg;
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700415 struct mdp_histogram_cfg hist_cfg;
Carl Vanderlip57027132013-03-18 13:53:16 -0700416 struct mdp_hist_lut_data hist_lut_cfg;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700417};
418
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530419/**
420 * enum mdss_mdp_blend_op - Different blend operations set by userspace
421 *
422 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
423 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
424 * would appear opaque in case fg plane alpha is
425 * 0xff.
426 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has
427 * alpha pre-multiplication done. If fg plane alpha
428 * is less than 0xff, apply modulation as well. This
429 * operation is intended on layers having alpha
430 * channel.
431 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha
432 * pre-multiplied. Apply pre-multiplication. If fg
433 * plane alpha is less than 0xff, apply modulation as
434 * well.
435 * @BLEND_OP_MAX: Used to track maximum blend operation possible by
436 * mdp.
437 */
438enum mdss_mdp_blend_op {
439 BLEND_OP_NOT_DEFINED = 0,
440 BLEND_OP_OPAQUE,
441 BLEND_OP_PREMULTIPLIED,
442 BLEND_OP_COVERAGE,
443 BLEND_OP_MAX,
444};
445
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700446struct mdp_overlay {
447 struct msmfb_img src;
448 struct mdp_rect src_rect;
449 struct mdp_rect dst_rect;
450 uint32_t z_order; /* stage number */
451 uint32_t is_fg; /* control alpha & transp */
452 uint32_t alpha;
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530453 uint32_t blend_op;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700454 uint32_t transp_mask;
455 uint32_t flags;
456 uint32_t id;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700457 uint32_t user_data[7];
458 uint8_t horz_deci;
459 uint8_t vert_deci;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700460 struct mdp_overlay_pp_params overlay_pp_cfg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700461};
462
463struct msmfb_overlay_3d {
464 uint32_t is_3d;
465 uint32_t width;
466 uint32_t height;
467};
468
469
470struct msmfb_overlay_blt {
471 uint32_t enable;
472 uint32_t offset;
473 uint32_t width;
474 uint32_t height;
475 uint32_t bpp;
476};
477
478struct mdp_histogram {
479 uint32_t frame_cnt;
480 uint32_t bin_cnt;
481 uint32_t *r;
482 uint32_t *g;
483 uint32_t *b;
484};
485
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700486enum {
487 DISPLAY_MISR_EDP,
488 DISPLAY_MISR_DSI0,
489 DISPLAY_MISR_DSI1,
490 DISPLAY_MISR_HDMI,
491 DISPLAY_MISR_LCDC,
492 DISPLAY_MISR_ATV,
493 DISPLAY_MISR_DSI_CMD,
494 DISPLAY_MISR_MAX
495};
496
497enum {
498 MISR_OP_NONE,
499 MISR_OP_SFM,
500 MISR_OP_MFM,
501 MISR_OP_BM,
502 MISR_OP_MAX
503};
504
505struct mdp_misr {
506 uint32_t block_id;
507 uint32_t frame_count;
508 uint32_t crc_op_mode;
509 uint32_t crc_value[32];
510};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800511
512/*
513
Ken Zhang6a431632012-08-08 16:46:22 -0400514 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800515
516 MDP_BLOCK_RESERVED is provided for backward compatibility and is
517 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
518 instead.
519
Ken Zhang6a431632012-08-08 16:46:22 -0400520 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
521 same for others.
522
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800523*/
524
525enum {
526 MDP_BLOCK_RESERVED = 0,
527 MDP_BLOCK_OVERLAY_0,
528 MDP_BLOCK_OVERLAY_1,
529 MDP_BLOCK_VG_1,
530 MDP_BLOCK_VG_2,
531 MDP_BLOCK_RGB_1,
532 MDP_BLOCK_RGB_2,
533 MDP_BLOCK_DMA_P,
534 MDP_BLOCK_DMA_S,
535 MDP_BLOCK_DMA_E,
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700536 MDP_BLOCK_OVERLAY_2,
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700537 MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
Ken Zhang6a431632012-08-08 16:46:22 -0400538 MDP_LOGICAL_BLOCK_DISP_1,
539 MDP_LOGICAL_BLOCK_DISP_2,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800540 MDP_BLOCK_MAX,
541};
542
Carl Vanderlipba093a22011-11-22 13:59:59 -0800543/*
544 * mdp_histogram_start_req is used to provide the parameters for
545 * histogram start request
546 */
547
548struct mdp_histogram_start_req {
549 uint32_t block;
550 uint8_t frame_cnt;
551 uint8_t bit_mask;
Carl Vanderlip16316322012-10-08 16:47:34 -0700552 uint16_t num_bins;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800553};
554
555/*
556 * mdp_histogram_data is used to return the histogram data, once
557 * the histogram is done/stopped/cance
558 */
559
560struct mdp_histogram_data {
561 uint32_t block;
Ken Zhang0f523bd2012-08-23 11:14:03 -0400562 uint32_t bin_cnt;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800563 uint32_t *c0;
564 uint32_t *c1;
565 uint32_t *c2;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800566 uint32_t *extra_info;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800567};
568
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800569struct mdp_pcc_coeff {
570 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
571};
572
573struct mdp_pcc_cfg_data {
574 uint32_t block;
575 uint32_t ops;
576 struct mdp_pcc_coeff r, g, b;
577};
578
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400579#define MDP_GAMUT_TABLE_NUM 8
580
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800581enum {
582 mdp_lut_igc,
583 mdp_lut_pgc,
584 mdp_lut_hist,
585 mdp_lut_max,
586};
587
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800588struct mdp_ar_gc_lut_data {
589 uint32_t x_start;
590 uint32_t slope;
591 uint32_t offset;
592};
593
594struct mdp_pgc_lut_data {
595 uint32_t block;
596 uint32_t flags;
597 uint8_t num_r_stages;
598 uint8_t num_g_stages;
599 uint8_t num_b_stages;
600 struct mdp_ar_gc_lut_data *r_data;
601 struct mdp_ar_gc_lut_data *g_data;
602 struct mdp_ar_gc_lut_data *b_data;
603};
604
605
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800606struct mdp_lut_cfg_data {
607 uint32_t lut_type;
608 union {
609 struct mdp_igc_lut_data igc_lut_data;
610 struct mdp_pgc_lut_data pgc_lut_data;
611 struct mdp_hist_lut_data hist_lut_data;
612 } data;
613};
614
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700615struct mdp_bl_scale_data {
616 uint32_t min_lvl;
617 uint32_t scale;
618};
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700619
Ken Zhang77ce0192012-08-10 11:27:19 -0400620struct mdp_pa_cfg_data {
621 uint32_t block;
Ping Li58229242012-11-30 14:05:43 -0500622 struct mdp_pa_cfg pa_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400623};
624
Ken Zhang7fb85772012-08-18 14:51:33 -0400625struct mdp_dither_cfg_data {
626 uint32_t block;
627 uint32_t flags;
628 uint32_t g_y_depth;
629 uint32_t r_cr_depth;
630 uint32_t b_cb_depth;
631};
632
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400633struct mdp_gamut_cfg_data {
634 uint32_t block;
635 uint32_t flags;
636 uint32_t gamut_first;
637 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
638 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
639 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
640 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
641};
642
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700643struct mdp_calib_config_data {
644 uint32_t ops;
645 uint32_t addr;
646 uint32_t data;
647};
648
Arpita Banerjee676eea22013-06-04 19:43:24 -0700649struct mdp_calib_config_buffer {
650 uint32_t ops;
651 uint32_t size;
652 uint32_t *buffer;
653};
654
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700655struct mdp_calib_dcm_state {
656 uint32_t ops;
657 uint32_t dcm_state;
658};
659
660enum {
661 DCM_UNINIT,
662 DCM_UNBLANK,
663 DCM_ENTER,
664 DCM_EXIT,
665 DCM_BLANK,
666};
667
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700668#define MDSS_MAX_BL_BRIGHTNESS 255
669#define AD_BL_LIN_LEN (MDSS_MAX_BL_BRIGHTNESS + 1)
670
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700671#define MDSS_AD_MODE_AUTO_BL 0x0
672#define MDSS_AD_MODE_AUTO_STR 0x1
673#define MDSS_AD_MODE_TARG_STR 0x3
674#define MDSS_AD_MODE_MAN_STR 0x7
Carl Vanderlip819c5092013-05-19 12:08:33 -0700675#define MDSS_AD_MODE_CALIB 0xF
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700676
677#define MDP_PP_AD_INIT 0x10
678#define MDP_PP_AD_CFG 0x20
679
680struct mdss_ad_init {
681 uint32_t asym_lut[33];
682 uint32_t color_corr_lut[33];
683 uint8_t i_control[2];
684 uint16_t black_lvl;
685 uint16_t white_lvl;
686 uint8_t var;
687 uint8_t limit_ampl;
688 uint8_t i_dither;
689 uint8_t slope_max;
690 uint8_t slope_min;
691 uint8_t dither_ctl;
692 uint8_t format;
693 uint8_t auto_size;
694 uint16_t frame_w;
695 uint16_t frame_h;
696 uint8_t logo_v;
697 uint8_t logo_h;
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700698 uint32_t bl_lin_len;
699 uint32_t *bl_lin;
700 uint32_t *bl_lin_inv;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700701};
702
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700703#define MDSS_AD_BL_CTRL_MODE_EN 1
704#define MDSS_AD_BL_CTRL_MODE_DIS 0
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700705struct mdss_ad_cfg {
706 uint32_t mode;
707 uint32_t al_calib_lut[33];
708 uint16_t backlight_min;
709 uint16_t backlight_max;
710 uint16_t backlight_scale;
711 uint16_t amb_light_min;
712 uint16_t filter[2];
713 uint16_t calib[4];
714 uint8_t strength_limit;
715 uint8_t t_filter_recursion;
Carl Vanderlip956360e2013-04-04 20:57:17 -0700716 uint16_t stab_itr;
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700717 uint32_t bl_ctrl_mode;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700718};
719
720/* ops uses standard MDP_PP_* flags */
721struct mdss_ad_init_cfg {
722 uint32_t ops;
723 union {
724 struct mdss_ad_init init;
725 struct mdss_ad_cfg cfg;
726 } params;
727};
728
729/* mode uses MDSS_AD_MODE_* flags */
730struct mdss_ad_input {
731 uint32_t mode;
732 union {
733 uint32_t amb_light;
734 uint32_t strength;
Carl Vanderlip819c5092013-05-19 12:08:33 -0700735 uint32_t calib_bl;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700736 } in;
Carl Vanderlip16e79532013-04-02 11:12:16 -0700737 uint32_t output;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700738};
739
Carl Vanderlipa088b7c2013-05-17 13:52:53 -0700740#define MDSS_CALIB_MODE_BL 0x1
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700741struct mdss_calib_cfg {
742 uint32_t ops;
743 uint32_t calib_mask;
744};
745
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800746enum {
747 mdp_op_pcc_cfg,
748 mdp_op_csc_cfg,
749 mdp_op_lut_cfg,
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700750 mdp_op_qseed_cfg,
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700751 mdp_bl_scale_cfg,
Ken Zhang77ce0192012-08-10 11:27:19 -0400752 mdp_op_pa_cfg,
Ken Zhang7fb85772012-08-18 14:51:33 -0400753 mdp_op_dither_cfg,
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400754 mdp_op_gamut_cfg,
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700755 mdp_op_calib_cfg,
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700756 mdp_op_ad_cfg,
757 mdp_op_ad_input,
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700758 mdp_op_calib_mode,
Arpita Banerjee676eea22013-06-04 19:43:24 -0700759 mdp_op_calib_buffer,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700760 mdp_op_calib_dcm_state,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800761 mdp_op_max,
762};
763
Pawan Kumar9807ea12013-02-14 18:12:02 +0530764enum {
765 WB_FORMAT_NV12,
766 WB_FORMAT_RGB_565,
767 WB_FORMAT_RGB_888,
768 WB_FORMAT_xRGB_8888,
769 WB_FORMAT_ARGB_8888,
Pawan Kumaree811932013-07-09 15:45:01 +0530770 WB_FORMAT_BGRA_8888,
771 WB_FORMAT_BGRX_8888,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530772 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
773};
774
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800775struct msmfb_mdp_pp {
776 uint32_t op;
777 union {
778 struct mdp_pcc_cfg_data pcc_cfg_data;
779 struct mdp_csc_cfg_data csc_cfg_data;
780 struct mdp_lut_cfg_data lut_cfg_data;
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700781 struct mdp_qseed_cfg_data qseed_cfg_data;
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700782 struct mdp_bl_scale_data bl_scale_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400783 struct mdp_pa_cfg_data pa_cfg_data;
Ken Zhang7fb85772012-08-18 14:51:33 -0400784 struct mdp_dither_cfg_data dither_cfg_data;
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400785 struct mdp_gamut_cfg_data gamut_cfg_data;
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700786 struct mdp_calib_config_data calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700787 struct mdss_ad_init_cfg ad_init_cfg;
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700788 struct mdss_calib_cfg mdss_calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700789 struct mdss_ad_input ad_input;
Arpita Banerjee676eea22013-06-04 19:43:24 -0700790 struct mdp_calib_config_buffer calib_buffer;
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700791 struct mdp_calib_dcm_state calib_dcm;
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800792 } data;
793};
794
Manoj Raoa8e39d92013-02-16 08:47:21 -0800795#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
Ken Zhang5cf85c02012-08-23 19:32:52 -0700796enum {
797 metadata_op_none,
798 metadata_op_base_blend,
Ken Zhang420dd202013-01-08 14:28:20 -0500799 metadata_op_frame_rate,
Manoj Raoa8e39d92013-02-16 08:47:21 -0800800 metadata_op_vic,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530801 metadata_op_wb_format,
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800802 metadata_op_get_caps,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700803 metadata_op_crc,
Ken Zhang5cf85c02012-08-23 19:32:52 -0700804 metadata_op_max
805};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800806
Ken Zhang5cf85c02012-08-23 19:32:52 -0700807struct mdp_blend_cfg {
808 uint32_t is_premultiplied;
809};
810
Pawan Kumar9807ea12013-02-14 18:12:02 +0530811struct mdp_mixer_cfg {
812 uint32_t writeback_format;
813 uint32_t alpha;
814};
815
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800816struct mdss_hw_caps {
817 uint32_t mdp_rev;
818 uint8_t rgb_pipes;
819 uint8_t vig_pipes;
820 uint8_t dma_pipes;
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700821 uint32_t features;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800822};
823
Ken Zhang5cf85c02012-08-23 19:32:52 -0700824struct msmfb_metadata {
825 uint32_t op;
826 uint32_t flags;
827 union {
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700828 struct mdp_misr misr_request;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700829 struct mdp_blend_cfg blend_cfg;
Pawan Kumar9807ea12013-02-14 18:12:02 +0530830 struct mdp_mixer_cfg mixer_cfg;
Ken Zhang420dd202013-01-08 14:28:20 -0500831 uint32_t panel_frame_rate;
Manoj Raoa8e39d92013-02-16 08:47:21 -0800832 uint32_t video_info_code;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800833 struct mdss_hw_caps caps;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700834 } data;
835};
Ken Zhang5295d802012-11-07 18:33:16 -0500836
Adrian Salido-Moreno1a74a492013-05-11 21:24:43 -0700837#define MDP_MAX_FENCE_FD 32
Ken Zhang5295d802012-11-07 18:33:16 -0500838#define MDP_BUF_SYNC_FLAG_WAIT 1
839
840struct mdp_buf_sync {
841 uint32_t flags;
842 uint32_t acq_fen_fd_cnt;
Jayant Shekharf3996992013-08-22 14:28:10 +0530843 uint32_t session_id;
Ken Zhang5295d802012-11-07 18:33:16 -0500844 int *acq_fen_fd;
845 int *rel_fen_fd;
846};
847
Terence Hampson3e636aa2013-05-08 19:01:51 -0400848struct mdp_async_blit_req_list {
849 struct mdp_buf_sync sync;
850 uint32_t count;
851 struct mdp_blit_req req[];
852};
853
Ken Zhang4e83b932012-12-02 21:15:47 -0500854#define MDP_DISPLAY_COMMIT_OVERLAY 1
Ken Zhang5e8588d2012-10-01 11:46:42 -0700855struct mdp_buf_fence {
856 uint32_t flags;
857 uint32_t acq_fen_fd_cnt;
858 int acq_fen_fd[MDP_MAX_FENCE_FD];
859 int rel_fen_fd[MDP_MAX_FENCE_FD];
860};
861
Ken Zhang4e83b932012-12-02 21:15:47 -0500862
863struct mdp_display_commit {
864 uint32_t flags;
865 uint32_t wait_for_finish;
866 struct fb_var_screeninfo var;
Ken Zhang5e8588d2012-10-01 11:46:42 -0700867 struct mdp_buf_fence buf_fence;
Jeykumar Sankaranb826f332013-09-07 00:58:43 -0700868 struct mdp_rect roi;
Ken Zhang4e83b932012-12-02 21:15:47 -0500869};
870
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700871struct mdp_page_protection {
872 uint32_t page_protection;
873};
874
kuogee hsieh405dc302011-07-21 15:06:59 -0700875
876struct mdp_mixer_info {
877 int pndx;
878 int pnum;
879 int ptype;
880 int mixer_num;
881 int z_order;
882};
883
884#define MAX_PIPE_PER_MIXER 4
885
886struct msmfb_mixer_info_req {
887 int mixer_num;
888 int cnt;
889 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
890};
891
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700892enum {
893 DISPLAY_SUBSYSTEM_ID,
894 ROTATOR_SUBSYSTEM_ID,
895};
kuogee hsieh405dc302011-07-21 15:06:59 -0700896
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800897enum {
898 MDP_IOMMU_DOMAIN_CP,
899 MDP_IOMMU_DOMAIN_NS,
900};
901
Deva Ramasubramanian166b0982013-01-25 20:11:41 -0800902enum {
903 MDP_WRITEBACK_MIRROR_OFF,
904 MDP_WRITEBACK_MIRROR_ON,
905 MDP_WRITEBACK_MIRROR_PAUSE,
906 MDP_WRITEBACK_MIRROR_RESUME,
907};
908
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700909#ifdef __KERNEL__
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800910int msm_fb_get_iommu_domain(struct fb_info *info, int domain);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700911/* get the framebuffer physical address information */
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700912int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
913 int subsys_id);
Vinay Kalia27020d12011-10-14 17:50:29 -0700914struct fb_info *msm_fb_get_writeback_fb(void);
915int msm_fb_writeback_init(struct fb_info *info);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800916int msm_fb_writeback_start(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700917int msm_fb_writeback_queue_buffer(struct fb_info *info,
918 struct msmfb_data *data);
919int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
920 struct msmfb_data *data);
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800921int msm_fb_writeback_stop(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -0700922int msm_fb_writeback_terminate(struct fb_info *info);
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -0800923int msm_fb_writeback_set_secure(struct fb_info *info, int enable);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700924#endif
925
926#endif /*_MSM_MDP_H_*/