blob: f99e5de8afacfd6bea9590f9f31a39f357abc888 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070029#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030
31#include "clock-local.h"
32#include "clock-rpm.h"
33#include "clock-voter.h"
34#include "clock-dss-8960.h"
35#include "devices.h"
Vikram Mulukutla681d8682012-03-09 23:56:20 -080036#include "clock-pll.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070037
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080044#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Tianyi Gou352955d2012-05-18 19:44:01 -070045#define SFAB_SATA_S_HCLK_CTL_REG REG(0x2480)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070046#define CE1_HCLK_CTL_REG REG(0x2720)
47#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou05e01102012-02-08 22:15:49 -080048#define PRNG_CLK_NS_REG REG(0x2E80)
Tianyi Gou41515e22011-09-01 19:37:43 -070049#define CE3_HCLK_CTL_REG REG(0x36C4)
50#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
51#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou6613de52012-01-27 17:57:53 -080053#define CLK_HALT_AFAB_SFAB_STATEA_REG REG(0x2FC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070054#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070055#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
56#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
57#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
58#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070059/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
61#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070062#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070064#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
65#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
67#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
68#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
69#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
70#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
71#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070072#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070073/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#define BB_PLL_ENA_SC0_REG REG(0x34C0)
Tianyi Gou59608a72012-01-31 22:19:30 -080075#define BB_PLL_ENA_RPM_REG REG(0x34A0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#define BB_PLL0_STATUS_REG REG(0x30D8)
77#define BB_PLL5_STATUS_REG REG(0x30F8)
78#define BB_PLL6_STATUS_REG REG(0x3118)
79#define BB_PLL7_STATUS_REG REG(0x3138)
80#define BB_PLL8_L_VAL_REG REG(0x3144)
81#define BB_PLL8_M_VAL_REG REG(0x3148)
82#define BB_PLL8_MODE_REG REG(0x3140)
83#define BB_PLL8_N_VAL_REG REG(0x314C)
84#define BB_PLL8_STATUS_REG REG(0x3158)
85#define BB_PLL8_CONFIG_REG REG(0x3154)
86#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070087#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
88#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070089#define BB_PLL14_MODE_REG REG(0x31C0)
90#define BB_PLL14_L_VAL_REG REG(0x31C4)
91#define BB_PLL14_M_VAL_REG REG(0x31C8)
92#define BB_PLL14_N_VAL_REG REG(0x31CC)
93#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
94#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070095#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070096#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
97#define PMEM_ACLK_CTL_REG REG(0x25A0)
98#define RINGOSC_NS_REG REG(0x2DC0)
99#define RINGOSC_STATUS_REG REG(0x2DCC)
100#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -0800101#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700102#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
103#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
104#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
105#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
106#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
107#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
108#define TSIF_HCLK_CTL_REG REG(0x2700)
109#define TSIF_REF_CLK_MD_REG REG(0x270C)
110#define TSIF_REF_CLK_NS_REG REG(0x2710)
111#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou352955d2012-05-18 19:44:01 -0700112#define SATA_HCLK_CTL_REG REG(0x2C00)
Tianyi Gou41515e22011-09-01 19:37:43 -0700113#define SATA_CLK_SRC_NS_REG REG(0x2C08)
114#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
115#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
116#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
Tianyi Gou352955d2012-05-18 19:44:01 -0700117#define SATA_ACLK_CTL_REG REG(0x2C20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700118#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700119#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
120#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
121#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
122#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
123#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
124#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700125#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700126#define USB_HS1_RESET_REG REG(0x2910)
127#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
128#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700129#define USB_HS3_HCLK_CTL_REG REG(0x3700)
130#define USB_HS3_HCLK_FS_REG REG(0x3704)
131#define USB_HS3_RESET_REG REG(0x3710)
132#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
133#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
134#define USB_HS4_HCLK_CTL_REG REG(0x3720)
135#define USB_HS4_HCLK_FS_REG REG(0x3724)
136#define USB_HS4_RESET_REG REG(0x3730)
137#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
138#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700139#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
140#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
141#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
142#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
143#define USB_HSIC_RESET_REG REG(0x2934)
144#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
145#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
146#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700147#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700148#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
Tianyi Gou6613de52012-01-27 17:57:53 -0800149#define PCIE_ACLK_CTL_REG REG(0x22C0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700150#define PCIE_HCLK_CTL_REG REG(0x22CC)
Tianyi Gou6613de52012-01-27 17:57:53 -0800151#define PCIE_PCLK_CTL_REG REG(0x22D0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700152#define GPLL1_MODE_REG REG(0x3160)
153#define GPLL1_L_VAL_REG REG(0x3164)
154#define GPLL1_M_VAL_REG REG(0x3168)
155#define GPLL1_N_VAL_REG REG(0x316C)
156#define GPLL1_CONFIG_REG REG(0x3174)
157#define GPLL1_STATUS_REG REG(0x3178)
158#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700159
160/* Multimedia clock registers. */
161#define AHB_EN_REG REG_MM(0x0008)
162#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700163#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700164#define AHB_NS_REG REG_MM(0x0004)
165#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700166#define CAMCLK0_NS_REG REG_MM(0x0148)
167#define CAMCLK0_CC_REG REG_MM(0x0140)
168#define CAMCLK0_MD_REG REG_MM(0x0144)
169#define CAMCLK1_NS_REG REG_MM(0x015C)
170#define CAMCLK1_CC_REG REG_MM(0x0154)
171#define CAMCLK1_MD_REG REG_MM(0x0158)
172#define CAMCLK2_NS_REG REG_MM(0x0228)
173#define CAMCLK2_CC_REG REG_MM(0x0220)
174#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700175#define CSI0_NS_REG REG_MM(0x0048)
176#define CSI0_CC_REG REG_MM(0x0040)
177#define CSI0_MD_REG REG_MM(0x0044)
178#define CSI1_NS_REG REG_MM(0x0010)
179#define CSI1_CC_REG REG_MM(0x0024)
180#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700181#define CSI2_NS_REG REG_MM(0x0234)
182#define CSI2_CC_REG REG_MM(0x022C)
183#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700184#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
185#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
186#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
187#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
188#define DSI1_BYTE_CC_REG REG_MM(0x0090)
189#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
190#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
191#define DSI1_ESC_NS_REG REG_MM(0x011C)
192#define DSI1_ESC_CC_REG REG_MM(0x00CC)
193#define DSI2_ESC_NS_REG REG_MM(0x0150)
194#define DSI2_ESC_CC_REG REG_MM(0x013C)
195#define DSI_PIXEL_CC_REG REG_MM(0x0130)
196#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
197#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
198#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
199#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
200#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
201#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
202#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
203#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
204#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
205#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700206#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700207#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
208#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
209#define GFX2D0_CC_REG REG_MM(0x0060)
210#define GFX2D0_MD0_REG REG_MM(0x0064)
211#define GFX2D0_MD1_REG REG_MM(0x0068)
212#define GFX2D0_NS_REG REG_MM(0x0070)
213#define GFX2D1_CC_REG REG_MM(0x0074)
214#define GFX2D1_MD0_REG REG_MM(0x0078)
215#define GFX2D1_MD1_REG REG_MM(0x006C)
216#define GFX2D1_NS_REG REG_MM(0x007C)
217#define GFX3D_CC_REG REG_MM(0x0080)
218#define GFX3D_MD0_REG REG_MM(0x0084)
219#define GFX3D_MD1_REG REG_MM(0x0088)
220#define GFX3D_NS_REG REG_MM(0x008C)
221#define IJPEG_CC_REG REG_MM(0x0098)
222#define IJPEG_MD_REG REG_MM(0x009C)
223#define IJPEG_NS_REG REG_MM(0x00A0)
224#define JPEGD_CC_REG REG_MM(0x00A4)
225#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700226#define VCAP_CC_REG REG_MM(0x0178)
227#define VCAP_NS_REG REG_MM(0x021C)
228#define VCAP_MD0_REG REG_MM(0x01EC)
229#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700230#define MAXI_EN_REG REG_MM(0x0018)
231#define MAXI_EN2_REG REG_MM(0x0020)
232#define MAXI_EN3_REG REG_MM(0x002C)
233#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700234#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700235#define MDP_CC_REG REG_MM(0x00C0)
236#define MDP_LUT_CC_REG REG_MM(0x016C)
237#define MDP_MD0_REG REG_MM(0x00C4)
238#define MDP_MD1_REG REG_MM(0x00C8)
239#define MDP_NS_REG REG_MM(0x00D0)
240#define MISC_CC_REG REG_MM(0x0058)
241#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700242#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700243#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700244#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
245#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
246#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
247#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
248#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
249#define MM_PLL1_STATUS_REG REG_MM(0x0334)
250#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700251#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
252#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
253#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
254#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
255#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
256#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700257#define ROT_CC_REG REG_MM(0x00E0)
258#define ROT_NS_REG REG_MM(0x00E8)
259#define SAXI_EN_REG REG_MM(0x0030)
260#define SW_RESET_AHB_REG REG_MM(0x020C)
261#define SW_RESET_AHB2_REG REG_MM(0x0200)
262#define SW_RESET_ALL_REG REG_MM(0x0204)
263#define SW_RESET_AXI_REG REG_MM(0x0208)
264#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700265#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700266#define TV_CC_REG REG_MM(0x00EC)
267#define TV_CC2_REG REG_MM(0x0124)
268#define TV_MD_REG REG_MM(0x00F0)
269#define TV_NS_REG REG_MM(0x00F4)
270#define VCODEC_CC_REG REG_MM(0x00F8)
271#define VCODEC_MD0_REG REG_MM(0x00FC)
272#define VCODEC_MD1_REG REG_MM(0x0128)
273#define VCODEC_NS_REG REG_MM(0x0100)
274#define VFE_CC_REG REG_MM(0x0104)
275#define VFE_MD_REG REG_MM(0x0108)
276#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700277#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700278#define VPE_CC_REG REG_MM(0x0110)
279#define VPE_NS_REG REG_MM(0x0118)
280
281/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700282#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700283#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
284#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
285#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
286#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
287#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
288#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
289#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
290#define LCC_MI2S_MD_REG REG_LPA(0x004C)
291#define LCC_MI2S_NS_REG REG_LPA(0x0048)
292#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
293#define LCC_PCM_MD_REG REG_LPA(0x0058)
294#define LCC_PCM_NS_REG REG_LPA(0x0054)
295#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700296#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
297#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
298#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
299#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
300#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700301#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700302#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
303#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
304#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
305#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
306#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
307#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
308#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
309#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
310#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
311#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700312#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700313
Matt Wagantall8b38f942011-08-02 18:23:18 -0700314#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
315
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700316/* MUX source input identifiers. */
317#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700318#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700319#define pll0_to_bb_mux 2
320#define pll8_to_bb_mux 3
321#define pll6_to_bb_mux 4
322#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700323#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700324#define pxo_to_mm_mux 0
325#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700326#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
327#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700328#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700329#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700330#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700331#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700332#define hdmi_pll_to_mm_mux 3
333#define cxo_to_xo_mux 0
334#define pxo_to_xo_mux 1
335#define gnd_to_xo_mux 3
336#define pxo_to_lpa_mux 0
337#define cxo_to_lpa_mux 1
338#define pll4_to_lpa_mux 2
339#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700340#define pxo_to_pcie_mux 0
341#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700342
343/* Test Vector Macros */
344#define TEST_TYPE_PER_LS 1
345#define TEST_TYPE_PER_HS 2
346#define TEST_TYPE_MM_LS 3
347#define TEST_TYPE_MM_HS 4
348#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700349#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700350#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700351#define TEST_TYPE_SHIFT 24
352#define TEST_CLK_SEL_MASK BM(23, 0)
353#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
354#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
355#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
356#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
357#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
358#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700359#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700360#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700361
362#define MN_MODE_DUAL_EDGE 0x2
363
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700364struct pll_rate {
365 const uint32_t l_val;
366 const uint32_t m_val;
367 const uint32_t n_val;
368 const uint32_t vco;
369 const uint32_t post_div;
370 const uint32_t i_bits;
371};
372#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
373
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700374enum vdd_dig_levels {
375 VDD_DIG_NONE,
376 VDD_DIG_LOW,
377 VDD_DIG_NOMINAL,
378 VDD_DIG_HIGH
379};
380
Saravana Kannan298ec392012-02-08 19:21:47 -0800381static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700382{
383 static const int vdd_uv[] = {
384 [VDD_DIG_NONE] = 0,
385 [VDD_DIG_LOW] = 945000,
386 [VDD_DIG_NOMINAL] = 1050000,
387 [VDD_DIG_HIGH] = 1150000
388 };
Saravana Kannan298ec392012-02-08 19:21:47 -0800389 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700390 vdd_uv[level], 1150000, 1);
391}
392
Saravana Kannan298ec392012-02-08 19:21:47 -0800393static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960);
394
395static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level)
396{
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800397 static const int vdd_corner[] = {
398 [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE,
399 [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW,
400 [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL,
401 [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH,
Saravana Kannan298ec392012-02-08 19:21:47 -0800402 };
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800403 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_VDD_DIG_CORNER,
404 RPM_VREG_VOTER3,
405 vdd_corner[level],
406 RPM_VREG_CORNER_HIGH, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800407}
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700408
409#define VDD_DIG_FMAX_MAP1(l1, f1) \
410 .vdd_class = &vdd_dig, \
411 .fmax[VDD_DIG_##l1] = (f1)
412#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
413 .vdd_class = &vdd_dig, \
414 .fmax[VDD_DIG_##l1] = (f1), \
415 .fmax[VDD_DIG_##l2] = (f2)
416#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
417 .vdd_class = &vdd_dig, \
418 .fmax[VDD_DIG_##l1] = (f1), \
419 .fmax[VDD_DIG_##l2] = (f2), \
420 .fmax[VDD_DIG_##l3] = (f3)
421
Tianyi Goue1faaf22012-01-24 16:07:19 -0800422enum vdd_sr2_pll_levels {
423 VDD_SR2_PLL_OFF,
424 VDD_SR2_PLL_ON
Matt Wagantallc57577d2011-10-06 17:06:53 -0700425};
426
Saravana Kannan298ec392012-02-08 19:21:47 -0800427static int set_vdd_sr2_pll_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantallc57577d2011-10-06 17:06:53 -0700428{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800429 int rc = 0;
Saravana Kannan298ec392012-02-08 19:21:47 -0800430
431 if (level == VDD_SR2_PLL_OFF) {
432 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
433 RPM_VREG_VOTER3, 0, 0, 1);
434 if (rc)
435 return rc;
436 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
437 RPM_VREG_VOTER3, 0, 0, 1);
438 if (rc)
439 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
440 RPM_VREG_VOTER3, 1800000, 1800000, 1);
Tianyi Goue1faaf22012-01-24 16:07:19 -0800441 } else {
Saravana Kannan298ec392012-02-08 19:21:47 -0800442 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
David Collins9a81d6c2012-03-29 15:11:33 -0700443 RPM_VREG_VOTER3, 2050000, 2100000, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800444 if (rc)
445 return rc;
446 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
447 RPM_VREG_VOTER3, 1800000, 1800000, 1);
448 if (rc)
449 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800450 RPM_VREG_VOTER3, 0, 0, 1);
Matt Wagantallc57577d2011-10-06 17:06:53 -0700451 }
452
453 return rc;
454}
455
Saravana Kannan298ec392012-02-08 19:21:47 -0800456static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll_8960);
457
458static int sr2_lreg_uv[] = {
459 [VDD_SR2_PLL_OFF] = 0,
460 [VDD_SR2_PLL_ON] = 1800000,
461};
462
463static int set_vdd_sr2_pll_8064(struct clk_vdd_class *vdd_class, int level)
464{
465 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3,
466 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
467}
468
469static int set_vdd_sr2_pll_8930(struct clk_vdd_class *vdd_class, int level)
470{
471 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3,
472 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
473}
Matt Wagantallc57577d2011-10-06 17:06:53 -0700474
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700475/*
476 * Clock Descriptions
477 */
478
Stephen Boyd72a80352012-01-26 15:57:38 -0800479DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000);
480DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700481
482static struct pll_clk pll2_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700483 .mode_reg = MM_PLL1_MODE_REG,
484 .parent = &pxo_clk.c,
485 .c = {
486 .dbg_name = "pll2_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800487 .rate = 800000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800488 .ops = &clk_ops_local_pll,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700489 CLK_INIT(pll2_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800490 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700491 },
492};
493
Stephen Boyd94625ef2011-07-12 17:06:01 -0700494static struct pll_clk pll3_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700495 .mode_reg = BB_MMCC_PLL2_MODE_REG,
496 .parent = &pxo_clk.c,
497 .c = {
498 .dbg_name = "pll3_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800499 .rate = 1200000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800500 .ops = &clk_ops_local_pll,
Tianyi Goue1faaf22012-01-24 16:07:19 -0800501 .vdd_class = &vdd_sr2_pll,
502 .fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700503 CLK_INIT(pll3_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800504 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700505 },
506};
507
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700508static struct pll_vote_clk pll4_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700509 .en_reg = BB_PLL_ENA_SC0_REG,
510 .en_mask = BIT(4),
511 .status_reg = LCC_PLL0_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800512 .status_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700513 .parent = &pxo_clk.c,
514 .c = {
515 .dbg_name = "pll4_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800516 .rate = 393216000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700517 .ops = &clk_ops_pll_vote,
518 CLK_INIT(pll4_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800519 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700520 },
521};
522
523static struct pll_vote_clk pll8_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700524 .en_reg = BB_PLL_ENA_SC0_REG,
525 .en_mask = BIT(8),
526 .status_reg = BB_PLL8_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800527 .status_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700528 .parent = &pxo_clk.c,
529 .c = {
530 .dbg_name = "pll8_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800531 .rate = 384000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700532 .ops = &clk_ops_pll_vote,
533 CLK_INIT(pll8_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800534 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700535 },
536};
537
Stephen Boyd94625ef2011-07-12 17:06:01 -0700538static struct pll_vote_clk pll14_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700539 .en_reg = BB_PLL_ENA_SC0_REG,
540 .en_mask = BIT(14),
541 .status_reg = BB_PLL14_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800542 .status_mask = BIT(16),
Stephen Boyd94625ef2011-07-12 17:06:01 -0700543 .parent = &pxo_clk.c,
544 .c = {
545 .dbg_name = "pll14_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800546 .rate = 480000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700547 .ops = &clk_ops_pll_vote,
548 CLK_INIT(pll14_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800549 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700550 },
551};
552
Tianyi Gou41515e22011-09-01 19:37:43 -0700553static struct pll_clk pll15_clk = {
Tianyi Gou41515e22011-09-01 19:37:43 -0700554 .mode_reg = MM_PLL3_MODE_REG,
555 .parent = &pxo_clk.c,
556 .c = {
557 .dbg_name = "pll15_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800558 .rate = 975000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800559 .ops = &clk_ops_local_pll,
Tianyi Gou41515e22011-09-01 19:37:43 -0700560 CLK_INIT(pll15_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800561 .warned = true,
Tianyi Gou41515e22011-09-01 19:37:43 -0700562 },
563};
564
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700565/* AXI Interfaces */
566static struct branch_clk gmem_axi_clk = {
567 .b = {
568 .ctl_reg = MAXI_EN_REG,
569 .en_mask = BIT(24),
570 .halt_reg = DBG_BUS_VEC_E_REG,
571 .halt_bit = 6,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800572 .retain_reg = MAXI_EN2_REG,
573 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700574 },
575 .c = {
576 .dbg_name = "gmem_axi_clk",
577 .ops = &clk_ops_branch,
578 CLK_INIT(gmem_axi_clk.c),
579 },
580};
581
582static struct branch_clk ijpeg_axi_clk = {
583 .b = {
584 .ctl_reg = MAXI_EN_REG,
585 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800586 .hwcg_reg = MAXI_EN_REG,
587 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700588 .reset_reg = SW_RESET_AXI_REG,
589 .reset_mask = BIT(14),
590 .halt_reg = DBG_BUS_VEC_E_REG,
591 .halt_bit = 4,
592 },
593 .c = {
594 .dbg_name = "ijpeg_axi_clk",
595 .ops = &clk_ops_branch,
596 CLK_INIT(ijpeg_axi_clk.c),
597 },
598};
599
600static struct branch_clk imem_axi_clk = {
601 .b = {
602 .ctl_reg = MAXI_EN_REG,
603 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800604 .hwcg_reg = MAXI_EN_REG,
605 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700606 .reset_reg = SW_RESET_CORE_REG,
607 .reset_mask = BIT(10),
608 .halt_reg = DBG_BUS_VEC_E_REG,
609 .halt_bit = 7,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800610 .retain_reg = MAXI_EN2_REG,
611 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700612 },
613 .c = {
614 .dbg_name = "imem_axi_clk",
615 .ops = &clk_ops_branch,
616 CLK_INIT(imem_axi_clk.c),
617 },
618};
619
620static struct branch_clk jpegd_axi_clk = {
621 .b = {
622 .ctl_reg = MAXI_EN_REG,
623 .en_mask = BIT(25),
624 .halt_reg = DBG_BUS_VEC_E_REG,
625 .halt_bit = 5,
626 },
627 .c = {
628 .dbg_name = "jpegd_axi_clk",
629 .ops = &clk_ops_branch,
630 CLK_INIT(jpegd_axi_clk.c),
631 },
632};
633
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700634static struct branch_clk vcodec_axi_b_clk = {
635 .b = {
636 .ctl_reg = MAXI_EN4_REG,
637 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800638 .hwcg_reg = MAXI_EN4_REG,
639 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700640 .halt_reg = DBG_BUS_VEC_I_REG,
641 .halt_bit = 25,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800642 .retain_reg = MAXI_EN4_REG,
643 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700644 },
645 .c = {
646 .dbg_name = "vcodec_axi_b_clk",
647 .ops = &clk_ops_branch,
648 CLK_INIT(vcodec_axi_b_clk.c),
649 },
650};
651
Matt Wagantall91f42702011-07-14 12:01:15 -0700652static struct branch_clk vcodec_axi_a_clk = {
653 .b = {
654 .ctl_reg = MAXI_EN4_REG,
655 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800656 .hwcg_reg = MAXI_EN4_REG,
657 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700658 .halt_reg = DBG_BUS_VEC_I_REG,
659 .halt_bit = 26,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800660 .retain_reg = MAXI_EN4_REG,
661 .retain_mask = BIT(10),
Matt Wagantall91f42702011-07-14 12:01:15 -0700662 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700663 .c = {
664 .dbg_name = "vcodec_axi_a_clk",
665 .ops = &clk_ops_branch,
666 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700667 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700668 },
669};
670
671static struct branch_clk vcodec_axi_clk = {
672 .b = {
673 .ctl_reg = MAXI_EN_REG,
674 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800675 .hwcg_reg = MAXI_EN_REG,
676 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700677 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800678 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700679 .halt_reg = DBG_BUS_VEC_E_REG,
680 .halt_bit = 3,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800681 .retain_reg = MAXI_EN2_REG,
682 .retain_mask = BIT(28),
Matt Wagantall91f42702011-07-14 12:01:15 -0700683 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700684 .c = {
685 .dbg_name = "vcodec_axi_clk",
686 .ops = &clk_ops_branch,
687 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700688 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700689 },
690};
691
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700692static struct branch_clk vfe_axi_clk = {
693 .b = {
694 .ctl_reg = MAXI_EN_REG,
695 .en_mask = BIT(18),
696 .reset_reg = SW_RESET_AXI_REG,
697 .reset_mask = BIT(9),
698 .halt_reg = DBG_BUS_VEC_E_REG,
699 .halt_bit = 0,
700 },
701 .c = {
702 .dbg_name = "vfe_axi_clk",
703 .ops = &clk_ops_branch,
704 CLK_INIT(vfe_axi_clk.c),
705 },
706};
707
708static struct branch_clk mdp_axi_clk = {
709 .b = {
710 .ctl_reg = MAXI_EN_REG,
711 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800712 .hwcg_reg = MAXI_EN_REG,
713 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700714 .reset_reg = SW_RESET_AXI_REG,
715 .reset_mask = BIT(13),
716 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700717 .halt_bit = 8,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800718 .retain_reg = MAXI_EN_REG,
719 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700720 },
721 .c = {
722 .dbg_name = "mdp_axi_clk",
723 .ops = &clk_ops_branch,
724 CLK_INIT(mdp_axi_clk.c),
725 },
726};
727
728static struct branch_clk rot_axi_clk = {
729 .b = {
730 .ctl_reg = MAXI_EN2_REG,
731 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800732 .hwcg_reg = MAXI_EN2_REG,
733 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700734 .reset_reg = SW_RESET_AXI_REG,
735 .reset_mask = BIT(6),
736 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700737 .halt_bit = 2,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800738 .retain_reg = MAXI_EN3_REG,
739 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700740 },
741 .c = {
742 .dbg_name = "rot_axi_clk",
743 .ops = &clk_ops_branch,
744 CLK_INIT(rot_axi_clk.c),
745 },
746};
747
748static struct branch_clk vpe_axi_clk = {
749 .b = {
750 .ctl_reg = MAXI_EN2_REG,
751 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800752 .hwcg_reg = MAXI_EN2_REG,
753 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700754 .reset_reg = SW_RESET_AXI_REG,
755 .reset_mask = BIT(15),
756 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700757 .halt_bit = 1,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800758 .retain_reg = MAXI_EN3_REG,
759 .retain_mask = BIT(21),
760
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700761 },
762 .c = {
763 .dbg_name = "vpe_axi_clk",
764 .ops = &clk_ops_branch,
765 CLK_INIT(vpe_axi_clk.c),
766 },
767};
768
Tianyi Gou41515e22011-09-01 19:37:43 -0700769static struct branch_clk vcap_axi_clk = {
770 .b = {
771 .ctl_reg = MAXI_EN5_REG,
772 .en_mask = BIT(12),
Tianyi Gouf3095ea2012-05-22 14:16:06 -0700773 .hwcg_reg = MAXI_EN5_REG,
774 .hwcg_mask = BIT(11),
Tianyi Gou41515e22011-09-01 19:37:43 -0700775 .reset_reg = SW_RESET_AXI_REG,
776 .reset_mask = BIT(16),
777 .halt_reg = DBG_BUS_VEC_J_REG,
778 .halt_bit = 20,
779 },
780 .c = {
781 .dbg_name = "vcap_axi_clk",
782 .ops = &clk_ops_branch,
783 CLK_INIT(vcap_axi_clk.c),
784 },
785};
786
Tianyi Goue3d4f542012-03-15 17:06:45 -0700787/* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
788static struct branch_clk gfx3d_axi_clk_8064 = {
Tianyi Gou621f8742011-09-01 21:45:01 -0700789 .b = {
790 .ctl_reg = MAXI_EN5_REG,
791 .en_mask = BIT(25),
Tianyi Gouf3095ea2012-05-22 14:16:06 -0700792 .hwcg_reg = MAXI_EN5_REG,
793 .hwcg_mask = BIT(24),
Tianyi Gou621f8742011-09-01 21:45:01 -0700794 .reset_reg = SW_RESET_AXI_REG,
795 .reset_mask = BIT(17),
796 .halt_reg = DBG_BUS_VEC_J_REG,
797 .halt_bit = 30,
798 },
799 .c = {
800 .dbg_name = "gfx3d_axi_clk",
801 .ops = &clk_ops_branch,
Tianyi Goue3d4f542012-03-15 17:06:45 -0700802 CLK_INIT(gfx3d_axi_clk_8064.c),
803 },
804};
805
806static struct branch_clk gfx3d_axi_clk_8930 = {
807 .b = {
808 .ctl_reg = MAXI_EN5_REG,
809 .en_mask = BIT(12),
810 .reset_reg = SW_RESET_AXI_REG,
811 .reset_mask = BIT(16),
812 .halt_reg = DBG_BUS_VEC_J_REG,
813 .halt_bit = 12,
814 },
815 .c = {
816 .dbg_name = "gfx3d_axi_clk",
817 .ops = &clk_ops_branch,
818 CLK_INIT(gfx3d_axi_clk_8930.c),
Tianyi Gou621f8742011-09-01 21:45:01 -0700819 },
820};
821
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822/* AHB Interfaces */
823static struct branch_clk amp_p_clk = {
824 .b = {
825 .ctl_reg = AHB_EN_REG,
826 .en_mask = BIT(24),
Matt Wagantalld40857a2012-04-10 19:15:43 -0700827 .reset_reg = SW_RESET_CORE_REG,
828 .reset_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700829 .halt_reg = DBG_BUS_VEC_F_REG,
830 .halt_bit = 18,
831 },
832 .c = {
833 .dbg_name = "amp_p_clk",
834 .ops = &clk_ops_branch,
835 CLK_INIT(amp_p_clk.c),
836 },
837};
838
Matt Wagantallc23eee92011-08-16 23:06:52 -0700839static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700840 .b = {
841 .ctl_reg = AHB_EN_REG,
842 .en_mask = BIT(7),
843 .reset_reg = SW_RESET_AHB_REG,
844 .reset_mask = BIT(17),
845 .halt_reg = DBG_BUS_VEC_F_REG,
846 .halt_bit = 16,
847 },
848 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700849 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700850 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700851 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700852 },
853};
854
855static struct branch_clk dsi1_m_p_clk = {
856 .b = {
857 .ctl_reg = AHB_EN_REG,
858 .en_mask = BIT(9),
859 .reset_reg = SW_RESET_AHB_REG,
860 .reset_mask = BIT(6),
861 .halt_reg = DBG_BUS_VEC_F_REG,
862 .halt_bit = 19,
863 },
864 .c = {
865 .dbg_name = "dsi1_m_p_clk",
866 .ops = &clk_ops_branch,
867 CLK_INIT(dsi1_m_p_clk.c),
868 },
869};
870
871static struct branch_clk dsi1_s_p_clk = {
872 .b = {
873 .ctl_reg = AHB_EN_REG,
874 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800875 .hwcg_reg = AHB_EN2_REG,
876 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700877 .reset_reg = SW_RESET_AHB_REG,
878 .reset_mask = BIT(5),
879 .halt_reg = DBG_BUS_VEC_F_REG,
880 .halt_bit = 21,
881 },
882 .c = {
883 .dbg_name = "dsi1_s_p_clk",
884 .ops = &clk_ops_branch,
885 CLK_INIT(dsi1_s_p_clk.c),
886 },
887};
888
889static struct branch_clk dsi2_m_p_clk = {
890 .b = {
891 .ctl_reg = AHB_EN_REG,
892 .en_mask = BIT(17),
893 .reset_reg = SW_RESET_AHB2_REG,
894 .reset_mask = BIT(1),
895 .halt_reg = DBG_BUS_VEC_E_REG,
896 .halt_bit = 18,
897 },
898 .c = {
899 .dbg_name = "dsi2_m_p_clk",
900 .ops = &clk_ops_branch,
901 CLK_INIT(dsi2_m_p_clk.c),
902 },
903};
904
905static struct branch_clk dsi2_s_p_clk = {
906 .b = {
907 .ctl_reg = AHB_EN_REG,
908 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800909 .hwcg_reg = AHB_EN2_REG,
910 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700911 .reset_reg = SW_RESET_AHB2_REG,
912 .reset_mask = BIT(0),
913 .halt_reg = DBG_BUS_VEC_F_REG,
914 .halt_bit = 20,
915 },
916 .c = {
917 .dbg_name = "dsi2_s_p_clk",
918 .ops = &clk_ops_branch,
919 CLK_INIT(dsi2_s_p_clk.c),
920 },
921};
922
923static struct branch_clk gfx2d0_p_clk = {
924 .b = {
925 .ctl_reg = AHB_EN_REG,
926 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800927 .hwcg_reg = AHB_EN2_REG,
928 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700929 .reset_reg = SW_RESET_AHB_REG,
930 .reset_mask = BIT(12),
931 .halt_reg = DBG_BUS_VEC_F_REG,
932 .halt_bit = 2,
933 },
934 .c = {
935 .dbg_name = "gfx2d0_p_clk",
936 .ops = &clk_ops_branch,
Matt Wagantall158f73b2012-05-16 11:29:35 -0700937 .flags = CLKFLAG_SKIP_HANDOFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700938 CLK_INIT(gfx2d0_p_clk.c),
939 },
940};
941
942static struct branch_clk gfx2d1_p_clk = {
943 .b = {
944 .ctl_reg = AHB_EN_REG,
945 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800946 .hwcg_reg = AHB_EN2_REG,
947 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700948 .reset_reg = SW_RESET_AHB_REG,
949 .reset_mask = BIT(11),
950 .halt_reg = DBG_BUS_VEC_F_REG,
951 .halt_bit = 3,
952 },
953 .c = {
954 .dbg_name = "gfx2d1_p_clk",
955 .ops = &clk_ops_branch,
Matt Wagantall158f73b2012-05-16 11:29:35 -0700956 .flags = CLKFLAG_SKIP_HANDOFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700957 CLK_INIT(gfx2d1_p_clk.c),
958 },
959};
960
961static struct branch_clk gfx3d_p_clk = {
962 .b = {
963 .ctl_reg = AHB_EN_REG,
964 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800965 .hwcg_reg = AHB_EN2_REG,
966 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700967 .reset_reg = SW_RESET_AHB_REG,
968 .reset_mask = BIT(10),
969 .halt_reg = DBG_BUS_VEC_F_REG,
970 .halt_bit = 4,
971 },
972 .c = {
973 .dbg_name = "gfx3d_p_clk",
974 .ops = &clk_ops_branch,
975 CLK_INIT(gfx3d_p_clk.c),
976 },
977};
978
979static struct branch_clk hdmi_m_p_clk = {
980 .b = {
981 .ctl_reg = AHB_EN_REG,
982 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800983 .hwcg_reg = AHB_EN2_REG,
984 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700985 .reset_reg = SW_RESET_AHB_REG,
986 .reset_mask = BIT(9),
987 .halt_reg = DBG_BUS_VEC_F_REG,
988 .halt_bit = 5,
989 },
990 .c = {
991 .dbg_name = "hdmi_m_p_clk",
992 .ops = &clk_ops_branch,
993 CLK_INIT(hdmi_m_p_clk.c),
994 },
995};
996
997static struct branch_clk hdmi_s_p_clk = {
998 .b = {
999 .ctl_reg = AHB_EN_REG,
1000 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001001 .hwcg_reg = AHB_EN2_REG,
1002 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001003 .reset_reg = SW_RESET_AHB_REG,
1004 .reset_mask = BIT(9),
1005 .halt_reg = DBG_BUS_VEC_F_REG,
1006 .halt_bit = 6,
1007 },
1008 .c = {
1009 .dbg_name = "hdmi_s_p_clk",
1010 .ops = &clk_ops_branch,
1011 CLK_INIT(hdmi_s_p_clk.c),
1012 },
1013};
1014
1015static struct branch_clk ijpeg_p_clk = {
1016 .b = {
1017 .ctl_reg = AHB_EN_REG,
1018 .en_mask = BIT(5),
1019 .reset_reg = SW_RESET_AHB_REG,
1020 .reset_mask = BIT(7),
1021 .halt_reg = DBG_BUS_VEC_F_REG,
1022 .halt_bit = 9,
1023 },
1024 .c = {
1025 .dbg_name = "ijpeg_p_clk",
1026 .ops = &clk_ops_branch,
1027 CLK_INIT(ijpeg_p_clk.c),
1028 },
1029};
1030
1031static struct branch_clk imem_p_clk = {
1032 .b = {
1033 .ctl_reg = AHB_EN_REG,
1034 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001035 .hwcg_reg = AHB_EN2_REG,
1036 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001037 .reset_reg = SW_RESET_AHB_REG,
1038 .reset_mask = BIT(8),
1039 .halt_reg = DBG_BUS_VEC_F_REG,
1040 .halt_bit = 10,
1041 },
1042 .c = {
1043 .dbg_name = "imem_p_clk",
1044 .ops = &clk_ops_branch,
1045 CLK_INIT(imem_p_clk.c),
1046 },
1047};
1048
1049static struct branch_clk jpegd_p_clk = {
1050 .b = {
1051 .ctl_reg = AHB_EN_REG,
1052 .en_mask = BIT(21),
1053 .reset_reg = SW_RESET_AHB_REG,
1054 .reset_mask = BIT(4),
1055 .halt_reg = DBG_BUS_VEC_F_REG,
1056 .halt_bit = 7,
1057 },
1058 .c = {
1059 .dbg_name = "jpegd_p_clk",
1060 .ops = &clk_ops_branch,
1061 CLK_INIT(jpegd_p_clk.c),
1062 },
1063};
1064
1065static struct branch_clk mdp_p_clk = {
1066 .b = {
1067 .ctl_reg = AHB_EN_REG,
1068 .en_mask = BIT(10),
1069 .reset_reg = SW_RESET_AHB_REG,
1070 .reset_mask = BIT(3),
1071 .halt_reg = DBG_BUS_VEC_F_REG,
1072 .halt_bit = 11,
1073 },
1074 .c = {
1075 .dbg_name = "mdp_p_clk",
1076 .ops = &clk_ops_branch,
1077 CLK_INIT(mdp_p_clk.c),
1078 },
1079};
1080
1081static struct branch_clk rot_p_clk = {
1082 .b = {
1083 .ctl_reg = AHB_EN_REG,
1084 .en_mask = BIT(12),
1085 .reset_reg = SW_RESET_AHB_REG,
1086 .reset_mask = BIT(2),
1087 .halt_reg = DBG_BUS_VEC_F_REG,
1088 .halt_bit = 13,
1089 },
1090 .c = {
1091 .dbg_name = "rot_p_clk",
1092 .ops = &clk_ops_branch,
1093 CLK_INIT(rot_p_clk.c),
1094 },
1095};
1096
1097static struct branch_clk smmu_p_clk = {
1098 .b = {
1099 .ctl_reg = AHB_EN_REG,
1100 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001101 .hwcg_reg = AHB_EN_REG,
1102 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001103 .halt_reg = DBG_BUS_VEC_F_REG,
1104 .halt_bit = 22,
1105 },
1106 .c = {
1107 .dbg_name = "smmu_p_clk",
1108 .ops = &clk_ops_branch,
1109 CLK_INIT(smmu_p_clk.c),
1110 },
1111};
1112
1113static struct branch_clk tv_enc_p_clk = {
1114 .b = {
1115 .ctl_reg = AHB_EN_REG,
1116 .en_mask = BIT(25),
1117 .reset_reg = SW_RESET_AHB_REG,
1118 .reset_mask = BIT(15),
1119 .halt_reg = DBG_BUS_VEC_F_REG,
1120 .halt_bit = 23,
1121 },
1122 .c = {
1123 .dbg_name = "tv_enc_p_clk",
1124 .ops = &clk_ops_branch,
1125 CLK_INIT(tv_enc_p_clk.c),
1126 },
1127};
1128
1129static struct branch_clk vcodec_p_clk = {
1130 .b = {
1131 .ctl_reg = AHB_EN_REG,
1132 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001133 .hwcg_reg = AHB_EN2_REG,
1134 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001135 .reset_reg = SW_RESET_AHB_REG,
1136 .reset_mask = BIT(1),
1137 .halt_reg = DBG_BUS_VEC_F_REG,
1138 .halt_bit = 12,
1139 },
1140 .c = {
1141 .dbg_name = "vcodec_p_clk",
1142 .ops = &clk_ops_branch,
1143 CLK_INIT(vcodec_p_clk.c),
1144 },
1145};
1146
1147static struct branch_clk vfe_p_clk = {
1148 .b = {
1149 .ctl_reg = AHB_EN_REG,
1150 .en_mask = BIT(13),
1151 .reset_reg = SW_RESET_AHB_REG,
1152 .reset_mask = BIT(0),
1153 .halt_reg = DBG_BUS_VEC_F_REG,
1154 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08001155 .retain_reg = AHB_EN2_REG,
1156 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001157 },
1158 .c = {
1159 .dbg_name = "vfe_p_clk",
1160 .ops = &clk_ops_branch,
1161 CLK_INIT(vfe_p_clk.c),
1162 },
1163};
1164
1165static struct branch_clk vpe_p_clk = {
1166 .b = {
1167 .ctl_reg = AHB_EN_REG,
1168 .en_mask = BIT(16),
1169 .reset_reg = SW_RESET_AHB_REG,
1170 .reset_mask = BIT(14),
1171 .halt_reg = DBG_BUS_VEC_F_REG,
1172 .halt_bit = 15,
1173 },
1174 .c = {
1175 .dbg_name = "vpe_p_clk",
1176 .ops = &clk_ops_branch,
1177 CLK_INIT(vpe_p_clk.c),
1178 },
1179};
1180
Tianyi Gou41515e22011-09-01 19:37:43 -07001181static struct branch_clk vcap_p_clk = {
1182 .b = {
1183 .ctl_reg = AHB_EN3_REG,
1184 .en_mask = BIT(1),
Tianyi Gouf3095ea2012-05-22 14:16:06 -07001185 .hwcg_reg = AHB_EN3_REG,
1186 .hwcg_mask = BIT(0),
Tianyi Gou41515e22011-09-01 19:37:43 -07001187 .reset_reg = SW_RESET_AHB2_REG,
1188 .reset_mask = BIT(2),
1189 .halt_reg = DBG_BUS_VEC_J_REG,
1190 .halt_bit = 23,
1191 },
1192 .c = {
1193 .dbg_name = "vcap_p_clk",
1194 .ops = &clk_ops_branch,
1195 CLK_INIT(vcap_p_clk.c),
1196 },
1197};
1198
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001199/*
1200 * Peripheral Clocks
1201 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001202#define CLK_GP(i, n, h_r, h_b) \
1203 struct rcg_clk i##_clk = { \
1204 .b = { \
1205 .ctl_reg = GPn_NS_REG(n), \
1206 .en_mask = BIT(9), \
1207 .halt_reg = h_r, \
1208 .halt_bit = h_b, \
1209 }, \
1210 .ns_reg = GPn_NS_REG(n), \
1211 .md_reg = GPn_MD_REG(n), \
1212 .root_en_mask = BIT(11), \
1213 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001214 .mnd_en_mask = BIT(8), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001215 .set_rate = set_rate_mnd, \
1216 .freq_tbl = clk_tbl_gp, \
1217 .current_freq = &rcg_dummy_freq, \
1218 .c = { \
1219 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001220 .ops = &clk_ops_rcg, \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001221 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1222 CLK_INIT(i##_clk.c), \
1223 }, \
1224 }
1225#define F_GP(f, s, d, m, n) \
1226 { \
1227 .freq_hz = f, \
1228 .src_clk = &s##_clk.c, \
1229 .md_val = MD8(16, m, 0, n), \
1230 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001231 }
1232static struct clk_freq_tbl clk_tbl_gp[] = {
1233 F_GP( 0, gnd, 1, 0, 0),
1234 F_GP( 9600000, cxo, 2, 0, 0),
1235 F_GP( 13500000, pxo, 2, 0, 0),
1236 F_GP( 19200000, cxo, 1, 0, 0),
1237 F_GP( 27000000, pxo, 1, 0, 0),
1238 F_GP( 64000000, pll8, 2, 1, 3),
1239 F_GP( 76800000, pll8, 1, 1, 5),
1240 F_GP( 96000000, pll8, 4, 0, 0),
1241 F_GP(128000000, pll8, 3, 0, 0),
1242 F_GP(192000000, pll8, 2, 0, 0),
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001243 F_END
1244};
1245
1246static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1247static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1248static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1249
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001250#define CLK_GSBI_UART(i, n, h_r, h_b) \
1251 struct rcg_clk i##_clk = { \
1252 .b = { \
1253 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1254 .en_mask = BIT(9), \
1255 .reset_reg = GSBIn_RESET_REG(n), \
1256 .reset_mask = BIT(0), \
1257 .halt_reg = h_r, \
1258 .halt_bit = h_b, \
1259 }, \
1260 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1261 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1262 .root_en_mask = BIT(11), \
1263 .ns_mask = (BM(31, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001264 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001265 .set_rate = set_rate_mnd, \
1266 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001267 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001268 .c = { \
1269 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001270 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001271 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001272 CLK_INIT(i##_clk.c), \
1273 }, \
1274 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001275#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001276 { \
1277 .freq_hz = f, \
1278 .src_clk = &s##_clk.c, \
1279 .md_val = MD16(m, n), \
1280 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001281 }
1282static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001283 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001284 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1285 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1286 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1287 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001288 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1289 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1290 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1291 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1292 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1293 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1294 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1295 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1296 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1297 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001298 F_END
1299};
1300
1301static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1302static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1303static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1304static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1305static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1306static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1307static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1308static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1309static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1310static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1311static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1312static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1313
1314#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1315 struct rcg_clk i##_clk = { \
1316 .b = { \
1317 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1318 .en_mask = BIT(9), \
1319 .reset_reg = GSBIn_RESET_REG(n), \
1320 .reset_mask = BIT(0), \
1321 .halt_reg = h_r, \
1322 .halt_bit = h_b, \
1323 }, \
1324 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1325 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1326 .root_en_mask = BIT(11), \
1327 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001328 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001329 .set_rate = set_rate_mnd, \
1330 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001331 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001332 .c = { \
1333 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001334 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001335 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001336 CLK_INIT(i##_clk.c), \
1337 }, \
1338 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001339#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001340 { \
1341 .freq_hz = f, \
1342 .src_clk = &s##_clk.c, \
1343 .md_val = MD8(16, m, 0, n), \
1344 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001345 }
1346static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001347 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1348 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1349 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1350 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1351 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1352 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1353 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1354 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1355 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1356 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001357 F_END
1358};
1359
1360static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1361static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1362static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1363static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1364static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1365static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1366static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1367static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1368static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1369static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1370static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1371static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1372
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001373#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001374 { \
1375 .freq_hz = f, \
1376 .src_clk = &s##_clk.c, \
1377 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001378 }
1379static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001380 F_PDM( 0, gnd, 1),
1381 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001382 F_END
1383};
1384
1385static struct rcg_clk pdm_clk = {
1386 .b = {
1387 .ctl_reg = PDM_CLK_NS_REG,
1388 .en_mask = BIT(9),
1389 .reset_reg = PDM_CLK_NS_REG,
1390 .reset_mask = BIT(12),
1391 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1392 .halt_bit = 3,
1393 },
1394 .ns_reg = PDM_CLK_NS_REG,
1395 .root_en_mask = BIT(11),
1396 .ns_mask = BM(1, 0),
1397 .set_rate = set_rate_nop,
1398 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001399 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001400 .c = {
1401 .dbg_name = "pdm_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001402 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001403 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001404 CLK_INIT(pdm_clk.c),
1405 },
1406};
1407
1408static struct branch_clk pmem_clk = {
1409 .b = {
1410 .ctl_reg = PMEM_ACLK_CTL_REG,
1411 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001412 .hwcg_reg = PMEM_ACLK_CTL_REG,
1413 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001414 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1415 .halt_bit = 20,
1416 },
1417 .c = {
1418 .dbg_name = "pmem_clk",
1419 .ops = &clk_ops_branch,
1420 CLK_INIT(pmem_clk.c),
1421 },
1422};
1423
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001424#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001425 { \
1426 .freq_hz = f, \
1427 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001428 }
Stephen Boyd842a1f62012-04-26 19:07:38 -07001429static struct clk_freq_tbl clk_tbl_prng_32[] = {
1430 F_PRNG(32000000, pll8),
1431 F_END
1432};
1433
1434static struct clk_freq_tbl clk_tbl_prng_64[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001435 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001436 F_END
1437};
1438
1439static struct rcg_clk prng_clk = {
1440 .b = {
1441 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1442 .en_mask = BIT(10),
1443 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1444 .halt_check = HALT_VOTED,
1445 .halt_bit = 10,
1446 },
1447 .set_rate = set_rate_nop,
Stephen Boyd842a1f62012-04-26 19:07:38 -07001448 .freq_tbl = clk_tbl_prng_32,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001449 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001450 .c = {
1451 .dbg_name = "prng_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001452 .ops = &clk_ops_rcg,
Stephen Boyd842a1f62012-04-26 19:07:38 -07001453 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001454 CLK_INIT(prng_clk.c),
1455 },
1456};
1457
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001458#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001459 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001460 .b = { \
1461 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1462 .en_mask = BIT(9), \
1463 .reset_reg = SDCn_RESET_REG(n), \
1464 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001465 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001466 .halt_bit = h_b, \
1467 }, \
1468 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1469 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1470 .root_en_mask = BIT(11), \
1471 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001472 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001473 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001474 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001475 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001476 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001477 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001478 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001479 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001480 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001481 }, \
1482 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001483#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001484 { \
1485 .freq_hz = f, \
1486 .src_clk = &s##_clk.c, \
1487 .md_val = MD8(16, m, 0, n), \
1488 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001489 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001490static struct clk_freq_tbl clk_tbl_sdc[] = {
1491 F_SDC( 0, gnd, 1, 0, 0),
1492 F_SDC( 144000, pxo, 3, 2, 125),
1493 F_SDC( 400000, pll8, 4, 1, 240),
1494 F_SDC( 16000000, pll8, 4, 1, 6),
1495 F_SDC( 17070000, pll8, 1, 2, 45),
1496 F_SDC( 20210000, pll8, 1, 1, 19),
1497 F_SDC( 24000000, pll8, 4, 1, 4),
1498 F_SDC( 48000000, pll8, 4, 1, 2),
1499 F_SDC( 64000000, pll8, 3, 1, 2),
1500 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301501 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001502 F_END
1503};
1504
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001505static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1506static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1507static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1508static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1509static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001510
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001511#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001512 { \
1513 .freq_hz = f, \
1514 .src_clk = &s##_clk.c, \
1515 .md_val = MD16(m, n), \
1516 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001517 }
1518static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001519 F_TSIF_REF( 0, gnd, 1, 0, 0),
1520 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001521 F_END
1522};
1523
1524static struct rcg_clk tsif_ref_clk = {
1525 .b = {
1526 .ctl_reg = TSIF_REF_CLK_NS_REG,
1527 .en_mask = BIT(9),
1528 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1529 .halt_bit = 5,
1530 },
1531 .ns_reg = TSIF_REF_CLK_NS_REG,
1532 .md_reg = TSIF_REF_CLK_MD_REG,
1533 .root_en_mask = BIT(11),
1534 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001535 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001536 .set_rate = set_rate_mnd,
1537 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001538 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001539 .c = {
1540 .dbg_name = "tsif_ref_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001541 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001542 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001543 CLK_INIT(tsif_ref_clk.c),
1544 },
1545};
1546
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001547#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001548 { \
1549 .freq_hz = f, \
1550 .src_clk = &s##_clk.c, \
1551 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001552 }
1553static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001554 F_TSSC( 0, gnd),
1555 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001556 F_END
1557};
1558
1559static struct rcg_clk tssc_clk = {
1560 .b = {
1561 .ctl_reg = TSSC_CLK_CTL_REG,
1562 .en_mask = BIT(4),
1563 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1564 .halt_bit = 4,
1565 },
1566 .ns_reg = TSSC_CLK_CTL_REG,
1567 .ns_mask = BM(1, 0),
1568 .set_rate = set_rate_nop,
1569 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001570 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001571 .c = {
1572 .dbg_name = "tssc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001573 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001574 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001575 CLK_INIT(tssc_clk.c),
1576 },
1577};
1578
Tianyi Gou41515e22011-09-01 19:37:43 -07001579#define CLK_USB_HS(name, n, h_b) \
1580 static struct rcg_clk name = { \
1581 .b = { \
1582 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1583 .en_mask = BIT(9), \
1584 .reset_reg = USB_HS##n##_RESET_REG, \
1585 .reset_mask = BIT(0), \
1586 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1587 .halt_bit = h_b, \
1588 }, \
1589 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1590 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1591 .root_en_mask = BIT(11), \
1592 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001593 .mnd_en_mask = BIT(8), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001594 .set_rate = set_rate_mnd, \
1595 .freq_tbl = clk_tbl_usb, \
1596 .current_freq = &rcg_dummy_freq, \
1597 .c = { \
1598 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001599 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001600 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001601 CLK_INIT(name.c), \
1602 }, \
1603}
1604
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001605#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001606 { \
1607 .freq_hz = f, \
1608 .src_clk = &s##_clk.c, \
1609 .md_val = MD8(16, m, 0, n), \
1610 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001611 }
1612static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001613 F_USB( 0, gnd, 1, 0, 0),
1614 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001615 F_END
1616};
1617
Tianyi Gou41515e22011-09-01 19:37:43 -07001618CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1619CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1620CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001621
Stephen Boyd94625ef2011-07-12 17:06:01 -07001622static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001623 F_USB( 0, gnd, 1, 0, 0),
1624 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001625 F_END
1626};
1627
1628static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1629 .b = {
1630 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1631 .en_mask = BIT(9),
1632 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1633 .halt_bit = 26,
1634 },
1635 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1636 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1637 .root_en_mask = BIT(11),
1638 .ns_mask = (BM(23, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001639 .mnd_en_mask = BIT(8),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001640 .set_rate = set_rate_mnd,
1641 .freq_tbl = clk_tbl_usb_hsic,
1642 .current_freq = &rcg_dummy_freq,
1643 .c = {
1644 .dbg_name = "usb_hsic_xcvr_fs_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001645 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001646 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001647 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1648 },
1649};
1650
1651static struct branch_clk usb_hsic_system_clk = {
1652 .b = {
1653 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1654 .en_mask = BIT(4),
1655 .reset_reg = USB_HSIC_RESET_REG,
1656 .reset_mask = BIT(0),
1657 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1658 .halt_bit = 24,
1659 },
1660 .parent = &usb_hsic_xcvr_fs_clk.c,
1661 .c = {
1662 .dbg_name = "usb_hsic_system_clk",
1663 .ops = &clk_ops_branch,
1664 CLK_INIT(usb_hsic_system_clk.c),
1665 },
1666};
1667
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001668#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001669 { \
1670 .freq_hz = f, \
1671 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001672 }
1673static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001674 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001675 F_END
1676};
1677
1678static struct rcg_clk usb_hsic_hsic_src_clk = {
1679 .b = {
1680 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1681 .halt_check = NOCHECK,
1682 },
1683 .root_en_mask = BIT(0),
1684 .set_rate = set_rate_nop,
1685 .freq_tbl = clk_tbl_usb2_hsic,
1686 .current_freq = &rcg_dummy_freq,
1687 .c = {
1688 .dbg_name = "usb_hsic_hsic_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001689 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001690 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001691 CLK_INIT(usb_hsic_hsic_src_clk.c),
1692 },
1693};
1694
1695static struct branch_clk usb_hsic_hsic_clk = {
1696 .b = {
1697 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1698 .en_mask = BIT(0),
1699 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1700 .halt_bit = 19,
1701 },
1702 .parent = &usb_hsic_hsic_src_clk.c,
1703 .c = {
1704 .dbg_name = "usb_hsic_hsic_clk",
1705 .ops = &clk_ops_branch,
1706 CLK_INIT(usb_hsic_hsic_clk.c),
1707 },
1708};
1709
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001710#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001711 { \
1712 .freq_hz = f, \
1713 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001714 }
1715static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001716 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001717 F_END
1718};
1719
1720static struct rcg_clk usb_hsic_hsio_cal_clk = {
1721 .b = {
1722 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1723 .en_mask = BIT(0),
1724 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1725 .halt_bit = 23,
1726 },
1727 .set_rate = set_rate_nop,
1728 .freq_tbl = clk_tbl_usb_hsio_cal,
1729 .current_freq = &rcg_dummy_freq,
1730 .c = {
1731 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001732 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001733 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001734 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1735 },
1736};
1737
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001738static struct branch_clk usb_phy0_clk = {
1739 .b = {
1740 .reset_reg = USB_PHY0_RESET_REG,
1741 .reset_mask = BIT(0),
1742 },
1743 .c = {
1744 .dbg_name = "usb_phy0_clk",
1745 .ops = &clk_ops_reset,
1746 CLK_INIT(usb_phy0_clk.c),
1747 },
1748};
1749
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001750#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001751 struct rcg_clk i##_clk = { \
1752 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1753 .b = { \
1754 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1755 .halt_check = NOCHECK, \
1756 }, \
1757 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1758 .root_en_mask = BIT(11), \
1759 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001760 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001761 .set_rate = set_rate_mnd, \
1762 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001763 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001764 .c = { \
1765 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001766 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001767 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001768 CLK_INIT(i##_clk.c), \
1769 }, \
1770 }
1771
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001772static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001773static struct branch_clk usb_fs1_xcvr_clk = {
1774 .b = {
1775 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1776 .en_mask = BIT(9),
1777 .reset_reg = USB_FSn_RESET_REG(1),
1778 .reset_mask = BIT(1),
1779 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1780 .halt_bit = 15,
1781 },
1782 .parent = &usb_fs1_src_clk.c,
1783 .c = {
1784 .dbg_name = "usb_fs1_xcvr_clk",
1785 .ops = &clk_ops_branch,
1786 CLK_INIT(usb_fs1_xcvr_clk.c),
1787 },
1788};
1789
1790static struct branch_clk usb_fs1_sys_clk = {
1791 .b = {
1792 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1793 .en_mask = BIT(4),
1794 .reset_reg = USB_FSn_RESET_REG(1),
1795 .reset_mask = BIT(0),
1796 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1797 .halt_bit = 16,
1798 },
1799 .parent = &usb_fs1_src_clk.c,
1800 .c = {
1801 .dbg_name = "usb_fs1_sys_clk",
1802 .ops = &clk_ops_branch,
1803 CLK_INIT(usb_fs1_sys_clk.c),
1804 },
1805};
1806
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001807static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001808static struct branch_clk usb_fs2_xcvr_clk = {
1809 .b = {
1810 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1811 .en_mask = BIT(9),
1812 .reset_reg = USB_FSn_RESET_REG(2),
1813 .reset_mask = BIT(1),
1814 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1815 .halt_bit = 12,
1816 },
1817 .parent = &usb_fs2_src_clk.c,
1818 .c = {
1819 .dbg_name = "usb_fs2_xcvr_clk",
1820 .ops = &clk_ops_branch,
1821 CLK_INIT(usb_fs2_xcvr_clk.c),
1822 },
1823};
1824
1825static struct branch_clk usb_fs2_sys_clk = {
1826 .b = {
1827 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1828 .en_mask = BIT(4),
1829 .reset_reg = USB_FSn_RESET_REG(2),
1830 .reset_mask = BIT(0),
1831 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1832 .halt_bit = 13,
1833 },
1834 .parent = &usb_fs2_src_clk.c,
1835 .c = {
1836 .dbg_name = "usb_fs2_sys_clk",
1837 .ops = &clk_ops_branch,
1838 CLK_INIT(usb_fs2_sys_clk.c),
1839 },
1840};
1841
1842/* Fast Peripheral Bus Clocks */
1843static struct branch_clk ce1_core_clk = {
1844 .b = {
1845 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1846 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001847 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1848 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001849 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1850 .halt_bit = 27,
1851 },
1852 .c = {
1853 .dbg_name = "ce1_core_clk",
1854 .ops = &clk_ops_branch,
1855 CLK_INIT(ce1_core_clk.c),
1856 },
1857};
Tianyi Gou41515e22011-09-01 19:37:43 -07001858
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001859static struct branch_clk ce1_p_clk = {
1860 .b = {
1861 .ctl_reg = CE1_HCLK_CTL_REG,
1862 .en_mask = BIT(4),
1863 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1864 .halt_bit = 1,
1865 },
1866 .c = {
1867 .dbg_name = "ce1_p_clk",
1868 .ops = &clk_ops_branch,
1869 CLK_INIT(ce1_p_clk.c),
1870 },
1871};
1872
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001873#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001874 { \
1875 .freq_hz = f, \
1876 .src_clk = &s##_clk.c, \
1877 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001878 }
1879
1880static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001881 F_CE3( 0, gnd, 1),
1882 F_CE3( 48000000, pll8, 8),
1883 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001884 F_END
1885};
1886
1887static struct rcg_clk ce3_src_clk = {
1888 .b = {
1889 .ctl_reg = CE3_CLK_SRC_NS_REG,
1890 .halt_check = NOCHECK,
1891 },
1892 .ns_reg = CE3_CLK_SRC_NS_REG,
1893 .root_en_mask = BIT(7),
1894 .ns_mask = BM(6, 0),
1895 .set_rate = set_rate_nop,
1896 .freq_tbl = clk_tbl_ce3,
1897 .current_freq = &rcg_dummy_freq,
1898 .c = {
1899 .dbg_name = "ce3_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001900 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001901 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001902 CLK_INIT(ce3_src_clk.c),
1903 },
1904};
1905
1906static struct branch_clk ce3_core_clk = {
1907 .b = {
1908 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1909 .en_mask = BIT(4),
1910 .reset_reg = CE3_CORE_CLK_CTL_REG,
1911 .reset_mask = BIT(7),
1912 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1913 .halt_bit = 5,
1914 },
1915 .parent = &ce3_src_clk.c,
1916 .c = {
1917 .dbg_name = "ce3_core_clk",
1918 .ops = &clk_ops_branch,
1919 CLK_INIT(ce3_core_clk.c),
1920 }
1921};
1922
1923static struct branch_clk ce3_p_clk = {
1924 .b = {
1925 .ctl_reg = CE3_HCLK_CTL_REG,
1926 .en_mask = BIT(4),
1927 .reset_reg = CE3_HCLK_CTL_REG,
1928 .reset_mask = BIT(7),
1929 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1930 .halt_bit = 16,
1931 },
1932 .parent = &ce3_src_clk.c,
1933 .c = {
1934 .dbg_name = "ce3_p_clk",
1935 .ops = &clk_ops_branch,
1936 CLK_INIT(ce3_p_clk.c),
1937 }
1938};
1939
Tianyi Gou352955d2012-05-18 19:44:01 -07001940#define F_SATA(f, s, d) \
1941 { \
1942 .freq_hz = f, \
1943 .src_clk = &s##_clk.c, \
1944 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
1945 }
1946
1947static struct clk_freq_tbl clk_tbl_sata[] = {
1948 F_SATA( 0, gnd, 1),
1949 F_SATA( 48000000, pll8, 8),
1950 F_SATA(100000000, pll3, 12),
1951 F_END
1952};
1953
1954static struct rcg_clk sata_src_clk = {
1955 .b = {
1956 .ctl_reg = SATA_CLK_SRC_NS_REG,
1957 .halt_check = NOCHECK,
1958 },
1959 .ns_reg = SATA_CLK_SRC_NS_REG,
1960 .root_en_mask = BIT(7),
1961 .ns_mask = BM(6, 0),
1962 .set_rate = set_rate_nop,
1963 .freq_tbl = clk_tbl_sata,
1964 .current_freq = &rcg_dummy_freq,
1965 .c = {
1966 .dbg_name = "sata_src_clk",
1967 .ops = &clk_ops_rcg,
1968 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
1969 CLK_INIT(sata_src_clk.c),
1970 },
1971};
1972
1973static struct branch_clk sata_rxoob_clk = {
1974 .b = {
1975 .ctl_reg = SATA_RXOOB_CLK_CTL_REG,
1976 .en_mask = BIT(4),
1977 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1978 .halt_bit = 26,
1979 },
1980 .parent = &sata_src_clk.c,
1981 .c = {
1982 .dbg_name = "sata_rxoob_clk",
1983 .ops = &clk_ops_branch,
1984 CLK_INIT(sata_rxoob_clk.c),
1985 },
1986};
1987
1988static struct branch_clk sata_pmalive_clk = {
1989 .b = {
1990 .ctl_reg = SATA_PMALIVE_CLK_CTL_REG,
1991 .en_mask = BIT(4),
1992 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1993 .halt_bit = 25,
1994 },
1995 .parent = &sata_src_clk.c,
1996 .c = {
1997 .dbg_name = "sata_pmalive_clk",
1998 .ops = &clk_ops_branch,
1999 CLK_INIT(sata_pmalive_clk.c),
2000 },
2001};
2002
Tianyi Gou41515e22011-09-01 19:37:43 -07002003static struct branch_clk sata_phy_ref_clk = {
2004 .b = {
2005 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
2006 .en_mask = BIT(4),
2007 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2008 .halt_bit = 24,
2009 },
2010 .parent = &pxo_clk.c,
2011 .c = {
2012 .dbg_name = "sata_phy_ref_clk",
2013 .ops = &clk_ops_branch,
2014 CLK_INIT(sata_phy_ref_clk.c),
2015 },
2016};
2017
Tianyi Gou352955d2012-05-18 19:44:01 -07002018static struct branch_clk sata_a_clk = {
2019 .b = {
2020 .ctl_reg = SATA_ACLK_CTL_REG,
2021 .en_mask = BIT(4),
2022 .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG,
2023 .halt_bit = 12,
2024 },
2025 .c = {
2026 .dbg_name = "sata_a_clk",
2027 .ops = &clk_ops_branch,
2028 CLK_INIT(sata_a_clk.c),
2029 },
2030};
2031
2032static struct branch_clk sata_p_clk = {
2033 .b = {
2034 .ctl_reg = SATA_HCLK_CTL_REG,
2035 .en_mask = BIT(4),
2036 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2037 .halt_bit = 27,
2038 },
2039 .c = {
2040 .dbg_name = "sata_p_clk",
2041 .ops = &clk_ops_branch,
2042 CLK_INIT(sata_p_clk.c),
2043 },
2044};
2045
2046static struct branch_clk sfab_sata_s_p_clk = {
2047 .b = {
2048 .ctl_reg = SFAB_SATA_S_HCLK_CTL_REG,
2049 .en_mask = BIT(4),
2050 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
2051 .halt_bit = 14,
2052 },
2053 .c = {
2054 .dbg_name = "sfab_sata_s_p_clk",
2055 .ops = &clk_ops_branch,
2056 CLK_INIT(sfab_sata_s_p_clk.c),
2057 },
2058};
Tianyi Gou41515e22011-09-01 19:37:43 -07002059static struct branch_clk pcie_p_clk = {
2060 .b = {
2061 .ctl_reg = PCIE_HCLK_CTL_REG,
2062 .en_mask = BIT(4),
2063 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2064 .halt_bit = 8,
2065 },
2066 .c = {
2067 .dbg_name = "pcie_p_clk",
2068 .ops = &clk_ops_branch,
2069 CLK_INIT(pcie_p_clk.c),
2070 },
2071};
2072
Tianyi Gou6613de52012-01-27 17:57:53 -08002073static struct branch_clk pcie_phy_ref_clk = {
2074 .b = {
2075 .ctl_reg = PCIE_PCLK_CTL_REG,
2076 .en_mask = BIT(4),
2077 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2078 .halt_bit = 29,
2079 },
2080 .c = {
2081 .dbg_name = "pcie_phy_ref_clk",
2082 .ops = &clk_ops_branch,
2083 CLK_INIT(pcie_phy_ref_clk.c),
2084 },
2085};
2086
2087static struct branch_clk pcie_a_clk = {
2088 .b = {
2089 .ctl_reg = PCIE_ACLK_CTL_REG,
2090 .en_mask = BIT(4),
2091 .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG,
2092 .halt_bit = 13,
2093 },
2094 .c = {
2095 .dbg_name = "pcie_a_clk",
2096 .ops = &clk_ops_branch,
2097 CLK_INIT(pcie_a_clk.c),
2098 },
2099};
2100
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002101static struct branch_clk dma_bam_p_clk = {
2102 .b = {
2103 .ctl_reg = DMA_BAM_HCLK_CTL,
2104 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002105 .hwcg_reg = DMA_BAM_HCLK_CTL,
2106 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002107 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2108 .halt_bit = 12,
2109 },
2110 .c = {
2111 .dbg_name = "dma_bam_p_clk",
2112 .ops = &clk_ops_branch,
2113 CLK_INIT(dma_bam_p_clk.c),
2114 },
2115};
2116
2117static struct branch_clk gsbi1_p_clk = {
2118 .b = {
2119 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2120 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002121 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
2122 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002123 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2124 .halt_bit = 11,
2125 },
2126 .c = {
2127 .dbg_name = "gsbi1_p_clk",
2128 .ops = &clk_ops_branch,
2129 CLK_INIT(gsbi1_p_clk.c),
2130 },
2131};
2132
2133static struct branch_clk gsbi2_p_clk = {
2134 .b = {
2135 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2136 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002137 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2138 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002139 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2140 .halt_bit = 7,
2141 },
2142 .c = {
2143 .dbg_name = "gsbi2_p_clk",
2144 .ops = &clk_ops_branch,
2145 CLK_INIT(gsbi2_p_clk.c),
2146 },
2147};
2148
2149static struct branch_clk gsbi3_p_clk = {
2150 .b = {
2151 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2152 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002153 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2154 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002155 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2156 .halt_bit = 3,
2157 },
2158 .c = {
2159 .dbg_name = "gsbi3_p_clk",
2160 .ops = &clk_ops_branch,
2161 CLK_INIT(gsbi3_p_clk.c),
2162 },
2163};
2164
2165static struct branch_clk gsbi4_p_clk = {
2166 .b = {
2167 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2168 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002169 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2170 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002171 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2172 .halt_bit = 27,
2173 },
2174 .c = {
2175 .dbg_name = "gsbi4_p_clk",
2176 .ops = &clk_ops_branch,
2177 CLK_INIT(gsbi4_p_clk.c),
2178 },
2179};
2180
2181static struct branch_clk gsbi5_p_clk = {
2182 .b = {
2183 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2184 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002185 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2186 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002187 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2188 .halt_bit = 23,
2189 },
2190 .c = {
2191 .dbg_name = "gsbi5_p_clk",
2192 .ops = &clk_ops_branch,
2193 CLK_INIT(gsbi5_p_clk.c),
2194 },
2195};
2196
2197static struct branch_clk gsbi6_p_clk = {
2198 .b = {
2199 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2200 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002201 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2202 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002203 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2204 .halt_bit = 19,
2205 },
2206 .c = {
2207 .dbg_name = "gsbi6_p_clk",
2208 .ops = &clk_ops_branch,
2209 CLK_INIT(gsbi6_p_clk.c),
2210 },
2211};
2212
2213static struct branch_clk gsbi7_p_clk = {
2214 .b = {
2215 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2216 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002217 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2218 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002219 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2220 .halt_bit = 15,
2221 },
2222 .c = {
2223 .dbg_name = "gsbi7_p_clk",
2224 .ops = &clk_ops_branch,
2225 CLK_INIT(gsbi7_p_clk.c),
2226 },
2227};
2228
2229static struct branch_clk gsbi8_p_clk = {
2230 .b = {
2231 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2232 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002233 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2234 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002235 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2236 .halt_bit = 11,
2237 },
2238 .c = {
2239 .dbg_name = "gsbi8_p_clk",
2240 .ops = &clk_ops_branch,
2241 CLK_INIT(gsbi8_p_clk.c),
2242 },
2243};
2244
2245static struct branch_clk gsbi9_p_clk = {
2246 .b = {
2247 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2248 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002249 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2250 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002251 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2252 .halt_bit = 7,
2253 },
2254 .c = {
2255 .dbg_name = "gsbi9_p_clk",
2256 .ops = &clk_ops_branch,
2257 CLK_INIT(gsbi9_p_clk.c),
2258 },
2259};
2260
2261static struct branch_clk gsbi10_p_clk = {
2262 .b = {
2263 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2264 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002265 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2266 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002267 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2268 .halt_bit = 3,
2269 },
2270 .c = {
2271 .dbg_name = "gsbi10_p_clk",
2272 .ops = &clk_ops_branch,
2273 CLK_INIT(gsbi10_p_clk.c),
2274 },
2275};
2276
2277static struct branch_clk gsbi11_p_clk = {
2278 .b = {
2279 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2280 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002281 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2282 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002283 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2284 .halt_bit = 18,
2285 },
2286 .c = {
2287 .dbg_name = "gsbi11_p_clk",
2288 .ops = &clk_ops_branch,
2289 CLK_INIT(gsbi11_p_clk.c),
2290 },
2291};
2292
2293static struct branch_clk gsbi12_p_clk = {
2294 .b = {
2295 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2296 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002297 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2298 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002299 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2300 .halt_bit = 14,
2301 },
2302 .c = {
2303 .dbg_name = "gsbi12_p_clk",
2304 .ops = &clk_ops_branch,
2305 CLK_INIT(gsbi12_p_clk.c),
2306 },
2307};
2308
Tianyi Gou41515e22011-09-01 19:37:43 -07002309static struct branch_clk sata_phy_cfg_clk = {
2310 .b = {
2311 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2312 .en_mask = BIT(4),
2313 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2314 .halt_bit = 12,
2315 },
2316 .c = {
2317 .dbg_name = "sata_phy_cfg_clk",
2318 .ops = &clk_ops_branch,
2319 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002320 },
2321};
2322
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002323static struct branch_clk tsif_p_clk = {
2324 .b = {
2325 .ctl_reg = TSIF_HCLK_CTL_REG,
2326 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002327 .hwcg_reg = TSIF_HCLK_CTL_REG,
2328 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002329 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2330 .halt_bit = 7,
2331 },
2332 .c = {
2333 .dbg_name = "tsif_p_clk",
2334 .ops = &clk_ops_branch,
2335 CLK_INIT(tsif_p_clk.c),
2336 },
2337};
2338
2339static struct branch_clk usb_fs1_p_clk = {
2340 .b = {
2341 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2342 .en_mask = BIT(4),
2343 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2344 .halt_bit = 17,
2345 },
2346 .c = {
2347 .dbg_name = "usb_fs1_p_clk",
2348 .ops = &clk_ops_branch,
2349 CLK_INIT(usb_fs1_p_clk.c),
2350 },
2351};
2352
2353static struct branch_clk usb_fs2_p_clk = {
2354 .b = {
2355 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2356 .en_mask = BIT(4),
2357 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2358 .halt_bit = 14,
2359 },
2360 .c = {
2361 .dbg_name = "usb_fs2_p_clk",
2362 .ops = &clk_ops_branch,
2363 CLK_INIT(usb_fs2_p_clk.c),
2364 },
2365};
2366
2367static struct branch_clk usb_hs1_p_clk = {
2368 .b = {
2369 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2370 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002371 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2372 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002373 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2374 .halt_bit = 1,
2375 },
2376 .c = {
2377 .dbg_name = "usb_hs1_p_clk",
2378 .ops = &clk_ops_branch,
2379 CLK_INIT(usb_hs1_p_clk.c),
2380 },
2381};
2382
Tianyi Gou41515e22011-09-01 19:37:43 -07002383static struct branch_clk usb_hs3_p_clk = {
2384 .b = {
2385 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2386 .en_mask = BIT(4),
2387 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2388 .halt_bit = 31,
2389 },
2390 .c = {
2391 .dbg_name = "usb_hs3_p_clk",
2392 .ops = &clk_ops_branch,
2393 CLK_INIT(usb_hs3_p_clk.c),
2394 },
2395};
2396
2397static struct branch_clk usb_hs4_p_clk = {
2398 .b = {
2399 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2400 .en_mask = BIT(4),
2401 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2402 .halt_bit = 7,
2403 },
2404 .c = {
2405 .dbg_name = "usb_hs4_p_clk",
2406 .ops = &clk_ops_branch,
2407 CLK_INIT(usb_hs4_p_clk.c),
2408 },
2409};
2410
Stephen Boyd94625ef2011-07-12 17:06:01 -07002411static struct branch_clk usb_hsic_p_clk = {
2412 .b = {
2413 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2414 .en_mask = BIT(4),
2415 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2416 .halt_bit = 28,
2417 },
2418 .c = {
2419 .dbg_name = "usb_hsic_p_clk",
2420 .ops = &clk_ops_branch,
2421 CLK_INIT(usb_hsic_p_clk.c),
2422 },
2423};
2424
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002425static struct branch_clk sdc1_p_clk = {
2426 .b = {
2427 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2428 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002429 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2430 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002431 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2432 .halt_bit = 11,
2433 },
2434 .c = {
2435 .dbg_name = "sdc1_p_clk",
2436 .ops = &clk_ops_branch,
2437 CLK_INIT(sdc1_p_clk.c),
2438 },
2439};
2440
2441static struct branch_clk sdc2_p_clk = {
2442 .b = {
2443 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2444 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002445 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2446 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002447 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2448 .halt_bit = 10,
2449 },
2450 .c = {
2451 .dbg_name = "sdc2_p_clk",
2452 .ops = &clk_ops_branch,
2453 CLK_INIT(sdc2_p_clk.c),
2454 },
2455};
2456
2457static struct branch_clk sdc3_p_clk = {
2458 .b = {
2459 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2460 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002461 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2462 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002463 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2464 .halt_bit = 9,
2465 },
2466 .c = {
2467 .dbg_name = "sdc3_p_clk",
2468 .ops = &clk_ops_branch,
2469 CLK_INIT(sdc3_p_clk.c),
2470 },
2471};
2472
2473static struct branch_clk sdc4_p_clk = {
2474 .b = {
2475 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2476 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002477 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2478 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002479 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2480 .halt_bit = 8,
2481 },
2482 .c = {
2483 .dbg_name = "sdc4_p_clk",
2484 .ops = &clk_ops_branch,
2485 CLK_INIT(sdc4_p_clk.c),
2486 },
2487};
2488
2489static struct branch_clk sdc5_p_clk = {
2490 .b = {
2491 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2492 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002493 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2494 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002495 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2496 .halt_bit = 7,
2497 },
2498 .c = {
2499 .dbg_name = "sdc5_p_clk",
2500 .ops = &clk_ops_branch,
2501 CLK_INIT(sdc5_p_clk.c),
2502 },
2503};
2504
2505/* HW-Voteable Clocks */
2506static struct branch_clk adm0_clk = {
2507 .b = {
2508 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2509 .en_mask = BIT(2),
2510 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2511 .halt_check = HALT_VOTED,
2512 .halt_bit = 14,
2513 },
2514 .c = {
2515 .dbg_name = "adm0_clk",
2516 .ops = &clk_ops_branch,
2517 CLK_INIT(adm0_clk.c),
2518 },
2519};
2520
2521static struct branch_clk adm0_p_clk = {
2522 .b = {
2523 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2524 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002525 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2526 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002527 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2528 .halt_check = HALT_VOTED,
2529 .halt_bit = 13,
2530 },
2531 .c = {
2532 .dbg_name = "adm0_p_clk",
2533 .ops = &clk_ops_branch,
2534 CLK_INIT(adm0_p_clk.c),
2535 },
2536};
2537
2538static struct branch_clk pmic_arb0_p_clk = {
2539 .b = {
2540 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2541 .en_mask = BIT(8),
2542 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2543 .halt_check = HALT_VOTED,
2544 .halt_bit = 22,
2545 },
2546 .c = {
2547 .dbg_name = "pmic_arb0_p_clk",
2548 .ops = &clk_ops_branch,
2549 CLK_INIT(pmic_arb0_p_clk.c),
2550 },
2551};
2552
2553static struct branch_clk pmic_arb1_p_clk = {
2554 .b = {
2555 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2556 .en_mask = BIT(9),
2557 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2558 .halt_check = HALT_VOTED,
2559 .halt_bit = 21,
2560 },
2561 .c = {
2562 .dbg_name = "pmic_arb1_p_clk",
2563 .ops = &clk_ops_branch,
2564 CLK_INIT(pmic_arb1_p_clk.c),
2565 },
2566};
2567
2568static struct branch_clk pmic_ssbi2_clk = {
2569 .b = {
2570 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2571 .en_mask = BIT(7),
2572 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2573 .halt_check = HALT_VOTED,
2574 .halt_bit = 23,
2575 },
2576 .c = {
2577 .dbg_name = "pmic_ssbi2_clk",
2578 .ops = &clk_ops_branch,
2579 CLK_INIT(pmic_ssbi2_clk.c),
2580 },
2581};
2582
2583static struct branch_clk rpm_msg_ram_p_clk = {
2584 .b = {
2585 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2586 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002587 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2588 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002589 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2590 .halt_check = HALT_VOTED,
2591 .halt_bit = 12,
2592 },
2593 .c = {
2594 .dbg_name = "rpm_msg_ram_p_clk",
2595 .ops = &clk_ops_branch,
2596 CLK_INIT(rpm_msg_ram_p_clk.c),
2597 },
2598};
2599
2600/*
2601 * Multimedia Clocks
2602 */
2603
Stephen Boyd94625ef2011-07-12 17:06:01 -07002604#define CLK_CAM(name, n, hb) \
2605 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002606 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002607 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002608 .en_mask = BIT(0), \
2609 .halt_reg = DBG_BUS_VEC_I_REG, \
2610 .halt_bit = hb, \
2611 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002612 .ns_reg = CAMCLK##n##_NS_REG, \
2613 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002614 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002615 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Matt Wagantall07c45472012-02-10 23:27:24 -08002616 .mnd_en_mask = BIT(5), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002617 .ctl_mask = BM(7, 6), \
2618 .set_rate = set_rate_mnd_8, \
2619 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002620 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002621 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002622 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07002623 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002624 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002625 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002626 }, \
2627 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002628#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002629 { \
2630 .freq_hz = f, \
2631 .src_clk = &s##_clk.c, \
2632 .md_val = MD8(8, m, 0, n), \
2633 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2634 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002635 }
2636static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002637 F_CAM( 0, gnd, 1, 0, 0),
2638 F_CAM( 6000000, pll8, 4, 1, 16),
2639 F_CAM( 8000000, pll8, 4, 1, 12),
2640 F_CAM( 12000000, pll8, 4, 1, 8),
2641 F_CAM( 16000000, pll8, 4, 1, 6),
2642 F_CAM( 19200000, pll8, 4, 1, 5),
2643 F_CAM( 24000000, pll8, 4, 1, 4),
2644 F_CAM( 32000000, pll8, 4, 1, 3),
2645 F_CAM( 48000000, pll8, 4, 1, 2),
2646 F_CAM( 64000000, pll8, 3, 1, 2),
2647 F_CAM( 96000000, pll8, 4, 0, 0),
2648 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002649 F_END
2650};
2651
Stephen Boyd94625ef2011-07-12 17:06:01 -07002652static CLK_CAM(cam0_clk, 0, 15);
2653static CLK_CAM(cam1_clk, 1, 16);
2654static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002655
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002656#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002657 { \
2658 .freq_hz = f, \
2659 .src_clk = &s##_clk.c, \
2660 .md_val = MD8(8, m, 0, n), \
2661 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2662 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002663 }
2664static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002665 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002666 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002667 F_CSI( 85330000, pll8, 1, 2, 9),
2668 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002669 F_END
2670};
2671
2672static struct rcg_clk csi0_src_clk = {
2673 .ns_reg = CSI0_NS_REG,
2674 .b = {
2675 .ctl_reg = CSI0_CC_REG,
2676 .halt_check = NOCHECK,
2677 },
2678 .md_reg = CSI0_MD_REG,
2679 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002680 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002681 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002682 .ctl_mask = BM(7, 6),
2683 .set_rate = set_rate_mnd,
2684 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002685 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002686 .c = {
2687 .dbg_name = "csi0_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002688 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002689 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002690 CLK_INIT(csi0_src_clk.c),
2691 },
2692};
2693
2694static struct branch_clk csi0_clk = {
2695 .b = {
2696 .ctl_reg = CSI0_CC_REG,
2697 .en_mask = BIT(0),
2698 .reset_reg = SW_RESET_CORE_REG,
2699 .reset_mask = BIT(8),
2700 .halt_reg = DBG_BUS_VEC_B_REG,
2701 .halt_bit = 13,
2702 },
2703 .parent = &csi0_src_clk.c,
2704 .c = {
2705 .dbg_name = "csi0_clk",
2706 .ops = &clk_ops_branch,
2707 CLK_INIT(csi0_clk.c),
2708 },
2709};
2710
2711static struct branch_clk csi0_phy_clk = {
2712 .b = {
2713 .ctl_reg = CSI0_CC_REG,
2714 .en_mask = BIT(8),
2715 .reset_reg = SW_RESET_CORE_REG,
2716 .reset_mask = BIT(29),
2717 .halt_reg = DBG_BUS_VEC_I_REG,
2718 .halt_bit = 9,
2719 },
2720 .parent = &csi0_src_clk.c,
2721 .c = {
2722 .dbg_name = "csi0_phy_clk",
2723 .ops = &clk_ops_branch,
2724 CLK_INIT(csi0_phy_clk.c),
2725 },
2726};
2727
2728static struct rcg_clk csi1_src_clk = {
2729 .ns_reg = CSI1_NS_REG,
2730 .b = {
2731 .ctl_reg = CSI1_CC_REG,
2732 .halt_check = NOCHECK,
2733 },
2734 .md_reg = CSI1_MD_REG,
2735 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002736 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002737 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002738 .ctl_mask = BM(7, 6),
2739 .set_rate = set_rate_mnd,
2740 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002741 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002742 .c = {
2743 .dbg_name = "csi1_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002744 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002745 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002746 CLK_INIT(csi1_src_clk.c),
2747 },
2748};
2749
2750static struct branch_clk csi1_clk = {
2751 .b = {
2752 .ctl_reg = CSI1_CC_REG,
2753 .en_mask = BIT(0),
2754 .reset_reg = SW_RESET_CORE_REG,
2755 .reset_mask = BIT(18),
2756 .halt_reg = DBG_BUS_VEC_B_REG,
2757 .halt_bit = 14,
2758 },
2759 .parent = &csi1_src_clk.c,
2760 .c = {
2761 .dbg_name = "csi1_clk",
2762 .ops = &clk_ops_branch,
2763 CLK_INIT(csi1_clk.c),
2764 },
2765};
2766
2767static struct branch_clk csi1_phy_clk = {
2768 .b = {
2769 .ctl_reg = CSI1_CC_REG,
2770 .en_mask = BIT(8),
2771 .reset_reg = SW_RESET_CORE_REG,
2772 .reset_mask = BIT(28),
2773 .halt_reg = DBG_BUS_VEC_I_REG,
2774 .halt_bit = 10,
2775 },
2776 .parent = &csi1_src_clk.c,
2777 .c = {
2778 .dbg_name = "csi1_phy_clk",
2779 .ops = &clk_ops_branch,
2780 CLK_INIT(csi1_phy_clk.c),
2781 },
2782};
2783
Stephen Boyd94625ef2011-07-12 17:06:01 -07002784static struct rcg_clk csi2_src_clk = {
2785 .ns_reg = CSI2_NS_REG,
2786 .b = {
2787 .ctl_reg = CSI2_CC_REG,
2788 .halt_check = NOCHECK,
2789 },
2790 .md_reg = CSI2_MD_REG,
2791 .root_en_mask = BIT(2),
2792 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002793 .mnd_en_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002794 .ctl_mask = BM(7, 6),
2795 .set_rate = set_rate_mnd,
2796 .freq_tbl = clk_tbl_csi,
2797 .current_freq = &rcg_dummy_freq,
2798 .c = {
2799 .dbg_name = "csi2_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002800 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002801 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002802 CLK_INIT(csi2_src_clk.c),
2803 },
2804};
2805
2806static struct branch_clk csi2_clk = {
2807 .b = {
2808 .ctl_reg = CSI2_CC_REG,
2809 .en_mask = BIT(0),
2810 .reset_reg = SW_RESET_CORE2_REG,
2811 .reset_mask = BIT(2),
2812 .halt_reg = DBG_BUS_VEC_B_REG,
2813 .halt_bit = 29,
2814 },
2815 .parent = &csi2_src_clk.c,
2816 .c = {
2817 .dbg_name = "csi2_clk",
2818 .ops = &clk_ops_branch,
2819 CLK_INIT(csi2_clk.c),
2820 },
2821};
2822
2823static struct branch_clk csi2_phy_clk = {
2824 .b = {
2825 .ctl_reg = CSI2_CC_REG,
2826 .en_mask = BIT(8),
2827 .reset_reg = SW_RESET_CORE_REG,
2828 .reset_mask = BIT(31),
2829 .halt_reg = DBG_BUS_VEC_I_REG,
2830 .halt_bit = 29,
2831 },
2832 .parent = &csi2_src_clk.c,
2833 .c = {
2834 .dbg_name = "csi2_phy_clk",
2835 .ops = &clk_ops_branch,
2836 CLK_INIT(csi2_phy_clk.c),
2837 },
2838};
2839
Stephen Boyd092fd182011-10-21 15:56:30 -07002840static struct clk *pix_rdi_mux_map[] = {
2841 [0] = &csi0_clk.c,
2842 [1] = &csi1_clk.c,
2843 [2] = &csi2_clk.c,
2844 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002845};
2846
Stephen Boyd092fd182011-10-21 15:56:30 -07002847struct pix_rdi_clk {
2848 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002849 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002850
2851 void __iomem *const s_reg;
2852 u32 s_mask;
2853
2854 void __iomem *const s2_reg;
2855 u32 s2_mask;
2856
2857 struct branch b;
2858 struct clk c;
2859};
2860
Matt Wagantallf82f2942012-01-27 13:56:13 -08002861static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002862{
Matt Wagantallf82f2942012-01-27 13:56:13 -08002863 return container_of(c, struct pix_rdi_clk, c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002864}
2865
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002866static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002867{
2868 int ret, i;
2869 u32 reg;
2870 unsigned long flags;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002871 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002872 struct clk **mux_map = pix_rdi_mux_map;
2873
2874 /*
2875 * These clocks select three inputs via two muxes. One mux selects
2876 * between csi0 and csi1 and the second mux selects between that mux's
2877 * output and csi2. The source and destination selections for each
2878 * mux must be clocking for the switch to succeed so just turn on
2879 * all three sources because it's easier than figuring out what source
2880 * needs to be on at what time.
2881 */
2882 for (i = 0; mux_map[i]; i++) {
2883 ret = clk_enable(mux_map[i]);
2884 if (ret)
2885 goto err;
2886 }
2887 if (rate >= i) {
2888 ret = -EINVAL;
2889 goto err;
2890 }
2891 /* Keep the new source on when switching inputs of an enabled clock */
Matt Wagantallf82f2942012-01-27 13:56:13 -08002892 if (rdi->enabled) {
2893 clk_disable(mux_map[rdi->cur_rate]);
Stephen Boyd092fd182011-10-21 15:56:30 -07002894 clk_enable(mux_map[rate]);
2895 }
2896 spin_lock_irqsave(&local_clock_reg_lock, flags);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002897 reg = readl_relaxed(rdi->s2_reg);
2898 reg &= ~rdi->s2_mask;
2899 reg |= rate == 2 ? rdi->s2_mask : 0;
2900 writel_relaxed(reg, rdi->s2_reg);
Stephen Boyd092fd182011-10-21 15:56:30 -07002901 /*
2902 * Wait at least 6 cycles of slowest clock
2903 * for the glitch-free MUX to fully switch sources.
2904 */
2905 mb();
2906 udelay(1);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002907 reg = readl_relaxed(rdi->s_reg);
2908 reg &= ~rdi->s_mask;
2909 reg |= rate == 1 ? rdi->s_mask : 0;
2910 writel_relaxed(reg, rdi->s_reg);
Stephen Boyd092fd182011-10-21 15:56:30 -07002911 /*
2912 * Wait at least 6 cycles of slowest clock
2913 * for the glitch-free MUX to fully switch sources.
2914 */
2915 mb();
2916 udelay(1);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002917 rdi->cur_rate = rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002918 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2919err:
2920 for (i--; i >= 0; i--)
2921 clk_disable(mux_map[i]);
2922
2923 return 0;
2924}
2925
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002926static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002927{
2928 return to_pix_rdi_clk(c)->cur_rate;
2929}
2930
2931static int pix_rdi_clk_enable(struct clk *c)
2932{
2933 unsigned long flags;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002934 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002935
2936 spin_lock_irqsave(&local_clock_reg_lock, flags);
Matt Wagantall0de1b3f2012-06-05 19:52:43 -07002937 __branch_enable_reg(&rdi->b, rdi->c.dbg_name);
Stephen Boyd092fd182011-10-21 15:56:30 -07002938 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002939 rdi->enabled = true;
Stephen Boyd092fd182011-10-21 15:56:30 -07002940
2941 return 0;
2942}
2943
2944static void pix_rdi_clk_disable(struct clk *c)
2945{
2946 unsigned long flags;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002947 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002948
2949 spin_lock_irqsave(&local_clock_reg_lock, flags);
Matt Wagantall0de1b3f2012-06-05 19:52:43 -07002950 __branch_disable_reg(&rdi->b, rdi->c.dbg_name);
Stephen Boyd092fd182011-10-21 15:56:30 -07002951 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002952 rdi->enabled = false;
Stephen Boyd092fd182011-10-21 15:56:30 -07002953}
2954
Matt Wagantallf82f2942012-01-27 13:56:13 -08002955static int pix_rdi_clk_reset(struct clk *c, enum clk_reset_action action)
Stephen Boyd092fd182011-10-21 15:56:30 -07002956{
Matt Wagantallf82f2942012-01-27 13:56:13 -08002957 return branch_reset(&to_pix_rdi_clk(c)->b, action);
Stephen Boyd092fd182011-10-21 15:56:30 -07002958}
2959
2960static struct clk *pix_rdi_clk_get_parent(struct clk *c)
2961{
Matt Wagantallf82f2942012-01-27 13:56:13 -08002962 return pix_rdi_mux_map[to_pix_rdi_clk(c)->cur_rate];
Stephen Boyd092fd182011-10-21 15:56:30 -07002963}
2964
2965static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
2966{
2967 if (pix_rdi_mux_map[n])
2968 return n;
2969 return -ENXIO;
2970}
2971
Matt Wagantalla15833b2012-04-03 11:00:56 -07002972static enum handoff pix_rdi_clk_handoff(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002973{
2974 u32 reg;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002975 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Matt Wagantalla15833b2012-04-03 11:00:56 -07002976 enum handoff ret;
2977
Matt Wagantallf82f2942012-01-27 13:56:13 -08002978 ret = branch_handoff(&rdi->b, &rdi->c);
Matt Wagantalla15833b2012-04-03 11:00:56 -07002979 if (ret == HANDOFF_DISABLED_CLK)
2980 return ret;
Stephen Boyd092fd182011-10-21 15:56:30 -07002981
Matt Wagantallf82f2942012-01-27 13:56:13 -08002982 reg = readl_relaxed(rdi->s_reg);
2983 rdi->cur_rate = reg & rdi->s_mask ? 1 : 0;
2984 reg = readl_relaxed(rdi->s2_reg);
2985 rdi->cur_rate = reg & rdi->s2_mask ? 2 : rdi->cur_rate;
Matt Wagantalla15833b2012-04-03 11:00:56 -07002986
2987 return HANDOFF_ENABLED_CLK;
Stephen Boyd092fd182011-10-21 15:56:30 -07002988}
2989
2990static struct clk_ops clk_ops_pix_rdi_8960 = {
2991 .enable = pix_rdi_clk_enable,
2992 .disable = pix_rdi_clk_disable,
Stephen Boyd092fd182011-10-21 15:56:30 -07002993 .handoff = pix_rdi_clk_handoff,
2994 .set_rate = pix_rdi_clk_set_rate,
2995 .get_rate = pix_rdi_clk_get_rate,
2996 .list_rate = pix_rdi_clk_list_rate,
2997 .reset = pix_rdi_clk_reset,
Stephen Boyd092fd182011-10-21 15:56:30 -07002998 .get_parent = pix_rdi_clk_get_parent,
2999};
3000
3001static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003002 .b = {
3003 .ctl_reg = MISC_CC_REG,
3004 .en_mask = BIT(26),
3005 .halt_check = DELAY,
3006 .reset_reg = SW_RESET_CORE_REG,
3007 .reset_mask = BIT(26),
3008 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003009 .s_reg = MISC_CC_REG,
3010 .s_mask = BIT(25),
3011 .s2_reg = MISC_CC3_REG,
3012 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003013 .c = {
3014 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003015 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003016 CLK_INIT(csi_pix_clk.c),
3017 },
3018};
3019
Stephen Boyd092fd182011-10-21 15:56:30 -07003020static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003021 .b = {
3022 .ctl_reg = MISC_CC3_REG,
3023 .en_mask = BIT(10),
3024 .halt_check = DELAY,
3025 .reset_reg = SW_RESET_CORE_REG,
3026 .reset_mask = BIT(30),
3027 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003028 .s_reg = MISC_CC3_REG,
3029 .s_mask = BIT(8),
3030 .s2_reg = MISC_CC3_REG,
3031 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003032 .c = {
3033 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003034 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003035 CLK_INIT(csi_pix1_clk.c),
3036 },
3037};
3038
Stephen Boyd092fd182011-10-21 15:56:30 -07003039static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003040 .b = {
3041 .ctl_reg = MISC_CC_REG,
3042 .en_mask = BIT(13),
3043 .halt_check = DELAY,
3044 .reset_reg = SW_RESET_CORE_REG,
3045 .reset_mask = BIT(27),
3046 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003047 .s_reg = MISC_CC_REG,
3048 .s_mask = BIT(12),
3049 .s2_reg = MISC_CC3_REG,
3050 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003051 .c = {
3052 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003053 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003054 CLK_INIT(csi_rdi_clk.c),
3055 },
3056};
3057
Stephen Boyd092fd182011-10-21 15:56:30 -07003058static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003059 .b = {
3060 .ctl_reg = MISC_CC3_REG,
3061 .en_mask = BIT(2),
3062 .halt_check = DELAY,
3063 .reset_reg = SW_RESET_CORE2_REG,
3064 .reset_mask = BIT(1),
3065 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003066 .s_reg = MISC_CC3_REG,
3067 .s_mask = BIT(0),
3068 .s2_reg = MISC_CC3_REG,
3069 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003070 .c = {
3071 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003072 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003073 CLK_INIT(csi_rdi1_clk.c),
3074 },
3075};
3076
Stephen Boyd092fd182011-10-21 15:56:30 -07003077static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003078 .b = {
3079 .ctl_reg = MISC_CC3_REG,
3080 .en_mask = BIT(6),
3081 .halt_check = DELAY,
3082 .reset_reg = SW_RESET_CORE2_REG,
3083 .reset_mask = BIT(0),
3084 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003085 .s_reg = MISC_CC3_REG,
3086 .s_mask = BIT(4),
3087 .s2_reg = MISC_CC3_REG,
3088 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003089 .c = {
3090 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003091 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003092 CLK_INIT(csi_rdi2_clk.c),
3093 },
3094};
3095
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003096#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003097 { \
3098 .freq_hz = f, \
3099 .src_clk = &s##_clk.c, \
3100 .md_val = MD8(8, m, 0, n), \
3101 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3102 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003103 }
3104static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003105 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
3106 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
3107 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003108 F_END
3109};
3110
3111static struct rcg_clk csiphy_timer_src_clk = {
3112 .ns_reg = CSIPHYTIMER_NS_REG,
3113 .b = {
3114 .ctl_reg = CSIPHYTIMER_CC_REG,
3115 .halt_check = NOCHECK,
3116 },
3117 .md_reg = CSIPHYTIMER_MD_REG,
3118 .root_en_mask = BIT(2),
3119 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003120 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003121 .ctl_mask = BM(7, 6),
3122 .set_rate = set_rate_mnd_8,
3123 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003124 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003125 .c = {
3126 .dbg_name = "csiphy_timer_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003127 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003128 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003129 CLK_INIT(csiphy_timer_src_clk.c),
3130 },
3131};
3132
3133static struct branch_clk csi0phy_timer_clk = {
3134 .b = {
3135 .ctl_reg = CSIPHYTIMER_CC_REG,
3136 .en_mask = BIT(0),
3137 .halt_reg = DBG_BUS_VEC_I_REG,
3138 .halt_bit = 17,
3139 },
3140 .parent = &csiphy_timer_src_clk.c,
3141 .c = {
3142 .dbg_name = "csi0phy_timer_clk",
3143 .ops = &clk_ops_branch,
3144 CLK_INIT(csi0phy_timer_clk.c),
3145 },
3146};
3147
3148static struct branch_clk csi1phy_timer_clk = {
3149 .b = {
3150 .ctl_reg = CSIPHYTIMER_CC_REG,
3151 .en_mask = BIT(9),
3152 .halt_reg = DBG_BUS_VEC_I_REG,
3153 .halt_bit = 18,
3154 },
3155 .parent = &csiphy_timer_src_clk.c,
3156 .c = {
3157 .dbg_name = "csi1phy_timer_clk",
3158 .ops = &clk_ops_branch,
3159 CLK_INIT(csi1phy_timer_clk.c),
3160 },
3161};
3162
Stephen Boyd94625ef2011-07-12 17:06:01 -07003163static struct branch_clk csi2phy_timer_clk = {
3164 .b = {
3165 .ctl_reg = CSIPHYTIMER_CC_REG,
3166 .en_mask = BIT(11),
3167 .halt_reg = DBG_BUS_VEC_I_REG,
3168 .halt_bit = 30,
3169 },
3170 .parent = &csiphy_timer_src_clk.c,
3171 .c = {
3172 .dbg_name = "csi2phy_timer_clk",
3173 .ops = &clk_ops_branch,
3174 CLK_INIT(csi2phy_timer_clk.c),
3175 },
3176};
3177
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003178#define F_DSI(d) \
3179 { \
3180 .freq_hz = d, \
3181 .ns_val = BVAL(15, 12, (d-1)), \
3182 }
3183/*
3184 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3185 * without this clock driver knowing. So, overload the clk_set_rate() to set
3186 * the divider (1 to 16) of the clock with respect to the PLL rate.
3187 */
3188static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3189 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3190 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3191 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3192 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3193 F_END
3194};
3195
3196static struct rcg_clk dsi1_byte_clk = {
3197 .b = {
3198 .ctl_reg = DSI1_BYTE_CC_REG,
3199 .en_mask = BIT(0),
3200 .reset_reg = SW_RESET_CORE_REG,
3201 .reset_mask = BIT(7),
3202 .halt_reg = DBG_BUS_VEC_B_REG,
3203 .halt_bit = 21,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003204 .retain_reg = DSI1_BYTE_CC_REG,
3205 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003206 },
3207 .ns_reg = DSI1_BYTE_NS_REG,
3208 .root_en_mask = BIT(2),
3209 .ns_mask = BM(15, 12),
3210 .set_rate = set_rate_nop,
3211 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003212 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003213 .c = {
3214 .dbg_name = "dsi1_byte_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003215 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003216 CLK_INIT(dsi1_byte_clk.c),
3217 },
3218};
3219
3220static struct rcg_clk dsi2_byte_clk = {
3221 .b = {
3222 .ctl_reg = DSI2_BYTE_CC_REG,
3223 .en_mask = BIT(0),
3224 .reset_reg = SW_RESET_CORE_REG,
3225 .reset_mask = BIT(25),
3226 .halt_reg = DBG_BUS_VEC_B_REG,
3227 .halt_bit = 20,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003228 .retain_reg = DSI2_BYTE_CC_REG,
3229 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003230 },
3231 .ns_reg = DSI2_BYTE_NS_REG,
3232 .root_en_mask = BIT(2),
3233 .ns_mask = BM(15, 12),
3234 .set_rate = set_rate_nop,
3235 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003236 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003237 .c = {
3238 .dbg_name = "dsi2_byte_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003239 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003240 CLK_INIT(dsi2_byte_clk.c),
3241 },
3242};
3243
3244static struct rcg_clk dsi1_esc_clk = {
3245 .b = {
3246 .ctl_reg = DSI1_ESC_CC_REG,
3247 .en_mask = BIT(0),
3248 .reset_reg = SW_RESET_CORE_REG,
3249 .halt_reg = DBG_BUS_VEC_I_REG,
3250 .halt_bit = 1,
3251 },
3252 .ns_reg = DSI1_ESC_NS_REG,
3253 .root_en_mask = BIT(2),
3254 .ns_mask = BM(15, 12),
3255 .set_rate = set_rate_nop,
3256 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003257 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003258 .c = {
3259 .dbg_name = "dsi1_esc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003260 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003261 CLK_INIT(dsi1_esc_clk.c),
3262 },
3263};
3264
3265static struct rcg_clk dsi2_esc_clk = {
3266 .b = {
3267 .ctl_reg = DSI2_ESC_CC_REG,
3268 .en_mask = BIT(0),
3269 .halt_reg = DBG_BUS_VEC_I_REG,
3270 .halt_bit = 3,
3271 },
3272 .ns_reg = DSI2_ESC_NS_REG,
3273 .root_en_mask = BIT(2),
3274 .ns_mask = BM(15, 12),
3275 .set_rate = set_rate_nop,
3276 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003277 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003278 .c = {
3279 .dbg_name = "dsi2_esc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003280 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003281 CLK_INIT(dsi2_esc_clk.c),
3282 },
3283};
3284
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003285#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003286 { \
3287 .freq_hz = f, \
3288 .src_clk = &s##_clk.c, \
3289 .md_val = MD4(4, m, 0, n), \
3290 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3291 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003292 }
3293static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003294 F_GFX2D( 0, gnd, 0, 0),
3295 F_GFX2D( 27000000, pxo, 0, 0),
3296 F_GFX2D( 48000000, pll8, 1, 8),
3297 F_GFX2D( 54857000, pll8, 1, 7),
3298 F_GFX2D( 64000000, pll8, 1, 6),
3299 F_GFX2D( 76800000, pll8, 1, 5),
3300 F_GFX2D( 96000000, pll8, 1, 4),
3301 F_GFX2D(128000000, pll8, 1, 3),
3302 F_GFX2D(145455000, pll2, 2, 11),
3303 F_GFX2D(160000000, pll2, 1, 5),
3304 F_GFX2D(177778000, pll2, 2, 9),
3305 F_GFX2D(200000000, pll2, 1, 4),
3306 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003307 F_END
3308};
3309
3310static struct bank_masks bmnd_info_gfx2d0 = {
3311 .bank_sel_mask = BIT(11),
3312 .bank0_mask = {
3313 .md_reg = GFX2D0_MD0_REG,
3314 .ns_mask = BM(23, 20) | BM(5, 3),
3315 .rst_mask = BIT(25),
3316 .mnd_en_mask = BIT(8),
3317 .mode_mask = BM(10, 9),
3318 },
3319 .bank1_mask = {
3320 .md_reg = GFX2D0_MD1_REG,
3321 .ns_mask = BM(19, 16) | BM(2, 0),
3322 .rst_mask = BIT(24),
3323 .mnd_en_mask = BIT(5),
3324 .mode_mask = BM(7, 6),
3325 },
3326};
3327
3328static struct rcg_clk gfx2d0_clk = {
3329 .b = {
3330 .ctl_reg = GFX2D0_CC_REG,
3331 .en_mask = BIT(0),
3332 .reset_reg = SW_RESET_CORE_REG,
3333 .reset_mask = BIT(14),
3334 .halt_reg = DBG_BUS_VEC_A_REG,
3335 .halt_bit = 9,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003336 .retain_reg = GFX2D0_CC_REG,
3337 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003338 },
3339 .ns_reg = GFX2D0_NS_REG,
3340 .root_en_mask = BIT(2),
3341 .set_rate = set_rate_mnd_banked,
3342 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003343 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003344 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003345 .c = {
3346 .dbg_name = "gfx2d0_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003347 .ops = &clk_ops_rcg,
Matt Wagantall158f73b2012-05-16 11:29:35 -07003348 .flags = CLKFLAG_SKIP_HANDOFF,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003349 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3350 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003351 CLK_INIT(gfx2d0_clk.c),
3352 },
3353};
3354
3355static struct bank_masks bmnd_info_gfx2d1 = {
3356 .bank_sel_mask = BIT(11),
3357 .bank0_mask = {
3358 .md_reg = GFX2D1_MD0_REG,
3359 .ns_mask = BM(23, 20) | BM(5, 3),
3360 .rst_mask = BIT(25),
3361 .mnd_en_mask = BIT(8),
3362 .mode_mask = BM(10, 9),
3363 },
3364 .bank1_mask = {
3365 .md_reg = GFX2D1_MD1_REG,
3366 .ns_mask = BM(19, 16) | BM(2, 0),
3367 .rst_mask = BIT(24),
3368 .mnd_en_mask = BIT(5),
3369 .mode_mask = BM(7, 6),
3370 },
3371};
3372
3373static struct rcg_clk gfx2d1_clk = {
3374 .b = {
3375 .ctl_reg = GFX2D1_CC_REG,
3376 .en_mask = BIT(0),
3377 .reset_reg = SW_RESET_CORE_REG,
3378 .reset_mask = BIT(13),
3379 .halt_reg = DBG_BUS_VEC_A_REG,
3380 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003381 .retain_reg = GFX2D1_CC_REG,
3382 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003383 },
3384 .ns_reg = GFX2D1_NS_REG,
3385 .root_en_mask = BIT(2),
3386 .set_rate = set_rate_mnd_banked,
3387 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003388 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003389 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003390 .c = {
3391 .dbg_name = "gfx2d1_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003392 .ops = &clk_ops_rcg,
Matt Wagantall158f73b2012-05-16 11:29:35 -07003393 .flags = CLKFLAG_SKIP_HANDOFF,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003394 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3395 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003396 CLK_INIT(gfx2d1_clk.c),
3397 },
3398};
3399
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003400#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003401 { \
3402 .freq_hz = f, \
3403 .src_clk = &s##_clk.c, \
3404 .md_val = MD4(4, m, 0, n), \
3405 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3406 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003407 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003408
3409static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003410 F_GFX3D( 0, gnd, 0, 0),
3411 F_GFX3D( 27000000, pxo, 0, 0),
3412 F_GFX3D( 48000000, pll8, 1, 8),
3413 F_GFX3D( 54857000, pll8, 1, 7),
3414 F_GFX3D( 64000000, pll8, 1, 6),
3415 F_GFX3D( 76800000, pll8, 1, 5),
3416 F_GFX3D( 96000000, pll8, 1, 4),
3417 F_GFX3D(128000000, pll8, 1, 3),
3418 F_GFX3D(145455000, pll2, 2, 11),
3419 F_GFX3D(160000000, pll2, 1, 5),
3420 F_GFX3D(177778000, pll2, 2, 9),
3421 F_GFX3D(200000000, pll2, 1, 4),
3422 F_GFX3D(228571000, pll2, 2, 7),
3423 F_GFX3D(266667000, pll2, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003424 F_GFX3D(300000000, pll3, 1, 4),
3425 F_GFX3D(320000000, pll2, 2, 5),
3426 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003427 F_END
3428};
3429
Tianyi Gou41515e22011-09-01 19:37:43 -07003430static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003431 F_GFX3D( 0, gnd, 0, 0),
3432 F_GFX3D( 27000000, pxo, 0, 0),
3433 F_GFX3D( 48000000, pll8, 1, 8),
3434 F_GFX3D( 54857000, pll8, 1, 7),
3435 F_GFX3D( 64000000, pll8, 1, 6),
3436 F_GFX3D( 76800000, pll8, 1, 5),
3437 F_GFX3D( 96000000, pll8, 1, 4),
3438 F_GFX3D(128000000, pll8, 1, 3),
3439 F_GFX3D(145455000, pll2, 2, 11),
3440 F_GFX3D(160000000, pll2, 1, 5),
3441 F_GFX3D(177778000, pll2, 2, 9),
3442 F_GFX3D(200000000, pll2, 1, 4),
3443 F_GFX3D(228571000, pll2, 2, 7),
3444 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003445 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003446 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003447 F_END
3448};
3449
Tianyi Goue3d4f542012-03-15 17:06:45 -07003450static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = {
3451 F_GFX3D( 0, gnd, 0, 0),
3452 F_GFX3D( 27000000, pxo, 0, 0),
3453 F_GFX3D( 48000000, pll8, 1, 8),
3454 F_GFX3D( 54857000, pll8, 1, 7),
3455 F_GFX3D( 64000000, pll8, 1, 6),
3456 F_GFX3D( 76800000, pll8, 1, 5),
3457 F_GFX3D( 96000000, pll8, 1, 4),
3458 F_GFX3D(128000000, pll8, 1, 3),
3459 F_GFX3D(145455000, pll2, 2, 11),
3460 F_GFX3D(160000000, pll2, 1, 5),
3461 F_GFX3D(177778000, pll2, 2, 9),
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003462 F_GFX3D(192000000, pll8, 1, 2),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003463 F_GFX3D(200000000, pll2, 1, 4),
3464 F_GFX3D(228571000, pll2, 2, 7),
3465 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003466 F_GFX3D(320000000, pll2, 2, 5),
3467 F_GFX3D(400000000, pll2, 1, 2),
3468 F_GFX3D(450000000, pll15, 1, 2),
3469 F_END
3470};
3471
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003472static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3473 [VDD_DIG_LOW] = 128000000,
3474 [VDD_DIG_NOMINAL] = 325000000,
3475 [VDD_DIG_HIGH] = 400000000
3476};
3477
Tianyi Goue3d4f542012-03-15 17:06:45 -07003478static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = {
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003479 [VDD_DIG_LOW] = 192000000,
Tianyi Goue3d4f542012-03-15 17:06:45 -07003480 [VDD_DIG_NOMINAL] = 320000000,
3481 [VDD_DIG_HIGH] = 450000000
3482};
3483
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003484static struct bank_masks bmnd_info_gfx3d = {
3485 .bank_sel_mask = BIT(11),
3486 .bank0_mask = {
3487 .md_reg = GFX3D_MD0_REG,
3488 .ns_mask = BM(21, 18) | BM(5, 3),
3489 .rst_mask = BIT(23),
3490 .mnd_en_mask = BIT(8),
3491 .mode_mask = BM(10, 9),
3492 },
3493 .bank1_mask = {
3494 .md_reg = GFX3D_MD1_REG,
3495 .ns_mask = BM(17, 14) | BM(2, 0),
3496 .rst_mask = BIT(22),
3497 .mnd_en_mask = BIT(5),
3498 .mode_mask = BM(7, 6),
3499 },
3500};
3501
3502static struct rcg_clk gfx3d_clk = {
3503 .b = {
3504 .ctl_reg = GFX3D_CC_REG,
3505 .en_mask = BIT(0),
3506 .reset_reg = SW_RESET_CORE_REG,
3507 .reset_mask = BIT(12),
3508 .halt_reg = DBG_BUS_VEC_A_REG,
3509 .halt_bit = 4,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003510 .retain_reg = GFX3D_CC_REG,
3511 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003512 },
3513 .ns_reg = GFX3D_NS_REG,
3514 .root_en_mask = BIT(2),
3515 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003516 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003517 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003518 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003519 .c = {
3520 .dbg_name = "gfx3d_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003521 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003522 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
3523 HIGH, 400000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003524 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003525 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003526 },
3527};
3528
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003529#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003530 { \
3531 .freq_hz = f, \
3532 .src_clk = &s##_clk.c, \
3533 .md_val = MD4(4, m, 0, n), \
3534 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3535 .ctl_val = CC_BANKED(9, 6, n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003536 }
3537
3538static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003539 F_VCAP( 0, gnd, 0, 0),
3540 F_VCAP( 27000000, pxo, 0, 0),
3541 F_VCAP( 54860000, pll8, 1, 7),
3542 F_VCAP( 64000000, pll8, 1, 6),
3543 F_VCAP( 76800000, pll8, 1, 5),
3544 F_VCAP(128000000, pll8, 1, 3),
3545 F_VCAP(160000000, pll2, 1, 5),
3546 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003547 F_END
3548};
3549
3550static struct bank_masks bmnd_info_vcap = {
3551 .bank_sel_mask = BIT(11),
3552 .bank0_mask = {
3553 .md_reg = VCAP_MD0_REG,
3554 .ns_mask = BM(21, 18) | BM(5, 3),
3555 .rst_mask = BIT(23),
3556 .mnd_en_mask = BIT(8),
3557 .mode_mask = BM(10, 9),
3558 },
3559 .bank1_mask = {
3560 .md_reg = VCAP_MD1_REG,
3561 .ns_mask = BM(17, 14) | BM(2, 0),
3562 .rst_mask = BIT(22),
3563 .mnd_en_mask = BIT(5),
3564 .mode_mask = BM(7, 6),
3565 },
3566};
3567
3568static struct rcg_clk vcap_clk = {
3569 .b = {
3570 .ctl_reg = VCAP_CC_REG,
3571 .en_mask = BIT(0),
3572 .halt_reg = DBG_BUS_VEC_J_REG,
3573 .halt_bit = 15,
3574 },
3575 .ns_reg = VCAP_NS_REG,
3576 .root_en_mask = BIT(2),
3577 .set_rate = set_rate_mnd_banked,
3578 .freq_tbl = clk_tbl_vcap,
3579 .bank_info = &bmnd_info_vcap,
3580 .current_freq = &rcg_dummy_freq,
3581 .c = {
3582 .dbg_name = "vcap_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003583 .ops = &clk_ops_rcg,
Tianyi Gou621f8742011-09-01 21:45:01 -07003584 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003585 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003586 CLK_INIT(vcap_clk.c),
3587 },
3588};
3589
3590static struct branch_clk vcap_npl_clk = {
3591 .b = {
3592 .ctl_reg = VCAP_CC_REG,
3593 .en_mask = BIT(13),
3594 .halt_reg = DBG_BUS_VEC_J_REG,
3595 .halt_bit = 25,
3596 },
3597 .parent = &vcap_clk.c,
3598 .c = {
3599 .dbg_name = "vcap_npl_clk",
3600 .ops = &clk_ops_branch,
3601 CLK_INIT(vcap_npl_clk.c),
3602 },
3603};
3604
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003605#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003606 { \
3607 .freq_hz = f, \
3608 .src_clk = &s##_clk.c, \
3609 .md_val = MD8(8, m, 0, n), \
3610 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3611 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003612 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003613
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003614static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3615 F_IJPEG( 0, gnd, 1, 0, 0),
3616 F_IJPEG( 27000000, pxo, 1, 0, 0),
3617 F_IJPEG( 36570000, pll8, 1, 2, 21),
3618 F_IJPEG( 54860000, pll8, 7, 0, 0),
3619 F_IJPEG( 96000000, pll8, 4, 0, 0),
3620 F_IJPEG(109710000, pll8, 1, 2, 7),
3621 F_IJPEG(128000000, pll8, 3, 0, 0),
3622 F_IJPEG(153600000, pll8, 1, 2, 5),
3623 F_IJPEG(200000000, pll2, 4, 0, 0),
3624 F_IJPEG(228571000, pll2, 1, 2, 7),
3625 F_IJPEG(266667000, pll2, 1, 1, 3),
3626 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003627 F_END
3628};
3629
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003630static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3631 [VDD_DIG_LOW] = 128000000,
3632 [VDD_DIG_NOMINAL] = 266667000,
3633 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003634};
3635
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003636static struct rcg_clk ijpeg_clk = {
3637 .b = {
3638 .ctl_reg = IJPEG_CC_REG,
3639 .en_mask = BIT(0),
3640 .reset_reg = SW_RESET_CORE_REG,
3641 .reset_mask = BIT(9),
3642 .halt_reg = DBG_BUS_VEC_A_REG,
3643 .halt_bit = 24,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003644 .retain_reg = IJPEG_CC_REG,
3645 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003646 },
3647 .ns_reg = IJPEG_NS_REG,
3648 .md_reg = IJPEG_MD_REG,
3649 .root_en_mask = BIT(2),
3650 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003651 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003652 .ctl_mask = BM(7, 6),
3653 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003654 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003655 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003656 .c = {
3657 .dbg_name = "ijpeg_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003658 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003659 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
3660 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003661 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003662 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003663 },
3664};
3665
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003666#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003667 { \
3668 .freq_hz = f, \
3669 .src_clk = &s##_clk.c, \
3670 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003671 }
3672static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003673 F_JPEGD( 0, gnd, 1),
3674 F_JPEGD( 64000000, pll8, 6),
3675 F_JPEGD( 76800000, pll8, 5),
3676 F_JPEGD( 96000000, pll8, 4),
3677 F_JPEGD(160000000, pll2, 5),
3678 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003679 F_END
3680};
3681
3682static struct rcg_clk jpegd_clk = {
3683 .b = {
3684 .ctl_reg = JPEGD_CC_REG,
3685 .en_mask = BIT(0),
3686 .reset_reg = SW_RESET_CORE_REG,
3687 .reset_mask = BIT(19),
3688 .halt_reg = DBG_BUS_VEC_A_REG,
3689 .halt_bit = 19,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003690 .retain_reg = JPEGD_CC_REG,
3691 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003692 },
3693 .ns_reg = JPEGD_NS_REG,
3694 .root_en_mask = BIT(2),
3695 .ns_mask = (BM(15, 12) | BM(2, 0)),
3696 .set_rate = set_rate_nop,
3697 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003698 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003699 .c = {
3700 .dbg_name = "jpegd_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003701 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003702 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003703 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003704 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003705 },
3706};
3707
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003708#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003709 { \
3710 .freq_hz = f, \
3711 .src_clk = &s##_clk.c, \
3712 .md_val = MD8(8, m, 0, n), \
3713 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3714 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003715 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003716static struct clk_freq_tbl clk_tbl_mdp[] = {
3717 F_MDP( 0, gnd, 0, 0),
3718 F_MDP( 9600000, pll8, 1, 40),
3719 F_MDP( 13710000, pll8, 1, 28),
3720 F_MDP( 27000000, pxo, 0, 0),
3721 F_MDP( 29540000, pll8, 1, 13),
3722 F_MDP( 34910000, pll8, 1, 11),
3723 F_MDP( 38400000, pll8, 1, 10),
3724 F_MDP( 59080000, pll8, 2, 13),
3725 F_MDP( 76800000, pll8, 1, 5),
3726 F_MDP( 85330000, pll8, 2, 9),
3727 F_MDP( 96000000, pll8, 1, 4),
3728 F_MDP(128000000, pll8, 1, 3),
3729 F_MDP(160000000, pll2, 1, 5),
3730 F_MDP(177780000, pll2, 2, 9),
3731 F_MDP(200000000, pll2, 1, 4),
3732 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003733 F_END
3734};
3735
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003736static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3737 [VDD_DIG_LOW] = 128000000,
3738 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003739};
3740
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003741static struct bank_masks bmnd_info_mdp = {
3742 .bank_sel_mask = BIT(11),
3743 .bank0_mask = {
3744 .md_reg = MDP_MD0_REG,
3745 .ns_mask = BM(29, 22) | BM(5, 3),
3746 .rst_mask = BIT(31),
3747 .mnd_en_mask = BIT(8),
3748 .mode_mask = BM(10, 9),
3749 },
3750 .bank1_mask = {
3751 .md_reg = MDP_MD1_REG,
3752 .ns_mask = BM(21, 14) | BM(2, 0),
3753 .rst_mask = BIT(30),
3754 .mnd_en_mask = BIT(5),
3755 .mode_mask = BM(7, 6),
3756 },
3757};
3758
3759static struct rcg_clk mdp_clk = {
3760 .b = {
3761 .ctl_reg = MDP_CC_REG,
3762 .en_mask = BIT(0),
3763 .reset_reg = SW_RESET_CORE_REG,
3764 .reset_mask = BIT(21),
3765 .halt_reg = DBG_BUS_VEC_C_REG,
3766 .halt_bit = 10,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003767 .retain_reg = MDP_CC_REG,
3768 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003769 },
3770 .ns_reg = MDP_NS_REG,
3771 .root_en_mask = BIT(2),
3772 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003773 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003774 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003775 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003776 .c = {
3777 .dbg_name = "mdp_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003778 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003779 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003780 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003781 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003782 },
3783};
3784
3785static struct branch_clk lut_mdp_clk = {
3786 .b = {
3787 .ctl_reg = MDP_LUT_CC_REG,
3788 .en_mask = BIT(0),
3789 .halt_reg = DBG_BUS_VEC_I_REG,
3790 .halt_bit = 13,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003791 .retain_reg = MDP_LUT_CC_REG,
3792 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003793 },
3794 .parent = &mdp_clk.c,
3795 .c = {
3796 .dbg_name = "lut_mdp_clk",
3797 .ops = &clk_ops_branch,
3798 CLK_INIT(lut_mdp_clk.c),
3799 },
3800};
3801
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003802#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003803 { \
3804 .freq_hz = f, \
3805 .src_clk = &s##_clk.c, \
3806 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003807 }
3808static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003809 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003810 F_END
3811};
3812
3813static struct rcg_clk mdp_vsync_clk = {
3814 .b = {
3815 .ctl_reg = MISC_CC_REG,
3816 .en_mask = BIT(6),
3817 .reset_reg = SW_RESET_CORE_REG,
3818 .reset_mask = BIT(3),
3819 .halt_reg = DBG_BUS_VEC_B_REG,
3820 .halt_bit = 22,
3821 },
3822 .ns_reg = MISC_CC2_REG,
3823 .ns_mask = BIT(13),
3824 .set_rate = set_rate_nop,
3825 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003826 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003827 .c = {
3828 .dbg_name = "mdp_vsync_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003829 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003830 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003831 CLK_INIT(mdp_vsync_clk.c),
3832 },
3833};
3834
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003835#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003836 { \
3837 .freq_hz = f, \
3838 .src_clk = &s##_clk.c, \
3839 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3840 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003841 }
3842static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003843 F_ROT( 0, gnd, 1),
3844 F_ROT( 27000000, pxo, 1),
3845 F_ROT( 29540000, pll8, 13),
3846 F_ROT( 32000000, pll8, 12),
3847 F_ROT( 38400000, pll8, 10),
3848 F_ROT( 48000000, pll8, 8),
3849 F_ROT( 54860000, pll8, 7),
3850 F_ROT( 64000000, pll8, 6),
3851 F_ROT( 76800000, pll8, 5),
3852 F_ROT( 96000000, pll8, 4),
3853 F_ROT(100000000, pll2, 8),
3854 F_ROT(114290000, pll2, 7),
3855 F_ROT(133330000, pll2, 6),
3856 F_ROT(160000000, pll2, 5),
3857 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003858 F_END
3859};
3860
3861static struct bank_masks bdiv_info_rot = {
3862 .bank_sel_mask = BIT(30),
3863 .bank0_mask = {
3864 .ns_mask = BM(25, 22) | BM(18, 16),
3865 },
3866 .bank1_mask = {
3867 .ns_mask = BM(29, 26) | BM(21, 19),
3868 },
3869};
3870
3871static struct rcg_clk rot_clk = {
3872 .b = {
3873 .ctl_reg = ROT_CC_REG,
3874 .en_mask = BIT(0),
3875 .reset_reg = SW_RESET_CORE_REG,
3876 .reset_mask = BIT(2),
3877 .halt_reg = DBG_BUS_VEC_C_REG,
3878 .halt_bit = 15,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003879 .retain_reg = ROT_CC_REG,
3880 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003881 },
3882 .ns_reg = ROT_NS_REG,
3883 .root_en_mask = BIT(2),
3884 .set_rate = set_rate_div_banked,
3885 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003886 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003887 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003888 .c = {
3889 .dbg_name = "rot_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003890 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003891 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003892 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003893 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003894 },
3895};
3896
Matt Wagantallf82f2942012-01-27 13:56:13 -08003897static int hdmi_pll_clk_enable(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003898{
3899 int ret;
3900 unsigned long flags;
3901 spin_lock_irqsave(&local_clock_reg_lock, flags);
3902 ret = hdmi_pll_enable();
3903 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3904 return ret;
3905}
3906
Matt Wagantallf82f2942012-01-27 13:56:13 -08003907static void hdmi_pll_clk_disable(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003908{
3909 unsigned long flags;
3910 spin_lock_irqsave(&local_clock_reg_lock, flags);
3911 hdmi_pll_disable();
3912 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3913}
3914
Matt Wagantallf82f2942012-01-27 13:56:13 -08003915static unsigned long hdmi_pll_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003916{
3917 return hdmi_pll_get_rate();
3918}
3919
Matt Wagantallf82f2942012-01-27 13:56:13 -08003920static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003921{
3922 return &pxo_clk.c;
3923}
3924
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003925static struct clk_ops clk_ops_hdmi_pll = {
3926 .enable = hdmi_pll_clk_enable,
3927 .disable = hdmi_pll_clk_disable,
3928 .get_rate = hdmi_pll_clk_get_rate,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003929 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003930};
3931
3932static struct clk hdmi_pll_clk = {
3933 .dbg_name = "hdmi_pll_clk",
3934 .ops = &clk_ops_hdmi_pll,
3935 CLK_INIT(hdmi_pll_clk),
3936};
3937
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003938#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003939 { \
3940 .freq_hz = f, \
3941 .src_clk = &s##_clk.c, \
3942 .md_val = MD8(8, m, 0, n), \
3943 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3944 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003945 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003946#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003947 { \
3948 .freq_hz = f, \
3949 .src_clk = &s##_clk, \
3950 .md_val = MD8(8, m, 0, n), \
3951 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3952 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003953 .extra_freq_data = (void *)p_r, \
3954 }
3955/* Switching TV freqs requires PLL reconfiguration. */
3956static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003957 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3958 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3959 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3960 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3961 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3962 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003963 F_END
3964};
3965
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003966static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
3967 [VDD_DIG_LOW] = 74250000,
3968 [VDD_DIG_NOMINAL] = 149000000
3969};
3970
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003971/*
3972 * Unlike other clocks, the TV rate is adjusted through PLL
3973 * re-programming. It is also routed through an MND divider.
3974 */
Matt Wagantallf82f2942012-01-27 13:56:13 -08003975void set_rate_tv(struct rcg_clk *rcg, struct clk_freq_tbl *nf)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003976{
3977 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3978 if (pll_rate)
3979 hdmi_pll_set_rate(pll_rate);
Matt Wagantallf82f2942012-01-27 13:56:13 -08003980 set_rate_mnd(rcg, nf);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003981}
3982
3983static struct rcg_clk tv_src_clk = {
3984 .ns_reg = TV_NS_REG,
3985 .b = {
3986 .ctl_reg = TV_CC_REG,
3987 .halt_check = NOCHECK,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003988 .retain_reg = TV_CC_REG,
3989 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003990 },
3991 .md_reg = TV_MD_REG,
3992 .root_en_mask = BIT(2),
3993 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003994 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003995 .ctl_mask = BM(7, 6),
3996 .set_rate = set_rate_tv,
3997 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003998 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003999 .c = {
4000 .dbg_name = "tv_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004001 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004002 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004003 CLK_INIT(tv_src_clk.c),
4004 },
4005};
4006
Tianyi Gou51918802012-01-26 14:05:43 -08004007static struct cdiv_clk tv_src_div_clk = {
4008 .b = {
4009 .ctl_reg = TV_NS_REG,
4010 .halt_check = NOCHECK,
4011 },
4012 .ns_reg = TV_NS_REG,
4013 .div_offset = 6,
4014 .max_div = 2,
4015 .c = {
4016 .dbg_name = "tv_src_div_clk",
4017 .ops = &clk_ops_cdiv,
4018 CLK_INIT(tv_src_div_clk.c),
Stephen Boydd51d5e82012-06-18 18:09:50 -07004019 .rate = ULONG_MAX,
Tianyi Gou51918802012-01-26 14:05:43 -08004020 },
4021};
4022
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004023static struct branch_clk tv_enc_clk = {
4024 .b = {
4025 .ctl_reg = TV_CC_REG,
4026 .en_mask = BIT(8),
4027 .reset_reg = SW_RESET_CORE_REG,
4028 .reset_mask = BIT(0),
4029 .halt_reg = DBG_BUS_VEC_D_REG,
4030 .halt_bit = 9,
4031 },
4032 .parent = &tv_src_clk.c,
4033 .c = {
4034 .dbg_name = "tv_enc_clk",
4035 .ops = &clk_ops_branch,
4036 CLK_INIT(tv_enc_clk.c),
4037 },
4038};
4039
4040static struct branch_clk tv_dac_clk = {
4041 .b = {
4042 .ctl_reg = TV_CC_REG,
4043 .en_mask = BIT(10),
4044 .halt_reg = DBG_BUS_VEC_D_REG,
4045 .halt_bit = 10,
4046 },
4047 .parent = &tv_src_clk.c,
4048 .c = {
4049 .dbg_name = "tv_dac_clk",
4050 .ops = &clk_ops_branch,
4051 CLK_INIT(tv_dac_clk.c),
4052 },
4053};
4054
4055static struct branch_clk mdp_tv_clk = {
4056 .b = {
4057 .ctl_reg = TV_CC_REG,
4058 .en_mask = BIT(0),
4059 .reset_reg = SW_RESET_CORE_REG,
4060 .reset_mask = BIT(4),
4061 .halt_reg = DBG_BUS_VEC_D_REG,
4062 .halt_bit = 12,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004063 .retain_reg = TV_CC2_REG,
4064 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004065 },
4066 .parent = &tv_src_clk.c,
4067 .c = {
4068 .dbg_name = "mdp_tv_clk",
4069 .ops = &clk_ops_branch,
4070 CLK_INIT(mdp_tv_clk.c),
4071 },
4072};
4073
4074static struct branch_clk hdmi_tv_clk = {
4075 .b = {
4076 .ctl_reg = TV_CC_REG,
4077 .en_mask = BIT(12),
4078 .reset_reg = SW_RESET_CORE_REG,
4079 .reset_mask = BIT(1),
4080 .halt_reg = DBG_BUS_VEC_D_REG,
4081 .halt_bit = 11,
4082 },
4083 .parent = &tv_src_clk.c,
4084 .c = {
4085 .dbg_name = "hdmi_tv_clk",
4086 .ops = &clk_ops_branch,
4087 CLK_INIT(hdmi_tv_clk.c),
4088 },
4089};
4090
Tianyi Gou51918802012-01-26 14:05:43 -08004091static struct branch_clk rgb_tv_clk = {
4092 .b = {
4093 .ctl_reg = TV_CC2_REG,
4094 .en_mask = BIT(14),
4095 .halt_reg = DBG_BUS_VEC_J_REG,
4096 .halt_bit = 27,
4097 },
4098 .parent = &tv_src_clk.c,
4099 .c = {
4100 .dbg_name = "rgb_tv_clk",
4101 .ops = &clk_ops_branch,
4102 CLK_INIT(rgb_tv_clk.c),
4103 },
4104};
4105
4106static struct branch_clk npl_tv_clk = {
4107 .b = {
4108 .ctl_reg = TV_CC2_REG,
4109 .en_mask = BIT(16),
4110 .halt_reg = DBG_BUS_VEC_J_REG,
4111 .halt_bit = 26,
4112 },
4113 .parent = &tv_src_clk.c,
4114 .c = {
4115 .dbg_name = "npl_tv_clk",
4116 .ops = &clk_ops_branch,
4117 CLK_INIT(npl_tv_clk.c),
4118 },
4119};
4120
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004121static struct branch_clk hdmi_app_clk = {
4122 .b = {
4123 .ctl_reg = MISC_CC2_REG,
4124 .en_mask = BIT(11),
4125 .reset_reg = SW_RESET_CORE_REG,
4126 .reset_mask = BIT(11),
4127 .halt_reg = DBG_BUS_VEC_B_REG,
4128 .halt_bit = 25,
4129 },
4130 .c = {
4131 .dbg_name = "hdmi_app_clk",
4132 .ops = &clk_ops_branch,
4133 CLK_INIT(hdmi_app_clk.c),
4134 },
4135};
4136
4137static struct bank_masks bmnd_info_vcodec = {
4138 .bank_sel_mask = BIT(13),
4139 .bank0_mask = {
4140 .md_reg = VCODEC_MD0_REG,
4141 .ns_mask = BM(18, 11) | BM(2, 0),
4142 .rst_mask = BIT(31),
4143 .mnd_en_mask = BIT(5),
4144 .mode_mask = BM(7, 6),
4145 },
4146 .bank1_mask = {
4147 .md_reg = VCODEC_MD1_REG,
4148 .ns_mask = BM(26, 19) | BM(29, 27),
4149 .rst_mask = BIT(30),
4150 .mnd_en_mask = BIT(10),
4151 .mode_mask = BM(12, 11),
4152 },
4153};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004154#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004155 { \
4156 .freq_hz = f, \
4157 .src_clk = &s##_clk.c, \
4158 .md_val = MD8(8, m, 0, n), \
4159 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4160 .ctl_val = CC_BANKED(6, 11, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004161 }
4162static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004163 F_VCODEC( 0, gnd, 0, 0),
4164 F_VCODEC( 27000000, pxo, 0, 0),
4165 F_VCODEC( 32000000, pll8, 1, 12),
4166 F_VCODEC( 48000000, pll8, 1, 8),
4167 F_VCODEC( 54860000, pll8, 1, 7),
4168 F_VCODEC( 96000000, pll8, 1, 4),
4169 F_VCODEC(133330000, pll2, 1, 6),
4170 F_VCODEC(200000000, pll2, 1, 4),
4171 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004172 F_END
4173};
4174
4175static struct rcg_clk vcodec_clk = {
4176 .b = {
4177 .ctl_reg = VCODEC_CC_REG,
4178 .en_mask = BIT(0),
4179 .reset_reg = SW_RESET_CORE_REG,
4180 .reset_mask = BIT(6),
4181 .halt_reg = DBG_BUS_VEC_C_REG,
4182 .halt_bit = 29,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004183 .retain_reg = VCODEC_CC_REG,
4184 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004185 },
4186 .ns_reg = VCODEC_NS_REG,
4187 .root_en_mask = BIT(2),
4188 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004189 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004190 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004191 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004192 .c = {
4193 .dbg_name = "vcodec_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004194 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004195 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4196 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004197 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004198 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004199 },
4200};
4201
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004202#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004203 { \
4204 .freq_hz = f, \
4205 .src_clk = &s##_clk.c, \
4206 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004207 }
4208static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004209 F_VPE( 0, gnd, 1),
4210 F_VPE( 27000000, pxo, 1),
4211 F_VPE( 34909000, pll8, 11),
4212 F_VPE( 38400000, pll8, 10),
4213 F_VPE( 64000000, pll8, 6),
4214 F_VPE( 76800000, pll8, 5),
4215 F_VPE( 96000000, pll8, 4),
4216 F_VPE(100000000, pll2, 8),
4217 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004218 F_END
4219};
4220
4221static struct rcg_clk vpe_clk = {
4222 .b = {
4223 .ctl_reg = VPE_CC_REG,
4224 .en_mask = BIT(0),
4225 .reset_reg = SW_RESET_CORE_REG,
4226 .reset_mask = BIT(17),
4227 .halt_reg = DBG_BUS_VEC_A_REG,
4228 .halt_bit = 28,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004229 .retain_reg = VPE_CC_REG,
4230 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004231 },
4232 .ns_reg = VPE_NS_REG,
4233 .root_en_mask = BIT(2),
4234 .ns_mask = (BM(15, 12) | BM(2, 0)),
4235 .set_rate = set_rate_nop,
4236 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004237 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004238 .c = {
4239 .dbg_name = "vpe_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004240 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004241 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004242 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004243 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004244 },
4245};
4246
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004247#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004248 { \
4249 .freq_hz = f, \
4250 .src_clk = &s##_clk.c, \
4251 .md_val = MD8(8, m, 0, n), \
4252 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4253 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004254 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004255
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004256static struct clk_freq_tbl clk_tbl_vfe[] = {
4257 F_VFE( 0, gnd, 1, 0, 0),
4258 F_VFE( 13960000, pll8, 1, 2, 55),
4259 F_VFE( 27000000, pxo, 1, 0, 0),
4260 F_VFE( 36570000, pll8, 1, 2, 21),
4261 F_VFE( 38400000, pll8, 2, 1, 5),
4262 F_VFE( 45180000, pll8, 1, 2, 17),
4263 F_VFE( 48000000, pll8, 2, 1, 4),
4264 F_VFE( 54860000, pll8, 1, 1, 7),
4265 F_VFE( 64000000, pll8, 2, 1, 3),
4266 F_VFE( 76800000, pll8, 1, 1, 5),
4267 F_VFE( 96000000, pll8, 2, 1, 2),
4268 F_VFE(109710000, pll8, 1, 2, 7),
4269 F_VFE(128000000, pll8, 1, 1, 3),
4270 F_VFE(153600000, pll8, 1, 2, 5),
4271 F_VFE(200000000, pll2, 2, 1, 2),
4272 F_VFE(228570000, pll2, 1, 2, 7),
4273 F_VFE(266667000, pll2, 1, 1, 3),
4274 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004275 F_END
4276};
4277
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004278static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4279 [VDD_DIG_LOW] = 128000000,
4280 [VDD_DIG_NOMINAL] = 266667000,
4281 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004282};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004283
4284static struct rcg_clk vfe_clk = {
4285 .b = {
4286 .ctl_reg = VFE_CC_REG,
4287 .reset_reg = SW_RESET_CORE_REG,
4288 .reset_mask = BIT(15),
4289 .halt_reg = DBG_BUS_VEC_B_REG,
4290 .halt_bit = 6,
4291 .en_mask = BIT(0),
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004292 .retain_reg = VFE_CC2_REG,
4293 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004294 },
4295 .ns_reg = VFE_NS_REG,
4296 .md_reg = VFE_MD_REG,
4297 .root_en_mask = BIT(2),
4298 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004299 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004300 .ctl_mask = BM(7, 6),
4301 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004302 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004303 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004304 .c = {
4305 .dbg_name = "vfe_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004306 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08004307 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
4308 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004309 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004310 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004311 },
4312};
4313
Matt Wagantallc23eee92011-08-16 23:06:52 -07004314static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004315 .b = {
4316 .ctl_reg = VFE_CC_REG,
4317 .en_mask = BIT(12),
4318 .reset_reg = SW_RESET_CORE_REG,
4319 .reset_mask = BIT(24),
4320 .halt_reg = DBG_BUS_VEC_B_REG,
4321 .halt_bit = 8,
4322 },
4323 .parent = &vfe_clk.c,
4324 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004325 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004326 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004327 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004328 },
4329};
4330
4331/*
4332 * Low Power Audio Clocks
4333 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004334#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004335 { \
4336 .freq_hz = f, \
4337 .src_clk = &s##_clk.c, \
4338 .md_val = MD8(8, m, 0, n), \
4339 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004340 }
4341static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004342 F_AIF_OSR( 0, gnd, 1, 0, 0),
4343 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4344 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4345 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4346 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4347 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4348 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4349 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4350 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4351 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4352 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4353 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004354 F_END
4355};
4356
4357#define CLK_AIF_OSR(i, ns, md, h_r) \
4358 struct rcg_clk i##_clk = { \
4359 .b = { \
4360 .ctl_reg = ns, \
4361 .en_mask = BIT(17), \
4362 .reset_reg = ns, \
4363 .reset_mask = BIT(19), \
4364 .halt_reg = h_r, \
4365 .halt_check = ENABLE, \
4366 .halt_bit = 1, \
4367 }, \
4368 .ns_reg = ns, \
4369 .md_reg = md, \
4370 .root_en_mask = BIT(9), \
4371 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004372 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004373 .set_rate = set_rate_mnd, \
4374 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004375 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004376 .c = { \
4377 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07004378 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004379 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004380 CLK_INIT(i##_clk.c), \
4381 }, \
4382 }
4383#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4384 struct rcg_clk i##_clk = { \
4385 .b = { \
4386 .ctl_reg = ns, \
4387 .en_mask = BIT(21), \
4388 .reset_reg = ns, \
4389 .reset_mask = BIT(23), \
4390 .halt_reg = h_r, \
4391 .halt_check = ENABLE, \
4392 .halt_bit = 1, \
4393 }, \
4394 .ns_reg = ns, \
4395 .md_reg = md, \
4396 .root_en_mask = BIT(9), \
4397 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004398 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004399 .set_rate = set_rate_mnd, \
4400 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004401 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004402 .c = { \
4403 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07004404 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004405 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004406 CLK_INIT(i##_clk.c), \
4407 }, \
4408 }
4409
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004410#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004411 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004412 .b = { \
4413 .ctl_reg = ns, \
4414 .en_mask = BIT(15), \
4415 .halt_reg = h_r, \
4416 .halt_check = DELAY, \
4417 }, \
4418 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004419 .ext_mask = BIT(14), \
4420 .div_offset = 10, \
4421 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004422 .c = { \
4423 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004424 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004425 CLK_INIT(i##_clk.c), \
Stephen Boydd51d5e82012-06-18 18:09:50 -07004426 .rate = ULONG_MAX, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004427 }, \
4428 }
4429
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004430#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004431 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004432 .b = { \
4433 .ctl_reg = ns, \
4434 .en_mask = BIT(19), \
4435 .halt_reg = h_r, \
Stephen Boyd7bb9cf82012-01-25 18:09:01 -08004436 .halt_check = DELAY, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004437 }, \
4438 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004439 .ext_mask = BIT(18), \
4440 .div_offset = 10, \
4441 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004442 .c = { \
4443 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004444 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004445 CLK_INIT(i##_clk.c), \
Stephen Boydd51d5e82012-06-18 18:09:50 -07004446 .rate = ULONG_MAX, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004447 }, \
4448 }
4449
4450static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4451 LCC_MI2S_STATUS_REG);
4452static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4453
4454static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4455 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4456static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4457 LCC_CODEC_I2S_MIC_STATUS_REG);
4458
4459static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4460 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4461static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4462 LCC_SPARE_I2S_MIC_STATUS_REG);
4463
4464static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4465 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4466static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4467 LCC_CODEC_I2S_SPKR_STATUS_REG);
4468
4469static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4470 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4471static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4472 LCC_SPARE_I2S_SPKR_STATUS_REG);
4473
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004474#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004475 { \
4476 .freq_hz = f, \
4477 .src_clk = &s##_clk.c, \
4478 .md_val = MD16(m, n), \
4479 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004480 }
4481static struct clk_freq_tbl clk_tbl_pcm[] = {
Stephen Boyd630f3252012-01-31 00:10:08 -08004482 { .ns_val = BIT(10) /* external input */ },
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004483 F_PCM( 512000, pll4, 4, 1, 192),
4484 F_PCM( 768000, pll4, 4, 1, 128),
4485 F_PCM( 1024000, pll4, 4, 1, 96),
4486 F_PCM( 1536000, pll4, 4, 1, 64),
4487 F_PCM( 2048000, pll4, 4, 1, 48),
4488 F_PCM( 3072000, pll4, 4, 1, 32),
4489 F_PCM( 4096000, pll4, 4, 1, 24),
4490 F_PCM( 6144000, pll4, 4, 1, 16),
4491 F_PCM( 8192000, pll4, 4, 1, 12),
4492 F_PCM(12288000, pll4, 4, 1, 8),
4493 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004494 F_END
4495};
4496
4497static struct rcg_clk pcm_clk = {
4498 .b = {
4499 .ctl_reg = LCC_PCM_NS_REG,
4500 .en_mask = BIT(11),
4501 .reset_reg = LCC_PCM_NS_REG,
4502 .reset_mask = BIT(13),
4503 .halt_reg = LCC_PCM_STATUS_REG,
4504 .halt_check = ENABLE,
4505 .halt_bit = 0,
4506 },
4507 .ns_reg = LCC_PCM_NS_REG,
4508 .md_reg = LCC_PCM_MD_REG,
4509 .root_en_mask = BIT(9),
Stephen Boyd630f3252012-01-31 00:10:08 -08004510 .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08004511 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004512 .set_rate = set_rate_mnd,
4513 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004514 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004515 .c = {
4516 .dbg_name = "pcm_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004517 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004518 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004519 CLK_INIT(pcm_clk.c),
Stephen Boydc5492fc2012-06-18 18:47:03 -07004520 .rate = ULONG_MAX,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004521 },
4522};
4523
4524static struct rcg_clk audio_slimbus_clk = {
4525 .b = {
4526 .ctl_reg = LCC_SLIMBUS_NS_REG,
4527 .en_mask = BIT(10),
4528 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4529 .reset_mask = BIT(5),
4530 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4531 .halt_check = ENABLE,
4532 .halt_bit = 0,
4533 },
4534 .ns_reg = LCC_SLIMBUS_NS_REG,
4535 .md_reg = LCC_SLIMBUS_MD_REG,
4536 .root_en_mask = BIT(9),
4537 .ns_mask = (BM(31, 24) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004538 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004539 .set_rate = set_rate_mnd,
4540 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004541 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004542 .c = {
4543 .dbg_name = "audio_slimbus_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004544 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004545 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004546 CLK_INIT(audio_slimbus_clk.c),
4547 },
4548};
4549
4550static struct branch_clk sps_slimbus_clk = {
4551 .b = {
4552 .ctl_reg = LCC_SLIMBUS_NS_REG,
4553 .en_mask = BIT(12),
4554 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4555 .halt_check = ENABLE,
4556 .halt_bit = 1,
4557 },
4558 .parent = &audio_slimbus_clk.c,
4559 .c = {
4560 .dbg_name = "sps_slimbus_clk",
4561 .ops = &clk_ops_branch,
4562 CLK_INIT(sps_slimbus_clk.c),
4563 },
4564};
4565
4566static struct branch_clk slimbus_xo_src_clk = {
4567 .b = {
4568 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4569 .en_mask = BIT(2),
4570 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004571 .halt_bit = 28,
4572 },
4573 .parent = &sps_slimbus_clk.c,
4574 .c = {
4575 .dbg_name = "slimbus_xo_src_clk",
4576 .ops = &clk_ops_branch,
4577 CLK_INIT(slimbus_xo_src_clk.c),
4578 },
4579};
4580
Matt Wagantall735f01a2011-08-12 12:40:28 -07004581DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4582DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4583DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4584DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4585DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4586DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4587DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4588DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Stephen Boydc7fc3b12012-05-17 14:42:46 -07004589DEFINE_CLK_RPM_QDSS(qdss_clk, qdss_a_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004590
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004591static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c, 0);
4592static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c, 0);
Stephen Boydd7a143a2012-02-16 17:59:26 -08004593
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004594static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c, 0);
4595static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c, 0);
4596static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c, 0);
4597static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c, 0);
4598static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c, 0);
4599static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c, 0);
4600static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c, 0);
4601static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c, 0);
4602static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c, 0);
4603static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c, 0);
4604static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c, 0);
4605static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c, 0);
4606static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c, 0);
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004607static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c, 0);
4608static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004609
Matt Wagantall42cd12a2012-03-30 18:02:40 -07004610static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c, LONG_MAX);
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004611static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004612
Matt Wagantall33bac7e2012-05-22 14:59:05 -07004613static DEFINE_CLK_VOTER(ebi1_acpu_a_clk, &ebi1_a_clk.c, LONG_MAX);
4614static DEFINE_CLK_VOTER(ebi1_msmbus_a_clk, &ebi1_a_clk.c, LONG_MAX);
4615static DEFINE_CLK_VOTER(afab_acpu_a_clk, &afab_a_clk.c, LONG_MAX);
4616static DEFINE_CLK_VOTER(afab_msmbus_a_clk, &afab_a_clk.c, LONG_MAX);
4617
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004618#ifdef CONFIG_DEBUG_FS
4619struct measure_sel {
4620 u32 test_vector;
Matt Wagantallf82f2942012-01-27 13:56:13 -08004621 struct clk *c;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004622};
4623
Matt Wagantall8b38f942011-08-02 18:23:18 -07004624static DEFINE_CLK_MEASURE(l2_m_clk);
4625static DEFINE_CLK_MEASURE(krait0_m_clk);
4626static DEFINE_CLK_MEASURE(krait1_m_clk);
Tianyi Gou455c13c2012-02-02 16:33:24 -08004627static DEFINE_CLK_MEASURE(krait2_m_clk);
4628static DEFINE_CLK_MEASURE(krait3_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004629static DEFINE_CLK_MEASURE(q6sw_clk);
4630static DEFINE_CLK_MEASURE(q6fw_clk);
4631static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004632
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004633static struct measure_sel measure_mux[] = {
4634 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4635 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4636 { TEST_PER_LS(0x13), &sdc1_clk.c },
4637 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4638 { TEST_PER_LS(0x15), &sdc2_clk.c },
4639 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4640 { TEST_PER_LS(0x17), &sdc3_clk.c },
4641 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4642 { TEST_PER_LS(0x19), &sdc4_clk.c },
4643 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4644 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004645 { TEST_PER_LS(0x1F), &gp0_clk.c },
4646 { TEST_PER_LS(0x20), &gp1_clk.c },
4647 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004648 { TEST_PER_LS(0x25), &dfab_clk.c },
4649 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4650 { TEST_PER_LS(0x26), &pmem_clk.c },
4651 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4652 { TEST_PER_LS(0x33), &cfpb_clk.c },
4653 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4654 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4655 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4656 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4657 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4658 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4659 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4660 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4661 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4662 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4663 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4664 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4665 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4666 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4667 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4668 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4669 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4670 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4671 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4672 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4673 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4674 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4675 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
Tianyi Gou352955d2012-05-18 19:44:01 -07004676 { TEST_PER_LS(0x59), &sfab_sata_s_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004677 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
Tianyi Gou352955d2012-05-18 19:44:01 -07004678 { TEST_PER_LS(0x5A), &sata_p_clk.c },
4679 { TEST_PER_LS(0x5B), &sata_rxoob_clk.c },
4680 { TEST_PER_LS(0x5C), &sata_pmalive_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004681 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4682 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4683 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4684 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4685 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4686 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4687 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4688 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4689 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4690 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4691 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4692 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4693 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004694 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4695 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4696 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4697 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4698 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4699 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4700 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4701 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4702 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004703 { TEST_PER_LS(0x78), &sfpb_clk.c },
4704 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4705 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4706 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4707 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4708 { TEST_PER_LS(0x7D), &prng_clk.c },
4709 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4710 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4711 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4712 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004713 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4714 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4715 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004716 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4717 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4718 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4719 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4720 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4721 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4722 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4723 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4724 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4725 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004726 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004727 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4728
4729 { TEST_PER_HS(0x07), &afab_clk.c },
4730 { TEST_PER_HS(0x07), &afab_a_clk.c },
4731 { TEST_PER_HS(0x18), &sfab_clk.c },
4732 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004733 { TEST_PER_HS(0x26), &q6sw_clk },
4734 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004735 { TEST_PER_HS(0x2A), &adm0_clk.c },
Tianyi Gou352955d2012-05-18 19:44:01 -07004736 { TEST_PER_HS(0x31), &sata_a_clk.c },
Tianyi Gou6613de52012-01-27 17:57:53 -08004737 { TEST_PER_HS(0x2D), &pcie_phy_ref_clk.c },
4738 { TEST_PER_HS(0x32), &pcie_a_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004739 { TEST_PER_HS(0x34), &ebi1_clk.c },
4740 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004741 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004742
4743 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4744 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4745 { TEST_MM_LS(0x02), &cam1_clk.c },
4746 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004747 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004748 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4749 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4750 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4751 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4752 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4753 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4754 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4755 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4756 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4757 { TEST_MM_LS(0x12), &imem_p_clk.c },
4758 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4759 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4760 { TEST_MM_LS(0x16), &rot_p_clk.c },
4761 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4762 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4763 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4764 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4765 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4766 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4767 { TEST_MM_LS(0x1D), &cam0_clk.c },
4768 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4769 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4770 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4771 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4772 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4773 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4774 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4775 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004776 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004777 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004778
4779 { TEST_MM_HS(0x00), &csi0_clk.c },
4780 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004781 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004782 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4783 { TEST_MM_HS(0x06), &vfe_clk.c },
4784 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4785 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4786 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4787 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4788 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4789 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4790 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4791 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4792 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4793 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4794 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4795 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4796 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4797 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4798 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4799 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4800 { TEST_MM_HS(0x1A), &mdp_clk.c },
4801 { TEST_MM_HS(0x1B), &rot_clk.c },
4802 { TEST_MM_HS(0x1C), &vpe_clk.c },
4803 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4804 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4805 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4806 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4807 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4808 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4809 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4810 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4811 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4812 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4813 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004814 { TEST_MM_HS(0x2D), &csi2_clk.c },
4815 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4816 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4817 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4818 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4819 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004820 { TEST_MM_HS(0x33), &vcap_clk.c },
4821 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004822 { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004823 { TEST_MM_HS(0x35), &vcap_axi_clk.c },
Tianyi Gou51918802012-01-26 14:05:43 -08004824 { TEST_MM_HS(0x36), &rgb_tv_clk.c },
4825 { TEST_MM_HS(0x37), &npl_tv_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004826 { TEST_MM_HS(0x38), &gfx3d_axi_clk_8064.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004827
4828 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4829 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4830 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4831 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4832 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4833 { TEST_LPA(0x14), &pcm_clk.c },
4834 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004835
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004836 { TEST_LPA_HS(0x00), &q6_func_clk },
4837
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004838 { TEST_CPUL2(0x2), &l2_m_clk },
4839 { TEST_CPUL2(0x0), &krait0_m_clk },
4840 { TEST_CPUL2(0x1), &krait1_m_clk },
Tianyi Gou455c13c2012-02-02 16:33:24 -08004841 { TEST_CPUL2(0x4), &krait2_m_clk },
4842 { TEST_CPUL2(0x5), &krait3_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004843};
4844
Matt Wagantallf82f2942012-01-27 13:56:13 -08004845static struct measure_sel *find_measure_sel(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004846{
4847 int i;
4848
4849 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
Matt Wagantallf82f2942012-01-27 13:56:13 -08004850 if (measure_mux[i].c == c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004851 return &measure_mux[i];
4852 return NULL;
4853}
4854
Matt Wagantall8b38f942011-08-02 18:23:18 -07004855static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004856{
4857 int ret = 0;
4858 u32 clk_sel;
4859 struct measure_sel *p;
Matt Wagantallf82f2942012-01-27 13:56:13 -08004860 struct measure_clk *measure = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004861 unsigned long flags;
4862
4863 if (!parent)
4864 return -EINVAL;
4865
4866 p = find_measure_sel(parent);
4867 if (!p)
4868 return -EINVAL;
4869
4870 spin_lock_irqsave(&local_clock_reg_lock, flags);
4871
Matt Wagantall8b38f942011-08-02 18:23:18 -07004872 /*
4873 * Program the test vector, measurement period (sample_ticks)
4874 * and scaling multiplier.
4875 */
Matt Wagantallf82f2942012-01-27 13:56:13 -08004876 measure->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004877 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantallf82f2942012-01-27 13:56:13 -08004878 measure->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004879 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4880 case TEST_TYPE_PER_LS:
4881 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4882 break;
4883 case TEST_TYPE_PER_HS:
4884 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4885 break;
4886 case TEST_TYPE_MM_LS:
4887 writel_relaxed(0x4030D97, CLK_TEST_REG);
4888 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4889 break;
4890 case TEST_TYPE_MM_HS:
4891 writel_relaxed(0x402B800, CLK_TEST_REG);
4892 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4893 break;
4894 case TEST_TYPE_LPA:
4895 writel_relaxed(0x4030D98, CLK_TEST_REG);
4896 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4897 LCC_CLK_LS_DEBUG_CFG_REG);
4898 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004899 case TEST_TYPE_LPA_HS:
4900 writel_relaxed(0x402BC00, CLK_TEST_REG);
4901 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4902 LCC_CLK_HS_DEBUG_CFG_REG);
4903 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004904 case TEST_TYPE_CPUL2:
4905 writel_relaxed(0x4030400, CLK_TEST_REG);
4906 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
Matt Wagantallf82f2942012-01-27 13:56:13 -08004907 measure->sample_ticks = 0x4000;
4908 measure->multiplier = 2;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004909 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004910 default:
4911 ret = -EPERM;
4912 }
4913 /* Make sure test vector is set before starting measurements. */
4914 mb();
4915
4916 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4917
4918 return ret;
4919}
4920
4921/* Sample clock for 'ticks' reference clock ticks. */
4922static u32 run_measurement(unsigned ticks)
4923{
4924 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004925 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4926
4927 /* Wait for timer to become ready. */
4928 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4929 cpu_relax();
4930
4931 /* Run measurement and wait for completion. */
4932 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4933 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4934 cpu_relax();
4935
4936 /* Stop counters. */
4937 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4938
4939 /* Return measured ticks. */
4940 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4941}
4942
4943
4944/* Perform a hardware rate measurement for a given clock.
4945 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004946static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004947{
4948 unsigned long flags;
4949 u32 pdm_reg_backup, ringosc_reg_backup;
4950 u64 raw_count_short, raw_count_full;
Matt Wagantallf82f2942012-01-27 13:56:13 -08004951 struct measure_clk *measure = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004952 unsigned ret;
4953
Stephen Boyde334aeb2012-01-24 12:17:29 -08004954 ret = clk_prepare_enable(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004955 if (ret) {
4956 pr_warning("CXO clock failed to enable. Can't measure\n");
4957 return 0;
4958 }
4959
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004960 spin_lock_irqsave(&local_clock_reg_lock, flags);
4961
4962 /* Enable CXO/4 and RINGOSC branch and root. */
4963 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4964 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4965 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4966 writel_relaxed(0xA00, RINGOSC_NS_REG);
4967
4968 /*
4969 * The ring oscillator counter will not reset if the measured clock
4970 * is not running. To detect this, run a short measurement before
4971 * the full measurement. If the raw results of the two are the same
4972 * then the clock must be off.
4973 */
4974
4975 /* Run a short measurement. (~1 ms) */
4976 raw_count_short = run_measurement(0x1000);
4977 /* Run a full measurement. (~14 ms) */
Matt Wagantallf82f2942012-01-27 13:56:13 -08004978 raw_count_full = run_measurement(measure->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004979
4980 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4981 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4982
4983 /* Return 0 if the clock is off. */
4984 if (raw_count_full == raw_count_short)
4985 ret = 0;
4986 else {
4987 /* Compute rate in Hz. */
4988 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantallf82f2942012-01-27 13:56:13 -08004989 do_div(raw_count_full, ((measure->sample_ticks * 10) + 35));
4990 ret = (raw_count_full * measure->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004991 }
4992
4993 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004994 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004995 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4996
Stephen Boyde334aeb2012-01-24 12:17:29 -08004997 clk_disable_unprepare(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004998
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004999 return ret;
5000}
5001#else /* !CONFIG_DEBUG_FS */
Matt Wagantallf82f2942012-01-27 13:56:13 -08005002static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005003{
5004 return -EINVAL;
5005}
5006
Matt Wagantallf82f2942012-01-27 13:56:13 -08005007static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005008{
5009 return 0;
5010}
5011#endif /* CONFIG_DEBUG_FS */
5012
Matt Wagantallae053222012-05-14 19:42:07 -07005013static struct clk_ops clk_ops_measure = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005014 .set_parent = measure_clk_set_parent,
5015 .get_rate = measure_clk_get_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005016};
5017
Matt Wagantall8b38f942011-08-02 18:23:18 -07005018static struct measure_clk measure_clk = {
5019 .c = {
5020 .dbg_name = "measure_clk",
Matt Wagantallae053222012-05-14 19:42:07 -07005021 .ops = &clk_ops_measure,
Matt Wagantall8b38f942011-08-02 18:23:18 -07005022 CLK_INIT(measure_clk.c),
5023 },
5024 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005025};
5026
Tianyi Goua8b3cce2011-11-08 14:37:26 -08005027static struct clk_lookup msm_clocks_8064[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005028 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5029 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Mohan Pallaka804ca592012-06-14 14:37:38 +05305030 CLK_LOOKUP("pwm_clk", cxo_clk.c, "0-0048"),
Stephen Boyded630b02012-01-26 15:26:47 -08005031 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5032 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5033 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5034 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5035 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Matt Wagantall292aace2012-01-26 19:12:34 -08005036 CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005037 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08005038 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Stephen Boyded630b02012-01-26 15:26:47 -08005039 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5040 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5041 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5042 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005043
Matt Wagantalld75f1312012-05-23 16:17:35 -07005044 CLK_LOOKUP("bus_clk", afab_clk.c, ""),
5045 CLK_LOOKUP("bus_clk", afab_a_clk.c, ""),
5046 CLK_LOOKUP("bus_clk", cfpb_clk.c, ""),
5047 CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""),
5048 CLK_LOOKUP("bus_clk", dfab_clk.c, ""),
5049 CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""),
5050 CLK_LOOKUP("mem_clk", ebi1_clk.c, ""),
5051 CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""),
5052 CLK_LOOKUP("bus_clk", mmfab_clk.c, ""),
5053 CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""),
5054 CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""),
5055 CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""),
5056 CLK_LOOKUP("bus_clk", sfab_clk.c, ""),
5057 CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""),
5058 CLK_LOOKUP("bus_clk", sfpb_clk.c, ""),
5059 CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""),
5060
Tianyi Gou21a0e802012-02-04 22:34:10 -08005061 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005062 CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005063 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5064 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5065 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005066 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005067 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5068 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5069 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5070 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5071 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005072 CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005073 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5074 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Pratik Patelf17b1472012-05-25 22:23:52 -07005075 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""),
5076 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etb.0"),
5077 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_tpiu.0"),
5078 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_funnel.0"),
5079 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_stm.0"),
5080 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etm.0"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005081
Tianyi Gou21a0e802012-02-04 22:34:10 -08005082 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005083 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""),
5084 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5085 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005086
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005087 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5088 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5089 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005090 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005091 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5092 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5093 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
5094 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""),
5095 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005096 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"),
David Keitel3c40fc52012-02-09 17:53:52 -08005097 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005098 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08005099 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08005100 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08005101 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"),
Joel King8f839b92012-04-01 14:37:46 -07005102 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.5"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005103 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5104 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5105 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08005106 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Tianyi Gou05e01102012-02-08 22:15:49 -08005107 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Tianyi Gou43208a02011-09-27 15:35:13 -07005108 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5109 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5110 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5111 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005112 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5113 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005114 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5115 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
5116 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005117 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5118 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5119 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005120 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""),
5121 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""),
Tianyi Gou352955d2012-05-18 19:44:01 -07005122 CLK_LOOKUP("src_clk", sata_src_clk.c, ""),
5123 CLK_LOOKUP("core_rxoob_clk", sata_rxoob_clk.c, ""),
5124 CLK_LOOKUP("core_pmalive_clk", sata_pmalive_clk.c, ""),
5125 CLK_LOOKUP("bus_clk", sata_a_clk.c, ""),
5126 CLK_LOOKUP("iface_clk", sata_p_clk.c, ""),
5127 CLK_LOOKUP("slave_iface_clk", sfab_sata_s_p_clk.c, ""),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07005128 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
5129 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
5130 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
5131 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
5132 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
5133 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005134 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005135 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"),
David Keitel3c40fc52012-02-09 17:53:52 -08005136 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005137 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08005138 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08005139 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08005140 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"),
Joel King8f839b92012-04-01 14:37:46 -07005141 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "qup_i2c.5"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005142 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005143 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"),
Joel Nider6d7d16c2012-05-30 18:02:42 +03005144 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tspp.0"),
5145 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tspp.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005146 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005147 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05305148 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
5149 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07005150 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5151 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5152 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5153 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06005154 CLK_LOOKUP("iface_clk", pcie_p_clk.c, "msm_pcie"),
5155 CLK_LOOKUP("ref_clk", pcie_phy_ref_clk.c, "msm_pcie"),
5156 CLK_LOOKUP("bus_clk", pcie_a_clk.c, "msm_pcie"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005157 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5158 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005159 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5160 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5161 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5162 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Kevin Chand07220e2012-02-13 15:52:22 -08005163 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005164 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Sreesudhan Ramakrish Ramkumar8002a792012-04-09 17:42:58 -07005165 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar6c6f57c2012-02-21 15:12:44 -08005166 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Kevin Chand07220e2012-02-13 15:52:22 -08005167 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
5168 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5169 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5170 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5171 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5172 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5173 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5174 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5175 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5176 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5177 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5178 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5179 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5180 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5181 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5182 CLK_LOOKUP("csiphy_timer_src_clk",
5183 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5184 CLK_LOOKUP("csiphy_timer_src_clk",
5185 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5186 CLK_LOOKUP("csiphy_timer_src_clk",
5187 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5188 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5189 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5190 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005191 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5192 CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"),
5193 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
5194 CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"),
Tianyi Gou51918802012-01-26 14:05:43 -08005195 CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""),
5196 CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""),
5197
Pu Chen86b4be92011-11-03 17:27:57 -07005198 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005199 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005200 CLK_LOOKUP("bus_clk",
5201 gfx3d_axi_clk_8064.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005202 CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005203 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005204 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
5205 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005206 CLK_LOOKUP("core_clk", vcap_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005207 CLK_LOOKUP("core_clk", vcap_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005208 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005209 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005210 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005211 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005212 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5213 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005214 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005215 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005216 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005217 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005218 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005219 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005220 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005221 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005222 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005223 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Matt Wagantall61286312012-02-22 15:55:09 -08005224 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005225 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5226 CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""),
Greg Griscofa47b532011-11-11 10:32:06 -08005227 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005228 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005229 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
Tianyi Gou51918802012-01-26 14:05:43 -08005230 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005231 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005232 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Ujwal Pateld041f982012-03-27 19:51:44 -07005233 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005234 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chand07220e2012-02-13 15:52:22 -08005235 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005236 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chand07220e2012-02-13 15:52:22 -08005237 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005238 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5239 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5240 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5241 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5242 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5243 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5244 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005245 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
5246 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"),
Kevin Chand07220e2012-02-13 15:52:22 -08005247 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5248 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5249 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005250 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5251 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
5252 CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"),
5253 CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"),
Pu Chen86b4be92011-11-03 17:27:57 -07005254 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005255 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005256 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5257 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005258 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005259 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005260 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005261 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005262 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005263 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005264 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005265 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005266 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005267 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005268 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chand07220e2012-02-13 15:52:22 -08005269 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005270 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chanb20742b2012-02-27 15:47:35 -08005271 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall61286312012-02-22 15:55:09 -08005272 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005273
Patrick Lai04baee942012-05-01 14:38:47 -07005274 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c,
5275 "msm-dai-q6-mi2s"),
5276 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c,
5277 "msm-dai-q6-mi2s"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005278 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5279 "msm-dai-q6.1"),
5280 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5281 "msm-dai-q6.1"),
5282 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5283 "msm-dai-q6.5"),
5284 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5285 "msm-dai-q6.5"),
5286 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5287 "msm-dai-q6.16384"),
5288 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5289 "msm-dai-q6.16384"),
5290 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5291 "msm-dai-q6.4"),
5292 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5293 "msm-dai-q6.4"),
5294 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005295 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005296 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005297 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005298 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""),
5299 CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""),
5300 CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""),
5301 CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""),
5302 CLK_LOOKUP("core_clk", rot_axi_clk.c, ""),
5303 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""),
5304 CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
5305 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
5306 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005307 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005308
5309 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5310 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5311 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"),
5312 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"),
5313 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5314 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5315 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5316 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5317 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5318 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5319 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005320 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005321
Manu Gautam5143b252012-01-05 19:25:23 -08005322 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5323 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5324 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5325 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5326 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005327
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005328 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5329 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5330 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5331 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5332 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5333 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5334 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5335 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5336 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005337 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.9"),
5338 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.10"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005339 CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
5340
Deepak Kotur954b1782012-04-24 17:58:19 -07005341 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5342 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5343 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5344 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5345 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005346 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5347 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
5348
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005349 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005350 CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
5351 CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005352
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005353 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5354 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5355 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
Tianyi Gou455c13c2012-02-02 16:33:24 -08005356 CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""),
5357 CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005358};
5359
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005360static struct clk_lookup msm_clocks_8960[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005361 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5362 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyded630b02012-01-26 15:26:47 -08005363 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5364 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5365 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5366 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5367 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005368 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08005369 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Stephen Boyded630b02012-01-26 15:26:47 -08005370 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5371 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5372 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5373 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005374
Matt Wagantalld75f1312012-05-23 16:17:35 -07005375 CLK_LOOKUP("bus_clk", afab_clk.c, ""),
5376 CLK_LOOKUP("bus_clk", afab_a_clk.c, ""),
5377 CLK_LOOKUP("bus_clk", cfpb_clk.c, ""),
5378 CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""),
5379 CLK_LOOKUP("bus_clk", dfab_clk.c, ""),
5380 CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""),
5381 CLK_LOOKUP("mem_clk", ebi1_clk.c, ""),
5382 CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""),
5383 CLK_LOOKUP("bus_clk", mmfab_clk.c, ""),
5384 CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""),
5385 CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""),
5386 CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""),
5387 CLK_LOOKUP("bus_clk", sfab_clk.c, ""),
5388 CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""),
5389 CLK_LOOKUP("bus_clk", sfpb_clk.c, ""),
5390 CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""),
5391
Matt Wagantallb2710b82011-11-16 19:55:17 -08005392 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005393 CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005394 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5395 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5396 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005397 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005398 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5399 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5400 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5401 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5402 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005403 CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005404 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5405 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Pratik Patelf17b1472012-05-25 22:23:52 -07005406 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""),
5407 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etb.0"),
5408 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_tpiu.0"),
5409 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_funnel.0"),
5410 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_stm.0"),
5411 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etm.0"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005412
5413 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005414 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5415 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5416 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005417
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005418 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5419 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5420 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5421 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5422 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5423 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5424 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
Matt Wagantalle2522372011-08-17 14:52:21 -07005425 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5426 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005427 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
Stepan Moskovchenko2b4b1cd2012-03-29 18:21:04 -07005428 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"),
Mayank Ranae009c922012-03-22 03:02:06 +05305429 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005430 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5431 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5432 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005433 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005434 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005435 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5436 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005437 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5438 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5439 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5440 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005441 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005442 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005443 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005444 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005445 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005446 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005447 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005448 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5449 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5450 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5451 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5452 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005453 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005454 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005455 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5456 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005457 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5458 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5459 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5460 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5461 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5462 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005463 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5464 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5465 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5466 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5467 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005468 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005469 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005470 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005471 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005472 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005473 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005474 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005475 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5476 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005477 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5478 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005479 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
Stepan Moskovchenko2b4b1cd2012-03-29 18:21:04 -07005480 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"),
Mayank Ranae009c922012-03-22 03:02:06 +05305481 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"),
Matt Wagantallac294852011-08-17 15:44:58 -07005482 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005483 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005484 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005485 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
Joel Nider6d7d16c2012-05-30 18:02:42 +03005486 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tspp.0"),
5487 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tspp.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005488 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5489 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005490 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005491 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5492 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5493 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5494 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5495 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005496 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5497 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005498 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5499 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5500 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5501 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Kevin Chan09f4e662011-12-16 08:17:02 -08005502 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5503 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5504 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005505 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -08005506 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005507 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005508 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5509 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005510 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005511 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5512 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005513 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005514 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5515 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005516 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
Kevin Chane12c6672011-10-26 11:55:26 -07005517 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5518 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005519 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5520 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5521 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5522 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5523 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5524 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5525 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Kevin Chanf6216f22011-10-25 18:40:11 -07005526 CLK_LOOKUP("csiphy_timer_src_clk",
5527 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5528 CLK_LOOKUP("csiphy_timer_src_clk",
5529 csiphy_timer_src_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005530 CLK_LOOKUP("csiphy_timer_src_clk",
5531 csiphy_timer_src_clk.c, "msm_csiphy.2"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005532 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5533 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005534 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005535 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5536 CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"),
5537 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
5538 CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005539 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005540 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005541 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005542 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005543 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005544 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5545 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005546 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5547 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005548 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Kalyani Oruganti465d1e12012-05-15 10:23:05 -07005549 CLK_LOOKUP("core_clk", jpegd_clk.c, "msm_mercury.0"),
5550 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, "msm_mercury.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005551 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005552 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005553 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005554 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005555 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005556 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005557 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005558 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005559 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5560 CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005561 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005562 CLK_LOOKUP("enc_clk", tv_enc_clk.c, "tvenc.0"),
5563 CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005564 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005565 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005566 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
5567 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005568 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005569 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005570 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005571 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005572 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005573 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005574 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005575 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005576 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5577 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5578 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5579 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5580 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5581 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5582 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005583 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
5584 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005585 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5586 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005587 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005588 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5589 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
5590 CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"),
5591 CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005592 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005593 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005594 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005595 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005596 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005597 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005598 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5599 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005600 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005601 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005602 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005603 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005604 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005605 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005606 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005607 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005608 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005609 CLK_LOOKUP("iface_clk", tv_enc_p_clk.c, "tvenc.0"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005610 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005611 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005612 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005613 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005614 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005615 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Patrick Lai04baee942012-05-01 14:38:47 -07005616 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c,
5617 "msm-dai-q6-mi2s"),
5618 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c,
5619 "msm-dai-q6-mi2s"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005620 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5621 "msm-dai-q6.1"),
5622 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5623 "msm-dai-q6.1"),
5624 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5625 "msm-dai-q6.5"),
5626 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5627 "msm-dai-q6.5"),
5628 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5629 "msm-dai-q6.16384"),
5630 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5631 "msm-dai-q6.16384"),
5632 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5633 "msm-dai-q6.4"),
5634 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5635 "msm-dai-q6.4"),
5636 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005637 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005638 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005639 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005640 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5641 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5642 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5643 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5644 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5645 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5646 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5647 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5648 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5649 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5650 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5651 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005652
5653 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5654 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5655 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5656 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5657 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005658 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5659 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005660
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005661 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005662 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005663 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5664 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5665 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5666 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5667 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005668 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005669 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005670 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005671 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005672
Matt Wagantalle1a86062011-08-18 17:46:10 -07005673 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005674 CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
5675 CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005676
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005677 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5678 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5679 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5680 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5681 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5682 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005683};
5684
Tianyi Goue3d4f542012-03-15 17:06:45 -07005685static struct clk_lookup msm_clocks_8930[] = {
Stephen Boydbe1a7392012-04-02 20:17:11 -07005686 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005687 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5688 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5689 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5690 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5691 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
5692 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
5693 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5694 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5695 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5696 CLK_LOOKUP("measure", measure_clk.c, "debug"),
5697
Matt Wagantalld75f1312012-05-23 16:17:35 -07005698 CLK_LOOKUP("bus_clk", afab_clk.c, ""),
5699 CLK_LOOKUP("bus_clk", afab_a_clk.c, ""),
5700 CLK_LOOKUP("bus_clk", cfpb_clk.c, ""),
5701 CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""),
5702 CLK_LOOKUP("bus_clk", dfab_clk.c, ""),
5703 CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""),
5704 CLK_LOOKUP("mem_clk", ebi1_clk.c, ""),
5705 CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""),
5706 CLK_LOOKUP("bus_clk", mmfab_clk.c, ""),
5707 CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""),
5708 CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""),
5709 CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""),
5710 CLK_LOOKUP("bus_clk", sfab_clk.c, ""),
5711 CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""),
5712 CLK_LOOKUP("bus_clk", sfpb_clk.c, ""),
5713 CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""),
5714
Tianyi Goue3d4f542012-03-15 17:06:45 -07005715 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005716 CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005717 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5718 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5719 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
5720 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
5721 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5722 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5723 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5724 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5725 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005726 CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005727 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5728 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Pratik Patelf17b1472012-05-25 22:23:52 -07005729 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""),
5730 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etb.0"),
5731 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_tpiu.0"),
5732 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_funnel.0"),
5733 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_stm.0"),
5734 CLK_LOOKUP("core_clk", qdss_clk.c, "msm_etm.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005735
5736 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005737 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5738 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5739 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
5740
5741 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5742 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5743 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5744 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5745 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5746 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5747 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
5748 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5749 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5750 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5751 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5752 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5753 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5754 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5755 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
5756 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
5757 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
5758 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5759 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
5760 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5761 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5762 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5763 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
5764 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
5765 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
5766 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
5767 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
5768 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
5769 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
5770 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
5771 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5772 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5773 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5774 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5775 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
5776 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5777 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
5778 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5779 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
5780 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5781 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5782 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5783 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5784 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5785 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
5786 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5787 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5788 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5789 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5790 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
5791 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
5792 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
5793 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
5794 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
5795 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
5796 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
5797 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
5798 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5799 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
5800 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5801 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
5802 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5803 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
5804 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
5805 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
5806 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
5807 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
5808 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5809 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5810 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
5811 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
5812 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5813 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5814 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5815 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5816 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
5817 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5818 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
5819 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5820 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5821 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5822 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005823 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Hody Hung994f4622012-04-24 10:27:45 -07005824 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
Sreesudhan Ramakrish Ramkumar981c82c2012-04-30 17:31:37 -07005825 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005826 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5827 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
5828 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5829 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5830 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5831 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5832 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5833 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5834 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5835 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5836 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5837 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5838 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5839 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5840 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5841 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5842 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5843 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5844 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5845 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
5846 CLK_LOOKUP("csiphy_timer_src_clk",
5847 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5848 CLK_LOOKUP("csiphy_timer_src_clk",
5849 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5850 CLK_LOOKUP("csiphy_timer_src_clk",
5851 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5852 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5853 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5854 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005855 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5856 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005857 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
5858 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5859 CLK_LOOKUP("bus_clk",
5860 gfx3d_axi_clk_8930.c, "footswitch-8x60.2"),
5861 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005862 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5863 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005864 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005865 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005866 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005867 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005868 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005869 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005870 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
5871 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
5872 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005873 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5874 CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005875 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005876 CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005877 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
5878 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005879 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
5880 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005881 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005882 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005883 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
5884 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
5885 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
5886 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
5887 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
5888 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
5889 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5890 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5891 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5892 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5893 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5894 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5895 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005896 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005897 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5898 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5899 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005900 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5901 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005902 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
5903 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
5904 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5905 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005906 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005907 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
5908 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005909 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005910 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
5911 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
5912 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
5913 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
5914 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
5915 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
5916 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
5917 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
5918 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
5919 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
5920 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5921 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5922 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5923 "msm-dai-q6.1"),
5924 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5925 "msm-dai-q6.1"),
5926 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5927 "msm-dai-q6.5"),
5928 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5929 "msm-dai-q6.5"),
5930 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5931 "msm-dai-q6.16384"),
5932 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5933 "msm-dai-q6.16384"),
5934 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5935 "msm-dai-q6.4"),
5936 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5937 "msm-dai-q6.4"),
5938 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
5939 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5940 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
5941 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5942 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5943 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5944 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5945 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5946 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5947 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5948 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5949 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"),
5950 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"),
5951
5952 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5953 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5954 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5955 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5956 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005957 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5958 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005959
5960 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5961 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5962 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5963 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5964 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5965 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5966 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
5967 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5968 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5969 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
5970 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
5971
5972 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005973 CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
5974 CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005975
5976 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5977 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5978 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5979 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5980 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5981 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
5982};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005983/*
5984 * Miscellaneous clock register initializations
5985 */
5986
5987/* Read, modify, then write-back a register. */
5988static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5989{
5990 uint32_t regval = readl_relaxed(reg);
5991 regval &= ~mask;
5992 regval |= val;
5993 writel_relaxed(regval, reg);
5994}
5995
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005996static struct pll_config_regs pll4_regs __initdata = {
5997 .l_reg = LCC_PLL0_L_VAL_REG,
5998 .m_reg = LCC_PLL0_M_VAL_REG,
5999 .n_reg = LCC_PLL0_N_VAL_REG,
6000 .config_reg = LCC_PLL0_CONFIG_REG,
6001 .mode_reg = LCC_PLL0_MODE_REG,
6002};
Tianyi Gou41515e22011-09-01 19:37:43 -07006003
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006004static struct pll_config pll4_config __initdata = {
6005 .l = 0xE,
6006 .m = 0x27A,
6007 .n = 0x465,
6008 .vco_val = 0x0,
6009 .vco_mask = BM(17, 16),
6010 .pre_div_val = 0x0,
6011 .pre_div_mask = BIT(19),
6012 .post_div_val = 0x0,
6013 .post_div_mask = BM(21, 20),
6014 .mn_ena_val = BIT(22),
6015 .mn_ena_mask = BIT(22),
6016 .main_output_val = BIT(23),
6017 .main_output_mask = BIT(23),
6018};
Tianyi Gou41515e22011-09-01 19:37:43 -07006019
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006020static struct pll_config_regs pll15_regs __initdata = {
6021 .l_reg = MM_PLL3_L_VAL_REG,
6022 .m_reg = MM_PLL3_M_VAL_REG,
6023 .n_reg = MM_PLL3_N_VAL_REG,
6024 .config_reg = MM_PLL3_CONFIG_REG,
6025 .mode_reg = MM_PLL3_MODE_REG,
6026};
Tianyi Gou358c3862011-10-18 17:03:41 -07006027
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006028static struct pll_config pll15_config __initdata = {
6029 .l = (0x24 | BVAL(31, 7, 0x620)),
6030 .m = 0x1,
6031 .n = 0x9,
6032 .vco_val = BVAL(17, 16, 0x2),
6033 .vco_mask = BM(17, 16),
6034 .pre_div_val = 0x0,
6035 .pre_div_mask = BIT(19),
6036 .post_div_val = 0x0,
6037 .post_div_mask = BM(21, 20),
6038 .mn_ena_val = BIT(22),
6039 .mn_ena_mask = BIT(22),
6040 .main_output_val = BIT(23),
6041 .main_output_mask = BIT(23),
6042};
Tianyi Gou41515e22011-09-01 19:37:43 -07006043
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006044static struct pll_config_regs pll14_regs __initdata = {
6045 .l_reg = BB_PLL14_L_VAL_REG,
6046 .m_reg = BB_PLL14_M_VAL_REG,
6047 .n_reg = BB_PLL14_N_VAL_REG,
6048 .config_reg = BB_PLL14_CONFIG_REG,
6049 .mode_reg = BB_PLL14_MODE_REG,
6050};
6051
6052static struct pll_config pll14_config __initdata = {
6053 .l = (0x11 | BVAL(31, 7, 0x620)),
6054 .m = 0x7,
6055 .n = 0x9,
6056 .vco_val = 0x0,
6057 .vco_mask = BM(17, 16),
6058 .pre_div_val = 0x0,
6059 .pre_div_mask = BIT(19),
6060 .post_div_val = 0x0,
6061 .post_div_mask = BM(21, 20),
6062 .mn_ena_val = BIT(22),
6063 .mn_ena_mask = BIT(22),
6064 .main_output_val = BIT(23),
6065 .main_output_mask = BIT(23),
6066};
Tianyi Gou41515e22011-09-01 19:37:43 -07006067
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006068static void __init reg_init(void)
6069{
Stephen Boydd471e7a2011-11-19 01:37:39 -08006070 void __iomem *imem_reg;
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006071
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006072 /* Deassert MM SW_RESET_ALL signal. */
6073 writel_relaxed(0, SW_RESET_ALL_REG);
6074
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006075 /*
Tianyi Goue3d4f542012-03-15 17:06:45 -07006076 * Some bits are only used on 8960 or 8064 or 8930 and are marked as
6077 * reserved bits on the other SoCs. Writing to these reserved bits
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006078 * should have no effect.
6079 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08006080 /*
6081 * Initialize MM AHB registers: Enable the FPB clock and disable HW
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006082 * gating on 8627 for all clocks. Also set VFE_AHB's
Stephen Boydd471e7a2011-11-19 01:37:39 -08006083 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
6084 * the clock is halted. The sleep and wake-up delays are set to safe
6085 * values.
6086 */
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006087 if (cpu_is_msm8627()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08006088 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
6089 writel_relaxed(0x000007F9, AHB_EN2_REG);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006090 } else {
6091 rmwreg(0x44000000, AHB_EN_REG, 0x6C000103);
6092 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
Stephen Boydd471e7a2011-11-19 01:37:39 -08006093 }
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006094
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006095 if (cpu_is_apq8064())
Tianyi Gouf3095ea2012-05-22 14:16:06 -07006096 rmwreg(0x00000001, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006097
6098 /* Deassert all locally-owned MM AHB resets. */
6099 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07006100 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006101
6102 /* Initialize MM AXI registers: Enable HW gating for all clocks that
6103 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
6104 * delays to safe values. */
Tianyi Gouf3095ea2012-05-22 14:16:06 -07006105 if ((cpu_is_msm8960() &&
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006106 SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 3) ||
6107 cpu_is_msm8627()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08006108 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
6109 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006110 } else {
6111 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
6112 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08006113 }
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006114
Matt Wagantall53d968f2011-07-19 13:22:53 -07006115 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006116 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
6117
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006118 if (cpu_is_apq8064())
Tianyi Gouf3095ea2012-05-22 14:16:06 -07006119 rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF);
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006120 if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627())
Tianyi Goue3d4f542012-03-15 17:06:45 -07006121 rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006122 if (cpu_is_msm8627())
Stephen Boydd471e7a2011-11-19 01:37:39 -08006123 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006124 else
6125 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08006126
6127 /* Enable IMEM's clk_on signal */
6128 imem_reg = ioremap(0x04b00040, 4);
6129 if (imem_reg) {
6130 writel_relaxed(0x3, imem_reg);
6131 iounmap(imem_reg);
6132 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006133
6134 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
6135 * memories retain state even when not clocked. Also, set sleep and
6136 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07006137 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
6138 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
6139 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006140 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07006141 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006142 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006143 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
6144 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
6145 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006146 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
6147 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
6148 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07006149 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006150 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Tianyi Goue3d4f542012-03-15 17:06:45 -07006151 if (cpu_is_msm8960() || cpu_is_apq8064()) {
6152 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
6153 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
6154 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
6155 }
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006156 if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
6157 cpu_is_msm8627())
Tianyi Goue3d4f542012-03-15 17:06:45 -07006158 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
6159
6160 if (cpu_is_msm8960()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006161 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
6162 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006163 }
6164 if (cpu_is_apq8064()) {
6165 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07006166 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006167 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006168
Tianyi Gou41515e22011-09-01 19:37:43 -07006169 /*
6170 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
6171 * core remain active during halt state of the clk. Also, set sleep
6172 * and wake-up value to max.
6173 */
6174 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006175 if (cpu_is_apq8064()) {
6176 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
6177 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
6178 }
Tianyi Gou41515e22011-09-01 19:37:43 -07006179
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006180 /* De-assert MM AXI resets to all hardware blocks. */
6181 writel_relaxed(0, SW_RESET_AXI_REG);
6182
6183 /* Deassert all MM core resets. */
6184 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07006185 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006186
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006187 /* Enable TSSC and PDM PXO sources. */
6188 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
6189 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
6190
6191 /* Source SLIMBus xo src from slimbus reference clock */
Tianyi Goue3d4f542012-03-15 17:06:45 -07006192 if (cpu_is_msm8960())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006193 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006194
6195 /* Source the dsi_byte_clks from the DSI PHY PLLs */
6196 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
Tianyi Goue3d4f542012-03-15 17:06:45 -07006197 if (cpu_is_msm8960() || cpu_is_apq8064())
6198 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07006199
Siddhartha Agrawal482459c2012-05-24 15:28:53 -07006200 /* Source the dsi1_esc_clk from the DSI1 PHY PLLs */
6201 rmwreg(0x1, DSI1_ESC_NS_REG, 0x7);
6202
Tianyi Gou352955d2012-05-18 19:44:01 -07006203 /*
6204 * Source the sata_phy_ref_clk from PXO and set predivider of
6205 * sata_pmalive_clk to 1.
6206 */
6207 if (cpu_is_apq8064()) {
Tianyi Gou41515e22011-09-01 19:37:43 -07006208 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
Tianyi Gou352955d2012-05-18 19:44:01 -07006209 rmwreg(0, SATA_PMALIVE_CLK_CTL_REG, 0x3);
6210 }
Tianyi Gou41515e22011-09-01 19:37:43 -07006211
6212 /*
Tianyi Gou05e01102012-02-08 22:15:49 -08006213 * TODO: Programming below PLLs and prng_clk is temporary and
6214 * needs to be removed after bootloaders program them.
Tianyi Gou41515e22011-09-01 19:37:43 -07006215 */
6216 if (cpu_is_apq8064()) {
Tianyi Gou317aa862012-02-06 14:31:07 -08006217 u32 is_pll_enabled;
Tianyi Gou41515e22011-09-01 19:37:43 -07006218
6219 /* Program pxo_src_clk to source from PXO */
6220 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
6221
Tianyi Gou41515e22011-09-01 19:37:43 -07006222 /* Check if PLL14 is active */
6223 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006224 if (!is_pll_enabled)
Tianyi Goudf71f2e2011-10-24 22:25:04 -07006225 /* Ref clk = 27MHz and program pll14 to 480MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006226 configure_pll(&pll14_config, &pll14_regs, 1);
Tianyi Gou621f8742011-09-01 21:45:01 -07006227
Tianyi Gou621f8742011-09-01 21:45:01 -07006228 /* Program PLL15 to 975MHz with ref clk = 27MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006229 configure_pll(&pll15_config, &pll15_regs, 0);
Tianyi Gouc29c3242011-10-12 21:02:15 -07006230
6231 /* Check if PLL4 is active */
6232 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006233 if (!is_pll_enabled)
Tianyi Goudf71f2e2011-10-24 22:25:04 -07006234 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006235 configure_pll(&pll4_config, &pll4_regs, 1);
Tianyi Gouc29c3242011-10-12 21:02:15 -07006236
6237 /* Enable PLL4 source on the LPASS Primary PLL Mux */
6238 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou05e01102012-02-08 22:15:49 -08006239
6240 /* Program prng_clk to 64MHz if it isn't configured */
6241 if (!readl_relaxed(PRNG_CLK_NS_REG))
6242 writel_relaxed(0x2B, PRNG_CLK_NS_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07006243 }
Tianyi Gou65c536a2012-03-20 23:20:29 -07006244
6245 /*
6246 * Program PLL15 to 900MHz with ref clk = 27MHz and
6247 * only enable PLL main output.
6248 */
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006249 if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006250 pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
6251 pll15_config.m = 0x1;
6252 pll15_config.n = 0x3;
6253 configure_pll(&pll15_config, &pll15_regs, 0);
6254 /* Disable AUX and BIST outputs */
6255 writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
Tianyi Gou65c536a2012-03-20 23:20:29 -07006256 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006257}
6258
Matt Wagantallb64888f2012-04-02 21:35:07 -07006259static void __init msm8960_clock_pre_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006260{
Saravana Kannan298ec392012-02-08 19:21:47 -08006261 if (cpu_is_apq8064()) {
6262 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8064;
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006263 } else if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
Saravana Kannan298ec392012-02-08 19:21:47 -08006264 vdd_dig.set_vdd = set_vdd_dig_8930;
6265 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8930;
Tianyi Goue1faaf22012-01-24 16:07:19 -08006266 }
Tianyi Goubf3d0b12012-01-23 14:37:28 -08006267
Tianyi Gou41515e22011-09-01 19:37:43 -07006268 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006269 * Change the freq tables for and voltage requirements for
6270 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07006271 */
6272 if (cpu_is_apq8064()) {
6273 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006274
6275 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
6276 sizeof(gfx3d_clk.c.fmax));
6277 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
6278 sizeof(ijpeg_clk.c.fmax));
6279 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
6280 sizeof(ijpeg_clk.c.fmax));
6281 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
6282 sizeof(tv_src_clk.c.fmax));
6283 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
6284 sizeof(vfe_clk.c.fmax));
6285
Tianyi Goue3d4f542012-03-15 17:06:45 -07006286 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8064.c;
6287 }
6288
6289 /*
6290 * Change the freq tables and voltage requirements for
6291 * clocks which differ between 8960 and 8930.
6292 */
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006293 if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
Tianyi Goue3d4f542012-03-15 17:06:45 -07006294 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
6295
6296 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930,
6297 sizeof(gfx3d_clk.c.fmax));
6298
6299 pll15_clk.c.rate = 900000000;
6300 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07006301 }
Stephen Boyd842a1f62012-04-26 19:07:38 -07006302 if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B)
6303 prng_clk.freq_tbl = clk_tbl_prng_64;
Stephen Boyd94625ef2011-07-12 17:06:01 -07006304
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006305 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006306
Vikram Mulukutla681d8682012-03-09 23:56:20 -08006307 clk_ops_local_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006308
6309 /* Initialize clock registers. */
6310 reg_init();
Matt Wagantallb64888f2012-04-02 21:35:07 -07006311}
6312
6313static void __init msm8960_clock_post_init(void)
6314{
6315 /* Keep PXO on whenever APPS cpu is active */
6316 clk_prepare_enable(&pxo_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006317
Matt Wagantalle655cd72012-04-09 10:15:03 -07006318 /* Reset 3D core while clocked to ensure it resets completely. */
6319 clk_set_rate(&gfx3d_clk.c, 27000000);
6320 clk_prepare_enable(&gfx3d_clk.c);
6321 clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT);
6322 udelay(5);
6323 clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT);
6324 clk_disable_unprepare(&gfx3d_clk.c);
6325
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006326 /* Initialize rates for clocks that only support one. */
6327 clk_set_rate(&pdm_clk.c, 27000000);
Stephen Boyd842a1f62012-04-26 19:07:38 -07006328 clk_set_rate(&prng_clk.c, prng_clk.freq_tbl->freq_hz);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006329 clk_set_rate(&mdp_vsync_clk.c, 27000000);
6330 clk_set_rate(&tsif_ref_clk.c, 105000);
6331 clk_set_rate(&tssc_clk.c, 27000000);
6332 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07006333 if (cpu_is_apq8064()) {
6334 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
6335 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
6336 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006337 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006338 if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
6339 cpu_is_msm8627())
Tianyi Gou41515e22011-09-01 19:37:43 -07006340 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07006341 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
6342 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
6343 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Lena Salman127823f2012-02-14 17:13:53 +02006344 clk_set_rate(&usb_hsic_system_clk.c, 60000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07006345 /*
6346 * Set the CSI rates to a safe default to avoid warnings when
6347 * switching csi pix and rdi clocks.
6348 */
6349 clk_set_rate(&csi0_src_clk.c, 27000000);
6350 clk_set_rate(&csi1_src_clk.c, 27000000);
6351 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006352
6353 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07006354 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006355 * Toggle these clocks on and off to refresh them.
6356 */
Stephen Boyd409b8b42012-04-10 12:12:56 -07006357 clk_prepare_enable(&pdm_clk.c);
6358 clk_disable_unprepare(&pdm_clk.c);
6359 clk_prepare_enable(&tssc_clk.c);
6360 clk_disable_unprepare(&tssc_clk.c);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006361 clk_prepare_enable(&usb_hsic_hsic_clk.c);
6362 clk_disable_unprepare(&usb_hsic_hsic_clk.c);
Stephen Boydd7a143a2012-02-16 17:59:26 -08006363
6364 /*
6365 * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all
6366 * times when Apps CPU is active. This ensures the timer's requirement
6367 * of Krait AHB running 4 times as fast as the timer itself.
6368 */
6369 clk_set_rate(&sfab_tmr_a_clk.c, 54000000);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006370 clk_prepare_enable(&sfab_tmr_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006371}
6372
Stephen Boydbb600ae2011-08-02 20:11:40 -07006373static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006374{
Stephen Boyda3787f32011-09-16 18:55:13 -07006375 int rc;
6376 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07006377 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07006378
6379 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
6380 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
6381 PTR_ERR(mmfpb_a_clk)))
6382 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006383 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07006384 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
6385 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006386 rc = clk_prepare_enable(mmfpb_a_clk);
Stephen Boyda3787f32011-09-16 18:55:13 -07006387 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
6388 return rc;
6389
Stephen Boyd85436132011-09-16 18:55:13 -07006390 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
6391 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
6392 PTR_ERR(cfpb_a_clk)))
6393 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006394 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07006395 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
6396 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006397 rc = clk_prepare_enable(cfpb_a_clk);
Stephen Boyd85436132011-09-16 18:55:13 -07006398 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
6399 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006400
6401 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006402}
Stephen Boydbb600ae2011-08-02 20:11:40 -07006403
6404struct clock_init_data msm8960_clock_init_data __initdata = {
6405 .table = msm_clocks_8960,
6406 .size = ARRAY_SIZE(msm_clocks_8960),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006407 .pre_init = msm8960_clock_pre_init,
6408 .post_init = msm8960_clock_post_init,
Stephen Boydbb600ae2011-08-02 20:11:40 -07006409 .late_init = msm8960_clock_late_init,
6410};
Tianyi Gou41515e22011-09-01 19:37:43 -07006411
6412struct clock_init_data apq8064_clock_init_data __initdata = {
6413 .table = msm_clocks_8064,
6414 .size = ARRAY_SIZE(msm_clocks_8064),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006415 .pre_init = msm8960_clock_pre_init,
6416 .post_init = msm8960_clock_post_init,
Tianyi Gou41515e22011-09-01 19:37:43 -07006417 .late_init = msm8960_clock_late_init,
6418};
Tianyi Goue3d4f542012-03-15 17:06:45 -07006419
6420struct clock_init_data msm8930_clock_init_data __initdata = {
6421 .table = msm_clocks_8930,
6422 .size = ARRAY_SIZE(msm_clocks_8930),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006423 .pre_init = msm8960_clock_pre_init,
6424 .post_init = msm8960_clock_post_init,
Tianyi Goue3d4f542012-03-15 17:06:45 -07006425 .late_init = msm8960_clock_late_init,
6426};