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Kevin Hilman95a34772009-04-29 12:10:55 -07001/*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
Kevin Hilman95a34772009-04-29 12:10:55 -070011#include <linux/init.h>
12#include <linux/clk.h>
Mark A. Greer65e866a2009-03-18 12:36:08 -050013#include <linux/serial_8250.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070014#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
Mark A. Greera9949552009-04-15 12:40:35 -070016#include <linux/gpio.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070017
18#include <linux/spi/spi.h>
19
Mark A. Greer79c3c0b2009-04-15 12:38:58 -070020#include <asm/mach/map.h>
21
Kevin Hilman95a34772009-04-29 12:10:55 -070022#include <mach/dm355.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070023#include <mach/cputype.h>
24#include <mach/edma.h>
25#include <mach/psc.h>
26#include <mach/mux.h>
27#include <mach/irqs.h>
Mark A. Greerf64691b2009-04-15 12:40:11 -070028#include <mach/time.h>
Mark A. Greer65e866a2009-03-18 12:36:08 -050029#include <mach/serial.h>
Mark A. Greer79c3c0b2009-04-15 12:38:58 -070030#include <mach/common.h>
Chaithrika U S25acf552009-06-05 06:28:08 -040031#include <mach/asp.h>
Sandeep Paulraj15e86582010-02-01 09:51:15 -050032#include <mach/spi.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070033
34#include "clock.h"
35#include "mux.h"
36
Kevin Hilman96ed2992009-04-30 11:20:24 -070037#define DM355_UART2_BASE (IO_PHYS + 0x206000)
38
Kevin Hilman95a34772009-04-29 12:10:55 -070039/*
40 * Device specific clocks
41 */
42#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
43
44static struct pll_data pll1_data = {
45 .num = 1,
46 .phys_base = DAVINCI_PLL1_BASE,
47 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
48};
49
50static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53 .flags = PLL_HAS_PREDIV,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 /* FIXME -- crystal rate is board-specific */
59 .rate = DM355_REF_FREQ,
60};
61
62static struct clk pll1_clk = {
63 .name = "pll1",
64 .parent = &ref_clk,
65 .flags = CLK_PLL,
66 .pll_data = &pll1_data,
67};
68
69static struct clk pll1_aux_clk = {
70 .name = "pll1_aux_clk",
71 .parent = &pll1_clk,
72 .flags = CLK_PLL | PRE_PLL,
73};
74
75static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV1,
80};
81
82static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV2,
87};
88
89static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV3,
94};
95
96static struct clk pll1_sysclk4 = {
97 .name = "pll1_sysclk4",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV4,
101};
102
103static struct clk pll1_sysclkbp = {
104 .name = "pll1_sysclkbp",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL | PRE_PLL,
107 .div_reg = BPDIV
108};
109
110static struct clk vpss_dac_clk = {
111 .name = "vpss_dac",
112 .parent = &pll1_sysclk3,
113 .lpsc = DM355_LPSC_VPSS_DAC,
114};
115
116static struct clk vpss_master_clk = {
117 .name = "vpss_master",
118 .parent = &pll1_sysclk4,
119 .lpsc = DAVINCI_LPSC_VPSSMSTR,
120 .flags = CLK_PSC,
121};
122
123static struct clk vpss_slave_clk = {
124 .name = "vpss_slave",
125 .parent = &pll1_sysclk4,
126 .lpsc = DAVINCI_LPSC_VPSSSLV,
127};
128
Kevin Hilman95a34772009-04-29 12:10:55 -0700129static struct clk clkout1_clk = {
130 .name = "clkout1",
131 .parent = &pll1_aux_clk,
132 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
133};
134
135static struct clk clkout2_clk = {
136 .name = "clkout2",
137 .parent = &pll1_sysclkbp,
138};
139
140static struct clk pll2_clk = {
141 .name = "pll2",
142 .parent = &ref_clk,
143 .flags = CLK_PLL,
144 .pll_data = &pll2_data,
145};
146
147static struct clk pll2_sysclk1 = {
148 .name = "pll2_sysclk1",
149 .parent = &pll2_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV1,
152};
153
154static struct clk pll2_sysclkbp = {
155 .name = "pll2_sysclkbp",
156 .parent = &pll2_clk,
157 .flags = CLK_PLL | PRE_PLL,
158 .div_reg = BPDIV
159};
160
161static struct clk clkout3_clk = {
162 .name = "clkout3",
163 .parent = &pll2_sysclkbp,
164 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
165};
166
167static struct clk arm_clk = {
168 .name = "arm_clk",
169 .parent = &pll1_sysclk1,
170 .lpsc = DAVINCI_LPSC_ARM,
171 .flags = ALWAYS_ENABLED,
172};
173
174/*
175 * NOT LISTED below, and not touched by Linux
176 * - in SyncReset state by default
177 * .lpsc = DAVINCI_LPSC_TPCC,
178 * .lpsc = DAVINCI_LPSC_TPTC0,
179 * .lpsc = DAVINCI_LPSC_TPTC1,
180 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
181 * .lpsc = DAVINCI_LPSC_MEMSTICK,
182 * - in Enabled state by default
183 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
184 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
185 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
187 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
188 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
189 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
191 */
192
193static struct clk mjcp_clk = {
194 .name = "mjcp",
195 .parent = &pll1_sysclk1,
196 .lpsc = DAVINCI_LPSC_IMCOP,
197};
198
199static struct clk uart0_clk = {
200 .name = "uart0",
201 .parent = &pll1_aux_clk,
202 .lpsc = DAVINCI_LPSC_UART0,
203};
204
205static struct clk uart1_clk = {
206 .name = "uart1",
207 .parent = &pll1_aux_clk,
208 .lpsc = DAVINCI_LPSC_UART1,
209};
210
211static struct clk uart2_clk = {
212 .name = "uart2",
213 .parent = &pll1_sysclk2,
214 .lpsc = DAVINCI_LPSC_UART2,
215};
216
217static struct clk i2c_clk = {
218 .name = "i2c",
219 .parent = &pll1_aux_clk,
220 .lpsc = DAVINCI_LPSC_I2C,
221};
222
223static struct clk asp0_clk = {
224 .name = "asp0",
225 .parent = &pll1_sysclk2,
226 .lpsc = DAVINCI_LPSC_McBSP,
227};
228
229static struct clk asp1_clk = {
230 .name = "asp1",
231 .parent = &pll1_sysclk2,
232 .lpsc = DM355_LPSC_McBSP1,
233};
234
235static struct clk mmcsd0_clk = {
236 .name = "mmcsd0",
237 .parent = &pll1_sysclk2,
238 .lpsc = DAVINCI_LPSC_MMC_SD,
239};
240
241static struct clk mmcsd1_clk = {
242 .name = "mmcsd1",
243 .parent = &pll1_sysclk2,
244 .lpsc = DM355_LPSC_MMC_SD1,
245};
246
247static struct clk spi0_clk = {
248 .name = "spi0",
249 .parent = &pll1_sysclk2,
250 .lpsc = DAVINCI_LPSC_SPI,
251};
252
253static struct clk spi1_clk = {
254 .name = "spi1",
255 .parent = &pll1_sysclk2,
256 .lpsc = DM355_LPSC_SPI1,
257};
258
259static struct clk spi2_clk = {
260 .name = "spi2",
261 .parent = &pll1_sysclk2,
262 .lpsc = DM355_LPSC_SPI2,
263};
264
265static struct clk gpio_clk = {
266 .name = "gpio",
267 .parent = &pll1_sysclk2,
268 .lpsc = DAVINCI_LPSC_GPIO,
269};
270
271static struct clk aemif_clk = {
272 .name = "aemif",
273 .parent = &pll1_sysclk2,
274 .lpsc = DAVINCI_LPSC_AEMIF,
275};
276
277static struct clk pwm0_clk = {
278 .name = "pwm0",
279 .parent = &pll1_aux_clk,
280 .lpsc = DAVINCI_LPSC_PWM0,
281};
282
283static struct clk pwm1_clk = {
284 .name = "pwm1",
285 .parent = &pll1_aux_clk,
286 .lpsc = DAVINCI_LPSC_PWM1,
287};
288
289static struct clk pwm2_clk = {
290 .name = "pwm2",
291 .parent = &pll1_aux_clk,
292 .lpsc = DAVINCI_LPSC_PWM2,
293};
294
295static struct clk pwm3_clk = {
296 .name = "pwm3",
297 .parent = &pll1_aux_clk,
298 .lpsc = DM355_LPSC_PWM3,
299};
300
301static struct clk timer0_clk = {
302 .name = "timer0",
303 .parent = &pll1_aux_clk,
304 .lpsc = DAVINCI_LPSC_TIMER0,
305};
306
307static struct clk timer1_clk = {
308 .name = "timer1",
309 .parent = &pll1_aux_clk,
310 .lpsc = DAVINCI_LPSC_TIMER1,
311};
312
313static struct clk timer2_clk = {
314 .name = "timer2",
315 .parent = &pll1_aux_clk,
316 .lpsc = DAVINCI_LPSC_TIMER2,
317 .usecount = 1, /* REVISIT: why cant' this be disabled? */
318};
319
320static struct clk timer3_clk = {
321 .name = "timer3",
322 .parent = &pll1_aux_clk,
323 .lpsc = DM355_LPSC_TIMER3,
324};
325
326static struct clk rto_clk = {
327 .name = "rto",
328 .parent = &pll1_aux_clk,
329 .lpsc = DM355_LPSC_RTO,
330};
331
332static struct clk usb_clk = {
333 .name = "usb",
334 .parent = &pll1_sysclk2,
335 .lpsc = DAVINCI_LPSC_USB,
336};
337
Kevin Hilman08aca082010-01-11 08:22:23 -0800338static struct clk_lookup dm355_clks[] = {
Kevin Hilman95a34772009-04-29 12:10:55 -0700339 CLK(NULL, "ref", &ref_clk),
340 CLK(NULL, "pll1", &pll1_clk),
341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
342 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
343 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
344 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
345 CLK(NULL, "pll1_aux", &pll1_aux_clk),
346 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
347 CLK(NULL, "vpss_dac", &vpss_dac_clk),
348 CLK(NULL, "vpss_master", &vpss_master_clk),
349 CLK(NULL, "vpss_slave", &vpss_slave_clk),
350 CLK(NULL, "clkout1", &clkout1_clk),
351 CLK(NULL, "clkout2", &clkout2_clk),
352 CLK(NULL, "pll2", &pll2_clk),
353 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
354 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
355 CLK(NULL, "clkout3", &clkout3_clk),
356 CLK(NULL, "arm", &arm_clk),
357 CLK(NULL, "mjcp", &mjcp_clk),
358 CLK(NULL, "uart0", &uart0_clk),
359 CLK(NULL, "uart1", &uart1_clk),
360 CLK(NULL, "uart2", &uart2_clk),
361 CLK("i2c_davinci.1", NULL, &i2c_clk),
Kevin Hilman61aa0732009-07-15 08:47:48 -0700362 CLK("davinci-asp.0", NULL, &asp0_clk),
363 CLK("davinci-asp.1", NULL, &asp1_clk),
Kevin Hilman95a34772009-04-29 12:10:55 -0700364 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
365 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
Sandeep Paulraj15e86582010-02-01 09:51:15 -0500366 CLK("spi_davinci.0", NULL, &spi0_clk),
367 CLK("spi_davinci.1", NULL, &spi1_clk),
368 CLK("spi_davinci.2", NULL, &spi2_clk),
Kevin Hilman95a34772009-04-29 12:10:55 -0700369 CLK(NULL, "gpio", &gpio_clk),
370 CLK(NULL, "aemif", &aemif_clk),
371 CLK(NULL, "pwm0", &pwm0_clk),
372 CLK(NULL, "pwm1", &pwm1_clk),
373 CLK(NULL, "pwm2", &pwm2_clk),
374 CLK(NULL, "pwm3", &pwm3_clk),
375 CLK(NULL, "timer0", &timer0_clk),
376 CLK(NULL, "timer1", &timer1_clk),
377 CLK("watchdog", NULL, &timer2_clk),
378 CLK(NULL, "timer3", &timer3_clk),
379 CLK(NULL, "rto", &rto_clk),
380 CLK(NULL, "usb", &usb_clk),
381 CLK(NULL, NULL, NULL),
382};
383
384/*----------------------------------------------------------------------*/
385
386static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
387
388static struct resource dm355_spi0_resources[] = {
389 {
390 .start = 0x01c66000,
391 .end = 0x01c667ff,
392 .flags = IORESOURCE_MEM,
393 },
394 {
Sandeep Paulraj15e86582010-02-01 09:51:15 -0500395 .start = IRQ_DM355_SPINT0_0,
Kevin Hilman95a34772009-04-29 12:10:55 -0700396 .flags = IORESOURCE_IRQ,
397 },
Sandeep Paulraj15e86582010-02-01 09:51:15 -0500398 {
399 .start = 17,
400 .flags = IORESOURCE_DMA,
401 },
402 {
403 .start = 16,
404 .flags = IORESOURCE_DMA,
405 },
406 {
407 .start = EVENTQ_1,
408 .flags = IORESOURCE_DMA,
409 },
Kevin Hilman95a34772009-04-29 12:10:55 -0700410};
411
Sandeep Paulraj15e86582010-02-01 09:51:15 -0500412static struct davinci_spi_platform_data dm355_spi0_pdata = {
413 .version = SPI_VERSION_1,
414 .num_chipselect = 2,
415 .clk_internal = 1,
416 .cs_hold = 1,
417 .intr_level = 0,
418 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
419 .c2tdelay = 0,
420 .t2cdelay = 0,
421};
Kevin Hilman95a34772009-04-29 12:10:55 -0700422static struct platform_device dm355_spi0_device = {
423 .name = "spi_davinci",
424 .id = 0,
425 .dev = {
426 .dma_mask = &dm355_spi0_dma_mask,
427 .coherent_dma_mask = DMA_BIT_MASK(32),
Sandeep Paulraj15e86582010-02-01 09:51:15 -0500428 .platform_data = &dm355_spi0_pdata,
Kevin Hilman95a34772009-04-29 12:10:55 -0700429 },
430 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
431 .resource = dm355_spi0_resources,
432};
433
434void __init dm355_init_spi0(unsigned chipselect_mask,
435 struct spi_board_info *info, unsigned len)
436{
437 /* for now, assume we need MISO */
438 davinci_cfg_reg(DM355_SPI0_SDI);
439
440 /* not all slaves will be wired up */
441 if (chipselect_mask & BIT(0))
442 davinci_cfg_reg(DM355_SPI0_SDENA0);
443 if (chipselect_mask & BIT(1))
444 davinci_cfg_reg(DM355_SPI0_SDENA1);
445
446 spi_register_board_info(info, len);
447
448 platform_device_register(&dm355_spi0_device);
449}
450
451/*----------------------------------------------------------------------*/
452
Mark A. Greer55700782009-04-15 12:42:06 -0700453#define PINMUX0 0x00
454#define PINMUX1 0x04
455#define PINMUX2 0x08
456#define PINMUX3 0x0c
457#define PINMUX4 0x10
458#define INTMUX 0x18
459#define EVTMUX 0x1c
460
Kevin Hilman95a34772009-04-29 12:10:55 -0700461/*
462 * Device specific mux setup
463 *
464 * soc description mux mode mode mux dbg
465 * reg offset mask mode
466 */
467static const struct mux_config dm355_pins[] = {
Mark A. Greer0e585952009-04-15 12:39:48 -0700468#ifdef CONFIG_DAVINCI_MUX
Kevin Hilman95a34772009-04-29 12:10:55 -0700469MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
470
471MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
472MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
473MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
474MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
475MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
476MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
477
478MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
479MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
480
481MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
482MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
483MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
484MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
485MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
486MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
487
488MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
489MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
490MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
491
492INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
493INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
494INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
495
496EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
497EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
498EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
Sandeep Paulraj1aebb502009-08-21 12:38:11 -0400499
500MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
501MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
502MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
503MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
504MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400505
506MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
507MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
508MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
509MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
510MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
511MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
512MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
Mark A. Greer0e585952009-04-15 12:39:48 -0700513#endif
Kevin Hilman95a34772009-04-29 12:10:55 -0700514};
515
Mark A. Greer673dd362009-04-15 12:40:00 -0700516static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
517 [IRQ_DM355_CCDC_VDINT0] = 2,
518 [IRQ_DM355_CCDC_VDINT1] = 6,
519 [IRQ_DM355_CCDC_VDINT2] = 6,
520 [IRQ_DM355_IPIPE_HST] = 6,
521 [IRQ_DM355_H3AINT] = 6,
522 [IRQ_DM355_IPIPE_SDR] = 6,
523 [IRQ_DM355_IPIPEIFINT] = 6,
524 [IRQ_DM355_OSDINT] = 7,
525 [IRQ_DM355_VENCINT] = 6,
526 [IRQ_ASQINT] = 6,
527 [IRQ_IMXINT] = 6,
528 [IRQ_USBINT] = 4,
529 [IRQ_DM355_RTOINT] = 4,
530 [IRQ_DM355_UARTINT2] = 7,
531 [IRQ_DM355_TINT6] = 7,
532 [IRQ_CCINT0] = 5, /* dma */
533 [IRQ_CCERRINT] = 5, /* dma */
534 [IRQ_TCERRINT0] = 5, /* dma */
535 [IRQ_TCERRINT] = 5, /* dma */
536 [IRQ_DM355_SPINT2_1] = 7,
537 [IRQ_DM355_TINT7] = 4,
538 [IRQ_DM355_SDIOINT0] = 7,
539 [IRQ_MBXINT] = 7,
540 [IRQ_MBRINT] = 7,
541 [IRQ_MMCINT] = 7,
542 [IRQ_DM355_MMCINT1] = 7,
543 [IRQ_DM355_PWMINT3] = 7,
544 [IRQ_DDRINT] = 7,
545 [IRQ_AEMIFINT] = 7,
546 [IRQ_DM355_SDIOINT1] = 4,
547 [IRQ_TINT0_TINT12] = 2, /* clockevent */
548 [IRQ_TINT0_TINT34] = 2, /* clocksource */
549 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
550 [IRQ_TINT1_TINT34] = 7, /* system tick */
551 [IRQ_PWMINT0] = 7,
552 [IRQ_PWMINT1] = 7,
553 [IRQ_PWMINT2] = 7,
554 [IRQ_I2C] = 3,
555 [IRQ_UARTINT0] = 3,
556 [IRQ_UARTINT1] = 3,
557 [IRQ_DM355_SPINT0_0] = 3,
558 [IRQ_DM355_SPINT0_1] = 3,
559 [IRQ_DM355_GPIO0] = 3,
560 [IRQ_DM355_GPIO1] = 7,
561 [IRQ_DM355_GPIO2] = 4,
562 [IRQ_DM355_GPIO3] = 4,
563 [IRQ_DM355_GPIO4] = 7,
564 [IRQ_DM355_GPIO5] = 7,
565 [IRQ_DM355_GPIO6] = 7,
566 [IRQ_DM355_GPIO7] = 7,
567 [IRQ_DM355_GPIO8] = 7,
568 [IRQ_DM355_GPIO9] = 7,
569 [IRQ_DM355_GPIOBNK0] = 7,
570 [IRQ_DM355_GPIOBNK1] = 7,
571 [IRQ_DM355_GPIOBNK2] = 7,
572 [IRQ_DM355_GPIOBNK3] = 7,
573 [IRQ_DM355_GPIOBNK4] = 7,
574 [IRQ_DM355_GPIOBNK5] = 7,
575 [IRQ_DM355_GPIOBNK6] = 7,
576 [IRQ_COMMTX] = 7,
577 [IRQ_COMMRX] = 7,
578 [IRQ_EMUINT] = 7,
579};
580
Kevin Hilman95a34772009-04-29 12:10:55 -0700581/*----------------------------------------------------------------------*/
582
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400583static const s8
584queue_tc_mapping[][2] = {
585 /* {event queue no, TC no} */
586 {0, 0},
587 {1, 1},
588 {-1, -1},
589};
590
591static const s8
592queue_priority_mapping[][2] = {
593 /* {event queue no, Priority} */
594 {0, 3},
595 {1, 7},
596 {-1, -1},
597};
598
599static struct edma_soc_info dm355_edma_info[] = {
600 {
601 .n_channel = 64,
602 .n_region = 4,
603 .n_slot = 128,
604 .n_tc = 2,
605 .n_cc = 1,
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400606 .queue_tc_mapping = queue_tc_mapping,
607 .queue_priority_mapping = queue_priority_mapping,
608 },
Kevin Hilman95a34772009-04-29 12:10:55 -0700609};
610
611static struct resource edma_resources[] = {
612 {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400613 .name = "edma_cc0",
Kevin Hilman95a34772009-04-29 12:10:55 -0700614 .start = 0x01c00000,
615 .end = 0x01c00000 + SZ_64K - 1,
616 .flags = IORESOURCE_MEM,
617 },
618 {
619 .name = "edma_tc0",
620 .start = 0x01c10000,
621 .end = 0x01c10000 + SZ_1K - 1,
622 .flags = IORESOURCE_MEM,
623 },
624 {
625 .name = "edma_tc1",
626 .start = 0x01c10400,
627 .end = 0x01c10400 + SZ_1K - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400631 .name = "edma0",
Kevin Hilman95a34772009-04-29 12:10:55 -0700632 .start = IRQ_CCINT0,
633 .flags = IORESOURCE_IRQ,
634 },
635 {
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400636 .name = "edma0_err",
Kevin Hilman95a34772009-04-29 12:10:55 -0700637 .start = IRQ_CCERRINT,
638 .flags = IORESOURCE_IRQ,
639 },
640 /* not using (or muxing) TC*_ERR */
641};
642
643static struct platform_device dm355_edma_device = {
644 .name = "edma",
Sudhakar Rajashekhara60902a22009-05-21 07:41:35 -0400645 .id = 0,
646 .dev.platform_data = dm355_edma_info,
Kevin Hilman95a34772009-04-29 12:10:55 -0700647 .num_resources = ARRAY_SIZE(edma_resources),
648 .resource = edma_resources,
649};
650
Chaithrika U S25acf552009-06-05 06:28:08 -0400651static struct resource dm355_asp1_resources[] = {
652 {
653 .start = DAVINCI_ASP1_BASE,
654 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
655 .flags = IORESOURCE_MEM,
656 },
657 {
658 .start = DAVINCI_DMA_ASP1_TX,
659 .end = DAVINCI_DMA_ASP1_TX,
660 .flags = IORESOURCE_DMA,
661 },
662 {
663 .start = DAVINCI_DMA_ASP1_RX,
664 .end = DAVINCI_DMA_ASP1_RX,
665 .flags = IORESOURCE_DMA,
666 },
667};
668
669static struct platform_device dm355_asp1_device = {
670 .name = "davinci-asp",
Kevin Hilman61aa0732009-07-15 08:47:48 -0700671 .id = 1,
Chaithrika U S25acf552009-06-05 06:28:08 -0400672 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
673 .resource = dm355_asp1_resources,
674};
675
Muralidharan Karicheri77c8b5f2010-01-13 20:27:08 -0300676static void dm355_ccdc_setup_pinmux(void)
677{
678 davinci_cfg_reg(DM355_VIN_PCLK);
679 davinci_cfg_reg(DM355_VIN_CAM_WEN);
680 davinci_cfg_reg(DM355_VIN_CAM_VD);
681 davinci_cfg_reg(DM355_VIN_CAM_HD);
682 davinci_cfg_reg(DM355_VIN_YIN_EN);
683 davinci_cfg_reg(DM355_VIN_CINL_EN);
684 davinci_cfg_reg(DM355_VIN_CINH_EN);
685}
686
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400687static struct resource dm355_vpss_resources[] = {
688 {
689 /* VPSS BL Base address */
690 .name = "vpss",
691 .start = 0x01c70800,
692 .end = 0x01c70800 + 0xff,
693 .flags = IORESOURCE_MEM,
694 },
695 {
696 /* VPSS CLK Base address */
697 .name = "vpss",
698 .start = 0x01c70000,
699 .end = 0x01c70000 + 0xf,
700 .flags = IORESOURCE_MEM,
701 },
702};
703
704static struct platform_device dm355_vpss_device = {
705 .name = "vpss",
706 .id = -1,
707 .dev.platform_data = "dm355_vpss",
708 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
709 .resource = dm355_vpss_resources,
710};
711
712static struct resource vpfe_resources[] = {
713 {
714 .start = IRQ_VDINT0,
715 .end = IRQ_VDINT0,
716 .flags = IORESOURCE_IRQ,
717 },
718 {
719 .start = IRQ_VDINT1,
720 .end = IRQ_VDINT1,
721 .flags = IORESOURCE_IRQ,
722 },
Muralidharan Karicheri77c8b5f2010-01-13 20:27:08 -0300723};
724
725static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
726static struct resource dm355_ccdc_resource[] = {
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400727 /* CCDC Base address */
728 {
729 .flags = IORESOURCE_MEM,
730 .start = 0x01c70600,
731 .end = 0x01c70600 + 0x1ff,
732 },
733};
Muralidharan Karicheri77c8b5f2010-01-13 20:27:08 -0300734static struct platform_device dm355_ccdc_dev = {
735 .name = "dm355_ccdc",
736 .id = -1,
737 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
738 .resource = dm355_ccdc_resource,
739 .dev = {
740 .dma_mask = &vpfe_capture_dma_mask,
741 .coherent_dma_mask = DMA_BIT_MASK(32),
742 .platform_data = dm355_ccdc_setup_pinmux,
743 },
744};
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400745
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400746static struct platform_device vpfe_capture_dev = {
747 .name = CAPTURE_DRV_NAME,
748 .id = -1,
749 .num_resources = ARRAY_SIZE(vpfe_resources),
750 .resource = vpfe_resources,
751 .dev = {
752 .dma_mask = &vpfe_capture_dma_mask,
753 .coherent_dma_mask = DMA_BIT_MASK(32),
754 },
755};
756
757void dm355_set_vpfe_config(struct vpfe_config *cfg)
758{
759 vpfe_capture_dev.dev.platform_data = cfg;
760}
761
Kevin Hilman95a34772009-04-29 12:10:55 -0700762/*----------------------------------------------------------------------*/
763
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700764static struct map_desc dm355_io_desc[] = {
765 {
766 .virtual = IO_VIRT,
767 .pfn = __phys_to_pfn(IO_PHYS),
768 .length = IO_SIZE,
769 .type = MT_DEVICE
770 },
David Brownell0d04eb42009-04-30 17:35:48 -0700771 {
772 .virtual = SRAM_VIRT,
773 .pfn = __phys_to_pfn(0x00010000),
774 .length = SZ_32K,
775 /* MT_MEMORY_NONCACHED requires supersection alignment */
776 .type = MT_DEVICE,
777 },
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700778};
779
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700780/* Contents of JTAG ID register used to identify exact cpu type */
781static struct davinci_id dm355_ids[] = {
782 {
783 .variant = 0x0,
784 .part_no = 0xb73b,
785 .manufacturer = 0x00f,
786 .cpu_id = DAVINCI_CPU_ID_DM355,
787 .name = "dm355",
788 },
789};
790
Mark A. Greerd81d1882009-04-15 12:39:33 -0700791static void __iomem *dm355_psc_bases[] = {
792 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
793};
794
Mark A. Greerf64691b2009-04-15 12:40:11 -0700795/*
796 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
797 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
798 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
799 * T1_TOP: Timer 1, top : <unused>
800 */
801struct davinci_timer_info dm355_timer_info = {
802 .timers = davinci_timer_instance,
803 .clockevent_id = T0_BOT,
804 .clocksource_id = T0_TOP,
805};
806
Mark A. Greer65e866a2009-03-18 12:36:08 -0500807static struct plat_serial8250_port dm355_serial_platform_data[] = {
808 {
809 .mapbase = DAVINCI_UART0_BASE,
810 .irq = IRQ_UARTINT0,
811 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
812 UPF_IOREMAP,
813 .iotype = UPIO_MEM,
814 .regshift = 2,
815 },
816 {
817 .mapbase = DAVINCI_UART1_BASE,
818 .irq = IRQ_UARTINT1,
819 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
820 UPF_IOREMAP,
821 .iotype = UPIO_MEM,
822 .regshift = 2,
823 },
824 {
825 .mapbase = DM355_UART2_BASE,
826 .irq = IRQ_DM355_UARTINT2,
827 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
828 UPF_IOREMAP,
829 .iotype = UPIO_MEM,
830 .regshift = 2,
831 },
832 {
833 .flags = 0
834 },
835};
836
837static struct platform_device dm355_serial_device = {
838 .name = "serial8250",
839 .id = PLAT8250_DEV_PLATFORM,
840 .dev = {
841 .platform_data = dm355_serial_platform_data,
842 },
843};
844
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700845static struct davinci_soc_info davinci_soc_info_dm355 = {
846 .io_desc = dm355_io_desc,
847 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700848 .jtag_id_base = IO_ADDRESS(0x01c40028),
849 .ids = dm355_ids,
850 .ids_num = ARRAY_SIZE(dm355_ids),
Mark A. Greer66e0c392009-04-15 12:39:23 -0700851 .cpu_clks = dm355_clks,
Mark A. Greerd81d1882009-04-15 12:39:33 -0700852 .psc_bases = dm355_psc_bases,
853 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
Mark A. Greer0e585952009-04-15 12:39:48 -0700854 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
855 .pinmux_pins = dm355_pins,
856 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
Mark A. Greer673dd362009-04-15 12:40:00 -0700857 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
858 .intc_type = DAVINCI_INTC_TYPE_AINTC,
859 .intc_irq_prios = dm355_default_priorities,
860 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
Mark A. Greerf64691b2009-04-15 12:40:11 -0700861 .timer_info = &dm355_timer_info,
Mark A. Greera9949552009-04-15 12:40:35 -0700862 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
863 .gpio_num = 104,
864 .gpio_irq = IRQ_DM355_GPIOBNK0,
Mark A. Greer65e866a2009-03-18 12:36:08 -0500865 .serial_dev = &dm355_serial_device,
David Brownell0d04eb42009-04-30 17:35:48 -0700866 .sram_dma = 0x00010000,
867 .sram_len = SZ_32K,
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700868};
869
Chaithrika U S25acf552009-06-05 06:28:08 -0400870void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
871{
872 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
873 if (evt_enable & ASP1_TX_EVT_EN)
874 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
875
876 if (evt_enable & ASP1_RX_EVT_EN)
877 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
878
879 dm355_asp1_device.dev.platform_data = pdata;
880 platform_device_register(&dm355_asp1_device);
881}
882
Kevin Hilman95a34772009-04-29 12:10:55 -0700883void __init dm355_init(void)
884{
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700885 davinci_common_init(&davinci_soc_info_dm355);
Kevin Hilman95a34772009-04-29 12:10:55 -0700886}
887
888static int __init dm355_init_devices(void)
889{
890 if (!cpu_is_davinci_dm355())
891 return 0;
892
Muralidharan Karicheri77c8b5f2010-01-13 20:27:08 -0300893 /* Add ccdc clock aliases */
894 clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
895 clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
Kevin Hilman95a34772009-04-29 12:10:55 -0700896 davinci_cfg_reg(DM355_INT_EDMA_CC);
897 platform_device_register(&dm355_edma_device);
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400898 platform_device_register(&dm355_vpss_device);
Muralidharan Karicheri77c8b5f2010-01-13 20:27:08 -0300899 platform_device_register(&dm355_ccdc_dev);
Muralidharan Karicheri51e68e22009-09-16 12:02:50 -0400900 platform_device_register(&vpfe_capture_dev);
901
Kevin Hilman95a34772009-04-29 12:10:55 -0700902 return 0;
903}
904postcore_initcall(dm355_init_devices);