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Vitaly Wool78818e42006-05-16 11:54:37 +01001/*
2 * arch/arm/mach-pnx4008/time.c
3 *
4 * PNX4008 Timers
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
Vitaly Wool78818e42006-05-16 11:54:37 +010014#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/sched.h>
19#include <linux/spinlock.h>
20#include <linux/module.h>
21#include <linux/kallsyms.h>
Vitaly Wool5904a7f2006-07-05 14:47:20 +010022#include <linux/time.h>
23#include <linux/timex.h>
24#include <linux/irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010025#include <linux/io.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010026
27#include <asm/system.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010028#include <mach/hardware.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010029#include <asm/leds.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010030#include <asm/mach/time.h>
Vitaly Wool78818e42006-05-16 11:54:37 +010031#include <asm/errno.h>
32
Russell King27816812009-11-21 11:43:33 +000033#include "time.h"
34
Vitaly Wool78818e42006-05-16 11:54:37 +010035/*! Note: all timers are UPCOUNTING */
36
37/*!
38 * Returns number of us since last clock interrupt. Note that interrupts
39 * will have been disabled by do_gettimeoffset()
40 */
41static unsigned long pnx4008_gettimeoffset(void)
42{
43 u32 ticks_to_match =
44 __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
45 u32 elapsed = LATCH - ticks_to_match;
46 return (elapsed * (tick_nsec / 1000)) / LATCH;
47}
48
49/*!
50 * IRQ handler for the timer
51 */
Linus Torvalds0cd61b62006-10-06 10:53:39 -070052static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
Vitaly Wool78818e42006-05-16 11:54:37 +010053{
54 if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
55
Vitaly Wool78818e42006-05-16 11:54:37 +010056 do {
Linus Torvalds0cd61b62006-10-06 10:53:39 -070057 timer_tick();
Vitaly Wool78818e42006-05-16 11:54:37 +010058
59 /*
60 * this algorithm takes care of possible delay
61 * for this interrupt handling longer than a normal
62 * timer period
63 */
64 __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
65 HSTIM_MATCH0);
66 __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
67
68 /*
69 * The goal is to keep incrementing HSTIM_MATCH0
70 * register until HSTIM_MATCH0 indicates time after
71 * what HSTIM_COUNTER indicates.
72 */
73 } while ((signed)
74 (__raw_readl(HSTIM_MATCH0) -
75 __raw_readl(HSTIM_COUNTER)) < 0);
Vitaly Wool78818e42006-05-16 11:54:37 +010076 }
77
78 return IRQ_HANDLED;
79}
80
81static struct irqaction pnx4008_timer_irq = {
82 .name = "PNX4008 Tick Timer",
Bernhard Walleb30faba2007-05-08 00:35:39 -070083 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Vitaly Wool78818e42006-05-16 11:54:37 +010084 .handler = pnx4008_timer_interrupt
85};
86
87/*!
88 * Set up timer and timer interrupt.
89 */
90static __init void pnx4008_setup_timer(void)
91{
92 __raw_writel(RESET_COUNT, MSTIM_CTRL);
93 while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
94 __raw_writel(0, MSTIM_CTRL); /* stop the timer */
95 __raw_writel(0, MSTIM_MCTRL);
96
97 __raw_writel(RESET_COUNT, HSTIM_CTRL);
98 while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
99 __raw_writel(0, HSTIM_CTRL);
100 __raw_writel(0, HSTIM_MCTRL);
101 __raw_writel(0, HSTIM_CCR);
102 __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
103 __raw_writel(LATCH, HSTIM_MATCH0);
104 __raw_writel(MR0_INT, HSTIM_MCTRL);
105
106 setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
107
108 __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */
109}
110
111/* Timer Clock Control in PM register */
112#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
113#define WATCHDOG_CLK_EN 1
114#define TIMER_CLK_EN 2 /* HS and MS timers? */
115
116static u32 timclk_ctrl_reg_save;
117
118void pnx4008_timer_suspend(void)
119{
120 timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
121 __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */
122}
123
124void pnx4008_timer_resume(void)
125{
126 __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */
127}
128
129struct sys_timer pnx4008_timer = {
130 .init = pnx4008_setup_timer,
131 .offset = pnx4008_gettimeoffset,
132 .suspend = pnx4008_timer_suspend,
133 .resume = pnx4008_timer_resume,
134};
135