blob: 4fe36d2e104930cc99cc7014b27614277d75c9f8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
Chris Wright6faf17f2009-08-28 13:00:06 -070028#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Yinghai Lu568ddef2010-01-22 01:02:21 -080030struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 unsigned long flags;
37};
38
39static void add_to_failed_list(struct resource_list_x *head,
40 struct pci_dev *dev, struct resource *res)
41{
42 struct resource_list_x *list = head;
43 struct resource_list_x *ln = list->next;
44 struct resource_list_x *tmp;
45
46 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
47 if (!tmp) {
48 pr_warning("add_to_failed_list: kmalloc() failed!\n");
49 return;
50 }
51
52 tmp->next = ln;
53 tmp->res = res;
54 tmp->dev = dev;
55 tmp->start = res->start;
56 tmp->end = res->end;
57 tmp->flags = res->flags;
58 list->next = tmp;
59}
60
61static void free_failed_list(struct resource_list_x *head)
62{
63 struct resource_list_x *list, *tmp;
64
65 for (list = head->next; list;) {
66 tmp = list;
67 list = list->next;
68 kfree(tmp);
69 }
70
71 head->next = NULL;
72}
73
Yinghai Lu6841ec62010-01-22 01:02:25 -080074static void __dev_sort_resources(struct pci_dev *dev,
75 struct resource_list *head)
Linus Torvalds1da177e2005-04-16 15:20:36 -070076{
Yinghai Lu6841ec62010-01-22 01:02:25 -080077 u16 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
Yinghai Lu6841ec62010-01-22 01:02:25 -080079 /* Don't touch classless devices or host bridges or ioapics. */
80 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
81 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
Yinghai Lu6841ec62010-01-22 01:02:25 -080083 /* Don't touch ioapic devices already enabled by firmware */
84 if (class == PCI_CLASS_SYSTEM_PIC) {
85 u16 command;
86 pci_read_config_word(dev, PCI_COMMAND, &command);
87 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
88 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 }
90
Yinghai Lu6841ec62010-01-22 01:02:25 -080091 pdev_sort_resources(dev, head);
92}
93
94static void __assign_resources_sorted(struct resource_list *head,
95 struct resource_list_x *fail_head)
96{
97 struct resource *res;
98 struct resource_list *list, *tmp;
99 int idx;
100
101 for (list = head->next; list;) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 res = list->res;
103 idx = res - &list->dev->resource[0];
Yinghai Lu9a928662010-02-28 15:49:39 -0800104
Rajesh Shah542df5d2005-04-28 00:25:50 -0700105 if (pci_assign_resource(list->dev, idx)) {
Yinghai Lu9a928662010-02-28 15:49:39 -0800106 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
107 /*
108 * if the failed res is for ROM BAR, and it will
109 * be enabled later, don't add it to the list
110 */
111 if (!((idx == PCI_ROM_RESOURCE) &&
112 (!(res->flags & IORESOURCE_ROM_ENABLE))))
113 add_to_failed_list(fail_head, list->dev, res);
114 }
Rajesh Shah542df5d2005-04-28 00:25:50 -0700115 res->start = 0;
Ivan Kokshaysky960b8462005-07-07 03:07:56 +0400116 res->end = 0;
Rajesh Shah542df5d2005-04-28 00:25:50 -0700117 res->flags = 0;
118 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 tmp = list;
120 list = list->next;
121 kfree(tmp);
122 }
123}
124
Yinghai Lu6841ec62010-01-22 01:02:25 -0800125static void pdev_assign_resources_sorted(struct pci_dev *dev,
126 struct resource_list_x *fail_head)
127{
128 struct resource_list head;
129
130 head.next = NULL;
131 __dev_sort_resources(dev, &head);
132 __assign_resources_sorted(&head, fail_head);
133
134}
135
136static void pbus_assign_resources_sorted(const struct pci_bus *bus,
137 struct resource_list_x *fail_head)
138{
139 struct pci_dev *dev;
140 struct resource_list head;
141
142 head.next = NULL;
143 list_for_each_entry(dev, &bus->devices, bus_list)
144 __dev_sort_resources(dev, &head);
145
146 __assign_resources_sorted(&head, fail_head);
147}
148
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700149void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150{
151 struct pci_dev *bridge = bus->self;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600152 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 struct pci_bus_region region;
154
Bjorn Helgaas865df572009-11-04 10:32:57 -0700155 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
156 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600158 res = bus->resource[0];
159 pcibios_resource_to_bus(bridge, &region, res);
160 if (res->flags & IORESOURCE_IO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161 /*
162 * The IO resource is allocated a range twice as large as it
163 * would normally need. This allows us to set both IO regs.
164 */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600165 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
167 region.start);
168 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
169 region.end);
170 }
171
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600172 res = bus->resource[1];
173 pcibios_resource_to_bus(bridge, &region, res);
174 if (res->flags & IORESOURCE_IO) {
175 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
177 region.start);
178 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
179 region.end);
180 }
181
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600182 res = bus->resource[2];
183 pcibios_resource_to_bus(bridge, &region, res);
184 if (res->flags & IORESOURCE_MEM) {
185 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
187 region.start);
188 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
189 region.end);
190 }
191
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600192 res = bus->resource[3];
193 pcibios_resource_to_bus(bridge, &region, res);
194 if (res->flags & IORESOURCE_MEM) {
195 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
197 region.start);
198 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
199 region.end);
200 }
201}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700202EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
204/* Initialize bridges with base/limit values we have collected.
205 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
206 requires that if there is no I/O ports or memory behind the
207 bridge, corresponding range must be turned off by writing base
208 value greater than limit to the bridge's base/limit registers.
209
210 Note: care must be taken when updating I/O base/limit registers
211 of bridges which support 32-bit I/O. This update requires two
212 config space writes, so it's quite possible that an I/O window of
213 the bridge will have some undesirable address (e.g. 0) after the
214 first write. Ditto 64-bit prefetchable MMIO. */
Yinghai Lu7cc59972009-12-22 15:02:21 -0800215static void pci_setup_bridge_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216{
217 struct pci_dev *bridge = bus->self;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600218 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 struct pci_bus_region region;
Yinghai Lu7cc59972009-12-22 15:02:21 -0800220 u32 l, io_upper16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221
222 /* Set up the top and bottom of the PCI I/O segment for this bus. */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600223 res = bus->resource[0];
224 pcibios_resource_to_bus(bridge, &region, res);
225 if (res->flags & IORESOURCE_IO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
227 l &= 0xffff0000;
228 l |= (region.start >> 8) & 0x00f0;
229 l |= region.end & 0xf000;
230 /* Set up upper 16 bits of I/O base/limit. */
231 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600232 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800233 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 /* Clear upper 16 bits of I/O base/limit. */
235 io_upper16 = 0;
236 l = 0x00f0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600237 dev_info(&bridge->dev, " bridge window [io disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 }
239 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
240 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
241 /* Update lower 16 bits of I/O base/limit. */
242 pci_write_config_dword(bridge, PCI_IO_BASE, l);
243 /* Update upper 16 bits of I/O base/limit. */
244 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800245}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246
Yinghai Lu7cc59972009-12-22 15:02:21 -0800247static void pci_setup_bridge_mmio(struct pci_bus *bus)
248{
249 struct pci_dev *bridge = bus->self;
250 struct resource *res;
251 struct pci_bus_region region;
252 u32 l;
253
254 /* Set up the top and bottom of the PCI Memory segment for this bus. */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600255 res = bus->resource[1];
256 pcibios_resource_to_bus(bridge, &region, res);
257 if (res->flags & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 l = (region.start >> 16) & 0xfff0;
259 l |= region.end & 0xfff00000;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600260 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800261 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 l = 0x0000fff0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600263 dev_info(&bridge->dev, " bridge window [mem disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 }
265 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800266}
267
268static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
269{
270 struct pci_dev *bridge = bus->self;
271 struct resource *res;
272 struct pci_bus_region region;
273 u32 l, bu, lu;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
275 /* Clear out the upper 32 bits of PREF limit.
276 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
277 disables PREF range, which is ok. */
278 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
279
280 /* Set up PREF base/limit. */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100281 bu = lu = 0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600282 res = bus->resource[2];
283 pcibios_resource_to_bus(bridge, &region, res);
284 if (res->flags & IORESOURCE_PREFETCH) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 l = (region.start >> 16) & 0xfff0;
286 l |= region.end & 0xfff00000;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600287 if (res->flags & IORESOURCE_MEM_64) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700288 bu = upper_32_bits(region.start);
289 lu = upper_32_bits(region.end);
Yinghai Lu1f82de12009-04-23 20:48:32 -0700290 }
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600291 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800292 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 l = 0x0000fff0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600294 dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 }
296 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
297
Alex Williamson59353ea2009-11-30 14:51:44 -0700298 /* Set the upper 32 bits of PREF base & limit. */
299 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
300 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800301}
302
303static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
304{
305 struct pci_dev *bridge = bus->self;
306
Yinghai Lu7cc59972009-12-22 15:02:21 -0800307 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
308 bus->secondary, bus->subordinate);
309
310 if (type & IORESOURCE_IO)
311 pci_setup_bridge_io(bus);
312
313 if (type & IORESOURCE_MEM)
314 pci_setup_bridge_mmio(bus);
315
316 if (type & IORESOURCE_PREFETCH)
317 pci_setup_bridge_mmio_pref(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318
319 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
320}
321
Yinghai Lu7cc59972009-12-22 15:02:21 -0800322static void pci_setup_bridge(struct pci_bus *bus)
323{
324 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
325 IORESOURCE_PREFETCH;
326
327 __pci_setup_bridge(bus, type);
328}
329
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330/* Check whether the bridge supports optional I/O and
331 prefetchable memory ranges. If not, the respective
332 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800333static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334{
335 u16 io;
336 u32 pmem;
337 struct pci_dev *bridge = bus->self;
338 struct resource *b_res;
339
340 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
341 b_res[1].flags |= IORESOURCE_MEM;
342
343 pci_read_config_word(bridge, PCI_IO_BASE, &io);
344 if (!io) {
345 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
346 pci_read_config_word(bridge, PCI_IO_BASE, &io);
347 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
348 }
349 if (io)
350 b_res[0].flags |= IORESOURCE_IO;
351 /* DECchip 21050 pass 2 errata: the bridge may miss an address
352 disconnect boundary by one PCI data phase.
353 Workaround: do not use prefetching on this device. */
354 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
355 return;
356 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
357 if (!pmem) {
358 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
359 0xfff0fff0);
360 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
361 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
362 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700363 if (pmem) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
Yinghai Lu99586102010-01-22 01:02:28 -0800365 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
366 PCI_PREF_RANGE_TYPE_64) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700367 b_res[2].flags |= IORESOURCE_MEM_64;
Yinghai Lu99586102010-01-22 01:02:28 -0800368 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
369 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700370 }
371
372 /* double check if bridge does support 64 bit pref */
373 if (b_res[2].flags & IORESOURCE_MEM_64) {
374 u32 mem_base_hi, tmp;
375 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
376 &mem_base_hi);
377 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
378 0xffffffff);
379 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
380 if (!tmp)
381 b_res[2].flags &= ~IORESOURCE_MEM_64;
382 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
383 mem_base_hi);
384 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385}
386
387/* Helper function for sizing routines: find first available
388 bus resource of a given type. Note: we intentionally skip
389 the bus resources which have already been assigned (that is,
390 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800391static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392{
393 int i;
394 struct resource *r;
395 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
396 IORESOURCE_PREFETCH;
397
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700398 pci_bus_for_each_resource(bus, r, i) {
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400399 if (r == &ioport_resource || r == &iomem_resource)
400 continue;
Jesse Barnes55a10982009-10-27 09:39:18 -0700401 if (r && (r->flags & type_mask) == type && !r->parent)
402 return r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 }
404 return NULL;
405}
406
407/* Sizing the IO windows of the PCI-PCI bridge is trivial,
408 since these windows have 4K granularity and the IO ranges
409 of non-bridge PCI devices are limited to 256 bytes.
410 We must be careful with the ISA aliasing though. */
Eric W. Biederman28760482009-09-09 14:09:24 -0700411static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412{
413 struct pci_dev *dev;
414 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
Yinghai Lud65245c2010-01-22 01:02:23 -0800415 unsigned long size = 0, size1 = 0, old_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416
417 if (!b_res)
418 return;
419
420 list_for_each_entry(dev, &bus->devices, bus_list) {
421 int i;
422
423 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
424 struct resource *r = &dev->resource[i];
425 unsigned long r_size;
426
427 if (r->parent || !(r->flags & IORESOURCE_IO))
428 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800429 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430
431 if (r_size < 0x400)
432 /* Might be re-aligned for ISA */
433 size += r_size;
434 else
435 size1 += r_size;
436 }
437 }
Eric W. Biederman28760482009-09-09 14:09:24 -0700438 if (size < min_size)
439 size = min_size;
Yinghai Lud65245c2010-01-22 01:02:23 -0800440 old_size = resource_size(b_res);
441 if (old_size == 1)
442 old_size = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443/* To be fixed in 2.5: we should have sort of HAVE_ISA
444 flag in the struct pci_bus. */
445#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
446 size = (size & 0xff) + ((size & ~0xffUL) << 2);
447#endif
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700448 size = ALIGN(size + size1, 4096);
Yinghai Lud65245c2010-01-22 01:02:23 -0800449 if (size < old_size)
450 size = old_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451 if (!size) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700452 if (b_res->start || b_res->end)
453 dev_info(&bus->self->dev, "disabling bridge window "
454 "%pR to [bus %02x-%02x] (unused)\n", b_res,
455 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 b_res->flags = 0;
457 return;
458 }
459 /* Alignment of the IO window is always 4K */
460 b_res->start = 4096;
461 b_res->end = b_res->start + size - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400462 b_res->flags |= IORESOURCE_STARTALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463}
464
465/* Calculate the size of the bus and minimal alignment which
466 guarantees that all child resources fit in this size. */
Eric W. Biederman28760482009-09-09 14:09:24 -0700467static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
468 unsigned long type, resource_size_t min_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469{
470 struct pci_dev *dev;
Yinghai Lud65245c2010-01-22 01:02:23 -0800471 resource_size_t min_align, align, size, old_size;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100472 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 int order, max_order;
474 struct resource *b_res = find_free_bus_resource(bus, type);
Yinghai Lu1f82de12009-04-23 20:48:32 -0700475 unsigned int mem64_mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
477 if (!b_res)
478 return 0;
479
480 memset(aligns, 0, sizeof(aligns));
481 max_order = 0;
482 size = 0;
483
Yinghai Lu1f82de12009-04-23 20:48:32 -0700484 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
485 b_res->flags &= ~IORESOURCE_MEM_64;
486
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487 list_for_each_entry(dev, &bus->devices, bus_list) {
488 int i;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700489
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
491 struct resource *r = &dev->resource[i];
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100492 resource_size_t r_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
494 if (r->parent || (r->flags & mask) != type)
495 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800496 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 /* For bridges size != alignment */
Chris Wright6faf17f2009-08-28 13:00:06 -0700498 align = pci_resource_alignment(dev, r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 order = __ffs(align) - 20;
500 if (order > 11) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700501 dev_warn(&dev->dev, "disabling BAR %d: %pR "
502 "(bad alignment %#llx)\n", i, r,
503 (unsigned long long) align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 r->flags = 0;
505 continue;
506 }
507 size += r_size;
508 if (order < 0)
509 order = 0;
510 /* Exclude ranges with size > align from
511 calculation of the alignment. */
512 if (r_size == align)
513 aligns[order] += align;
514 if (order > max_order)
515 max_order = order;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700516 mem64_mask &= r->flags & IORESOURCE_MEM_64;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 }
518 }
Eric W. Biederman28760482009-09-09 14:09:24 -0700519 if (size < min_size)
520 size = min_size;
Yinghai Lud65245c2010-01-22 01:02:23 -0800521 old_size = resource_size(b_res);
522 if (old_size == 1)
523 old_size = 0;
524 if (size < old_size)
525 size = old_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526
527 align = 0;
528 min_align = 0;
529 for (order = 0; order <= max_order; order++) {
Jeremy Fitzhardinge8308c542008-09-11 01:31:50 -0700530 resource_size_t align1 = 1;
531
532 align1 <<= (order + 20);
533
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 if (!align)
535 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700536 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 min_align = align1 >> 1;
538 align += aligns[order];
539 }
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700540 size = ALIGN(size, min_align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 if (!size) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700542 if (b_res->start || b_res->end)
543 dev_info(&bus->self->dev, "disabling bridge window "
544 "%pR to [bus %02x-%02x] (unused)\n", b_res,
545 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546 b_res->flags = 0;
547 return 1;
548 }
549 b_res->start = min_align;
550 b_res->end = size + min_align - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400551 b_res->flags |= IORESOURCE_STARTALIGN;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700552 b_res->flags |= mem64_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 return 1;
554}
555
Adrian Bunk5468ae62008-04-18 13:53:56 -0700556static void pci_bus_size_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557{
558 struct pci_dev *bridge = bus->self;
559 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
560 u16 ctrl;
561
562 /*
563 * Reserve some resources for CardBus. We reserve
564 * a fixed amount of bus space for CardBus bridges.
565 */
Linus Torvalds934b7022008-04-22 18:16:30 -0700566 b_res[0].start = 0;
567 b_res[0].end = pci_cardbus_io_size - 1;
568 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569
Linus Torvalds934b7022008-04-22 18:16:30 -0700570 b_res[1].start = 0;
571 b_res[1].end = pci_cardbus_io_size - 1;
572 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573
574 /*
575 * Check whether prefetchable memory is supported
576 * by this bridge.
577 */
578 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
579 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
580 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
581 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
582 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
583 }
584
585 /*
586 * If we have prefetchable memory support, allocate
587 * two regions. Otherwise, allocate one region of
588 * twice the size.
589 */
590 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Linus Torvalds934b7022008-04-22 18:16:30 -0700591 b_res[2].start = 0;
592 b_res[2].end = pci_cardbus_mem_size - 1;
593 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594
Linus Torvalds934b7022008-04-22 18:16:30 -0700595 b_res[3].start = 0;
596 b_res[3].end = pci_cardbus_mem_size - 1;
597 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 } else {
Linus Torvalds934b7022008-04-22 18:16:30 -0700599 b_res[3].start = 0;
600 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
601 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602 }
603}
604
Sam Ravnborg451124a2008-02-02 22:33:43 +0100605void __ref pci_bus_size_bridges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606{
607 struct pci_dev *dev;
608 unsigned long mask, prefmask;
Eric W. Biederman28760482009-09-09 14:09:24 -0700609 resource_size_t min_mem_size = 0, min_io_size = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610
611 list_for_each_entry(dev, &bus->devices, bus_list) {
612 struct pci_bus *b = dev->subordinate;
613 if (!b)
614 continue;
615
616 switch (dev->class >> 8) {
617 case PCI_CLASS_BRIDGE_CARDBUS:
618 pci_bus_size_cardbus(b);
619 break;
620
621 case PCI_CLASS_BRIDGE_PCI:
622 default:
623 pci_bus_size_bridges(b);
624 break;
625 }
626 }
627
628 /* The root bus? */
629 if (!bus->self)
630 return;
631
632 switch (bus->self->class >> 8) {
633 case PCI_CLASS_BRIDGE_CARDBUS:
634 /* don't size cardbuses yet. */
635 break;
636
637 case PCI_CLASS_BRIDGE_PCI:
638 pci_bridge_check_ranges(bus);
Eric W. Biederman28760482009-09-09 14:09:24 -0700639 if (bus->self->is_hotplug_bridge) {
640 min_io_size = pci_hotplug_io_size;
641 min_mem_size = pci_hotplug_mem_size;
642 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 default:
Eric W. Biederman28760482009-09-09 14:09:24 -0700644 pbus_size_io(bus, min_io_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 /* If the bridge supports prefetchable range, size it
646 separately. If it doesn't, or its prefetchable window
647 has already been allocated by arch code, try
648 non-prefetchable range for both types of PCI memory
649 resources. */
650 mask = IORESOURCE_MEM;
651 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
Eric W. Biederman28760482009-09-09 14:09:24 -0700652 if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 mask = prefmask; /* Success, size non-prefetch only. */
Eric W. Biederman28760482009-09-09 14:09:24 -0700654 else
655 min_mem_size += min_mem_size;
656 pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 break;
658 }
659}
660EXPORT_SYMBOL(pci_bus_size_bridges);
661
Yinghai Lu568ddef2010-01-22 01:02:21 -0800662static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
663 struct resource_list_x *fail_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664{
665 struct pci_bus *b;
666 struct pci_dev *dev;
667
Yinghai Lu568ddef2010-01-22 01:02:21 -0800668 pbus_assign_resources_sorted(bus, fail_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 list_for_each_entry(dev, &bus->devices, bus_list) {
671 b = dev->subordinate;
672 if (!b)
673 continue;
674
Yinghai Lu568ddef2010-01-22 01:02:21 -0800675 __pci_bus_assign_resources(b, fail_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676
677 switch (dev->class >> 8) {
678 case PCI_CLASS_BRIDGE_PCI:
Yinghai Lu6841ec62010-01-22 01:02:25 -0800679 if (!pci_is_enabled(dev))
680 pci_setup_bridge(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681 break;
682
683 case PCI_CLASS_BRIDGE_CARDBUS:
684 pci_setup_cardbus(b);
685 break;
686
687 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600688 dev_info(&dev->dev, "not setting up bridge for bus "
689 "%04x:%02x\n", pci_domain_nr(b), b->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690 break;
691 }
692 }
693}
Yinghai Lu568ddef2010-01-22 01:02:21 -0800694
695void __ref pci_bus_assign_resources(const struct pci_bus *bus)
696{
697 __pci_bus_assign_resources(bus, NULL);
698}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699EXPORT_SYMBOL(pci_bus_assign_resources);
700
Yinghai Lu6841ec62010-01-22 01:02:25 -0800701static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
702 struct resource_list_x *fail_head)
703{
704 struct pci_bus *b;
705
706 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
707
708 b = bridge->subordinate;
709 if (!b)
710 return;
711
712 __pci_bus_assign_resources(b, fail_head);
713
714 switch (bridge->class >> 8) {
715 case PCI_CLASS_BRIDGE_PCI:
716 pci_setup_bridge(b);
717 break;
718
719 case PCI_CLASS_BRIDGE_CARDBUS:
720 pci_setup_cardbus(b);
721 break;
722
723 default:
724 dev_info(&bridge->dev, "not setting up bridge for bus "
725 "%04x:%02x\n", pci_domain_nr(b), b->number);
726 break;
727 }
728}
Yinghai Lu5009b462010-01-22 01:02:20 -0800729static void pci_bridge_release_resources(struct pci_bus *bus,
730 unsigned long type)
731{
732 int idx;
733 bool changed = false;
734 struct pci_dev *dev;
735 struct resource *r;
736 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
737 IORESOURCE_PREFETCH;
738
739 dev = bus->self;
740 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
741 idx++) {
742 r = &dev->resource[idx];
743 if ((r->flags & type_mask) != type)
744 continue;
745 if (!r->parent)
746 continue;
747 /*
748 * if there are children under that, we should release them
749 * all
750 */
751 release_child_resources(r);
752 if (!release_resource(r)) {
753 dev_printk(KERN_DEBUG, &dev->dev,
754 "resource %d %pR released\n", idx, r);
755 /* keep the old size */
756 r->end = resource_size(r) - 1;
757 r->start = 0;
758 r->flags = 0;
759 changed = true;
760 }
761 }
762
763 if (changed) {
764 /* avoiding touch the one without PREF */
765 if (type & IORESOURCE_PREFETCH)
766 type = IORESOURCE_PREFETCH;
767 __pci_setup_bridge(bus, type);
768 }
769}
770
771enum release_type {
772 leaf_only,
773 whole_subtree,
774};
775/*
776 * try to release pci bridge resources that is from leaf bridge,
777 * so we can allocate big new one later
778 */
779static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
780 unsigned long type,
781 enum release_type rel_type)
782{
783 struct pci_dev *dev;
784 bool is_leaf_bridge = true;
785
786 list_for_each_entry(dev, &bus->devices, bus_list) {
787 struct pci_bus *b = dev->subordinate;
788 if (!b)
789 continue;
790
791 is_leaf_bridge = false;
792
793 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
794 continue;
795
796 if (rel_type == whole_subtree)
797 pci_bus_release_bridge_resources(b, type,
798 whole_subtree);
799 }
800
801 if (pci_is_root_bus(bus))
802 return;
803
804 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
805 return;
806
807 if ((rel_type == whole_subtree) || is_leaf_bridge)
808 pci_bridge_release_resources(bus, type);
809}
810
Yinghai Lu76fbc262008-06-23 20:33:06 +0200811static void pci_bus_dump_res(struct pci_bus *bus)
812{
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700813 struct resource *res;
814 int i;
Yinghai Lu76fbc262008-06-23 20:33:06 +0200815
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700816 pci_bus_for_each_resource(bus, res, i) {
Yinghai Lu7c9342b2009-12-22 15:02:24 -0800817 if (!res || !res->end || !res->flags)
Yinghai Lu76fbc262008-06-23 20:33:06 +0200818 continue;
819
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600820 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
Yinghai Lu76fbc262008-06-23 20:33:06 +0200821 }
822}
823
824static void pci_bus_dump_resources(struct pci_bus *bus)
825{
826 struct pci_bus *b;
827 struct pci_dev *dev;
828
829
830 pci_bus_dump_res(bus);
831
832 list_for_each_entry(dev, &bus->devices, bus_list) {
833 b = dev->subordinate;
834 if (!b)
835 continue;
836
837 pci_bus_dump_resources(b);
838 }
839}
840
Yinghai Lu977d17b2010-01-22 01:02:24 -0800841static int __init pci_bus_get_depth(struct pci_bus *bus)
842{
843 int depth = 0;
844 struct pci_dev *dev;
845
846 list_for_each_entry(dev, &bus->devices, bus_list) {
847 int ret;
848 struct pci_bus *b = dev->subordinate;
849 if (!b)
850 continue;
851
852 ret = pci_bus_get_depth(b);
853 if (ret + 1 > depth)
854 depth = ret + 1;
855 }
856
857 return depth;
858}
859static int __init pci_get_max_depth(void)
860{
861 int depth = 0;
862 struct pci_bus *bus;
863
864 list_for_each_entry(bus, &pci_root_buses, node) {
865 int ret;
866
867 ret = pci_bus_get_depth(bus);
868 if (ret > depth)
869 depth = ret;
870 }
871
872 return depth;
873}
874
875/*
876 * first try will not touch pci bridge res
877 * second and later try will clear small leaf bridge res
878 * will stop till to the max deepth if can not find good one
879 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880void __init
881pci_assign_unassigned_resources(void)
882{
883 struct pci_bus *bus;
Yinghai Lu977d17b2010-01-22 01:02:24 -0800884 int tried_times = 0;
885 enum release_type rel_type = leaf_only;
886 struct resource_list_x head, *list;
887 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
888 IORESOURCE_PREFETCH;
889 unsigned long failed_type;
890 int max_depth = pci_get_max_depth();
891 int pci_try_num;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892
Yinghai Lu977d17b2010-01-22 01:02:24 -0800893 head.next = NULL;
894
895 pci_try_num = max_depth + 1;
896 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
897 max_depth, pci_try_num);
898
899again:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 /* Depth first, calculate sizes and alignments of all
901 subordinate buses. */
902 list_for_each_entry(bus, &pci_root_buses, node) {
903 pci_bus_size_bridges(bus);
904 }
905 /* Depth last, allocate resources and update the hardware. */
906 list_for_each_entry(bus, &pci_root_buses, node) {
Yinghai Lu977d17b2010-01-22 01:02:24 -0800907 __pci_bus_assign_resources(bus, &head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700908 }
Yinghai Lu977d17b2010-01-22 01:02:24 -0800909 tried_times++;
910
911 /* any device complain? */
912 if (!head.next)
913 goto enable_and_dump;
914 failed_type = 0;
915 for (list = head.next; list;) {
916 failed_type |= list->flags;
917 list = list->next;
918 }
919 /*
920 * io port are tight, don't try extra
921 * or if reach the limit, don't want to try more
922 */
923 failed_type &= type_mask;
924 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
925 free_failed_list(&head);
926 goto enable_and_dump;
927 }
928
929 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
930 tried_times + 1);
931
932 /* third times and later will not check if it is leaf */
933 if ((tried_times + 1) > 2)
934 rel_type = whole_subtree;
935
936 /*
937 * Try to release leaf bridge's resources that doesn't fit resource of
938 * child device under that bridge
939 */
940 for (list = head.next; list;) {
941 bus = list->dev->bus;
942 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
943 rel_type);
944 list = list->next;
945 }
946 /* restore size and flags */
947 for (list = head.next; list;) {
948 struct resource *res = list->res;
949
950 res->start = list->start;
951 res->end = list->end;
952 res->flags = list->flags;
953 if (list->dev->subordinate)
954 res->flags = 0;
955
956 list = list->next;
957 }
958 free_failed_list(&head);
959
960 goto again;
961
962enable_and_dump:
963 /* Depth last, update the hardware. */
964 list_for_each_entry(bus, &pci_root_buses, node)
965 pci_enable_bridges(bus);
Yinghai Lu76fbc262008-06-23 20:33:06 +0200966
967 /* dump the resource on buses */
968 list_for_each_entry(bus, &pci_root_buses, node) {
969 pci_bus_dump_resources(bus);
970 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971}
Yinghai Lu6841ec62010-01-22 01:02:25 -0800972
973void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
974{
975 struct pci_bus *parent = bridge->subordinate;
Yinghai Lu32180e42010-01-22 01:02:27 -0800976 int tried_times = 0;
977 struct resource_list_x head, *list;
Yinghai Lu6841ec62010-01-22 01:02:25 -0800978 int retval;
Yinghai Lu32180e42010-01-22 01:02:27 -0800979 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
980 IORESOURCE_PREFETCH;
Yinghai Lu6841ec62010-01-22 01:02:25 -0800981
Yinghai Lu32180e42010-01-22 01:02:27 -0800982 head.next = NULL;
983
984again:
Yinghai Lu6841ec62010-01-22 01:02:25 -0800985 pci_bus_size_bridges(parent);
Yinghai Lu32180e42010-01-22 01:02:27 -0800986 __pci_bridge_assign_resources(bridge, &head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800987 retval = pci_reenable_device(bridge);
988 pci_set_master(bridge);
989 pci_enable_bridges(parent);
Yinghai Lu32180e42010-01-22 01:02:27 -0800990
991 tried_times++;
992
993 if (!head.next)
994 return;
995
996 if (tried_times >= 2) {
997 /* still fail, don't need to try more */
998 free_failed_list(&head);
999 return;
1000 }
1001
1002 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1003 tried_times + 1);
1004
1005 /*
1006 * Try to release leaf bridge's resources that doesn't fit resource of
1007 * child device under that bridge
1008 */
1009 for (list = head.next; list;) {
1010 struct pci_bus *bus = list->dev->bus;
1011 unsigned long flags = list->flags;
1012
1013 pci_bus_release_bridge_resources(bus, flags & type_mask,
1014 whole_subtree);
1015 list = list->next;
1016 }
1017 /* restore size and flags */
1018 for (list = head.next; list;) {
1019 struct resource *res = list->res;
1020
1021 res->start = list->start;
1022 res->end = list->end;
1023 res->flags = list->flags;
1024 if (list->dev->subordinate)
1025 res->flags = 0;
1026
1027 list = list->next;
1028 }
1029 free_failed_list(&head);
1030
1031 goto again;
Yinghai Lu6841ec62010-01-22 01:02:25 -08001032}
1033EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);