blob: 01bc9dd3f64fbaafbc1105888efb4384d1794a6d [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070029#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030
31#include "clock-local.h"
32#include "clock-rpm.h"
33#include "clock-voter.h"
34#include "clock-dss-8960.h"
35#include "devices.h"
Vikram Mulukutla681d8682012-03-09 23:56:20 -080036#include "clock-pll.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070037
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080044#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Tianyi Gou352955d2012-05-18 19:44:01 -070045#define SFAB_SATA_S_HCLK_CTL_REG REG(0x2480)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070046#define CE1_HCLK_CTL_REG REG(0x2720)
47#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou05e01102012-02-08 22:15:49 -080048#define PRNG_CLK_NS_REG REG(0x2E80)
Tianyi Gou41515e22011-09-01 19:37:43 -070049#define CE3_HCLK_CTL_REG REG(0x36C4)
50#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
51#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou6613de52012-01-27 17:57:53 -080053#define CLK_HALT_AFAB_SFAB_STATEA_REG REG(0x2FC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070054#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070055#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
56#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
57#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
58#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070059/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
61#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070062#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070064#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
65#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
67#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
68#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
69#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
70#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
71#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070072#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070073/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#define BB_PLL_ENA_SC0_REG REG(0x34C0)
Tianyi Gou59608a72012-01-31 22:19:30 -080075#define BB_PLL_ENA_RPM_REG REG(0x34A0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#define BB_PLL0_STATUS_REG REG(0x30D8)
77#define BB_PLL5_STATUS_REG REG(0x30F8)
78#define BB_PLL6_STATUS_REG REG(0x3118)
79#define BB_PLL7_STATUS_REG REG(0x3138)
80#define BB_PLL8_L_VAL_REG REG(0x3144)
81#define BB_PLL8_M_VAL_REG REG(0x3148)
82#define BB_PLL8_MODE_REG REG(0x3140)
83#define BB_PLL8_N_VAL_REG REG(0x314C)
84#define BB_PLL8_STATUS_REG REG(0x3158)
85#define BB_PLL8_CONFIG_REG REG(0x3154)
86#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070087#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
88#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070089#define BB_PLL14_MODE_REG REG(0x31C0)
90#define BB_PLL14_L_VAL_REG REG(0x31C4)
91#define BB_PLL14_M_VAL_REG REG(0x31C8)
92#define BB_PLL14_N_VAL_REG REG(0x31CC)
93#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
94#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070095#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070096#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
97#define PMEM_ACLK_CTL_REG REG(0x25A0)
98#define RINGOSC_NS_REG REG(0x2DC0)
99#define RINGOSC_STATUS_REG REG(0x2DCC)
100#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -0800101#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700102#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
103#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
104#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
105#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
106#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
107#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
108#define TSIF_HCLK_CTL_REG REG(0x2700)
109#define TSIF_REF_CLK_MD_REG REG(0x270C)
110#define TSIF_REF_CLK_NS_REG REG(0x2710)
111#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou352955d2012-05-18 19:44:01 -0700112#define SATA_HCLK_CTL_REG REG(0x2C00)
Tianyi Gou41515e22011-09-01 19:37:43 -0700113#define SATA_CLK_SRC_NS_REG REG(0x2C08)
114#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
115#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
116#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
Tianyi Gou352955d2012-05-18 19:44:01 -0700117#define SATA_ACLK_CTL_REG REG(0x2C20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700118#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700119#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
120#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
121#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
122#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
123#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
124#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700125#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700126#define USB_HS1_RESET_REG REG(0x2910)
127#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
128#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700129#define USB_HS3_HCLK_CTL_REG REG(0x3700)
130#define USB_HS3_HCLK_FS_REG REG(0x3704)
131#define USB_HS3_RESET_REG REG(0x3710)
132#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
133#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
134#define USB_HS4_HCLK_CTL_REG REG(0x3720)
135#define USB_HS4_HCLK_FS_REG REG(0x3724)
136#define USB_HS4_RESET_REG REG(0x3730)
137#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
138#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700139#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
140#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
141#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
142#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
143#define USB_HSIC_RESET_REG REG(0x2934)
144#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
145#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
146#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700147#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700148#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
Tianyi Gou6613de52012-01-27 17:57:53 -0800149#define PCIE_ACLK_CTL_REG REG(0x22C0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700150#define PCIE_HCLK_CTL_REG REG(0x22CC)
Tianyi Gou6613de52012-01-27 17:57:53 -0800151#define PCIE_PCLK_CTL_REG REG(0x22D0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700152#define GPLL1_MODE_REG REG(0x3160)
153#define GPLL1_L_VAL_REG REG(0x3164)
154#define GPLL1_M_VAL_REG REG(0x3168)
155#define GPLL1_N_VAL_REG REG(0x316C)
156#define GPLL1_CONFIG_REG REG(0x3174)
157#define GPLL1_STATUS_REG REG(0x3178)
158#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700159
160/* Multimedia clock registers. */
161#define AHB_EN_REG REG_MM(0x0008)
162#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700163#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700164#define AHB_NS_REG REG_MM(0x0004)
165#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700166#define CAMCLK0_NS_REG REG_MM(0x0148)
167#define CAMCLK0_CC_REG REG_MM(0x0140)
168#define CAMCLK0_MD_REG REG_MM(0x0144)
169#define CAMCLK1_NS_REG REG_MM(0x015C)
170#define CAMCLK1_CC_REG REG_MM(0x0154)
171#define CAMCLK1_MD_REG REG_MM(0x0158)
172#define CAMCLK2_NS_REG REG_MM(0x0228)
173#define CAMCLK2_CC_REG REG_MM(0x0220)
174#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700175#define CSI0_NS_REG REG_MM(0x0048)
176#define CSI0_CC_REG REG_MM(0x0040)
177#define CSI0_MD_REG REG_MM(0x0044)
178#define CSI1_NS_REG REG_MM(0x0010)
179#define CSI1_CC_REG REG_MM(0x0024)
180#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700181#define CSI2_NS_REG REG_MM(0x0234)
182#define CSI2_CC_REG REG_MM(0x022C)
183#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700184#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
185#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
186#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
187#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
188#define DSI1_BYTE_CC_REG REG_MM(0x0090)
189#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
190#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
191#define DSI1_ESC_NS_REG REG_MM(0x011C)
192#define DSI1_ESC_CC_REG REG_MM(0x00CC)
193#define DSI2_ESC_NS_REG REG_MM(0x0150)
194#define DSI2_ESC_CC_REG REG_MM(0x013C)
195#define DSI_PIXEL_CC_REG REG_MM(0x0130)
196#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
Patrick Dalye6f489042012-07-11 15:29:15 -0700197#define DSI2_PIXEL_CC2_REG REG_MM(0x0264)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700198#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
199#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
200#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
201#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
202#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
203#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
204#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
205#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
206#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700207#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700208#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
209#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
210#define GFX2D0_CC_REG REG_MM(0x0060)
211#define GFX2D0_MD0_REG REG_MM(0x0064)
212#define GFX2D0_MD1_REG REG_MM(0x0068)
213#define GFX2D0_NS_REG REG_MM(0x0070)
214#define GFX2D1_CC_REG REG_MM(0x0074)
215#define GFX2D1_MD0_REG REG_MM(0x0078)
216#define GFX2D1_MD1_REG REG_MM(0x006C)
217#define GFX2D1_NS_REG REG_MM(0x007C)
218#define GFX3D_CC_REG REG_MM(0x0080)
219#define GFX3D_MD0_REG REG_MM(0x0084)
220#define GFX3D_MD1_REG REG_MM(0x0088)
221#define GFX3D_NS_REG REG_MM(0x008C)
222#define IJPEG_CC_REG REG_MM(0x0098)
223#define IJPEG_MD_REG REG_MM(0x009C)
224#define IJPEG_NS_REG REG_MM(0x00A0)
225#define JPEGD_CC_REG REG_MM(0x00A4)
226#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700227#define VCAP_CC_REG REG_MM(0x0178)
228#define VCAP_NS_REG REG_MM(0x021C)
229#define VCAP_MD0_REG REG_MM(0x01EC)
230#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700231#define MAXI_EN_REG REG_MM(0x0018)
232#define MAXI_EN2_REG REG_MM(0x0020)
233#define MAXI_EN3_REG REG_MM(0x002C)
234#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700235#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700236#define MDP_CC_REG REG_MM(0x00C0)
237#define MDP_LUT_CC_REG REG_MM(0x016C)
238#define MDP_MD0_REG REG_MM(0x00C4)
239#define MDP_MD1_REG REG_MM(0x00C8)
240#define MDP_NS_REG REG_MM(0x00D0)
241#define MISC_CC_REG REG_MM(0x0058)
242#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700243#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700244#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700245#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
246#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
247#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
248#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
249#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
250#define MM_PLL1_STATUS_REG REG_MM(0x0334)
251#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700252#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
253#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
254#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
255#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
256#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
257#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700258#define ROT_CC_REG REG_MM(0x00E0)
259#define ROT_NS_REG REG_MM(0x00E8)
260#define SAXI_EN_REG REG_MM(0x0030)
261#define SW_RESET_AHB_REG REG_MM(0x020C)
262#define SW_RESET_AHB2_REG REG_MM(0x0200)
263#define SW_RESET_ALL_REG REG_MM(0x0204)
264#define SW_RESET_AXI_REG REG_MM(0x0208)
265#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700266#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700267#define TV_CC_REG REG_MM(0x00EC)
268#define TV_CC2_REG REG_MM(0x0124)
269#define TV_MD_REG REG_MM(0x00F0)
270#define TV_NS_REG REG_MM(0x00F4)
271#define VCODEC_CC_REG REG_MM(0x00F8)
272#define VCODEC_MD0_REG REG_MM(0x00FC)
273#define VCODEC_MD1_REG REG_MM(0x0128)
274#define VCODEC_NS_REG REG_MM(0x0100)
275#define VFE_CC_REG REG_MM(0x0104)
276#define VFE_MD_REG REG_MM(0x0108)
277#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700278#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700279#define VPE_CC_REG REG_MM(0x0110)
280#define VPE_NS_REG REG_MM(0x0118)
281
282/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700283#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700284#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
285#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
286#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
287#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
288#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
289#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
290#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
291#define LCC_MI2S_MD_REG REG_LPA(0x004C)
292#define LCC_MI2S_NS_REG REG_LPA(0x0048)
293#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
294#define LCC_PCM_MD_REG REG_LPA(0x0058)
295#define LCC_PCM_NS_REG REG_LPA(0x0054)
296#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700297#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
298#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
299#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
300#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
301#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700302#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700303#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
304#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
305#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
306#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
307#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
308#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
309#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
310#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
311#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
312#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700313#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700314
Matt Wagantall8b38f942011-08-02 18:23:18 -0700315#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
316
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700317/* MUX source input identifiers. */
318#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700319#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700320#define pll0_to_bb_mux 2
321#define pll8_to_bb_mux 3
322#define pll6_to_bb_mux 4
323#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700324#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700325#define pxo_to_mm_mux 0
326#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700327#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
328#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700329#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700330#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700331#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700332#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700333#define hdmi_pll_to_mm_mux 3
334#define cxo_to_xo_mux 0
335#define pxo_to_xo_mux 1
336#define gnd_to_xo_mux 3
337#define pxo_to_lpa_mux 0
338#define cxo_to_lpa_mux 1
339#define pll4_to_lpa_mux 2
340#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700341#define pxo_to_pcie_mux 0
342#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700343
344/* Test Vector Macros */
345#define TEST_TYPE_PER_LS 1
346#define TEST_TYPE_PER_HS 2
347#define TEST_TYPE_MM_LS 3
348#define TEST_TYPE_MM_HS 4
349#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700350#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700351#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700352#define TEST_TYPE_SHIFT 24
353#define TEST_CLK_SEL_MASK BM(23, 0)
354#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
355#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
356#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
357#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
358#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
359#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700360#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700361#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700362
363#define MN_MODE_DUAL_EDGE 0x2
364
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700365struct pll_rate {
366 const uint32_t l_val;
367 const uint32_t m_val;
368 const uint32_t n_val;
369 const uint32_t vco;
370 const uint32_t post_div;
371 const uint32_t i_bits;
372};
373#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
374
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700375enum vdd_dig_levels {
376 VDD_DIG_NONE,
377 VDD_DIG_LOW,
378 VDD_DIG_NOMINAL,
379 VDD_DIG_HIGH
380};
381
Saravana Kannan298ec392012-02-08 19:21:47 -0800382static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700383{
384 static const int vdd_uv[] = {
385 [VDD_DIG_NONE] = 0,
386 [VDD_DIG_LOW] = 945000,
387 [VDD_DIG_NOMINAL] = 1050000,
388 [VDD_DIG_HIGH] = 1150000
389 };
Saravana Kannan298ec392012-02-08 19:21:47 -0800390 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700391 vdd_uv[level], 1150000, 1);
392}
393
Saravana Kannan298ec392012-02-08 19:21:47 -0800394static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960);
395
Patrick Daly1a3859f2012-08-27 16:10:26 -0700396static int rpm_vreg_dig_8930 = RPM_VREG_ID_PM8038_VDD_DIG_CORNER;
Saravana Kannan298ec392012-02-08 19:21:47 -0800397static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level)
398{
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800399 static const int vdd_corner[] = {
400 [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE,
401 [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW,
402 [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL,
403 [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH,
Saravana Kannan298ec392012-02-08 19:21:47 -0800404 };
Patrick Daly1a3859f2012-08-27 16:10:26 -0700405 return rpm_vreg_set_voltage(rpm_vreg_dig_8930,
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800406 RPM_VREG_VOTER3,
407 vdd_corner[level],
408 RPM_VREG_CORNER_HIGH, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800409}
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700410
411#define VDD_DIG_FMAX_MAP1(l1, f1) \
412 .vdd_class = &vdd_dig, \
413 .fmax[VDD_DIG_##l1] = (f1)
414#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
415 .vdd_class = &vdd_dig, \
416 .fmax[VDD_DIG_##l1] = (f1), \
417 .fmax[VDD_DIG_##l2] = (f2)
418#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
419 .vdd_class = &vdd_dig, \
420 .fmax[VDD_DIG_##l1] = (f1), \
421 .fmax[VDD_DIG_##l2] = (f2), \
422 .fmax[VDD_DIG_##l3] = (f3)
423
Matt Wagantall82feaa12012-07-09 10:54:49 -0700424enum vdd_sr2_hdmi_pll_levels {
425 VDD_SR2_HDMI_PLL_OFF,
426 VDD_SR2_HDMI_PLL_ON
Matt Wagantallc57577d2011-10-06 17:06:53 -0700427};
428
Matt Wagantall82feaa12012-07-09 10:54:49 -0700429static int set_vdd_sr2_hdmi_pll_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantallc57577d2011-10-06 17:06:53 -0700430{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800431 int rc = 0;
Saravana Kannan298ec392012-02-08 19:21:47 -0800432
Matt Wagantall82feaa12012-07-09 10:54:49 -0700433 if (level == VDD_SR2_HDMI_PLL_OFF) {
Saravana Kannan298ec392012-02-08 19:21:47 -0800434 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
435 RPM_VREG_VOTER3, 0, 0, 1);
436 if (rc)
437 return rc;
438 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
439 RPM_VREG_VOTER3, 0, 0, 1);
440 if (rc)
441 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
442 RPM_VREG_VOTER3, 1800000, 1800000, 1);
Tianyi Goue1faaf22012-01-24 16:07:19 -0800443 } else {
Saravana Kannan298ec392012-02-08 19:21:47 -0800444 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
David Collins9a81d6c2012-03-29 15:11:33 -0700445 RPM_VREG_VOTER3, 2050000, 2100000, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800446 if (rc)
447 return rc;
448 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
449 RPM_VREG_VOTER3, 1800000, 1800000, 1);
450 if (rc)
451 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800452 RPM_VREG_VOTER3, 0, 0, 1);
Matt Wagantallc57577d2011-10-06 17:06:53 -0700453 }
454
455 return rc;
456}
457
Matt Wagantall82feaa12012-07-09 10:54:49 -0700458static DEFINE_VDD_CLASS(vdd_sr2_hdmi_pll, set_vdd_sr2_hdmi_pll_8960);
Saravana Kannan298ec392012-02-08 19:21:47 -0800459
460static int sr2_lreg_uv[] = {
Matt Wagantall82feaa12012-07-09 10:54:49 -0700461 [VDD_SR2_HDMI_PLL_OFF] = 0,
462 [VDD_SR2_HDMI_PLL_ON] = 1800000,
Saravana Kannan298ec392012-02-08 19:21:47 -0800463};
464
Matt Wagantall82feaa12012-07-09 10:54:49 -0700465static int set_vdd_sr2_hdmi_pll_8064(struct clk_vdd_class *vdd_class, int level)
Saravana Kannan298ec392012-02-08 19:21:47 -0800466{
467 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3,
468 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
469}
470
Patrick Daly1a3859f2012-08-27 16:10:26 -0700471static int set_vdd_sr2_hdmi_pll_8930_pm8917(struct clk_vdd_class *vdd_class,
472 int level)
473{
474 int rc = 0;
475
476 if (level == VDD_SR2_HDMI_PLL_OFF) {
477 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8917_L23,
478 RPM_VREG_VOTER3, 0, 0, 1);
479 if (rc)
480 return rc;
481 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8917_S8,
482 RPM_VREG_VOTER3, 0, 0, 1);
483 if (rc)
484 rpm_vreg_set_voltage(RPM_VREG_ID_PM8917_L23,
485 RPM_VREG_VOTER3, 1800000, 1800000, 1);
486 } else {
487 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8917_S8,
488 RPM_VREG_VOTER3, 2050000, 2100000, 1);
489 if (rc)
490 return rc;
491 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8917_L23,
492 RPM_VREG_VOTER3, 1800000, 1800000, 1);
493 if (rc)
494 rpm_vreg_set_voltage(RPM_VREG_ID_PM8917_S8,
495 RPM_VREG_VOTER3, 0, 0, 1);
496 }
497
498 return rc;
499}
500
Matt Wagantall82feaa12012-07-09 10:54:49 -0700501static int set_vdd_sr2_hdmi_pll_8930(struct clk_vdd_class *vdd_class, int level)
Saravana Kannan298ec392012-02-08 19:21:47 -0800502{
503 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3,
504 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
505}
Matt Wagantallc57577d2011-10-06 17:06:53 -0700506
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700507/*
508 * Clock Descriptions
509 */
510
Stephen Boyd72a80352012-01-26 15:57:38 -0800511DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000);
512DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700513
514static struct pll_clk pll2_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700515 .mode_reg = MM_PLL1_MODE_REG,
516 .parent = &pxo_clk.c,
517 .c = {
518 .dbg_name = "pll2_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800519 .rate = 800000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800520 .ops = &clk_ops_local_pll,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700521 CLK_INIT(pll2_clk.c),
522 },
523};
524
Stephen Boyd94625ef2011-07-12 17:06:01 -0700525static struct pll_clk pll3_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700526 .mode_reg = BB_MMCC_PLL2_MODE_REG,
527 .parent = &pxo_clk.c,
528 .c = {
529 .dbg_name = "pll3_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800530 .rate = 1200000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800531 .ops = &clk_ops_local_pll,
Matt Wagantall82feaa12012-07-09 10:54:49 -0700532 .vdd_class = &vdd_sr2_hdmi_pll,
533 .fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700534 CLK_INIT(pll3_clk.c),
535 },
536};
537
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700538static struct pll_vote_clk pll4_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700539 .en_reg = BB_PLL_ENA_SC0_REG,
540 .en_mask = BIT(4),
541 .status_reg = LCC_PLL0_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800542 .status_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700543 .parent = &pxo_clk.c,
544 .c = {
545 .dbg_name = "pll4_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800546 .rate = 393216000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700547 .ops = &clk_ops_pll_vote,
548 CLK_INIT(pll4_clk.c),
549 },
550};
551
552static struct pll_vote_clk pll8_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700553 .en_reg = BB_PLL_ENA_SC0_REG,
554 .en_mask = BIT(8),
555 .status_reg = BB_PLL8_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800556 .status_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700557 .parent = &pxo_clk.c,
558 .c = {
559 .dbg_name = "pll8_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800560 .rate = 384000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700561 .ops = &clk_ops_pll_vote,
562 CLK_INIT(pll8_clk.c),
563 },
564};
565
Stephen Boyd94625ef2011-07-12 17:06:01 -0700566static struct pll_vote_clk pll14_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700567 .en_reg = BB_PLL_ENA_SC0_REG,
568 .en_mask = BIT(14),
569 .status_reg = BB_PLL14_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800570 .status_mask = BIT(16),
Stephen Boyd94625ef2011-07-12 17:06:01 -0700571 .parent = &pxo_clk.c,
572 .c = {
573 .dbg_name = "pll14_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800574 .rate = 480000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700575 .ops = &clk_ops_pll_vote,
576 CLK_INIT(pll14_clk.c),
577 },
578};
579
Tianyi Gou41515e22011-09-01 19:37:43 -0700580static struct pll_clk pll15_clk = {
Tianyi Gou41515e22011-09-01 19:37:43 -0700581 .mode_reg = MM_PLL3_MODE_REG,
582 .parent = &pxo_clk.c,
583 .c = {
584 .dbg_name = "pll15_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800585 .rate = 975000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800586 .ops = &clk_ops_local_pll,
Tianyi Gou41515e22011-09-01 19:37:43 -0700587 CLK_INIT(pll15_clk.c),
588 },
589};
590
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700591/* AXI Interfaces */
592static struct branch_clk gmem_axi_clk = {
593 .b = {
594 .ctl_reg = MAXI_EN_REG,
595 .en_mask = BIT(24),
596 .halt_reg = DBG_BUS_VEC_E_REG,
597 .halt_bit = 6,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800598 .retain_reg = MAXI_EN2_REG,
599 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700600 },
601 .c = {
602 .dbg_name = "gmem_axi_clk",
603 .ops = &clk_ops_branch,
604 CLK_INIT(gmem_axi_clk.c),
605 },
606};
607
608static struct branch_clk ijpeg_axi_clk = {
609 .b = {
610 .ctl_reg = MAXI_EN_REG,
611 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800612 .hwcg_reg = MAXI_EN_REG,
613 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700614 .reset_reg = SW_RESET_AXI_REG,
615 .reset_mask = BIT(14),
616 .halt_reg = DBG_BUS_VEC_E_REG,
617 .halt_bit = 4,
618 },
619 .c = {
620 .dbg_name = "ijpeg_axi_clk",
621 .ops = &clk_ops_branch,
622 CLK_INIT(ijpeg_axi_clk.c),
623 },
624};
625
626static struct branch_clk imem_axi_clk = {
627 .b = {
628 .ctl_reg = MAXI_EN_REG,
629 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800630 .hwcg_reg = MAXI_EN_REG,
631 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700632 .reset_reg = SW_RESET_CORE_REG,
633 .reset_mask = BIT(10),
634 .halt_reg = DBG_BUS_VEC_E_REG,
635 .halt_bit = 7,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800636 .retain_reg = MAXI_EN2_REG,
637 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700638 },
639 .c = {
640 .dbg_name = "imem_axi_clk",
641 .ops = &clk_ops_branch,
642 CLK_INIT(imem_axi_clk.c),
643 },
644};
645
646static struct branch_clk jpegd_axi_clk = {
647 .b = {
648 .ctl_reg = MAXI_EN_REG,
649 .en_mask = BIT(25),
650 .halt_reg = DBG_BUS_VEC_E_REG,
651 .halt_bit = 5,
652 },
653 .c = {
654 .dbg_name = "jpegd_axi_clk",
655 .ops = &clk_ops_branch,
656 CLK_INIT(jpegd_axi_clk.c),
657 },
658};
659
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700660static struct branch_clk vcodec_axi_b_clk = {
661 .b = {
662 .ctl_reg = MAXI_EN4_REG,
663 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800664 .hwcg_reg = MAXI_EN4_REG,
665 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700666 .halt_reg = DBG_BUS_VEC_I_REG,
667 .halt_bit = 25,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800668 .retain_reg = MAXI_EN4_REG,
669 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700670 },
671 .c = {
672 .dbg_name = "vcodec_axi_b_clk",
673 .ops = &clk_ops_branch,
674 CLK_INIT(vcodec_axi_b_clk.c),
675 },
676};
677
Matt Wagantall91f42702011-07-14 12:01:15 -0700678static struct branch_clk vcodec_axi_a_clk = {
679 .b = {
680 .ctl_reg = MAXI_EN4_REG,
681 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800682 .hwcg_reg = MAXI_EN4_REG,
683 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700684 .halt_reg = DBG_BUS_VEC_I_REG,
685 .halt_bit = 26,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800686 .retain_reg = MAXI_EN4_REG,
687 .retain_mask = BIT(10),
Matt Wagantall91f42702011-07-14 12:01:15 -0700688 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700689 .c = {
690 .dbg_name = "vcodec_axi_a_clk",
691 .ops = &clk_ops_branch,
692 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700693 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700694 },
695};
696
697static struct branch_clk vcodec_axi_clk = {
698 .b = {
699 .ctl_reg = MAXI_EN_REG,
700 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800701 .hwcg_reg = MAXI_EN_REG,
702 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700703 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800704 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700705 .halt_reg = DBG_BUS_VEC_E_REG,
706 .halt_bit = 3,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800707 .retain_reg = MAXI_EN2_REG,
708 .retain_mask = BIT(28),
Matt Wagantall91f42702011-07-14 12:01:15 -0700709 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700710 .c = {
711 .dbg_name = "vcodec_axi_clk",
712 .ops = &clk_ops_branch,
713 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700714 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700715 },
716};
717
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700718static struct branch_clk vfe_axi_clk = {
719 .b = {
720 .ctl_reg = MAXI_EN_REG,
721 .en_mask = BIT(18),
722 .reset_reg = SW_RESET_AXI_REG,
723 .reset_mask = BIT(9),
724 .halt_reg = DBG_BUS_VEC_E_REG,
725 .halt_bit = 0,
726 },
727 .c = {
728 .dbg_name = "vfe_axi_clk",
729 .ops = &clk_ops_branch,
730 CLK_INIT(vfe_axi_clk.c),
731 },
732};
733
734static struct branch_clk mdp_axi_clk = {
735 .b = {
736 .ctl_reg = MAXI_EN_REG,
737 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800738 .hwcg_reg = MAXI_EN_REG,
739 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700740 .reset_reg = SW_RESET_AXI_REG,
741 .reset_mask = BIT(13),
742 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700743 .halt_bit = 8,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800744 .retain_reg = MAXI_EN_REG,
745 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700746 },
747 .c = {
748 .dbg_name = "mdp_axi_clk",
749 .ops = &clk_ops_branch,
750 CLK_INIT(mdp_axi_clk.c),
751 },
752};
753
754static struct branch_clk rot_axi_clk = {
755 .b = {
756 .ctl_reg = MAXI_EN2_REG,
757 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800758 .hwcg_reg = MAXI_EN2_REG,
759 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700760 .reset_reg = SW_RESET_AXI_REG,
761 .reset_mask = BIT(6),
762 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700763 .halt_bit = 2,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800764 .retain_reg = MAXI_EN3_REG,
765 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700766 },
767 .c = {
768 .dbg_name = "rot_axi_clk",
769 .ops = &clk_ops_branch,
770 CLK_INIT(rot_axi_clk.c),
771 },
772};
773
774static struct branch_clk vpe_axi_clk = {
775 .b = {
776 .ctl_reg = MAXI_EN2_REG,
777 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800778 .hwcg_reg = MAXI_EN2_REG,
779 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700780 .reset_reg = SW_RESET_AXI_REG,
781 .reset_mask = BIT(15),
782 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700783 .halt_bit = 1,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800784 .retain_reg = MAXI_EN3_REG,
785 .retain_mask = BIT(21),
786
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700787 },
788 .c = {
789 .dbg_name = "vpe_axi_clk",
790 .ops = &clk_ops_branch,
791 CLK_INIT(vpe_axi_clk.c),
792 },
793};
794
Tianyi Gou41515e22011-09-01 19:37:43 -0700795static struct branch_clk vcap_axi_clk = {
796 .b = {
797 .ctl_reg = MAXI_EN5_REG,
798 .en_mask = BIT(12),
Tianyi Gouf3095ea2012-05-22 14:16:06 -0700799 .hwcg_reg = MAXI_EN5_REG,
800 .hwcg_mask = BIT(11),
Tianyi Gou41515e22011-09-01 19:37:43 -0700801 .reset_reg = SW_RESET_AXI_REG,
802 .reset_mask = BIT(16),
803 .halt_reg = DBG_BUS_VEC_J_REG,
804 .halt_bit = 20,
805 },
806 .c = {
807 .dbg_name = "vcap_axi_clk",
808 .ops = &clk_ops_branch,
809 CLK_INIT(vcap_axi_clk.c),
810 },
811};
812
Tianyi Goue3d4f542012-03-15 17:06:45 -0700813/* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
Patrick Dalye6f489042012-07-11 15:29:15 -0700814static struct branch_clk gfx3d_axi_clk = {
Tianyi Gou621f8742011-09-01 21:45:01 -0700815 .b = {
816 .ctl_reg = MAXI_EN5_REG,
817 .en_mask = BIT(25),
Tianyi Gouf3095ea2012-05-22 14:16:06 -0700818 .hwcg_reg = MAXI_EN5_REG,
819 .hwcg_mask = BIT(24),
Tianyi Gou621f8742011-09-01 21:45:01 -0700820 .reset_reg = SW_RESET_AXI_REG,
821 .reset_mask = BIT(17),
822 .halt_reg = DBG_BUS_VEC_J_REG,
823 .halt_bit = 30,
824 },
825 .c = {
826 .dbg_name = "gfx3d_axi_clk",
827 .ops = &clk_ops_branch,
Patrick Dalye6f489042012-07-11 15:29:15 -0700828 CLK_INIT(gfx3d_axi_clk.c),
Tianyi Goue3d4f542012-03-15 17:06:45 -0700829 },
830};
831
832static struct branch_clk gfx3d_axi_clk_8930 = {
833 .b = {
834 .ctl_reg = MAXI_EN5_REG,
835 .en_mask = BIT(12),
836 .reset_reg = SW_RESET_AXI_REG,
837 .reset_mask = BIT(16),
838 .halt_reg = DBG_BUS_VEC_J_REG,
839 .halt_bit = 12,
840 },
841 .c = {
842 .dbg_name = "gfx3d_axi_clk",
843 .ops = &clk_ops_branch,
844 CLK_INIT(gfx3d_axi_clk_8930.c),
Tianyi Gou621f8742011-09-01 21:45:01 -0700845 },
846};
847
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700848/* AHB Interfaces */
849static struct branch_clk amp_p_clk = {
850 .b = {
851 .ctl_reg = AHB_EN_REG,
852 .en_mask = BIT(24),
Matt Wagantalld40857a2012-04-10 19:15:43 -0700853 .reset_reg = SW_RESET_CORE_REG,
854 .reset_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700855 .halt_reg = DBG_BUS_VEC_F_REG,
856 .halt_bit = 18,
857 },
858 .c = {
859 .dbg_name = "amp_p_clk",
860 .ops = &clk_ops_branch,
861 CLK_INIT(amp_p_clk.c),
862 },
863};
864
Matt Wagantallc23eee92011-08-16 23:06:52 -0700865static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700866 .b = {
867 .ctl_reg = AHB_EN_REG,
868 .en_mask = BIT(7),
869 .reset_reg = SW_RESET_AHB_REG,
870 .reset_mask = BIT(17),
871 .halt_reg = DBG_BUS_VEC_F_REG,
872 .halt_bit = 16,
873 },
874 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700875 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700876 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700877 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700878 },
879};
880
881static struct branch_clk dsi1_m_p_clk = {
882 .b = {
883 .ctl_reg = AHB_EN_REG,
884 .en_mask = BIT(9),
885 .reset_reg = SW_RESET_AHB_REG,
886 .reset_mask = BIT(6),
887 .halt_reg = DBG_BUS_VEC_F_REG,
888 .halt_bit = 19,
889 },
890 .c = {
891 .dbg_name = "dsi1_m_p_clk",
892 .ops = &clk_ops_branch,
893 CLK_INIT(dsi1_m_p_clk.c),
894 },
895};
896
897static struct branch_clk dsi1_s_p_clk = {
898 .b = {
899 .ctl_reg = AHB_EN_REG,
900 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800901 .hwcg_reg = AHB_EN2_REG,
902 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700903 .reset_reg = SW_RESET_AHB_REG,
904 .reset_mask = BIT(5),
905 .halt_reg = DBG_BUS_VEC_F_REG,
906 .halt_bit = 21,
907 },
908 .c = {
909 .dbg_name = "dsi1_s_p_clk",
910 .ops = &clk_ops_branch,
911 CLK_INIT(dsi1_s_p_clk.c),
912 },
913};
914
915static struct branch_clk dsi2_m_p_clk = {
916 .b = {
917 .ctl_reg = AHB_EN_REG,
918 .en_mask = BIT(17),
919 .reset_reg = SW_RESET_AHB2_REG,
920 .reset_mask = BIT(1),
921 .halt_reg = DBG_BUS_VEC_E_REG,
922 .halt_bit = 18,
923 },
924 .c = {
925 .dbg_name = "dsi2_m_p_clk",
926 .ops = &clk_ops_branch,
927 CLK_INIT(dsi2_m_p_clk.c),
928 },
929};
930
931static struct branch_clk dsi2_s_p_clk = {
932 .b = {
933 .ctl_reg = AHB_EN_REG,
934 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800935 .hwcg_reg = AHB_EN2_REG,
936 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700937 .reset_reg = SW_RESET_AHB2_REG,
938 .reset_mask = BIT(0),
939 .halt_reg = DBG_BUS_VEC_F_REG,
940 .halt_bit = 20,
941 },
942 .c = {
943 .dbg_name = "dsi2_s_p_clk",
944 .ops = &clk_ops_branch,
945 CLK_INIT(dsi2_s_p_clk.c),
946 },
947};
948
949static struct branch_clk gfx2d0_p_clk = {
950 .b = {
951 .ctl_reg = AHB_EN_REG,
952 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800953 .hwcg_reg = AHB_EN2_REG,
954 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700955 .reset_reg = SW_RESET_AHB_REG,
956 .reset_mask = BIT(12),
957 .halt_reg = DBG_BUS_VEC_F_REG,
958 .halt_bit = 2,
959 },
960 .c = {
961 .dbg_name = "gfx2d0_p_clk",
962 .ops = &clk_ops_branch,
Matt Wagantall158f73b2012-05-16 11:29:35 -0700963 .flags = CLKFLAG_SKIP_HANDOFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700964 CLK_INIT(gfx2d0_p_clk.c),
965 },
966};
967
968static struct branch_clk gfx2d1_p_clk = {
969 .b = {
970 .ctl_reg = AHB_EN_REG,
971 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800972 .hwcg_reg = AHB_EN2_REG,
973 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700974 .reset_reg = SW_RESET_AHB_REG,
975 .reset_mask = BIT(11),
976 .halt_reg = DBG_BUS_VEC_F_REG,
977 .halt_bit = 3,
978 },
979 .c = {
980 .dbg_name = "gfx2d1_p_clk",
981 .ops = &clk_ops_branch,
Matt Wagantall158f73b2012-05-16 11:29:35 -0700982 .flags = CLKFLAG_SKIP_HANDOFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700983 CLK_INIT(gfx2d1_p_clk.c),
984 },
985};
986
987static struct branch_clk gfx3d_p_clk = {
988 .b = {
989 .ctl_reg = AHB_EN_REG,
990 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800991 .hwcg_reg = AHB_EN2_REG,
992 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700993 .reset_reg = SW_RESET_AHB_REG,
994 .reset_mask = BIT(10),
995 .halt_reg = DBG_BUS_VEC_F_REG,
996 .halt_bit = 4,
997 },
998 .c = {
999 .dbg_name = "gfx3d_p_clk",
1000 .ops = &clk_ops_branch,
1001 CLK_INIT(gfx3d_p_clk.c),
1002 },
1003};
1004
1005static struct branch_clk hdmi_m_p_clk = {
1006 .b = {
1007 .ctl_reg = AHB_EN_REG,
1008 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001009 .hwcg_reg = AHB_EN2_REG,
1010 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001011 .reset_reg = SW_RESET_AHB_REG,
1012 .reset_mask = BIT(9),
1013 .halt_reg = DBG_BUS_VEC_F_REG,
1014 .halt_bit = 5,
1015 },
1016 .c = {
1017 .dbg_name = "hdmi_m_p_clk",
1018 .ops = &clk_ops_branch,
1019 CLK_INIT(hdmi_m_p_clk.c),
1020 },
1021};
1022
1023static struct branch_clk hdmi_s_p_clk = {
1024 .b = {
1025 .ctl_reg = AHB_EN_REG,
1026 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001027 .hwcg_reg = AHB_EN2_REG,
1028 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001029 .reset_reg = SW_RESET_AHB_REG,
1030 .reset_mask = BIT(9),
1031 .halt_reg = DBG_BUS_VEC_F_REG,
1032 .halt_bit = 6,
1033 },
1034 .c = {
1035 .dbg_name = "hdmi_s_p_clk",
1036 .ops = &clk_ops_branch,
1037 CLK_INIT(hdmi_s_p_clk.c),
1038 },
1039};
1040
1041static struct branch_clk ijpeg_p_clk = {
1042 .b = {
1043 .ctl_reg = AHB_EN_REG,
1044 .en_mask = BIT(5),
1045 .reset_reg = SW_RESET_AHB_REG,
1046 .reset_mask = BIT(7),
1047 .halt_reg = DBG_BUS_VEC_F_REG,
1048 .halt_bit = 9,
1049 },
1050 .c = {
1051 .dbg_name = "ijpeg_p_clk",
1052 .ops = &clk_ops_branch,
1053 CLK_INIT(ijpeg_p_clk.c),
1054 },
1055};
1056
1057static struct branch_clk imem_p_clk = {
1058 .b = {
1059 .ctl_reg = AHB_EN_REG,
1060 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001061 .hwcg_reg = AHB_EN2_REG,
1062 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001063 .reset_reg = SW_RESET_AHB_REG,
1064 .reset_mask = BIT(8),
1065 .halt_reg = DBG_BUS_VEC_F_REG,
1066 .halt_bit = 10,
1067 },
1068 .c = {
1069 .dbg_name = "imem_p_clk",
1070 .ops = &clk_ops_branch,
1071 CLK_INIT(imem_p_clk.c),
1072 },
1073};
1074
1075static struct branch_clk jpegd_p_clk = {
1076 .b = {
1077 .ctl_reg = AHB_EN_REG,
1078 .en_mask = BIT(21),
1079 .reset_reg = SW_RESET_AHB_REG,
1080 .reset_mask = BIT(4),
1081 .halt_reg = DBG_BUS_VEC_F_REG,
1082 .halt_bit = 7,
1083 },
1084 .c = {
1085 .dbg_name = "jpegd_p_clk",
1086 .ops = &clk_ops_branch,
1087 CLK_INIT(jpegd_p_clk.c),
1088 },
1089};
1090
1091static struct branch_clk mdp_p_clk = {
1092 .b = {
1093 .ctl_reg = AHB_EN_REG,
1094 .en_mask = BIT(10),
1095 .reset_reg = SW_RESET_AHB_REG,
1096 .reset_mask = BIT(3),
1097 .halt_reg = DBG_BUS_VEC_F_REG,
1098 .halt_bit = 11,
1099 },
1100 .c = {
1101 .dbg_name = "mdp_p_clk",
1102 .ops = &clk_ops_branch,
1103 CLK_INIT(mdp_p_clk.c),
1104 },
1105};
1106
1107static struct branch_clk rot_p_clk = {
1108 .b = {
1109 .ctl_reg = AHB_EN_REG,
1110 .en_mask = BIT(12),
1111 .reset_reg = SW_RESET_AHB_REG,
1112 .reset_mask = BIT(2),
1113 .halt_reg = DBG_BUS_VEC_F_REG,
1114 .halt_bit = 13,
1115 },
1116 .c = {
1117 .dbg_name = "rot_p_clk",
1118 .ops = &clk_ops_branch,
1119 CLK_INIT(rot_p_clk.c),
1120 },
1121};
1122
1123static struct branch_clk smmu_p_clk = {
1124 .b = {
1125 .ctl_reg = AHB_EN_REG,
1126 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001127 .hwcg_reg = AHB_EN_REG,
1128 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001129 .halt_reg = DBG_BUS_VEC_F_REG,
1130 .halt_bit = 22,
1131 },
1132 .c = {
1133 .dbg_name = "smmu_p_clk",
1134 .ops = &clk_ops_branch,
1135 CLK_INIT(smmu_p_clk.c),
1136 },
1137};
1138
1139static struct branch_clk tv_enc_p_clk = {
1140 .b = {
1141 .ctl_reg = AHB_EN_REG,
1142 .en_mask = BIT(25),
1143 .reset_reg = SW_RESET_AHB_REG,
1144 .reset_mask = BIT(15),
1145 .halt_reg = DBG_BUS_VEC_F_REG,
1146 .halt_bit = 23,
1147 },
1148 .c = {
1149 .dbg_name = "tv_enc_p_clk",
1150 .ops = &clk_ops_branch,
1151 CLK_INIT(tv_enc_p_clk.c),
1152 },
1153};
1154
1155static struct branch_clk vcodec_p_clk = {
1156 .b = {
1157 .ctl_reg = AHB_EN_REG,
1158 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001159 .hwcg_reg = AHB_EN2_REG,
1160 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001161 .reset_reg = SW_RESET_AHB_REG,
1162 .reset_mask = BIT(1),
1163 .halt_reg = DBG_BUS_VEC_F_REG,
1164 .halt_bit = 12,
1165 },
1166 .c = {
1167 .dbg_name = "vcodec_p_clk",
1168 .ops = &clk_ops_branch,
1169 CLK_INIT(vcodec_p_clk.c),
1170 },
1171};
1172
1173static struct branch_clk vfe_p_clk = {
1174 .b = {
1175 .ctl_reg = AHB_EN_REG,
1176 .en_mask = BIT(13),
1177 .reset_reg = SW_RESET_AHB_REG,
1178 .reset_mask = BIT(0),
1179 .halt_reg = DBG_BUS_VEC_F_REG,
1180 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08001181 .retain_reg = AHB_EN2_REG,
1182 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001183 },
1184 .c = {
1185 .dbg_name = "vfe_p_clk",
1186 .ops = &clk_ops_branch,
1187 CLK_INIT(vfe_p_clk.c),
1188 },
1189};
1190
1191static struct branch_clk vpe_p_clk = {
1192 .b = {
1193 .ctl_reg = AHB_EN_REG,
1194 .en_mask = BIT(16),
1195 .reset_reg = SW_RESET_AHB_REG,
1196 .reset_mask = BIT(14),
1197 .halt_reg = DBG_BUS_VEC_F_REG,
1198 .halt_bit = 15,
1199 },
1200 .c = {
1201 .dbg_name = "vpe_p_clk",
1202 .ops = &clk_ops_branch,
1203 CLK_INIT(vpe_p_clk.c),
1204 },
1205};
1206
Tianyi Gou41515e22011-09-01 19:37:43 -07001207static struct branch_clk vcap_p_clk = {
1208 .b = {
1209 .ctl_reg = AHB_EN3_REG,
1210 .en_mask = BIT(1),
Tianyi Gouf3095ea2012-05-22 14:16:06 -07001211 .hwcg_reg = AHB_EN3_REG,
1212 .hwcg_mask = BIT(0),
Tianyi Gou41515e22011-09-01 19:37:43 -07001213 .reset_reg = SW_RESET_AHB2_REG,
1214 .reset_mask = BIT(2),
1215 .halt_reg = DBG_BUS_VEC_J_REG,
1216 .halt_bit = 23,
1217 },
1218 .c = {
1219 .dbg_name = "vcap_p_clk",
1220 .ops = &clk_ops_branch,
1221 CLK_INIT(vcap_p_clk.c),
1222 },
1223};
1224
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001225/*
1226 * Peripheral Clocks
1227 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001228#define CLK_GP(i, n, h_r, h_b) \
1229 struct rcg_clk i##_clk = { \
1230 .b = { \
1231 .ctl_reg = GPn_NS_REG(n), \
1232 .en_mask = BIT(9), \
1233 .halt_reg = h_r, \
1234 .halt_bit = h_b, \
1235 }, \
1236 .ns_reg = GPn_NS_REG(n), \
1237 .md_reg = GPn_MD_REG(n), \
1238 .root_en_mask = BIT(11), \
1239 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001240 .mnd_en_mask = BIT(8), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001241 .set_rate = set_rate_mnd, \
1242 .freq_tbl = clk_tbl_gp, \
1243 .current_freq = &rcg_dummy_freq, \
1244 .c = { \
1245 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001246 .ops = &clk_ops_rcg, \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001247 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1248 CLK_INIT(i##_clk.c), \
1249 }, \
1250 }
1251#define F_GP(f, s, d, m, n) \
1252 { \
1253 .freq_hz = f, \
1254 .src_clk = &s##_clk.c, \
1255 .md_val = MD8(16, m, 0, n), \
1256 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001257 }
1258static struct clk_freq_tbl clk_tbl_gp[] = {
1259 F_GP( 0, gnd, 1, 0, 0),
1260 F_GP( 9600000, cxo, 2, 0, 0),
1261 F_GP( 13500000, pxo, 2, 0, 0),
1262 F_GP( 19200000, cxo, 1, 0, 0),
1263 F_GP( 27000000, pxo, 1, 0, 0),
1264 F_GP( 64000000, pll8, 2, 1, 3),
1265 F_GP( 76800000, pll8, 1, 1, 5),
1266 F_GP( 96000000, pll8, 4, 0, 0),
1267 F_GP(128000000, pll8, 3, 0, 0),
1268 F_GP(192000000, pll8, 2, 0, 0),
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001269 F_END
1270};
1271
1272static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1273static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1274static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1275
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001276#define CLK_GSBI_UART(i, n, h_r, h_b) \
1277 struct rcg_clk i##_clk = { \
1278 .b = { \
1279 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1280 .en_mask = BIT(9), \
1281 .reset_reg = GSBIn_RESET_REG(n), \
1282 .reset_mask = BIT(0), \
1283 .halt_reg = h_r, \
1284 .halt_bit = h_b, \
1285 }, \
1286 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1287 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1288 .root_en_mask = BIT(11), \
1289 .ns_mask = (BM(31, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001290 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001291 .set_rate = set_rate_mnd, \
1292 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001293 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001294 .c = { \
1295 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001296 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001297 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001298 CLK_INIT(i##_clk.c), \
1299 }, \
1300 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001301#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001302 { \
1303 .freq_hz = f, \
1304 .src_clk = &s##_clk.c, \
1305 .md_val = MD16(m, n), \
1306 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001307 }
1308static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001309 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001310 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1311 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1312 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1313 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001314 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1315 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1316 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1317 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1318 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1319 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1320 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1321 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1322 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1323 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001324 F_END
1325};
1326
1327static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1328static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1329static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1330static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1331static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1332static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1333static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1334static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1335static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1336static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1337static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1338static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1339
1340#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1341 struct rcg_clk i##_clk = { \
1342 .b = { \
1343 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1344 .en_mask = BIT(9), \
1345 .reset_reg = GSBIn_RESET_REG(n), \
1346 .reset_mask = BIT(0), \
1347 .halt_reg = h_r, \
1348 .halt_bit = h_b, \
1349 }, \
1350 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1351 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1352 .root_en_mask = BIT(11), \
1353 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001354 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001355 .set_rate = set_rate_mnd, \
1356 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001357 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001358 .c = { \
1359 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001360 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001361 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001362 CLK_INIT(i##_clk.c), \
1363 }, \
1364 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001365#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001366 { \
1367 .freq_hz = f, \
1368 .src_clk = &s##_clk.c, \
1369 .md_val = MD8(16, m, 0, n), \
1370 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001371 }
1372static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001373 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1374 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1375 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1376 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1377 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1378 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1379 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1380 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1381 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1382 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001383 F_END
1384};
1385
1386static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1387static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1388static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1389static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1390static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1391static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1392static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1393static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1394static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1395static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1396static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1397static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1398
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001399#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001400 { \
1401 .freq_hz = f, \
1402 .src_clk = &s##_clk.c, \
1403 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001404 }
1405static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001406 F_PDM( 0, gnd, 1),
1407 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001408 F_END
1409};
1410
1411static struct rcg_clk pdm_clk = {
1412 .b = {
1413 .ctl_reg = PDM_CLK_NS_REG,
1414 .en_mask = BIT(9),
1415 .reset_reg = PDM_CLK_NS_REG,
1416 .reset_mask = BIT(12),
1417 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1418 .halt_bit = 3,
1419 },
1420 .ns_reg = PDM_CLK_NS_REG,
1421 .root_en_mask = BIT(11),
1422 .ns_mask = BM(1, 0),
1423 .set_rate = set_rate_nop,
1424 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001425 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001426 .c = {
1427 .dbg_name = "pdm_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001428 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001429 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001430 CLK_INIT(pdm_clk.c),
1431 },
1432};
1433
1434static struct branch_clk pmem_clk = {
1435 .b = {
1436 .ctl_reg = PMEM_ACLK_CTL_REG,
1437 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001438 .hwcg_reg = PMEM_ACLK_CTL_REG,
1439 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001440 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1441 .halt_bit = 20,
1442 },
1443 .c = {
1444 .dbg_name = "pmem_clk",
1445 .ops = &clk_ops_branch,
1446 CLK_INIT(pmem_clk.c),
1447 },
1448};
1449
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001450#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001451 { \
1452 .freq_hz = f, \
1453 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001454 }
Stephen Boyd842a1f62012-04-26 19:07:38 -07001455static struct clk_freq_tbl clk_tbl_prng_32[] = {
1456 F_PRNG(32000000, pll8),
1457 F_END
1458};
1459
1460static struct clk_freq_tbl clk_tbl_prng_64[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001461 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001462 F_END
1463};
1464
1465static struct rcg_clk prng_clk = {
1466 .b = {
1467 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1468 .en_mask = BIT(10),
1469 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1470 .halt_check = HALT_VOTED,
1471 .halt_bit = 10,
1472 },
1473 .set_rate = set_rate_nop,
Stephen Boyd842a1f62012-04-26 19:07:38 -07001474 .freq_tbl = clk_tbl_prng_32,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001475 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001476 .c = {
1477 .dbg_name = "prng_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001478 .ops = &clk_ops_rcg,
Stephen Boyd842a1f62012-04-26 19:07:38 -07001479 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001480 CLK_INIT(prng_clk.c),
1481 },
1482};
1483
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001484#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001485 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001486 .b = { \
1487 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1488 .en_mask = BIT(9), \
1489 .reset_reg = SDCn_RESET_REG(n), \
1490 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001491 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001492 .halt_bit = h_b, \
1493 }, \
1494 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1495 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1496 .root_en_mask = BIT(11), \
1497 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001498 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001499 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001500 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001501 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001502 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001503 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001504 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001505 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001506 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001507 }, \
1508 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001509#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001510 { \
1511 .freq_hz = f, \
1512 .src_clk = &s##_clk.c, \
1513 .md_val = MD8(16, m, 0, n), \
1514 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001515 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001516static struct clk_freq_tbl clk_tbl_sdc[] = {
1517 F_SDC( 0, gnd, 1, 0, 0),
1518 F_SDC( 144000, pxo, 3, 2, 125),
1519 F_SDC( 400000, pll8, 4, 1, 240),
1520 F_SDC( 16000000, pll8, 4, 1, 6),
1521 F_SDC( 17070000, pll8, 1, 2, 45),
1522 F_SDC( 20210000, pll8, 1, 1, 19),
1523 F_SDC( 24000000, pll8, 4, 1, 4),
1524 F_SDC( 48000000, pll8, 4, 1, 2),
1525 F_SDC( 64000000, pll8, 3, 1, 2),
1526 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301527 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001528 F_END
1529};
1530
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001531static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1532static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1533static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1534static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1535static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001536
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001537#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001538 { \
1539 .freq_hz = f, \
1540 .src_clk = &s##_clk.c, \
1541 .md_val = MD16(m, n), \
1542 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001543 }
1544static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001545 F_TSIF_REF( 0, gnd, 1, 0, 0),
1546 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001547 F_END
1548};
1549
1550static struct rcg_clk tsif_ref_clk = {
1551 .b = {
1552 .ctl_reg = TSIF_REF_CLK_NS_REG,
1553 .en_mask = BIT(9),
1554 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1555 .halt_bit = 5,
1556 },
1557 .ns_reg = TSIF_REF_CLK_NS_REG,
1558 .md_reg = TSIF_REF_CLK_MD_REG,
1559 .root_en_mask = BIT(11),
1560 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001561 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001562 .set_rate = set_rate_mnd,
1563 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001564 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001565 .c = {
1566 .dbg_name = "tsif_ref_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001567 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001568 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001569 CLK_INIT(tsif_ref_clk.c),
1570 },
1571};
1572
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001573#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001574 { \
1575 .freq_hz = f, \
1576 .src_clk = &s##_clk.c, \
1577 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001578 }
1579static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001580 F_TSSC( 0, gnd),
1581 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001582 F_END
1583};
1584
1585static struct rcg_clk tssc_clk = {
1586 .b = {
1587 .ctl_reg = TSSC_CLK_CTL_REG,
1588 .en_mask = BIT(4),
1589 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1590 .halt_bit = 4,
1591 },
1592 .ns_reg = TSSC_CLK_CTL_REG,
1593 .ns_mask = BM(1, 0),
1594 .set_rate = set_rate_nop,
1595 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001596 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001597 .c = {
1598 .dbg_name = "tssc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001599 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001600 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001601 CLK_INIT(tssc_clk.c),
1602 },
1603};
1604
Tianyi Gou41515e22011-09-01 19:37:43 -07001605#define CLK_USB_HS(name, n, h_b) \
1606 static struct rcg_clk name = { \
1607 .b = { \
1608 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1609 .en_mask = BIT(9), \
1610 .reset_reg = USB_HS##n##_RESET_REG, \
1611 .reset_mask = BIT(0), \
1612 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1613 .halt_bit = h_b, \
1614 }, \
1615 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1616 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1617 .root_en_mask = BIT(11), \
1618 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001619 .mnd_en_mask = BIT(8), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001620 .set_rate = set_rate_mnd, \
1621 .freq_tbl = clk_tbl_usb, \
1622 .current_freq = &rcg_dummy_freq, \
1623 .c = { \
1624 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001625 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001626 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001627 CLK_INIT(name.c), \
1628 }, \
1629}
1630
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001631#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001632 { \
1633 .freq_hz = f, \
1634 .src_clk = &s##_clk.c, \
1635 .md_val = MD8(16, m, 0, n), \
1636 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001637 }
1638static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001639 F_USB( 0, gnd, 1, 0, 0),
1640 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001641 F_END
1642};
1643
Tianyi Gou41515e22011-09-01 19:37:43 -07001644CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1645CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1646CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001647
Stephen Boyd94625ef2011-07-12 17:06:01 -07001648static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001649 F_USB( 0, gnd, 1, 0, 0),
1650 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001651 F_END
1652};
1653
1654static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1655 .b = {
1656 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1657 .en_mask = BIT(9),
1658 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1659 .halt_bit = 26,
1660 },
1661 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1662 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1663 .root_en_mask = BIT(11),
1664 .ns_mask = (BM(23, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001665 .mnd_en_mask = BIT(8),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001666 .set_rate = set_rate_mnd,
1667 .freq_tbl = clk_tbl_usb_hsic,
1668 .current_freq = &rcg_dummy_freq,
1669 .c = {
1670 .dbg_name = "usb_hsic_xcvr_fs_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001671 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001672 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001673 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1674 },
1675};
1676
1677static struct branch_clk usb_hsic_system_clk = {
1678 .b = {
1679 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1680 .en_mask = BIT(4),
1681 .reset_reg = USB_HSIC_RESET_REG,
1682 .reset_mask = BIT(0),
1683 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1684 .halt_bit = 24,
1685 },
1686 .parent = &usb_hsic_xcvr_fs_clk.c,
1687 .c = {
1688 .dbg_name = "usb_hsic_system_clk",
1689 .ops = &clk_ops_branch,
1690 CLK_INIT(usb_hsic_system_clk.c),
1691 },
1692};
1693
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001694#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001695 { \
1696 .freq_hz = f, \
1697 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001698 }
1699static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001700 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001701 F_END
1702};
1703
1704static struct rcg_clk usb_hsic_hsic_src_clk = {
1705 .b = {
1706 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1707 .halt_check = NOCHECK,
1708 },
1709 .root_en_mask = BIT(0),
1710 .set_rate = set_rate_nop,
1711 .freq_tbl = clk_tbl_usb2_hsic,
1712 .current_freq = &rcg_dummy_freq,
1713 .c = {
1714 .dbg_name = "usb_hsic_hsic_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001715 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001716 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001717 CLK_INIT(usb_hsic_hsic_src_clk.c),
1718 },
1719};
1720
1721static struct branch_clk usb_hsic_hsic_clk = {
1722 .b = {
1723 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1724 .en_mask = BIT(0),
1725 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1726 .halt_bit = 19,
1727 },
1728 .parent = &usb_hsic_hsic_src_clk.c,
1729 .c = {
1730 .dbg_name = "usb_hsic_hsic_clk",
1731 .ops = &clk_ops_branch,
1732 CLK_INIT(usb_hsic_hsic_clk.c),
1733 },
1734};
1735
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001736#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001737 { \
1738 .freq_hz = f, \
1739 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001740 }
1741static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001742 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001743 F_END
1744};
1745
1746static struct rcg_clk usb_hsic_hsio_cal_clk = {
1747 .b = {
1748 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1749 .en_mask = BIT(0),
1750 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1751 .halt_bit = 23,
1752 },
1753 .set_rate = set_rate_nop,
1754 .freq_tbl = clk_tbl_usb_hsio_cal,
1755 .current_freq = &rcg_dummy_freq,
1756 .c = {
1757 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001758 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001759 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001760 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1761 },
1762};
1763
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001764static struct branch_clk usb_phy0_clk = {
1765 .b = {
1766 .reset_reg = USB_PHY0_RESET_REG,
1767 .reset_mask = BIT(0),
1768 },
1769 .c = {
1770 .dbg_name = "usb_phy0_clk",
1771 .ops = &clk_ops_reset,
1772 CLK_INIT(usb_phy0_clk.c),
1773 },
1774};
1775
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001776#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001777 struct rcg_clk i##_clk = { \
1778 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1779 .b = { \
1780 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1781 .halt_check = NOCHECK, \
1782 }, \
1783 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1784 .root_en_mask = BIT(11), \
1785 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001786 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001787 .set_rate = set_rate_mnd, \
1788 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001789 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001790 .c = { \
1791 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001792 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001793 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001794 CLK_INIT(i##_clk.c), \
1795 }, \
1796 }
1797
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001798static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001799static struct branch_clk usb_fs1_xcvr_clk = {
1800 .b = {
1801 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1802 .en_mask = BIT(9),
1803 .reset_reg = USB_FSn_RESET_REG(1),
1804 .reset_mask = BIT(1),
1805 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1806 .halt_bit = 15,
1807 },
1808 .parent = &usb_fs1_src_clk.c,
1809 .c = {
1810 .dbg_name = "usb_fs1_xcvr_clk",
1811 .ops = &clk_ops_branch,
1812 CLK_INIT(usb_fs1_xcvr_clk.c),
1813 },
1814};
1815
1816static struct branch_clk usb_fs1_sys_clk = {
1817 .b = {
1818 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1819 .en_mask = BIT(4),
1820 .reset_reg = USB_FSn_RESET_REG(1),
1821 .reset_mask = BIT(0),
1822 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1823 .halt_bit = 16,
1824 },
1825 .parent = &usb_fs1_src_clk.c,
1826 .c = {
1827 .dbg_name = "usb_fs1_sys_clk",
1828 .ops = &clk_ops_branch,
1829 CLK_INIT(usb_fs1_sys_clk.c),
1830 },
1831};
1832
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001833static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001834static struct branch_clk usb_fs2_xcvr_clk = {
1835 .b = {
1836 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1837 .en_mask = BIT(9),
1838 .reset_reg = USB_FSn_RESET_REG(2),
1839 .reset_mask = BIT(1),
1840 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1841 .halt_bit = 12,
1842 },
1843 .parent = &usb_fs2_src_clk.c,
1844 .c = {
1845 .dbg_name = "usb_fs2_xcvr_clk",
1846 .ops = &clk_ops_branch,
1847 CLK_INIT(usb_fs2_xcvr_clk.c),
1848 },
1849};
1850
1851static struct branch_clk usb_fs2_sys_clk = {
1852 .b = {
1853 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1854 .en_mask = BIT(4),
1855 .reset_reg = USB_FSn_RESET_REG(2),
1856 .reset_mask = BIT(0),
1857 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1858 .halt_bit = 13,
1859 },
1860 .parent = &usb_fs2_src_clk.c,
1861 .c = {
1862 .dbg_name = "usb_fs2_sys_clk",
1863 .ops = &clk_ops_branch,
1864 CLK_INIT(usb_fs2_sys_clk.c),
1865 },
1866};
1867
1868/* Fast Peripheral Bus Clocks */
1869static struct branch_clk ce1_core_clk = {
1870 .b = {
1871 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1872 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001873 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1874 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001875 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1876 .halt_bit = 27,
1877 },
1878 .c = {
1879 .dbg_name = "ce1_core_clk",
1880 .ops = &clk_ops_branch,
1881 CLK_INIT(ce1_core_clk.c),
1882 },
1883};
Tianyi Gou41515e22011-09-01 19:37:43 -07001884
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001885static struct branch_clk ce1_p_clk = {
1886 .b = {
1887 .ctl_reg = CE1_HCLK_CTL_REG,
1888 .en_mask = BIT(4),
1889 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1890 .halt_bit = 1,
1891 },
1892 .c = {
1893 .dbg_name = "ce1_p_clk",
1894 .ops = &clk_ops_branch,
1895 CLK_INIT(ce1_p_clk.c),
1896 },
1897};
1898
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001899#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001900 { \
1901 .freq_hz = f, \
1902 .src_clk = &s##_clk.c, \
1903 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001904 }
1905
1906static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001907 F_CE3( 0, gnd, 1),
1908 F_CE3( 48000000, pll8, 8),
1909 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001910 F_END
1911};
1912
1913static struct rcg_clk ce3_src_clk = {
1914 .b = {
1915 .ctl_reg = CE3_CLK_SRC_NS_REG,
1916 .halt_check = NOCHECK,
1917 },
1918 .ns_reg = CE3_CLK_SRC_NS_REG,
1919 .root_en_mask = BIT(7),
1920 .ns_mask = BM(6, 0),
1921 .set_rate = set_rate_nop,
1922 .freq_tbl = clk_tbl_ce3,
1923 .current_freq = &rcg_dummy_freq,
1924 .c = {
1925 .dbg_name = "ce3_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001926 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001927 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001928 CLK_INIT(ce3_src_clk.c),
1929 },
1930};
1931
1932static struct branch_clk ce3_core_clk = {
1933 .b = {
1934 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1935 .en_mask = BIT(4),
1936 .reset_reg = CE3_CORE_CLK_CTL_REG,
1937 .reset_mask = BIT(7),
1938 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1939 .halt_bit = 5,
1940 },
1941 .parent = &ce3_src_clk.c,
1942 .c = {
1943 .dbg_name = "ce3_core_clk",
1944 .ops = &clk_ops_branch,
1945 CLK_INIT(ce3_core_clk.c),
1946 }
1947};
1948
1949static struct branch_clk ce3_p_clk = {
1950 .b = {
1951 .ctl_reg = CE3_HCLK_CTL_REG,
1952 .en_mask = BIT(4),
1953 .reset_reg = CE3_HCLK_CTL_REG,
1954 .reset_mask = BIT(7),
1955 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1956 .halt_bit = 16,
1957 },
1958 .parent = &ce3_src_clk.c,
1959 .c = {
1960 .dbg_name = "ce3_p_clk",
1961 .ops = &clk_ops_branch,
1962 CLK_INIT(ce3_p_clk.c),
1963 }
1964};
1965
Tianyi Gou352955d2012-05-18 19:44:01 -07001966#define F_SATA(f, s, d) \
1967 { \
1968 .freq_hz = f, \
1969 .src_clk = &s##_clk.c, \
1970 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
1971 }
1972
1973static struct clk_freq_tbl clk_tbl_sata[] = {
1974 F_SATA( 0, gnd, 1),
1975 F_SATA( 48000000, pll8, 8),
1976 F_SATA(100000000, pll3, 12),
1977 F_END
1978};
1979
1980static struct rcg_clk sata_src_clk = {
1981 .b = {
1982 .ctl_reg = SATA_CLK_SRC_NS_REG,
1983 .halt_check = NOCHECK,
1984 },
1985 .ns_reg = SATA_CLK_SRC_NS_REG,
1986 .root_en_mask = BIT(7),
1987 .ns_mask = BM(6, 0),
1988 .set_rate = set_rate_nop,
1989 .freq_tbl = clk_tbl_sata,
1990 .current_freq = &rcg_dummy_freq,
1991 .c = {
1992 .dbg_name = "sata_src_clk",
1993 .ops = &clk_ops_rcg,
1994 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
1995 CLK_INIT(sata_src_clk.c),
1996 },
1997};
1998
1999static struct branch_clk sata_rxoob_clk = {
2000 .b = {
2001 .ctl_reg = SATA_RXOOB_CLK_CTL_REG,
2002 .en_mask = BIT(4),
2003 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2004 .halt_bit = 26,
2005 },
2006 .parent = &sata_src_clk.c,
2007 .c = {
2008 .dbg_name = "sata_rxoob_clk",
2009 .ops = &clk_ops_branch,
2010 CLK_INIT(sata_rxoob_clk.c),
2011 },
2012};
2013
2014static struct branch_clk sata_pmalive_clk = {
2015 .b = {
2016 .ctl_reg = SATA_PMALIVE_CLK_CTL_REG,
2017 .en_mask = BIT(4),
2018 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2019 .halt_bit = 25,
2020 },
2021 .parent = &sata_src_clk.c,
2022 .c = {
2023 .dbg_name = "sata_pmalive_clk",
2024 .ops = &clk_ops_branch,
2025 CLK_INIT(sata_pmalive_clk.c),
2026 },
2027};
2028
Tianyi Gou41515e22011-09-01 19:37:43 -07002029static struct branch_clk sata_phy_ref_clk = {
2030 .b = {
2031 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
2032 .en_mask = BIT(4),
2033 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2034 .halt_bit = 24,
2035 },
2036 .parent = &pxo_clk.c,
2037 .c = {
2038 .dbg_name = "sata_phy_ref_clk",
2039 .ops = &clk_ops_branch,
2040 CLK_INIT(sata_phy_ref_clk.c),
2041 },
2042};
2043
Tianyi Gou352955d2012-05-18 19:44:01 -07002044static struct branch_clk sata_a_clk = {
2045 .b = {
2046 .ctl_reg = SATA_ACLK_CTL_REG,
2047 .en_mask = BIT(4),
2048 .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG,
2049 .halt_bit = 12,
2050 },
2051 .c = {
2052 .dbg_name = "sata_a_clk",
2053 .ops = &clk_ops_branch,
2054 CLK_INIT(sata_a_clk.c),
2055 },
2056};
2057
2058static struct branch_clk sata_p_clk = {
2059 .b = {
2060 .ctl_reg = SATA_HCLK_CTL_REG,
2061 .en_mask = BIT(4),
2062 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2063 .halt_bit = 27,
2064 },
2065 .c = {
2066 .dbg_name = "sata_p_clk",
2067 .ops = &clk_ops_branch,
2068 CLK_INIT(sata_p_clk.c),
2069 },
2070};
2071
2072static struct branch_clk sfab_sata_s_p_clk = {
2073 .b = {
2074 .ctl_reg = SFAB_SATA_S_HCLK_CTL_REG,
2075 .en_mask = BIT(4),
2076 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
2077 .halt_bit = 14,
2078 },
2079 .c = {
2080 .dbg_name = "sfab_sata_s_p_clk",
2081 .ops = &clk_ops_branch,
2082 CLK_INIT(sfab_sata_s_p_clk.c),
2083 },
2084};
Tianyi Gou41515e22011-09-01 19:37:43 -07002085static struct branch_clk pcie_p_clk = {
2086 .b = {
2087 .ctl_reg = PCIE_HCLK_CTL_REG,
2088 .en_mask = BIT(4),
2089 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2090 .halt_bit = 8,
2091 },
2092 .c = {
2093 .dbg_name = "pcie_p_clk",
2094 .ops = &clk_ops_branch,
2095 CLK_INIT(pcie_p_clk.c),
2096 },
2097};
2098
Tianyi Gou6613de52012-01-27 17:57:53 -08002099static struct branch_clk pcie_phy_ref_clk = {
2100 .b = {
2101 .ctl_reg = PCIE_PCLK_CTL_REG,
2102 .en_mask = BIT(4),
2103 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2104 .halt_bit = 29,
2105 },
2106 .c = {
2107 .dbg_name = "pcie_phy_ref_clk",
2108 .ops = &clk_ops_branch,
2109 CLK_INIT(pcie_phy_ref_clk.c),
2110 },
2111};
2112
2113static struct branch_clk pcie_a_clk = {
2114 .b = {
2115 .ctl_reg = PCIE_ACLK_CTL_REG,
2116 .en_mask = BIT(4),
2117 .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG,
2118 .halt_bit = 13,
2119 },
2120 .c = {
2121 .dbg_name = "pcie_a_clk",
2122 .ops = &clk_ops_branch,
2123 CLK_INIT(pcie_a_clk.c),
2124 },
2125};
2126
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002127static struct branch_clk dma_bam_p_clk = {
2128 .b = {
2129 .ctl_reg = DMA_BAM_HCLK_CTL,
2130 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002131 .hwcg_reg = DMA_BAM_HCLK_CTL,
2132 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002133 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2134 .halt_bit = 12,
2135 },
2136 .c = {
2137 .dbg_name = "dma_bam_p_clk",
2138 .ops = &clk_ops_branch,
2139 CLK_INIT(dma_bam_p_clk.c),
2140 },
2141};
2142
2143static struct branch_clk gsbi1_p_clk = {
2144 .b = {
2145 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2146 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002147 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
2148 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002149 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2150 .halt_bit = 11,
2151 },
2152 .c = {
2153 .dbg_name = "gsbi1_p_clk",
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(gsbi1_p_clk.c),
2156 },
2157};
2158
2159static struct branch_clk gsbi2_p_clk = {
2160 .b = {
2161 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2162 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002163 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2164 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002165 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2166 .halt_bit = 7,
2167 },
2168 .c = {
2169 .dbg_name = "gsbi2_p_clk",
2170 .ops = &clk_ops_branch,
2171 CLK_INIT(gsbi2_p_clk.c),
2172 },
2173};
2174
2175static struct branch_clk gsbi3_p_clk = {
2176 .b = {
2177 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2178 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002179 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2180 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002181 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2182 .halt_bit = 3,
2183 },
2184 .c = {
2185 .dbg_name = "gsbi3_p_clk",
2186 .ops = &clk_ops_branch,
2187 CLK_INIT(gsbi3_p_clk.c),
2188 },
2189};
2190
2191static struct branch_clk gsbi4_p_clk = {
2192 .b = {
2193 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2194 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002195 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2196 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002197 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2198 .halt_bit = 27,
2199 },
2200 .c = {
2201 .dbg_name = "gsbi4_p_clk",
2202 .ops = &clk_ops_branch,
2203 CLK_INIT(gsbi4_p_clk.c),
2204 },
2205};
2206
2207static struct branch_clk gsbi5_p_clk = {
2208 .b = {
2209 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2210 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002211 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2212 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002213 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2214 .halt_bit = 23,
2215 },
2216 .c = {
2217 .dbg_name = "gsbi5_p_clk",
2218 .ops = &clk_ops_branch,
2219 CLK_INIT(gsbi5_p_clk.c),
2220 },
2221};
2222
2223static struct branch_clk gsbi6_p_clk = {
2224 .b = {
2225 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2226 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002227 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2228 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002229 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2230 .halt_bit = 19,
2231 },
2232 .c = {
2233 .dbg_name = "gsbi6_p_clk",
2234 .ops = &clk_ops_branch,
2235 CLK_INIT(gsbi6_p_clk.c),
2236 },
2237};
2238
2239static struct branch_clk gsbi7_p_clk = {
2240 .b = {
2241 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2242 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002243 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2244 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002245 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2246 .halt_bit = 15,
2247 },
2248 .c = {
2249 .dbg_name = "gsbi7_p_clk",
2250 .ops = &clk_ops_branch,
2251 CLK_INIT(gsbi7_p_clk.c),
2252 },
2253};
2254
2255static struct branch_clk gsbi8_p_clk = {
2256 .b = {
2257 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2258 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002259 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2260 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002261 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2262 .halt_bit = 11,
2263 },
2264 .c = {
2265 .dbg_name = "gsbi8_p_clk",
2266 .ops = &clk_ops_branch,
2267 CLK_INIT(gsbi8_p_clk.c),
2268 },
2269};
2270
2271static struct branch_clk gsbi9_p_clk = {
2272 .b = {
2273 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2274 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002275 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2276 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002277 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2278 .halt_bit = 7,
2279 },
2280 .c = {
2281 .dbg_name = "gsbi9_p_clk",
2282 .ops = &clk_ops_branch,
2283 CLK_INIT(gsbi9_p_clk.c),
2284 },
2285};
2286
2287static struct branch_clk gsbi10_p_clk = {
2288 .b = {
2289 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2290 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002291 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2292 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002293 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2294 .halt_bit = 3,
2295 },
2296 .c = {
2297 .dbg_name = "gsbi10_p_clk",
2298 .ops = &clk_ops_branch,
2299 CLK_INIT(gsbi10_p_clk.c),
2300 },
2301};
2302
2303static struct branch_clk gsbi11_p_clk = {
2304 .b = {
2305 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2306 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002307 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2308 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002309 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2310 .halt_bit = 18,
2311 },
2312 .c = {
2313 .dbg_name = "gsbi11_p_clk",
2314 .ops = &clk_ops_branch,
2315 CLK_INIT(gsbi11_p_clk.c),
2316 },
2317};
2318
2319static struct branch_clk gsbi12_p_clk = {
2320 .b = {
2321 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2322 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002323 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2324 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002325 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2326 .halt_bit = 14,
2327 },
2328 .c = {
2329 .dbg_name = "gsbi12_p_clk",
2330 .ops = &clk_ops_branch,
2331 CLK_INIT(gsbi12_p_clk.c),
2332 },
2333};
2334
Tianyi Gou41515e22011-09-01 19:37:43 -07002335static struct branch_clk sata_phy_cfg_clk = {
2336 .b = {
2337 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2338 .en_mask = BIT(4),
2339 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2340 .halt_bit = 12,
2341 },
2342 .c = {
2343 .dbg_name = "sata_phy_cfg_clk",
2344 .ops = &clk_ops_branch,
2345 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002346 },
2347};
2348
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002349static struct branch_clk tsif_p_clk = {
2350 .b = {
2351 .ctl_reg = TSIF_HCLK_CTL_REG,
2352 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002353 .hwcg_reg = TSIF_HCLK_CTL_REG,
2354 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002355 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2356 .halt_bit = 7,
2357 },
2358 .c = {
2359 .dbg_name = "tsif_p_clk",
2360 .ops = &clk_ops_branch,
2361 CLK_INIT(tsif_p_clk.c),
2362 },
2363};
2364
2365static struct branch_clk usb_fs1_p_clk = {
2366 .b = {
2367 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2368 .en_mask = BIT(4),
2369 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2370 .halt_bit = 17,
2371 },
2372 .c = {
2373 .dbg_name = "usb_fs1_p_clk",
2374 .ops = &clk_ops_branch,
2375 CLK_INIT(usb_fs1_p_clk.c),
2376 },
2377};
2378
2379static struct branch_clk usb_fs2_p_clk = {
2380 .b = {
2381 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2382 .en_mask = BIT(4),
2383 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2384 .halt_bit = 14,
2385 },
2386 .c = {
2387 .dbg_name = "usb_fs2_p_clk",
2388 .ops = &clk_ops_branch,
2389 CLK_INIT(usb_fs2_p_clk.c),
2390 },
2391};
2392
2393static struct branch_clk usb_hs1_p_clk = {
2394 .b = {
2395 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2396 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002397 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2398 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002399 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2400 .halt_bit = 1,
2401 },
2402 .c = {
2403 .dbg_name = "usb_hs1_p_clk",
2404 .ops = &clk_ops_branch,
2405 CLK_INIT(usb_hs1_p_clk.c),
2406 },
2407};
2408
Tianyi Gou41515e22011-09-01 19:37:43 -07002409static struct branch_clk usb_hs3_p_clk = {
2410 .b = {
2411 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2412 .en_mask = BIT(4),
2413 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2414 .halt_bit = 31,
2415 },
2416 .c = {
2417 .dbg_name = "usb_hs3_p_clk",
2418 .ops = &clk_ops_branch,
2419 CLK_INIT(usb_hs3_p_clk.c),
2420 },
2421};
2422
2423static struct branch_clk usb_hs4_p_clk = {
2424 .b = {
2425 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2426 .en_mask = BIT(4),
2427 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2428 .halt_bit = 7,
2429 },
2430 .c = {
2431 .dbg_name = "usb_hs4_p_clk",
2432 .ops = &clk_ops_branch,
2433 CLK_INIT(usb_hs4_p_clk.c),
2434 },
2435};
2436
Stephen Boyd94625ef2011-07-12 17:06:01 -07002437static struct branch_clk usb_hsic_p_clk = {
2438 .b = {
2439 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2440 .en_mask = BIT(4),
2441 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2442 .halt_bit = 28,
2443 },
2444 .c = {
2445 .dbg_name = "usb_hsic_p_clk",
2446 .ops = &clk_ops_branch,
2447 CLK_INIT(usb_hsic_p_clk.c),
2448 },
2449};
2450
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002451static struct branch_clk sdc1_p_clk = {
2452 .b = {
2453 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2454 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002455 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2456 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002457 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2458 .halt_bit = 11,
2459 },
2460 .c = {
2461 .dbg_name = "sdc1_p_clk",
2462 .ops = &clk_ops_branch,
2463 CLK_INIT(sdc1_p_clk.c),
2464 },
2465};
2466
2467static struct branch_clk sdc2_p_clk = {
2468 .b = {
2469 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2470 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002471 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2472 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002473 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2474 .halt_bit = 10,
2475 },
2476 .c = {
2477 .dbg_name = "sdc2_p_clk",
2478 .ops = &clk_ops_branch,
2479 CLK_INIT(sdc2_p_clk.c),
2480 },
2481};
2482
2483static struct branch_clk sdc3_p_clk = {
2484 .b = {
2485 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2486 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002487 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2488 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002489 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2490 .halt_bit = 9,
2491 },
2492 .c = {
2493 .dbg_name = "sdc3_p_clk",
2494 .ops = &clk_ops_branch,
2495 CLK_INIT(sdc3_p_clk.c),
2496 },
2497};
2498
2499static struct branch_clk sdc4_p_clk = {
2500 .b = {
2501 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2502 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002503 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2504 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002505 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2506 .halt_bit = 8,
2507 },
2508 .c = {
2509 .dbg_name = "sdc4_p_clk",
2510 .ops = &clk_ops_branch,
2511 CLK_INIT(sdc4_p_clk.c),
2512 },
2513};
2514
2515static struct branch_clk sdc5_p_clk = {
2516 .b = {
2517 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2518 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002519 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2520 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002521 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2522 .halt_bit = 7,
2523 },
2524 .c = {
2525 .dbg_name = "sdc5_p_clk",
2526 .ops = &clk_ops_branch,
2527 CLK_INIT(sdc5_p_clk.c),
2528 },
2529};
2530
2531/* HW-Voteable Clocks */
2532static struct branch_clk adm0_clk = {
2533 .b = {
2534 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2535 .en_mask = BIT(2),
2536 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2537 .halt_check = HALT_VOTED,
2538 .halt_bit = 14,
2539 },
2540 .c = {
2541 .dbg_name = "adm0_clk",
2542 .ops = &clk_ops_branch,
2543 CLK_INIT(adm0_clk.c),
2544 },
2545};
2546
2547static struct branch_clk adm0_p_clk = {
2548 .b = {
2549 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2550 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002551 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2552 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002553 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2554 .halt_check = HALT_VOTED,
2555 .halt_bit = 13,
2556 },
2557 .c = {
2558 .dbg_name = "adm0_p_clk",
2559 .ops = &clk_ops_branch,
2560 CLK_INIT(adm0_p_clk.c),
2561 },
2562};
2563
2564static struct branch_clk pmic_arb0_p_clk = {
2565 .b = {
2566 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2567 .en_mask = BIT(8),
2568 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2569 .halt_check = HALT_VOTED,
2570 .halt_bit = 22,
2571 },
2572 .c = {
2573 .dbg_name = "pmic_arb0_p_clk",
2574 .ops = &clk_ops_branch,
2575 CLK_INIT(pmic_arb0_p_clk.c),
2576 },
2577};
2578
2579static struct branch_clk pmic_arb1_p_clk = {
2580 .b = {
2581 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2582 .en_mask = BIT(9),
2583 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2584 .halt_check = HALT_VOTED,
2585 .halt_bit = 21,
2586 },
2587 .c = {
2588 .dbg_name = "pmic_arb1_p_clk",
2589 .ops = &clk_ops_branch,
2590 CLK_INIT(pmic_arb1_p_clk.c),
2591 },
2592};
2593
2594static struct branch_clk pmic_ssbi2_clk = {
2595 .b = {
2596 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2597 .en_mask = BIT(7),
2598 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2599 .halt_check = HALT_VOTED,
2600 .halt_bit = 23,
2601 },
2602 .c = {
2603 .dbg_name = "pmic_ssbi2_clk",
2604 .ops = &clk_ops_branch,
2605 CLK_INIT(pmic_ssbi2_clk.c),
2606 },
2607};
2608
2609static struct branch_clk rpm_msg_ram_p_clk = {
2610 .b = {
2611 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2612 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002613 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2614 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002615 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2616 .halt_check = HALT_VOTED,
2617 .halt_bit = 12,
2618 },
2619 .c = {
2620 .dbg_name = "rpm_msg_ram_p_clk",
2621 .ops = &clk_ops_branch,
2622 CLK_INIT(rpm_msg_ram_p_clk.c),
2623 },
2624};
2625
2626/*
2627 * Multimedia Clocks
2628 */
2629
Stephen Boyd94625ef2011-07-12 17:06:01 -07002630#define CLK_CAM(name, n, hb) \
2631 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002632 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002633 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002634 .en_mask = BIT(0), \
2635 .halt_reg = DBG_BUS_VEC_I_REG, \
2636 .halt_bit = hb, \
2637 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002638 .ns_reg = CAMCLK##n##_NS_REG, \
2639 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002640 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002641 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Matt Wagantall07c45472012-02-10 23:27:24 -08002642 .mnd_en_mask = BIT(5), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002643 .ctl_mask = BM(7, 6), \
2644 .set_rate = set_rate_mnd_8, \
2645 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002646 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002647 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002648 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07002649 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002650 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002651 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002652 }, \
2653 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002654#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002655 { \
2656 .freq_hz = f, \
2657 .src_clk = &s##_clk.c, \
2658 .md_val = MD8(8, m, 0, n), \
2659 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2660 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002661 }
2662static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002663 F_CAM( 0, gnd, 1, 0, 0),
2664 F_CAM( 6000000, pll8, 4, 1, 16),
2665 F_CAM( 8000000, pll8, 4, 1, 12),
2666 F_CAM( 12000000, pll8, 4, 1, 8),
2667 F_CAM( 16000000, pll8, 4, 1, 6),
2668 F_CAM( 19200000, pll8, 4, 1, 5),
2669 F_CAM( 24000000, pll8, 4, 1, 4),
2670 F_CAM( 32000000, pll8, 4, 1, 3),
2671 F_CAM( 48000000, pll8, 4, 1, 2),
2672 F_CAM( 64000000, pll8, 3, 1, 2),
2673 F_CAM( 96000000, pll8, 4, 0, 0),
2674 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002675 F_END
2676};
2677
Stephen Boyd94625ef2011-07-12 17:06:01 -07002678static CLK_CAM(cam0_clk, 0, 15);
2679static CLK_CAM(cam1_clk, 1, 16);
2680static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002681
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002682#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002683 { \
2684 .freq_hz = f, \
2685 .src_clk = &s##_clk.c, \
2686 .md_val = MD8(8, m, 0, n), \
2687 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2688 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002689 }
2690static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002691 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002692 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002693 F_CSI( 85330000, pll8, 1, 2, 9),
2694 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002695 F_END
2696};
2697
2698static struct rcg_clk csi0_src_clk = {
2699 .ns_reg = CSI0_NS_REG,
2700 .b = {
2701 .ctl_reg = CSI0_CC_REG,
2702 .halt_check = NOCHECK,
2703 },
2704 .md_reg = CSI0_MD_REG,
2705 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002706 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002707 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002708 .ctl_mask = BM(7, 6),
2709 .set_rate = set_rate_mnd,
2710 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002711 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002712 .c = {
2713 .dbg_name = "csi0_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002714 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002715 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002716 CLK_INIT(csi0_src_clk.c),
2717 },
2718};
2719
2720static struct branch_clk csi0_clk = {
2721 .b = {
2722 .ctl_reg = CSI0_CC_REG,
2723 .en_mask = BIT(0),
2724 .reset_reg = SW_RESET_CORE_REG,
2725 .reset_mask = BIT(8),
2726 .halt_reg = DBG_BUS_VEC_B_REG,
2727 .halt_bit = 13,
2728 },
2729 .parent = &csi0_src_clk.c,
2730 .c = {
2731 .dbg_name = "csi0_clk",
2732 .ops = &clk_ops_branch,
2733 CLK_INIT(csi0_clk.c),
2734 },
2735};
2736
2737static struct branch_clk csi0_phy_clk = {
2738 .b = {
2739 .ctl_reg = CSI0_CC_REG,
2740 .en_mask = BIT(8),
2741 .reset_reg = SW_RESET_CORE_REG,
2742 .reset_mask = BIT(29),
2743 .halt_reg = DBG_BUS_VEC_I_REG,
2744 .halt_bit = 9,
2745 },
2746 .parent = &csi0_src_clk.c,
2747 .c = {
2748 .dbg_name = "csi0_phy_clk",
2749 .ops = &clk_ops_branch,
2750 CLK_INIT(csi0_phy_clk.c),
2751 },
2752};
2753
2754static struct rcg_clk csi1_src_clk = {
2755 .ns_reg = CSI1_NS_REG,
2756 .b = {
2757 .ctl_reg = CSI1_CC_REG,
2758 .halt_check = NOCHECK,
2759 },
2760 .md_reg = CSI1_MD_REG,
2761 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002762 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002763 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002764 .ctl_mask = BM(7, 6),
2765 .set_rate = set_rate_mnd,
2766 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002767 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002768 .c = {
2769 .dbg_name = "csi1_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002770 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002771 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002772 CLK_INIT(csi1_src_clk.c),
2773 },
2774};
2775
2776static struct branch_clk csi1_clk = {
2777 .b = {
2778 .ctl_reg = CSI1_CC_REG,
2779 .en_mask = BIT(0),
2780 .reset_reg = SW_RESET_CORE_REG,
2781 .reset_mask = BIT(18),
2782 .halt_reg = DBG_BUS_VEC_B_REG,
2783 .halt_bit = 14,
2784 },
2785 .parent = &csi1_src_clk.c,
2786 .c = {
2787 .dbg_name = "csi1_clk",
2788 .ops = &clk_ops_branch,
2789 CLK_INIT(csi1_clk.c),
2790 },
2791};
2792
2793static struct branch_clk csi1_phy_clk = {
2794 .b = {
2795 .ctl_reg = CSI1_CC_REG,
2796 .en_mask = BIT(8),
2797 .reset_reg = SW_RESET_CORE_REG,
2798 .reset_mask = BIT(28),
2799 .halt_reg = DBG_BUS_VEC_I_REG,
2800 .halt_bit = 10,
2801 },
2802 .parent = &csi1_src_clk.c,
2803 .c = {
2804 .dbg_name = "csi1_phy_clk",
2805 .ops = &clk_ops_branch,
2806 CLK_INIT(csi1_phy_clk.c),
2807 },
2808};
2809
Stephen Boyd94625ef2011-07-12 17:06:01 -07002810static struct rcg_clk csi2_src_clk = {
2811 .ns_reg = CSI2_NS_REG,
2812 .b = {
2813 .ctl_reg = CSI2_CC_REG,
2814 .halt_check = NOCHECK,
2815 },
2816 .md_reg = CSI2_MD_REG,
2817 .root_en_mask = BIT(2),
2818 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002819 .mnd_en_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002820 .ctl_mask = BM(7, 6),
2821 .set_rate = set_rate_mnd,
2822 .freq_tbl = clk_tbl_csi,
2823 .current_freq = &rcg_dummy_freq,
2824 .c = {
2825 .dbg_name = "csi2_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002826 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002827 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002828 CLK_INIT(csi2_src_clk.c),
2829 },
2830};
2831
2832static struct branch_clk csi2_clk = {
2833 .b = {
2834 .ctl_reg = CSI2_CC_REG,
2835 .en_mask = BIT(0),
2836 .reset_reg = SW_RESET_CORE2_REG,
2837 .reset_mask = BIT(2),
2838 .halt_reg = DBG_BUS_VEC_B_REG,
2839 .halt_bit = 29,
2840 },
2841 .parent = &csi2_src_clk.c,
2842 .c = {
2843 .dbg_name = "csi2_clk",
2844 .ops = &clk_ops_branch,
2845 CLK_INIT(csi2_clk.c),
2846 },
2847};
2848
2849static struct branch_clk csi2_phy_clk = {
2850 .b = {
2851 .ctl_reg = CSI2_CC_REG,
2852 .en_mask = BIT(8),
2853 .reset_reg = SW_RESET_CORE_REG,
2854 .reset_mask = BIT(31),
2855 .halt_reg = DBG_BUS_VEC_I_REG,
2856 .halt_bit = 29,
2857 },
2858 .parent = &csi2_src_clk.c,
2859 .c = {
2860 .dbg_name = "csi2_phy_clk",
2861 .ops = &clk_ops_branch,
2862 CLK_INIT(csi2_phy_clk.c),
2863 },
2864};
2865
Stephen Boyd092fd182011-10-21 15:56:30 -07002866static struct clk *pix_rdi_mux_map[] = {
2867 [0] = &csi0_clk.c,
2868 [1] = &csi1_clk.c,
2869 [2] = &csi2_clk.c,
2870 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002871};
2872
Stephen Boyd092fd182011-10-21 15:56:30 -07002873struct pix_rdi_clk {
Stephen Boydd86d1f22012-01-24 17:36:34 -08002874 bool prepared;
Stephen Boyd092fd182011-10-21 15:56:30 -07002875 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002876 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002877
2878 void __iomem *const s_reg;
2879 u32 s_mask;
2880
2881 void __iomem *const s2_reg;
2882 u32 s2_mask;
2883
2884 struct branch b;
2885 struct clk c;
2886};
2887
Matt Wagantallf82f2942012-01-27 13:56:13 -08002888static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002889{
Matt Wagantallf82f2942012-01-27 13:56:13 -08002890 return container_of(c, struct pix_rdi_clk, c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002891}
2892
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002893static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002894{
2895 int ret, i;
2896 u32 reg;
2897 unsigned long flags;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002898 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002899 struct clk **mux_map = pix_rdi_mux_map;
Stephen Boydd86d1f22012-01-24 17:36:34 -08002900 unsigned long old_rate = rdi->cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002901
2902 /*
2903 * These clocks select three inputs via two muxes. One mux selects
2904 * between csi0 and csi1 and the second mux selects between that mux's
2905 * output and csi2. The source and destination selections for each
2906 * mux must be clocking for the switch to succeed so just turn on
2907 * all three sources because it's easier than figuring out what source
2908 * needs to be on at what time.
2909 */
2910 for (i = 0; mux_map[i]; i++) {
Stephen Boydd86d1f22012-01-24 17:36:34 -08002911 ret = clk_prepare_enable(mux_map[i]);
Stephen Boyd092fd182011-10-21 15:56:30 -07002912 if (ret)
2913 goto err;
2914 }
2915 if (rate >= i) {
2916 ret = -EINVAL;
2917 goto err;
2918 }
2919 /* Keep the new source on when switching inputs of an enabled clock */
Stephen Boydd86d1f22012-01-24 17:36:34 -08002920 if (rdi->prepared) {
2921 ret = clk_prepare(mux_map[rate]);
2922 if (ret)
2923 goto err;
Stephen Boyd092fd182011-10-21 15:56:30 -07002924 }
Stephen Boydd86d1f22012-01-24 17:36:34 -08002925 spin_lock_irqsave(&c->lock, flags);
2926 if (rdi->enabled) {
2927 ret = clk_enable(mux_map[rate]);
2928 if (ret) {
2929 spin_unlock_irqrestore(&c->lock, flags);
2930 clk_unprepare(mux_map[rate]);
2931 goto err;
2932 }
2933 }
2934 spin_lock(&local_clock_reg_lock);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002935 reg = readl_relaxed(rdi->s2_reg);
2936 reg &= ~rdi->s2_mask;
2937 reg |= rate == 2 ? rdi->s2_mask : 0;
2938 writel_relaxed(reg, rdi->s2_reg);
Stephen Boyd092fd182011-10-21 15:56:30 -07002939 /*
2940 * Wait at least 6 cycles of slowest clock
2941 * for the glitch-free MUX to fully switch sources.
2942 */
2943 mb();
2944 udelay(1);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002945 reg = readl_relaxed(rdi->s_reg);
2946 reg &= ~rdi->s_mask;
2947 reg |= rate == 1 ? rdi->s_mask : 0;
2948 writel_relaxed(reg, rdi->s_reg);
Stephen Boyd092fd182011-10-21 15:56:30 -07002949 /*
2950 * Wait at least 6 cycles of slowest clock
2951 * for the glitch-free MUX to fully switch sources.
2952 */
2953 mb();
2954 udelay(1);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002955 rdi->cur_rate = rate;
Stephen Boydd86d1f22012-01-24 17:36:34 -08002956 spin_unlock(&local_clock_reg_lock);
2957
2958 if (rdi->enabled)
2959 clk_disable(mux_map[old_rate]);
2960 spin_unlock_irqrestore(&c->lock, flags);
2961 if (rdi->prepared)
2962 clk_unprepare(mux_map[old_rate]);
Stephen Boyd092fd182011-10-21 15:56:30 -07002963err:
2964 for (i--; i >= 0; i--)
Stephen Boydd86d1f22012-01-24 17:36:34 -08002965 clk_disable_unprepare(mux_map[i]);
Stephen Boyd092fd182011-10-21 15:56:30 -07002966
2967 return 0;
2968}
2969
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002970static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002971{
2972 return to_pix_rdi_clk(c)->cur_rate;
2973}
2974
Stephen Boydd86d1f22012-01-24 17:36:34 -08002975static int pix_rdi_clk_prepare(struct clk *c)
2976{
2977 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
2978 rdi->prepared = true;
2979 return 0;
2980}
2981
Stephen Boyd092fd182011-10-21 15:56:30 -07002982static int pix_rdi_clk_enable(struct clk *c)
2983{
2984 unsigned long flags;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002985 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002986
2987 spin_lock_irqsave(&local_clock_reg_lock, flags);
Matt Wagantall0de1b3f2012-06-05 19:52:43 -07002988 __branch_enable_reg(&rdi->b, rdi->c.dbg_name);
Stephen Boyd092fd182011-10-21 15:56:30 -07002989 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
Matt Wagantallf82f2942012-01-27 13:56:13 -08002990 rdi->enabled = true;
Stephen Boyd092fd182011-10-21 15:56:30 -07002991
2992 return 0;
2993}
2994
2995static void pix_rdi_clk_disable(struct clk *c)
2996{
2997 unsigned long flags;
Matt Wagantallf82f2942012-01-27 13:56:13 -08002998 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Stephen Boyd092fd182011-10-21 15:56:30 -07002999
3000 spin_lock_irqsave(&local_clock_reg_lock, flags);
Matt Wagantall0de1b3f2012-06-05 19:52:43 -07003001 __branch_disable_reg(&rdi->b, rdi->c.dbg_name);
Stephen Boyd092fd182011-10-21 15:56:30 -07003002 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
Matt Wagantallf82f2942012-01-27 13:56:13 -08003003 rdi->enabled = false;
Stephen Boyd092fd182011-10-21 15:56:30 -07003004}
3005
Stephen Boydd86d1f22012-01-24 17:36:34 -08003006static void pix_rdi_clk_unprepare(struct clk *c)
3007{
3008 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
3009 rdi->prepared = false;
3010}
3011
Matt Wagantallf82f2942012-01-27 13:56:13 -08003012static int pix_rdi_clk_reset(struct clk *c, enum clk_reset_action action)
Stephen Boyd092fd182011-10-21 15:56:30 -07003013{
Matt Wagantallf82f2942012-01-27 13:56:13 -08003014 return branch_reset(&to_pix_rdi_clk(c)->b, action);
Stephen Boyd092fd182011-10-21 15:56:30 -07003015}
3016
3017static struct clk *pix_rdi_clk_get_parent(struct clk *c)
3018{
Matt Wagantallf82f2942012-01-27 13:56:13 -08003019 return pix_rdi_mux_map[to_pix_rdi_clk(c)->cur_rate];
Stephen Boyd092fd182011-10-21 15:56:30 -07003020}
3021
3022static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
3023{
3024 if (pix_rdi_mux_map[n])
3025 return n;
3026 return -ENXIO;
3027}
3028
Matt Wagantalla15833b2012-04-03 11:00:56 -07003029static enum handoff pix_rdi_clk_handoff(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07003030{
3031 u32 reg;
Matt Wagantallf82f2942012-01-27 13:56:13 -08003032 struct pix_rdi_clk *rdi = to_pix_rdi_clk(c);
Matt Wagantalla15833b2012-04-03 11:00:56 -07003033 enum handoff ret;
3034
Matt Wagantallf82f2942012-01-27 13:56:13 -08003035 ret = branch_handoff(&rdi->b, &rdi->c);
Matt Wagantalla15833b2012-04-03 11:00:56 -07003036 if (ret == HANDOFF_DISABLED_CLK)
3037 return ret;
Stephen Boyd092fd182011-10-21 15:56:30 -07003038
Matt Wagantallf82f2942012-01-27 13:56:13 -08003039 reg = readl_relaxed(rdi->s_reg);
3040 rdi->cur_rate = reg & rdi->s_mask ? 1 : 0;
3041 reg = readl_relaxed(rdi->s2_reg);
3042 rdi->cur_rate = reg & rdi->s2_mask ? 2 : rdi->cur_rate;
Matt Wagantalla15833b2012-04-03 11:00:56 -07003043
3044 return HANDOFF_ENABLED_CLK;
Stephen Boyd092fd182011-10-21 15:56:30 -07003045}
3046
3047static struct clk_ops clk_ops_pix_rdi_8960 = {
Stephen Boydd86d1f22012-01-24 17:36:34 -08003048 .prepare = pix_rdi_clk_prepare,
Stephen Boyd092fd182011-10-21 15:56:30 -07003049 .enable = pix_rdi_clk_enable,
3050 .disable = pix_rdi_clk_disable,
Stephen Boydd86d1f22012-01-24 17:36:34 -08003051 .unprepare = pix_rdi_clk_unprepare,
Stephen Boyd092fd182011-10-21 15:56:30 -07003052 .handoff = pix_rdi_clk_handoff,
3053 .set_rate = pix_rdi_clk_set_rate,
3054 .get_rate = pix_rdi_clk_get_rate,
3055 .list_rate = pix_rdi_clk_list_rate,
3056 .reset = pix_rdi_clk_reset,
Stephen Boyd092fd182011-10-21 15:56:30 -07003057 .get_parent = pix_rdi_clk_get_parent,
3058};
3059
3060static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003061 .b = {
3062 .ctl_reg = MISC_CC_REG,
3063 .en_mask = BIT(26),
3064 .halt_check = DELAY,
3065 .reset_reg = SW_RESET_CORE_REG,
3066 .reset_mask = BIT(26),
3067 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003068 .s_reg = MISC_CC_REG,
3069 .s_mask = BIT(25),
3070 .s2_reg = MISC_CC3_REG,
3071 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003072 .c = {
3073 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003074 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003075 CLK_INIT(csi_pix_clk.c),
3076 },
3077};
3078
Stephen Boyd092fd182011-10-21 15:56:30 -07003079static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003080 .b = {
3081 .ctl_reg = MISC_CC3_REG,
3082 .en_mask = BIT(10),
3083 .halt_check = DELAY,
3084 .reset_reg = SW_RESET_CORE_REG,
3085 .reset_mask = BIT(30),
3086 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003087 .s_reg = MISC_CC3_REG,
3088 .s_mask = BIT(8),
3089 .s2_reg = MISC_CC3_REG,
3090 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003091 .c = {
3092 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003093 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003094 CLK_INIT(csi_pix1_clk.c),
3095 },
3096};
3097
Stephen Boyd092fd182011-10-21 15:56:30 -07003098static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003099 .b = {
3100 .ctl_reg = MISC_CC_REG,
3101 .en_mask = BIT(13),
3102 .halt_check = DELAY,
3103 .reset_reg = SW_RESET_CORE_REG,
3104 .reset_mask = BIT(27),
3105 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003106 .s_reg = MISC_CC_REG,
3107 .s_mask = BIT(12),
3108 .s2_reg = MISC_CC3_REG,
3109 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003110 .c = {
3111 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003112 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003113 CLK_INIT(csi_rdi_clk.c),
3114 },
3115};
3116
Stephen Boyd092fd182011-10-21 15:56:30 -07003117static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003118 .b = {
3119 .ctl_reg = MISC_CC3_REG,
3120 .en_mask = BIT(2),
3121 .halt_check = DELAY,
3122 .reset_reg = SW_RESET_CORE2_REG,
3123 .reset_mask = BIT(1),
3124 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003125 .s_reg = MISC_CC3_REG,
3126 .s_mask = BIT(0),
3127 .s2_reg = MISC_CC3_REG,
3128 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003129 .c = {
3130 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003131 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003132 CLK_INIT(csi_rdi1_clk.c),
3133 },
3134};
3135
Stephen Boyd092fd182011-10-21 15:56:30 -07003136static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003137 .b = {
3138 .ctl_reg = MISC_CC3_REG,
3139 .en_mask = BIT(6),
3140 .halt_check = DELAY,
3141 .reset_reg = SW_RESET_CORE2_REG,
3142 .reset_mask = BIT(0),
3143 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003144 .s_reg = MISC_CC3_REG,
3145 .s_mask = BIT(4),
3146 .s2_reg = MISC_CC3_REG,
3147 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003148 .c = {
3149 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003150 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003151 CLK_INIT(csi_rdi2_clk.c),
3152 },
3153};
3154
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003155#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003156 { \
3157 .freq_hz = f, \
3158 .src_clk = &s##_clk.c, \
3159 .md_val = MD8(8, m, 0, n), \
3160 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3161 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003162 }
3163static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003164 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
3165 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
3166 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003167 F_END
3168};
3169
3170static struct rcg_clk csiphy_timer_src_clk = {
3171 .ns_reg = CSIPHYTIMER_NS_REG,
3172 .b = {
3173 .ctl_reg = CSIPHYTIMER_CC_REG,
3174 .halt_check = NOCHECK,
3175 },
3176 .md_reg = CSIPHYTIMER_MD_REG,
3177 .root_en_mask = BIT(2),
3178 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003179 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003180 .ctl_mask = BM(7, 6),
3181 .set_rate = set_rate_mnd_8,
3182 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003183 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003184 .c = {
3185 .dbg_name = "csiphy_timer_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003186 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003187 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003188 CLK_INIT(csiphy_timer_src_clk.c),
3189 },
3190};
3191
3192static struct branch_clk csi0phy_timer_clk = {
3193 .b = {
3194 .ctl_reg = CSIPHYTIMER_CC_REG,
3195 .en_mask = BIT(0),
3196 .halt_reg = DBG_BUS_VEC_I_REG,
3197 .halt_bit = 17,
3198 },
3199 .parent = &csiphy_timer_src_clk.c,
3200 .c = {
3201 .dbg_name = "csi0phy_timer_clk",
3202 .ops = &clk_ops_branch,
3203 CLK_INIT(csi0phy_timer_clk.c),
3204 },
3205};
3206
3207static struct branch_clk csi1phy_timer_clk = {
3208 .b = {
3209 .ctl_reg = CSIPHYTIMER_CC_REG,
3210 .en_mask = BIT(9),
3211 .halt_reg = DBG_BUS_VEC_I_REG,
3212 .halt_bit = 18,
3213 },
3214 .parent = &csiphy_timer_src_clk.c,
3215 .c = {
3216 .dbg_name = "csi1phy_timer_clk",
3217 .ops = &clk_ops_branch,
3218 CLK_INIT(csi1phy_timer_clk.c),
3219 },
3220};
3221
Stephen Boyd94625ef2011-07-12 17:06:01 -07003222static struct branch_clk csi2phy_timer_clk = {
3223 .b = {
3224 .ctl_reg = CSIPHYTIMER_CC_REG,
3225 .en_mask = BIT(11),
3226 .halt_reg = DBG_BUS_VEC_I_REG,
3227 .halt_bit = 30,
3228 },
3229 .parent = &csiphy_timer_src_clk.c,
3230 .c = {
3231 .dbg_name = "csi2phy_timer_clk",
3232 .ops = &clk_ops_branch,
3233 CLK_INIT(csi2phy_timer_clk.c),
3234 },
3235};
3236
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003237#define F_DSI(d) \
3238 { \
3239 .freq_hz = d, \
3240 .ns_val = BVAL(15, 12, (d-1)), \
3241 }
3242/*
3243 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3244 * without this clock driver knowing. So, overload the clk_set_rate() to set
3245 * the divider (1 to 16) of the clock with respect to the PLL rate.
3246 */
3247static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3248 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3249 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3250 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3251 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3252 F_END
3253};
3254
Matt Wagantall735e41b2012-07-23 17:18:58 -07003255static struct branch_clk dsi1_reset_clk = {
3256 .b = {
3257 .reset_reg = SW_RESET_CORE_REG,
3258 .reset_mask = BIT(7),
3259 .halt_check = NOCHECK,
3260 },
3261 .c = {
3262 .dbg_name = "dsi1_reset_clk",
3263 .ops = &clk_ops_branch,
3264 CLK_INIT(dsi1_reset_clk.c),
3265 },
3266};
3267
3268static struct branch_clk dsi2_reset_clk = {
3269 .b = {
3270 .reset_reg = SW_RESET_CORE_REG,
3271 .reset_mask = BIT(25),
3272 .halt_check = NOCHECK,
3273 },
3274 .c = {
3275 .dbg_name = "dsi2_reset_clk",
3276 .ops = &clk_ops_branch,
3277 CLK_INIT(dsi2_reset_clk.c),
3278 },
3279};
3280
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003281static struct rcg_clk dsi1_byte_clk = {
3282 .b = {
3283 .ctl_reg = DSI1_BYTE_CC_REG,
3284 .en_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003285 .halt_reg = DBG_BUS_VEC_B_REG,
3286 .halt_bit = 21,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003287 .retain_reg = DSI1_BYTE_CC_REG,
3288 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003289 },
3290 .ns_reg = DSI1_BYTE_NS_REG,
3291 .root_en_mask = BIT(2),
3292 .ns_mask = BM(15, 12),
3293 .set_rate = set_rate_nop,
3294 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003295 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003296 .c = {
3297 .dbg_name = "dsi1_byte_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003298 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003299 CLK_INIT(dsi1_byte_clk.c),
3300 },
3301};
3302
3303static struct rcg_clk dsi2_byte_clk = {
3304 .b = {
3305 .ctl_reg = DSI2_BYTE_CC_REG,
3306 .en_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003307 .halt_reg = DBG_BUS_VEC_B_REG,
3308 .halt_bit = 20,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003309 .retain_reg = DSI2_BYTE_CC_REG,
3310 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003311 },
3312 .ns_reg = DSI2_BYTE_NS_REG,
3313 .root_en_mask = BIT(2),
3314 .ns_mask = BM(15, 12),
3315 .set_rate = set_rate_nop,
3316 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003317 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003318 .c = {
3319 .dbg_name = "dsi2_byte_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003320 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003321 CLK_INIT(dsi2_byte_clk.c),
3322 },
3323};
3324
3325static struct rcg_clk dsi1_esc_clk = {
3326 .b = {
3327 .ctl_reg = DSI1_ESC_CC_REG,
3328 .en_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003329 .halt_reg = DBG_BUS_VEC_I_REG,
3330 .halt_bit = 1,
3331 },
3332 .ns_reg = DSI1_ESC_NS_REG,
3333 .root_en_mask = BIT(2),
3334 .ns_mask = BM(15, 12),
3335 .set_rate = set_rate_nop,
3336 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003337 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003338 .c = {
3339 .dbg_name = "dsi1_esc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003340 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003341 CLK_INIT(dsi1_esc_clk.c),
3342 },
3343};
3344
3345static struct rcg_clk dsi2_esc_clk = {
3346 .b = {
3347 .ctl_reg = DSI2_ESC_CC_REG,
3348 .en_mask = BIT(0),
3349 .halt_reg = DBG_BUS_VEC_I_REG,
3350 .halt_bit = 3,
3351 },
3352 .ns_reg = DSI2_ESC_NS_REG,
3353 .root_en_mask = BIT(2),
3354 .ns_mask = BM(15, 12),
3355 .set_rate = set_rate_nop,
3356 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003357 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003358 .c = {
3359 .dbg_name = "dsi2_esc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003360 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003361 CLK_INIT(dsi2_esc_clk.c),
3362 },
3363};
3364
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003365#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003366 { \
3367 .freq_hz = f, \
3368 .src_clk = &s##_clk.c, \
3369 .md_val = MD4(4, m, 0, n), \
3370 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3371 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003372 }
3373static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003374 F_GFX2D( 0, gnd, 0, 0),
3375 F_GFX2D( 27000000, pxo, 0, 0),
3376 F_GFX2D( 48000000, pll8, 1, 8),
3377 F_GFX2D( 54857000, pll8, 1, 7),
3378 F_GFX2D( 64000000, pll8, 1, 6),
3379 F_GFX2D( 76800000, pll8, 1, 5),
3380 F_GFX2D( 96000000, pll8, 1, 4),
3381 F_GFX2D(128000000, pll8, 1, 3),
3382 F_GFX2D(145455000, pll2, 2, 11),
3383 F_GFX2D(160000000, pll2, 1, 5),
3384 F_GFX2D(177778000, pll2, 2, 9),
3385 F_GFX2D(200000000, pll2, 1, 4),
3386 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003387 F_END
3388};
3389
3390static struct bank_masks bmnd_info_gfx2d0 = {
3391 .bank_sel_mask = BIT(11),
3392 .bank0_mask = {
3393 .md_reg = GFX2D0_MD0_REG,
3394 .ns_mask = BM(23, 20) | BM(5, 3),
3395 .rst_mask = BIT(25),
3396 .mnd_en_mask = BIT(8),
3397 .mode_mask = BM(10, 9),
3398 },
3399 .bank1_mask = {
3400 .md_reg = GFX2D0_MD1_REG,
3401 .ns_mask = BM(19, 16) | BM(2, 0),
3402 .rst_mask = BIT(24),
3403 .mnd_en_mask = BIT(5),
3404 .mode_mask = BM(7, 6),
3405 },
3406};
3407
3408static struct rcg_clk gfx2d0_clk = {
3409 .b = {
3410 .ctl_reg = GFX2D0_CC_REG,
3411 .en_mask = BIT(0),
3412 .reset_reg = SW_RESET_CORE_REG,
3413 .reset_mask = BIT(14),
3414 .halt_reg = DBG_BUS_VEC_A_REG,
3415 .halt_bit = 9,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003416 .retain_reg = GFX2D0_CC_REG,
3417 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003418 },
3419 .ns_reg = GFX2D0_NS_REG,
3420 .root_en_mask = BIT(2),
3421 .set_rate = set_rate_mnd_banked,
3422 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003423 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003424 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003425 .c = {
3426 .dbg_name = "gfx2d0_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003427 .ops = &clk_ops_rcg,
Matt Wagantall158f73b2012-05-16 11:29:35 -07003428 .flags = CLKFLAG_SKIP_HANDOFF,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003429 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3430 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003431 CLK_INIT(gfx2d0_clk.c),
3432 },
3433};
3434
3435static struct bank_masks bmnd_info_gfx2d1 = {
3436 .bank_sel_mask = BIT(11),
3437 .bank0_mask = {
3438 .md_reg = GFX2D1_MD0_REG,
3439 .ns_mask = BM(23, 20) | BM(5, 3),
3440 .rst_mask = BIT(25),
3441 .mnd_en_mask = BIT(8),
3442 .mode_mask = BM(10, 9),
3443 },
3444 .bank1_mask = {
3445 .md_reg = GFX2D1_MD1_REG,
3446 .ns_mask = BM(19, 16) | BM(2, 0),
3447 .rst_mask = BIT(24),
3448 .mnd_en_mask = BIT(5),
3449 .mode_mask = BM(7, 6),
3450 },
3451};
3452
3453static struct rcg_clk gfx2d1_clk = {
3454 .b = {
3455 .ctl_reg = GFX2D1_CC_REG,
3456 .en_mask = BIT(0),
3457 .reset_reg = SW_RESET_CORE_REG,
3458 .reset_mask = BIT(13),
3459 .halt_reg = DBG_BUS_VEC_A_REG,
3460 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003461 .retain_reg = GFX2D1_CC_REG,
3462 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003463 },
3464 .ns_reg = GFX2D1_NS_REG,
3465 .root_en_mask = BIT(2),
3466 .set_rate = set_rate_mnd_banked,
3467 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003468 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003469 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003470 .c = {
3471 .dbg_name = "gfx2d1_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003472 .ops = &clk_ops_rcg,
Matt Wagantall158f73b2012-05-16 11:29:35 -07003473 .flags = CLKFLAG_SKIP_HANDOFF,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003474 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3475 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003476 CLK_INIT(gfx2d1_clk.c),
3477 },
3478};
3479
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003480#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003481 { \
3482 .freq_hz = f, \
3483 .src_clk = &s##_clk.c, \
3484 .md_val = MD4(4, m, 0, n), \
3485 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3486 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003487 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003488
Patrick Dalye6f489042012-07-11 15:29:15 -07003489static struct clk_freq_tbl clk_tbl_gfx3d_8960ab[] = {
3490 F_GFX3D( 0, gnd, 0, 0),
3491 F_GFX3D( 27000000, pxo, 0, 0),
3492 F_GFX3D( 48000000, pll8, 1, 8),
3493 F_GFX3D( 54857000, pll8, 1, 7),
3494 F_GFX3D( 64000000, pll8, 1, 6),
3495 F_GFX3D( 76800000, pll8, 1, 5),
3496 F_GFX3D( 96000000, pll8, 1, 4),
3497 F_GFX3D(128000000, pll8, 1, 3),
3498 F_GFX3D(145455000, pll2, 2, 11),
3499 F_GFX3D(160000000, pll2, 1, 5),
3500 F_GFX3D(177778000, pll2, 2, 9),
3501 F_GFX3D(200000000, pll2, 1, 4),
3502 F_GFX3D(228571000, pll2, 2, 7),
3503 F_GFX3D(266667000, pll2, 1, 3),
3504 F_GFX3D(320000000, pll2, 2, 5),
3505 F_GFX3D(325000000, pll3, 1, 2),
3506 F_GFX3D(400000000, pll2, 1, 2),
3507 F_END
3508};
3509
Tianyi Gou41515e22011-09-01 19:37:43 -07003510static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003511 F_GFX3D( 0, gnd, 0, 0),
3512 F_GFX3D( 27000000, pxo, 0, 0),
3513 F_GFX3D( 48000000, pll8, 1, 8),
3514 F_GFX3D( 54857000, pll8, 1, 7),
3515 F_GFX3D( 64000000, pll8, 1, 6),
3516 F_GFX3D( 76800000, pll8, 1, 5),
3517 F_GFX3D( 96000000, pll8, 1, 4),
3518 F_GFX3D(128000000, pll8, 1, 3),
3519 F_GFX3D(145455000, pll2, 2, 11),
3520 F_GFX3D(160000000, pll2, 1, 5),
3521 F_GFX3D(177778000, pll2, 2, 9),
3522 F_GFX3D(200000000, pll2, 1, 4),
3523 F_GFX3D(228571000, pll2, 2, 7),
3524 F_GFX3D(266667000, pll2, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003525 F_GFX3D(300000000, pll3, 1, 4),
3526 F_GFX3D(320000000, pll2, 2, 5),
3527 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003528 F_END
3529};
3530
Tianyi Gou41515e22011-09-01 19:37:43 -07003531static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003532 F_GFX3D( 0, gnd, 0, 0),
3533 F_GFX3D( 27000000, pxo, 0, 0),
3534 F_GFX3D( 48000000, pll8, 1, 8),
3535 F_GFX3D( 54857000, pll8, 1, 7),
3536 F_GFX3D( 64000000, pll8, 1, 6),
3537 F_GFX3D( 76800000, pll8, 1, 5),
3538 F_GFX3D( 96000000, pll8, 1, 4),
3539 F_GFX3D(128000000, pll8, 1, 3),
3540 F_GFX3D(145455000, pll2, 2, 11),
3541 F_GFX3D(160000000, pll2, 1, 5),
3542 F_GFX3D(177778000, pll2, 2, 9),
3543 F_GFX3D(200000000, pll2, 1, 4),
3544 F_GFX3D(228571000, pll2, 2, 7),
3545 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003546 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003547 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003548 F_END
3549};
3550
Tianyi Goue3d4f542012-03-15 17:06:45 -07003551static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = {
3552 F_GFX3D( 0, gnd, 0, 0),
3553 F_GFX3D( 27000000, pxo, 0, 0),
3554 F_GFX3D( 48000000, pll8, 1, 8),
3555 F_GFX3D( 54857000, pll8, 1, 7),
3556 F_GFX3D( 64000000, pll8, 1, 6),
3557 F_GFX3D( 76800000, pll8, 1, 5),
3558 F_GFX3D( 96000000, pll8, 1, 4),
3559 F_GFX3D(128000000, pll8, 1, 3),
3560 F_GFX3D(145455000, pll2, 2, 11),
3561 F_GFX3D(160000000, pll2, 1, 5),
3562 F_GFX3D(177778000, pll2, 2, 9),
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003563 F_GFX3D(192000000, pll8, 1, 2),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003564 F_GFX3D(200000000, pll2, 1, 4),
3565 F_GFX3D(228571000, pll2, 2, 7),
3566 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003567 F_GFX3D(320000000, pll2, 2, 5),
3568 F_GFX3D(400000000, pll2, 1, 2),
3569 F_GFX3D(450000000, pll15, 1, 2),
3570 F_END
3571};
3572
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003573static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3574 [VDD_DIG_LOW] = 128000000,
3575 [VDD_DIG_NOMINAL] = 325000000,
3576 [VDD_DIG_HIGH] = 400000000
3577};
3578
Tianyi Goue3d4f542012-03-15 17:06:45 -07003579static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = {
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003580 [VDD_DIG_LOW] = 192000000,
Tianyi Goue3d4f542012-03-15 17:06:45 -07003581 [VDD_DIG_NOMINAL] = 320000000,
Patrick Dalyebe63c52012-08-07 15:41:30 -07003582 [VDD_DIG_HIGH] = 400000000
3583};
3584
3585static unsigned long fmax_gfx3d_8930aa[MAX_VDD_LEVELS] __initdata = {
3586 [VDD_DIG_LOW] = 192000000,
3587 [VDD_DIG_NOMINAL] = 320000000,
Tianyi Goue3d4f542012-03-15 17:06:45 -07003588 [VDD_DIG_HIGH] = 450000000
3589};
3590
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003591static struct bank_masks bmnd_info_gfx3d = {
3592 .bank_sel_mask = BIT(11),
3593 .bank0_mask = {
3594 .md_reg = GFX3D_MD0_REG,
3595 .ns_mask = BM(21, 18) | BM(5, 3),
3596 .rst_mask = BIT(23),
3597 .mnd_en_mask = BIT(8),
3598 .mode_mask = BM(10, 9),
3599 },
3600 .bank1_mask = {
3601 .md_reg = GFX3D_MD1_REG,
3602 .ns_mask = BM(17, 14) | BM(2, 0),
3603 .rst_mask = BIT(22),
3604 .mnd_en_mask = BIT(5),
3605 .mode_mask = BM(7, 6),
3606 },
3607};
3608
3609static struct rcg_clk gfx3d_clk = {
3610 .b = {
3611 .ctl_reg = GFX3D_CC_REG,
3612 .en_mask = BIT(0),
3613 .reset_reg = SW_RESET_CORE_REG,
3614 .reset_mask = BIT(12),
3615 .halt_reg = DBG_BUS_VEC_A_REG,
3616 .halt_bit = 4,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003617 .retain_reg = GFX3D_CC_REG,
3618 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003619 },
3620 .ns_reg = GFX3D_NS_REG,
3621 .root_en_mask = BIT(2),
3622 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003623 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003624 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003625 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003626 .c = {
3627 .dbg_name = "gfx3d_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003628 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003629 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
3630 HIGH, 400000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003631 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003632 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003633 },
3634};
3635
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003636#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003637 { \
3638 .freq_hz = f, \
3639 .src_clk = &s##_clk.c, \
3640 .md_val = MD4(4, m, 0, n), \
3641 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3642 .ctl_val = CC_BANKED(9, 6, n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003643 }
3644
3645static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003646 F_VCAP( 0, gnd, 0, 0),
3647 F_VCAP( 27000000, pxo, 0, 0),
3648 F_VCAP( 54860000, pll8, 1, 7),
3649 F_VCAP( 64000000, pll8, 1, 6),
3650 F_VCAP( 76800000, pll8, 1, 5),
3651 F_VCAP(128000000, pll8, 1, 3),
3652 F_VCAP(160000000, pll2, 1, 5),
3653 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003654 F_END
3655};
3656
3657static struct bank_masks bmnd_info_vcap = {
3658 .bank_sel_mask = BIT(11),
3659 .bank0_mask = {
3660 .md_reg = VCAP_MD0_REG,
3661 .ns_mask = BM(21, 18) | BM(5, 3),
3662 .rst_mask = BIT(23),
3663 .mnd_en_mask = BIT(8),
3664 .mode_mask = BM(10, 9),
3665 },
3666 .bank1_mask = {
3667 .md_reg = VCAP_MD1_REG,
3668 .ns_mask = BM(17, 14) | BM(2, 0),
3669 .rst_mask = BIT(22),
3670 .mnd_en_mask = BIT(5),
3671 .mode_mask = BM(7, 6),
3672 },
3673};
3674
3675static struct rcg_clk vcap_clk = {
3676 .b = {
3677 .ctl_reg = VCAP_CC_REG,
3678 .en_mask = BIT(0),
3679 .halt_reg = DBG_BUS_VEC_J_REG,
3680 .halt_bit = 15,
3681 },
3682 .ns_reg = VCAP_NS_REG,
3683 .root_en_mask = BIT(2),
3684 .set_rate = set_rate_mnd_banked,
3685 .freq_tbl = clk_tbl_vcap,
3686 .bank_info = &bmnd_info_vcap,
3687 .current_freq = &rcg_dummy_freq,
3688 .c = {
3689 .dbg_name = "vcap_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003690 .ops = &clk_ops_rcg,
Tianyi Gou621f8742011-09-01 21:45:01 -07003691 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003692 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003693 CLK_INIT(vcap_clk.c),
3694 },
3695};
3696
3697static struct branch_clk vcap_npl_clk = {
3698 .b = {
3699 .ctl_reg = VCAP_CC_REG,
3700 .en_mask = BIT(13),
3701 .halt_reg = DBG_BUS_VEC_J_REG,
3702 .halt_bit = 25,
3703 },
3704 .parent = &vcap_clk.c,
3705 .c = {
3706 .dbg_name = "vcap_npl_clk",
3707 .ops = &clk_ops_branch,
3708 CLK_INIT(vcap_npl_clk.c),
3709 },
3710};
3711
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003712#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003713 { \
3714 .freq_hz = f, \
3715 .src_clk = &s##_clk.c, \
3716 .md_val = MD8(8, m, 0, n), \
3717 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3718 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003719 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003720
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003721static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3722 F_IJPEG( 0, gnd, 1, 0, 0),
3723 F_IJPEG( 27000000, pxo, 1, 0, 0),
3724 F_IJPEG( 36570000, pll8, 1, 2, 21),
3725 F_IJPEG( 54860000, pll8, 7, 0, 0),
3726 F_IJPEG( 96000000, pll8, 4, 0, 0),
3727 F_IJPEG(109710000, pll8, 1, 2, 7),
3728 F_IJPEG(128000000, pll8, 3, 0, 0),
3729 F_IJPEG(153600000, pll8, 1, 2, 5),
3730 F_IJPEG(200000000, pll2, 4, 0, 0),
3731 F_IJPEG(228571000, pll2, 1, 2, 7),
3732 F_IJPEG(266667000, pll2, 1, 1, 3),
3733 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003734 F_END
3735};
3736
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003737static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3738 [VDD_DIG_LOW] = 128000000,
3739 [VDD_DIG_NOMINAL] = 266667000,
3740 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003741};
3742
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003743static struct rcg_clk ijpeg_clk = {
3744 .b = {
3745 .ctl_reg = IJPEG_CC_REG,
3746 .en_mask = BIT(0),
3747 .reset_reg = SW_RESET_CORE_REG,
3748 .reset_mask = BIT(9),
3749 .halt_reg = DBG_BUS_VEC_A_REG,
3750 .halt_bit = 24,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003751 .retain_reg = IJPEG_CC_REG,
3752 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003753 },
3754 .ns_reg = IJPEG_NS_REG,
3755 .md_reg = IJPEG_MD_REG,
3756 .root_en_mask = BIT(2),
3757 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003758 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003759 .ctl_mask = BM(7, 6),
3760 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003761 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003762 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003763 .c = {
3764 .dbg_name = "ijpeg_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003765 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003766 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
3767 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003768 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003769 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003770 },
3771};
3772
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003773#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003774 { \
3775 .freq_hz = f, \
3776 .src_clk = &s##_clk.c, \
3777 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003778 }
3779static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003780 F_JPEGD( 0, gnd, 1),
3781 F_JPEGD( 64000000, pll8, 6),
3782 F_JPEGD( 76800000, pll8, 5),
3783 F_JPEGD( 96000000, pll8, 4),
3784 F_JPEGD(160000000, pll2, 5),
3785 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003786 F_END
3787};
3788
3789static struct rcg_clk jpegd_clk = {
3790 .b = {
3791 .ctl_reg = JPEGD_CC_REG,
3792 .en_mask = BIT(0),
3793 .reset_reg = SW_RESET_CORE_REG,
3794 .reset_mask = BIT(19),
3795 .halt_reg = DBG_BUS_VEC_A_REG,
3796 .halt_bit = 19,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003797 .retain_reg = JPEGD_CC_REG,
3798 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003799 },
3800 .ns_reg = JPEGD_NS_REG,
3801 .root_en_mask = BIT(2),
3802 .ns_mask = (BM(15, 12) | BM(2, 0)),
3803 .set_rate = set_rate_nop,
3804 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003805 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003806 .c = {
3807 .dbg_name = "jpegd_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003808 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003809 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003810 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003811 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003812 },
3813};
3814
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003815#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003816 { \
3817 .freq_hz = f, \
3818 .src_clk = &s##_clk.c, \
3819 .md_val = MD8(8, m, 0, n), \
3820 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3821 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003822 }
Patrick Dalye6f489042012-07-11 15:29:15 -07003823static struct clk_freq_tbl clk_tbl_mdp_8960ab[] = {
3824 F_MDP( 0, gnd, 0, 0),
3825 F_MDP( 9600000, pll8, 1, 40),
3826 F_MDP( 13710000, pll8, 1, 28),
3827 F_MDP( 27000000, pxo, 0, 0),
3828 F_MDP( 29540000, pll8, 1, 13),
3829 F_MDP( 34910000, pll8, 1, 11),
3830 F_MDP( 38400000, pll8, 1, 10),
3831 F_MDP( 59080000, pll8, 2, 13),
3832 F_MDP( 76800000, pll8, 1, 5),
3833 F_MDP( 85330000, pll8, 2, 9),
3834 F_MDP( 96000000, pll8, 1, 4),
3835 F_MDP(128000000, pll8, 1, 3),
3836 F_MDP(160000000, pll2, 1, 5),
3837 F_MDP(177780000, pll2, 2, 9),
3838 F_MDP(200000000, pll2, 1, 4),
3839 F_MDP(228571000, pll2, 2, 7),
3840 F_MDP(266667000, pll2, 1, 3),
3841 F_END
3842};
3843
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003844static struct clk_freq_tbl clk_tbl_mdp[] = {
3845 F_MDP( 0, gnd, 0, 0),
3846 F_MDP( 9600000, pll8, 1, 40),
3847 F_MDP( 13710000, pll8, 1, 28),
3848 F_MDP( 27000000, pxo, 0, 0),
3849 F_MDP( 29540000, pll8, 1, 13),
3850 F_MDP( 34910000, pll8, 1, 11),
3851 F_MDP( 38400000, pll8, 1, 10),
3852 F_MDP( 59080000, pll8, 2, 13),
3853 F_MDP( 76800000, pll8, 1, 5),
3854 F_MDP( 85330000, pll8, 2, 9),
3855 F_MDP( 96000000, pll8, 1, 4),
3856 F_MDP(128000000, pll8, 1, 3),
3857 F_MDP(160000000, pll2, 1, 5),
3858 F_MDP(177780000, pll2, 2, 9),
3859 F_MDP(200000000, pll2, 1, 4),
3860 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003861 F_END
3862};
3863
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003864static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3865 [VDD_DIG_LOW] = 128000000,
3866 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003867};
3868
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003869static struct bank_masks bmnd_info_mdp = {
3870 .bank_sel_mask = BIT(11),
3871 .bank0_mask = {
3872 .md_reg = MDP_MD0_REG,
3873 .ns_mask = BM(29, 22) | BM(5, 3),
3874 .rst_mask = BIT(31),
3875 .mnd_en_mask = BIT(8),
3876 .mode_mask = BM(10, 9),
3877 },
3878 .bank1_mask = {
3879 .md_reg = MDP_MD1_REG,
3880 .ns_mask = BM(21, 14) | BM(2, 0),
3881 .rst_mask = BIT(30),
3882 .mnd_en_mask = BIT(5),
3883 .mode_mask = BM(7, 6),
3884 },
3885};
3886
3887static struct rcg_clk mdp_clk = {
3888 .b = {
3889 .ctl_reg = MDP_CC_REG,
3890 .en_mask = BIT(0),
3891 .reset_reg = SW_RESET_CORE_REG,
3892 .reset_mask = BIT(21),
3893 .halt_reg = DBG_BUS_VEC_C_REG,
3894 .halt_bit = 10,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003895 .retain_reg = MDP_CC_REG,
3896 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003897 },
3898 .ns_reg = MDP_NS_REG,
3899 .root_en_mask = BIT(2),
3900 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003901 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003902 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003903 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003904 .c = {
3905 .dbg_name = "mdp_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003906 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003907 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003908 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003909 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003910 },
3911};
3912
3913static struct branch_clk lut_mdp_clk = {
3914 .b = {
3915 .ctl_reg = MDP_LUT_CC_REG,
3916 .en_mask = BIT(0),
3917 .halt_reg = DBG_BUS_VEC_I_REG,
3918 .halt_bit = 13,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003919 .retain_reg = MDP_LUT_CC_REG,
3920 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003921 },
3922 .parent = &mdp_clk.c,
3923 .c = {
3924 .dbg_name = "lut_mdp_clk",
3925 .ops = &clk_ops_branch,
3926 CLK_INIT(lut_mdp_clk.c),
3927 },
3928};
3929
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003930#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003931 { \
3932 .freq_hz = f, \
3933 .src_clk = &s##_clk.c, \
3934 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003935 }
3936static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003937 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003938 F_END
3939};
3940
3941static struct rcg_clk mdp_vsync_clk = {
3942 .b = {
3943 .ctl_reg = MISC_CC_REG,
3944 .en_mask = BIT(6),
3945 .reset_reg = SW_RESET_CORE_REG,
3946 .reset_mask = BIT(3),
3947 .halt_reg = DBG_BUS_VEC_B_REG,
3948 .halt_bit = 22,
3949 },
3950 .ns_reg = MISC_CC2_REG,
3951 .ns_mask = BIT(13),
3952 .set_rate = set_rate_nop,
3953 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003954 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003955 .c = {
3956 .dbg_name = "mdp_vsync_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003957 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003958 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003959 CLK_INIT(mdp_vsync_clk.c),
3960 },
3961};
3962
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003963#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003964 { \
3965 .freq_hz = f, \
3966 .src_clk = &s##_clk.c, \
3967 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3968 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003969 }
3970static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003971 F_ROT( 0, gnd, 1),
3972 F_ROT( 27000000, pxo, 1),
3973 F_ROT( 29540000, pll8, 13),
3974 F_ROT( 32000000, pll8, 12),
3975 F_ROT( 38400000, pll8, 10),
3976 F_ROT( 48000000, pll8, 8),
3977 F_ROT( 54860000, pll8, 7),
3978 F_ROT( 64000000, pll8, 6),
3979 F_ROT( 76800000, pll8, 5),
3980 F_ROT( 96000000, pll8, 4),
3981 F_ROT(100000000, pll2, 8),
3982 F_ROT(114290000, pll2, 7),
3983 F_ROT(133330000, pll2, 6),
3984 F_ROT(160000000, pll2, 5),
3985 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003986 F_END
3987};
3988
3989static struct bank_masks bdiv_info_rot = {
3990 .bank_sel_mask = BIT(30),
3991 .bank0_mask = {
3992 .ns_mask = BM(25, 22) | BM(18, 16),
3993 },
3994 .bank1_mask = {
3995 .ns_mask = BM(29, 26) | BM(21, 19),
3996 },
3997};
3998
3999static struct rcg_clk rot_clk = {
4000 .b = {
4001 .ctl_reg = ROT_CC_REG,
4002 .en_mask = BIT(0),
4003 .reset_reg = SW_RESET_CORE_REG,
4004 .reset_mask = BIT(2),
4005 .halt_reg = DBG_BUS_VEC_C_REG,
4006 .halt_bit = 15,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004007 .retain_reg = ROT_CC_REG,
4008 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004009 },
4010 .ns_reg = ROT_NS_REG,
4011 .root_en_mask = BIT(2),
4012 .set_rate = set_rate_div_banked,
4013 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004014 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004015 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004016 .c = {
4017 .dbg_name = "rot_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004018 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004019 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004020 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004021 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004022 },
4023};
4024
Matt Wagantallf82f2942012-01-27 13:56:13 -08004025static int hdmi_pll_clk_enable(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004026{
4027 int ret;
4028 unsigned long flags;
4029 spin_lock_irqsave(&local_clock_reg_lock, flags);
4030 ret = hdmi_pll_enable();
4031 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4032 return ret;
4033}
4034
Matt Wagantallf82f2942012-01-27 13:56:13 -08004035static void hdmi_pll_clk_disable(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004036{
4037 unsigned long flags;
4038 spin_lock_irqsave(&local_clock_reg_lock, flags);
4039 hdmi_pll_disable();
4040 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4041}
4042
Matt Wagantallf82f2942012-01-27 13:56:13 -08004043static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
Stephen Boyd5b35dee2011-09-21 12:17:38 -07004044{
4045 return &pxo_clk.c;
4046}
4047
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004048static struct clk_ops clk_ops_hdmi_pll = {
4049 .enable = hdmi_pll_clk_enable,
4050 .disable = hdmi_pll_clk_disable,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07004051 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004052};
4053
4054static struct clk hdmi_pll_clk = {
4055 .dbg_name = "hdmi_pll_clk",
4056 .ops = &clk_ops_hdmi_pll,
Matt Wagantall82feaa12012-07-09 10:54:49 -07004057 .vdd_class = &vdd_sr2_hdmi_pll,
4058 .fmax[VDD_SR2_HDMI_PLL_ON] = ULONG_MAX,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004059 CLK_INIT(hdmi_pll_clk),
4060};
4061
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004062#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004063 { \
4064 .freq_hz = f, \
4065 .src_clk = &s##_clk.c, \
4066 .md_val = MD8(8, m, 0, n), \
4067 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
4068 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004069 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004070#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004071 { \
4072 .freq_hz = f, \
4073 .src_clk = &s##_clk, \
4074 .md_val = MD8(8, m, 0, n), \
4075 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
4076 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004077 .extra_freq_data = (void *)p_r, \
4078 }
4079/* Switching TV freqs requires PLL reconfiguration. */
4080static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004081 F_TV_GND( 0, gnd, 0, 1, 0, 0),
4082 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
4083 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
4084 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
4085 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
4086 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004087 F_END
4088};
4089
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004090static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
4091 [VDD_DIG_LOW] = 74250000,
4092 [VDD_DIG_NOMINAL] = 149000000
4093};
4094
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004095/*
4096 * Unlike other clocks, the TV rate is adjusted through PLL
4097 * re-programming. It is also routed through an MND divider.
4098 */
Matt Wagantallf82f2942012-01-27 13:56:13 -08004099void set_rate_tv(struct rcg_clk *rcg, struct clk_freq_tbl *nf)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004100{
4101 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
Matt Wagantallf6c39a12012-07-09 19:24:42 -07004102 if (pll_rate) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004103 hdmi_pll_set_rate(pll_rate);
Matt Wagantallf6c39a12012-07-09 19:24:42 -07004104 hdmi_pll_clk.rate = pll_rate;
4105 }
Matt Wagantallf82f2942012-01-27 13:56:13 -08004106 set_rate_mnd(rcg, nf);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004107}
4108
4109static struct rcg_clk tv_src_clk = {
4110 .ns_reg = TV_NS_REG,
4111 .b = {
4112 .ctl_reg = TV_CC_REG,
4113 .halt_check = NOCHECK,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004114 .retain_reg = TV_CC_REG,
4115 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004116 },
4117 .md_reg = TV_MD_REG,
4118 .root_en_mask = BIT(2),
4119 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004120 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004121 .ctl_mask = BM(7, 6),
4122 .set_rate = set_rate_tv,
4123 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004124 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004125 .c = {
4126 .dbg_name = "tv_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004127 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004128 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004129 CLK_INIT(tv_src_clk.c),
4130 },
4131};
4132
Tianyi Gou51918802012-01-26 14:05:43 -08004133static struct cdiv_clk tv_src_div_clk = {
4134 .b = {
4135 .ctl_reg = TV_NS_REG,
4136 .halt_check = NOCHECK,
4137 },
4138 .ns_reg = TV_NS_REG,
4139 .div_offset = 6,
4140 .max_div = 2,
4141 .c = {
4142 .dbg_name = "tv_src_div_clk",
4143 .ops = &clk_ops_cdiv,
4144 CLK_INIT(tv_src_div_clk.c),
Stephen Boydd51d5e82012-06-18 18:09:50 -07004145 .rate = ULONG_MAX,
Tianyi Gou51918802012-01-26 14:05:43 -08004146 },
4147};
4148
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004149static struct branch_clk tv_enc_clk = {
4150 .b = {
4151 .ctl_reg = TV_CC_REG,
4152 .en_mask = BIT(8),
4153 .reset_reg = SW_RESET_CORE_REG,
4154 .reset_mask = BIT(0),
4155 .halt_reg = DBG_BUS_VEC_D_REG,
4156 .halt_bit = 9,
4157 },
4158 .parent = &tv_src_clk.c,
4159 .c = {
4160 .dbg_name = "tv_enc_clk",
4161 .ops = &clk_ops_branch,
4162 CLK_INIT(tv_enc_clk.c),
4163 },
4164};
4165
4166static struct branch_clk tv_dac_clk = {
4167 .b = {
4168 .ctl_reg = TV_CC_REG,
4169 .en_mask = BIT(10),
4170 .halt_reg = DBG_BUS_VEC_D_REG,
4171 .halt_bit = 10,
4172 },
4173 .parent = &tv_src_clk.c,
4174 .c = {
4175 .dbg_name = "tv_dac_clk",
4176 .ops = &clk_ops_branch,
4177 CLK_INIT(tv_dac_clk.c),
4178 },
4179};
4180
4181static struct branch_clk mdp_tv_clk = {
4182 .b = {
4183 .ctl_reg = TV_CC_REG,
4184 .en_mask = BIT(0),
4185 .reset_reg = SW_RESET_CORE_REG,
4186 .reset_mask = BIT(4),
4187 .halt_reg = DBG_BUS_VEC_D_REG,
4188 .halt_bit = 12,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004189 .retain_reg = TV_CC2_REG,
4190 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004191 },
4192 .parent = &tv_src_clk.c,
4193 .c = {
4194 .dbg_name = "mdp_tv_clk",
4195 .ops = &clk_ops_branch,
4196 CLK_INIT(mdp_tv_clk.c),
4197 },
4198};
4199
4200static struct branch_clk hdmi_tv_clk = {
4201 .b = {
4202 .ctl_reg = TV_CC_REG,
4203 .en_mask = BIT(12),
4204 .reset_reg = SW_RESET_CORE_REG,
4205 .reset_mask = BIT(1),
4206 .halt_reg = DBG_BUS_VEC_D_REG,
4207 .halt_bit = 11,
4208 },
4209 .parent = &tv_src_clk.c,
4210 .c = {
4211 .dbg_name = "hdmi_tv_clk",
4212 .ops = &clk_ops_branch,
4213 CLK_INIT(hdmi_tv_clk.c),
4214 },
4215};
4216
Tianyi Gou51918802012-01-26 14:05:43 -08004217static struct branch_clk rgb_tv_clk = {
4218 .b = {
4219 .ctl_reg = TV_CC2_REG,
4220 .en_mask = BIT(14),
4221 .halt_reg = DBG_BUS_VEC_J_REG,
4222 .halt_bit = 27,
4223 },
4224 .parent = &tv_src_clk.c,
4225 .c = {
4226 .dbg_name = "rgb_tv_clk",
4227 .ops = &clk_ops_branch,
4228 CLK_INIT(rgb_tv_clk.c),
4229 },
4230};
4231
4232static struct branch_clk npl_tv_clk = {
4233 .b = {
4234 .ctl_reg = TV_CC2_REG,
4235 .en_mask = BIT(16),
4236 .halt_reg = DBG_BUS_VEC_J_REG,
4237 .halt_bit = 26,
4238 },
4239 .parent = &tv_src_clk.c,
4240 .c = {
4241 .dbg_name = "npl_tv_clk",
4242 .ops = &clk_ops_branch,
4243 CLK_INIT(npl_tv_clk.c),
4244 },
4245};
4246
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004247static struct branch_clk hdmi_app_clk = {
4248 .b = {
4249 .ctl_reg = MISC_CC2_REG,
4250 .en_mask = BIT(11),
4251 .reset_reg = SW_RESET_CORE_REG,
4252 .reset_mask = BIT(11),
4253 .halt_reg = DBG_BUS_VEC_B_REG,
4254 .halt_bit = 25,
4255 },
4256 .c = {
4257 .dbg_name = "hdmi_app_clk",
4258 .ops = &clk_ops_branch,
4259 CLK_INIT(hdmi_app_clk.c),
4260 },
4261};
4262
4263static struct bank_masks bmnd_info_vcodec = {
4264 .bank_sel_mask = BIT(13),
4265 .bank0_mask = {
4266 .md_reg = VCODEC_MD0_REG,
4267 .ns_mask = BM(18, 11) | BM(2, 0),
4268 .rst_mask = BIT(31),
4269 .mnd_en_mask = BIT(5),
4270 .mode_mask = BM(7, 6),
4271 },
4272 .bank1_mask = {
4273 .md_reg = VCODEC_MD1_REG,
4274 .ns_mask = BM(26, 19) | BM(29, 27),
4275 .rst_mask = BIT(30),
4276 .mnd_en_mask = BIT(10),
4277 .mode_mask = BM(12, 11),
4278 },
4279};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004280#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004281 { \
4282 .freq_hz = f, \
4283 .src_clk = &s##_clk.c, \
4284 .md_val = MD8(8, m, 0, n), \
4285 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4286 .ctl_val = CC_BANKED(6, 11, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004287 }
4288static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004289 F_VCODEC( 0, gnd, 0, 0),
4290 F_VCODEC( 27000000, pxo, 0, 0),
4291 F_VCODEC( 32000000, pll8, 1, 12),
4292 F_VCODEC( 48000000, pll8, 1, 8),
4293 F_VCODEC( 54860000, pll8, 1, 7),
4294 F_VCODEC( 96000000, pll8, 1, 4),
4295 F_VCODEC(133330000, pll2, 1, 6),
4296 F_VCODEC(200000000, pll2, 1, 4),
4297 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004298 F_END
4299};
4300
4301static struct rcg_clk vcodec_clk = {
4302 .b = {
4303 .ctl_reg = VCODEC_CC_REG,
4304 .en_mask = BIT(0),
4305 .reset_reg = SW_RESET_CORE_REG,
4306 .reset_mask = BIT(6),
4307 .halt_reg = DBG_BUS_VEC_C_REG,
4308 .halt_bit = 29,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004309 .retain_reg = VCODEC_CC_REG,
4310 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004311 },
4312 .ns_reg = VCODEC_NS_REG,
4313 .root_en_mask = BIT(2),
4314 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004315 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004316 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004317 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004318 .c = {
4319 .dbg_name = "vcodec_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004320 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004321 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4322 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004323 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004324 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004325 },
4326};
4327
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004328#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004329 { \
4330 .freq_hz = f, \
4331 .src_clk = &s##_clk.c, \
4332 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004333 }
4334static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004335 F_VPE( 0, gnd, 1),
4336 F_VPE( 27000000, pxo, 1),
4337 F_VPE( 34909000, pll8, 11),
4338 F_VPE( 38400000, pll8, 10),
4339 F_VPE( 64000000, pll8, 6),
4340 F_VPE( 76800000, pll8, 5),
4341 F_VPE( 96000000, pll8, 4),
4342 F_VPE(100000000, pll2, 8),
4343 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004344 F_END
4345};
4346
4347static struct rcg_clk vpe_clk = {
4348 .b = {
4349 .ctl_reg = VPE_CC_REG,
4350 .en_mask = BIT(0),
4351 .reset_reg = SW_RESET_CORE_REG,
4352 .reset_mask = BIT(17),
4353 .halt_reg = DBG_BUS_VEC_A_REG,
4354 .halt_bit = 28,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004355 .retain_reg = VPE_CC_REG,
4356 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004357 },
4358 .ns_reg = VPE_NS_REG,
4359 .root_en_mask = BIT(2),
4360 .ns_mask = (BM(15, 12) | BM(2, 0)),
4361 .set_rate = set_rate_nop,
4362 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004363 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004364 .c = {
4365 .dbg_name = "vpe_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004366 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004367 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004368 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004369 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004370 },
4371};
4372
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004373#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004374 { \
4375 .freq_hz = f, \
4376 .src_clk = &s##_clk.c, \
4377 .md_val = MD8(8, m, 0, n), \
4378 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4379 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004380 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004381
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004382static struct clk_freq_tbl clk_tbl_vfe[] = {
4383 F_VFE( 0, gnd, 1, 0, 0),
4384 F_VFE( 13960000, pll8, 1, 2, 55),
4385 F_VFE( 27000000, pxo, 1, 0, 0),
4386 F_VFE( 36570000, pll8, 1, 2, 21),
4387 F_VFE( 38400000, pll8, 2, 1, 5),
4388 F_VFE( 45180000, pll8, 1, 2, 17),
4389 F_VFE( 48000000, pll8, 2, 1, 4),
4390 F_VFE( 54860000, pll8, 1, 1, 7),
4391 F_VFE( 64000000, pll8, 2, 1, 3),
4392 F_VFE( 76800000, pll8, 1, 1, 5),
4393 F_VFE( 96000000, pll8, 2, 1, 2),
4394 F_VFE(109710000, pll8, 1, 2, 7),
4395 F_VFE(128000000, pll8, 1, 1, 3),
4396 F_VFE(153600000, pll8, 1, 2, 5),
4397 F_VFE(200000000, pll2, 2, 1, 2),
4398 F_VFE(228570000, pll2, 1, 2, 7),
4399 F_VFE(266667000, pll2, 1, 1, 3),
4400 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004401 F_END
4402};
4403
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004404static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4405 [VDD_DIG_LOW] = 128000000,
4406 [VDD_DIG_NOMINAL] = 266667000,
4407 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004408};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004409
4410static struct rcg_clk vfe_clk = {
4411 .b = {
4412 .ctl_reg = VFE_CC_REG,
4413 .reset_reg = SW_RESET_CORE_REG,
4414 .reset_mask = BIT(15),
4415 .halt_reg = DBG_BUS_VEC_B_REG,
4416 .halt_bit = 6,
4417 .en_mask = BIT(0),
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004418 .retain_reg = VFE_CC2_REG,
4419 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004420 },
4421 .ns_reg = VFE_NS_REG,
4422 .md_reg = VFE_MD_REG,
4423 .root_en_mask = BIT(2),
4424 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004425 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004426 .ctl_mask = BM(7, 6),
4427 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004428 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004429 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004430 .c = {
4431 .dbg_name = "vfe_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004432 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08004433 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
4434 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004435 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004436 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004437 },
4438};
4439
Matt Wagantallc23eee92011-08-16 23:06:52 -07004440static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004441 .b = {
4442 .ctl_reg = VFE_CC_REG,
4443 .en_mask = BIT(12),
4444 .reset_reg = SW_RESET_CORE_REG,
4445 .reset_mask = BIT(24),
4446 .halt_reg = DBG_BUS_VEC_B_REG,
4447 .halt_bit = 8,
4448 },
4449 .parent = &vfe_clk.c,
4450 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004451 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004452 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004453 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004454 },
4455};
4456
4457/*
4458 * Low Power Audio Clocks
4459 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004460#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004461 { \
4462 .freq_hz = f, \
4463 .src_clk = &s##_clk.c, \
4464 .md_val = MD8(8, m, 0, n), \
4465 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004466 }
Matt Wagantall86e03822011-12-12 10:59:24 -08004467static struct clk_freq_tbl clk_tbl_aif_osr_492[] = {
4468 F_AIF_OSR( 0, gnd, 1, 0, 0),
4469 F_AIF_OSR( 512000, pll4, 4, 1, 240),
4470 F_AIF_OSR( 768000, pll4, 4, 1, 160),
4471 F_AIF_OSR( 1024000, pll4, 4, 1, 120),
4472 F_AIF_OSR( 1536000, pll4, 4, 1, 80),
4473 F_AIF_OSR( 2048000, pll4, 4, 1, 60),
4474 F_AIF_OSR( 3072000, pll4, 4, 1, 40),
4475 F_AIF_OSR( 4096000, pll4, 4, 1, 30),
4476 F_AIF_OSR( 6144000, pll4, 4, 1, 20),
4477 F_AIF_OSR( 8192000, pll4, 4, 1, 15),
4478 F_AIF_OSR(12288000, pll4, 4, 1, 10),
4479 F_AIF_OSR(24576000, pll4, 4, 1, 5),
4480 F_END
4481};
4482
4483static struct clk_freq_tbl clk_tbl_aif_osr_393[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004484 F_AIF_OSR( 0, gnd, 1, 0, 0),
4485 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4486 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4487 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4488 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4489 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4490 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4491 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4492 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4493 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4494 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4495 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004496 F_END
4497};
4498
4499#define CLK_AIF_OSR(i, ns, md, h_r) \
4500 struct rcg_clk i##_clk = { \
4501 .b = { \
4502 .ctl_reg = ns, \
4503 .en_mask = BIT(17), \
4504 .reset_reg = ns, \
4505 .reset_mask = BIT(19), \
4506 .halt_reg = h_r, \
4507 .halt_check = ENABLE, \
4508 .halt_bit = 1, \
4509 }, \
4510 .ns_reg = ns, \
4511 .md_reg = md, \
4512 .root_en_mask = BIT(9), \
4513 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004514 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004515 .set_rate = set_rate_mnd, \
Matt Wagantall86e03822011-12-12 10:59:24 -08004516 .freq_tbl = clk_tbl_aif_osr_393, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004517 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004518 .c = { \
4519 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07004520 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004521 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004522 CLK_INIT(i##_clk.c), \
4523 }, \
4524 }
4525#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4526 struct rcg_clk i##_clk = { \
4527 .b = { \
4528 .ctl_reg = ns, \
4529 .en_mask = BIT(21), \
4530 .reset_reg = ns, \
4531 .reset_mask = BIT(23), \
4532 .halt_reg = h_r, \
4533 .halt_check = ENABLE, \
4534 .halt_bit = 1, \
4535 }, \
4536 .ns_reg = ns, \
4537 .md_reg = md, \
4538 .root_en_mask = BIT(9), \
4539 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004540 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004541 .set_rate = set_rate_mnd, \
Matt Wagantall86e03822011-12-12 10:59:24 -08004542 .freq_tbl = clk_tbl_aif_osr_393, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004543 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004544 .c = { \
4545 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07004546 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004547 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004548 CLK_INIT(i##_clk.c), \
4549 }, \
4550 }
4551
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004552#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004553 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004554 .b = { \
4555 .ctl_reg = ns, \
4556 .en_mask = BIT(15), \
4557 .halt_reg = h_r, \
4558 .halt_check = DELAY, \
4559 }, \
4560 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004561 .ext_mask = BIT(14), \
4562 .div_offset = 10, \
4563 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004564 .c = { \
4565 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004566 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004567 CLK_INIT(i##_clk.c), \
Stephen Boydd51d5e82012-06-18 18:09:50 -07004568 .rate = ULONG_MAX, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004569 }, \
4570 }
4571
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004572#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004573 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004574 .b = { \
4575 .ctl_reg = ns, \
4576 .en_mask = BIT(19), \
4577 .halt_reg = h_r, \
Stephen Boyd7bb9cf82012-01-25 18:09:01 -08004578 .halt_check = DELAY, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004579 }, \
4580 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004581 .ext_mask = BIT(18), \
4582 .div_offset = 10, \
4583 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004584 .c = { \
4585 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004586 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004587 CLK_INIT(i##_clk.c), \
Stephen Boydd51d5e82012-06-18 18:09:50 -07004588 .rate = ULONG_MAX, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004589 }, \
4590 }
4591
4592static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4593 LCC_MI2S_STATUS_REG);
4594static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4595
4596static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4597 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4598static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4599 LCC_CODEC_I2S_MIC_STATUS_REG);
4600
4601static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4602 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4603static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4604 LCC_SPARE_I2S_MIC_STATUS_REG);
4605
4606static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4607 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4608static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4609 LCC_CODEC_I2S_SPKR_STATUS_REG);
4610
4611static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4612 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4613static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4614 LCC_SPARE_I2S_SPKR_STATUS_REG);
4615
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004616#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004617 { \
4618 .freq_hz = f, \
4619 .src_clk = &s##_clk.c, \
4620 .md_val = MD16(m, n), \
4621 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004622 }
Matt Wagantall86e03822011-12-12 10:59:24 -08004623static struct clk_freq_tbl clk_tbl_pcm_492[] = {
4624 { .ns_val = BIT(10) /* external input */ },
Stephen Boyde9ed94d2012-08-02 10:57:11 -07004625 F_PCM( 256000, pll4, 4, 1, 480),
Matt Wagantall86e03822011-12-12 10:59:24 -08004626 F_PCM( 512000, pll4, 4, 1, 240),
4627 F_PCM( 768000, pll4, 4, 1, 160),
4628 F_PCM( 1024000, pll4, 4, 1, 120),
4629 F_PCM( 1536000, pll4, 4, 1, 80),
4630 F_PCM( 2048000, pll4, 4, 1, 60),
4631 F_PCM( 3072000, pll4, 4, 1, 40),
4632 F_PCM( 4096000, pll4, 4, 1, 30),
4633 F_PCM( 6144000, pll4, 4, 1, 20),
4634 F_PCM( 8192000, pll4, 4, 1, 15),
4635 F_PCM(12288000, pll4, 4, 1, 10),
4636 F_PCM(24576000, pll4, 4, 1, 5),
4637 F_END
4638};
4639
4640static struct clk_freq_tbl clk_tbl_pcm_393[] = {
Stephen Boyd630f3252012-01-31 00:10:08 -08004641 { .ns_val = BIT(10) /* external input */ },
Stephen Boyde9ed94d2012-08-02 10:57:11 -07004642 F_PCM( 256000, pll4, 4, 1, 384),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004643 F_PCM( 512000, pll4, 4, 1, 192),
4644 F_PCM( 768000, pll4, 4, 1, 128),
4645 F_PCM( 1024000, pll4, 4, 1, 96),
4646 F_PCM( 1536000, pll4, 4, 1, 64),
4647 F_PCM( 2048000, pll4, 4, 1, 48),
4648 F_PCM( 3072000, pll4, 4, 1, 32),
4649 F_PCM( 4096000, pll4, 4, 1, 24),
4650 F_PCM( 6144000, pll4, 4, 1, 16),
4651 F_PCM( 8192000, pll4, 4, 1, 12),
4652 F_PCM(12288000, pll4, 4, 1, 8),
4653 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004654 F_END
4655};
4656
4657static struct rcg_clk pcm_clk = {
4658 .b = {
4659 .ctl_reg = LCC_PCM_NS_REG,
4660 .en_mask = BIT(11),
4661 .reset_reg = LCC_PCM_NS_REG,
4662 .reset_mask = BIT(13),
4663 .halt_reg = LCC_PCM_STATUS_REG,
4664 .halt_check = ENABLE,
4665 .halt_bit = 0,
4666 },
4667 .ns_reg = LCC_PCM_NS_REG,
4668 .md_reg = LCC_PCM_MD_REG,
4669 .root_en_mask = BIT(9),
Stephen Boyd630f3252012-01-31 00:10:08 -08004670 .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08004671 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004672 .set_rate = set_rate_mnd,
Matt Wagantall86e03822011-12-12 10:59:24 -08004673 .freq_tbl = clk_tbl_pcm_393,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004674 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004675 .c = {
4676 .dbg_name = "pcm_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004677 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004678 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004679 CLK_INIT(pcm_clk.c),
Stephen Boydc5492fc2012-06-18 18:47:03 -07004680 .rate = ULONG_MAX,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004681 },
4682};
4683
4684static struct rcg_clk audio_slimbus_clk = {
4685 .b = {
4686 .ctl_reg = LCC_SLIMBUS_NS_REG,
4687 .en_mask = BIT(10),
4688 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4689 .reset_mask = BIT(5),
4690 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4691 .halt_check = ENABLE,
4692 .halt_bit = 0,
4693 },
4694 .ns_reg = LCC_SLIMBUS_NS_REG,
4695 .md_reg = LCC_SLIMBUS_MD_REG,
4696 .root_en_mask = BIT(9),
4697 .ns_mask = (BM(31, 24) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004698 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004699 .set_rate = set_rate_mnd,
Matt Wagantall86e03822011-12-12 10:59:24 -08004700 .freq_tbl = clk_tbl_aif_osr_393,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004701 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004702 .c = {
4703 .dbg_name = "audio_slimbus_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004704 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004705 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004706 CLK_INIT(audio_slimbus_clk.c),
4707 },
4708};
4709
4710static struct branch_clk sps_slimbus_clk = {
4711 .b = {
4712 .ctl_reg = LCC_SLIMBUS_NS_REG,
4713 .en_mask = BIT(12),
4714 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4715 .halt_check = ENABLE,
4716 .halt_bit = 1,
4717 },
4718 .parent = &audio_slimbus_clk.c,
4719 .c = {
4720 .dbg_name = "sps_slimbus_clk",
4721 .ops = &clk_ops_branch,
4722 CLK_INIT(sps_slimbus_clk.c),
4723 },
4724};
4725
4726static struct branch_clk slimbus_xo_src_clk = {
4727 .b = {
4728 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4729 .en_mask = BIT(2),
4730 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004731 .halt_bit = 28,
4732 },
4733 .parent = &sps_slimbus_clk.c,
4734 .c = {
4735 .dbg_name = "slimbus_xo_src_clk",
4736 .ops = &clk_ops_branch,
4737 CLK_INIT(slimbus_xo_src_clk.c),
4738 },
4739};
4740
Matt Wagantall735f01a2011-08-12 12:40:28 -07004741DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4742DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4743DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4744DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4745DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4746DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4747DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4748DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Stephen Boydc7fc3b12012-05-17 14:42:46 -07004749DEFINE_CLK_RPM_QDSS(qdss_clk, qdss_a_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004750
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004751static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c, 0);
4752static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c, 0);
Stephen Boydd7a143a2012-02-16 17:59:26 -08004753
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004754static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c, 0);
4755static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c, 0);
4756static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c, 0);
4757static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c, 0);
4758static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c, 0);
4759static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c, 0);
4760static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c, 0);
4761static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c, 0);
4762static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c, 0);
4763static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c, 0);
4764static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c, 0);
4765static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c, 0);
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004766static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c, 0);
4767static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004768
Matt Wagantall42cd12a2012-03-30 18:02:40 -07004769static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c, LONG_MAX);
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004770static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004771
Matt Wagantall33bac7e2012-05-22 14:59:05 -07004772static DEFINE_CLK_VOTER(ebi1_acpu_a_clk, &ebi1_a_clk.c, LONG_MAX);
4773static DEFINE_CLK_VOTER(ebi1_msmbus_a_clk, &ebi1_a_clk.c, LONG_MAX);
4774static DEFINE_CLK_VOTER(afab_acpu_a_clk, &afab_a_clk.c, LONG_MAX);
4775static DEFINE_CLK_VOTER(afab_msmbus_a_clk, &afab_a_clk.c, LONG_MAX);
4776
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004777#ifdef CONFIG_DEBUG_FS
4778struct measure_sel {
4779 u32 test_vector;
Matt Wagantallf82f2942012-01-27 13:56:13 -08004780 struct clk *c;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004781};
4782
Matt Wagantall8b38f942011-08-02 18:23:18 -07004783static DEFINE_CLK_MEASURE(l2_m_clk);
4784static DEFINE_CLK_MEASURE(krait0_m_clk);
4785static DEFINE_CLK_MEASURE(krait1_m_clk);
Tianyi Gou455c13c2012-02-02 16:33:24 -08004786static DEFINE_CLK_MEASURE(krait2_m_clk);
4787static DEFINE_CLK_MEASURE(krait3_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004788static DEFINE_CLK_MEASURE(q6sw_clk);
4789static DEFINE_CLK_MEASURE(q6fw_clk);
4790static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004791
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004792static struct measure_sel measure_mux[] = {
4793 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4794 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4795 { TEST_PER_LS(0x13), &sdc1_clk.c },
4796 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4797 { TEST_PER_LS(0x15), &sdc2_clk.c },
4798 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4799 { TEST_PER_LS(0x17), &sdc3_clk.c },
4800 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4801 { TEST_PER_LS(0x19), &sdc4_clk.c },
4802 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4803 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004804 { TEST_PER_LS(0x1F), &gp0_clk.c },
4805 { TEST_PER_LS(0x20), &gp1_clk.c },
4806 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004807 { TEST_PER_LS(0x25), &dfab_clk.c },
4808 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4809 { TEST_PER_LS(0x26), &pmem_clk.c },
4810 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4811 { TEST_PER_LS(0x33), &cfpb_clk.c },
4812 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4813 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4814 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4815 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4816 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4817 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4818 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4819 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4820 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4821 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4822 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4823 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4824 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4825 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4826 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4827 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4828 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4829 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4830 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4831 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4832 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4833 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4834 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
Tianyi Gou352955d2012-05-18 19:44:01 -07004835 { TEST_PER_LS(0x59), &sfab_sata_s_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004836 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
Tianyi Gou352955d2012-05-18 19:44:01 -07004837 { TEST_PER_LS(0x5A), &sata_p_clk.c },
4838 { TEST_PER_LS(0x5B), &sata_rxoob_clk.c },
4839 { TEST_PER_LS(0x5C), &sata_pmalive_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004840 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4841 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4842 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4843 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4844 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4845 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4846 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4847 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4848 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4849 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4850 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4851 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4852 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004853 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4854 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4855 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4856 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4857 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4858 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4859 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4860 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4861 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004862 { TEST_PER_LS(0x78), &sfpb_clk.c },
4863 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4864 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4865 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4866 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4867 { TEST_PER_LS(0x7D), &prng_clk.c },
4868 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4869 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4870 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4871 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004872 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4873 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4874 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004875 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4876 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4877 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4878 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4879 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4880 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4881 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4882 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4883 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4884 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004885 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004886 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4887
4888 { TEST_PER_HS(0x07), &afab_clk.c },
4889 { TEST_PER_HS(0x07), &afab_a_clk.c },
4890 { TEST_PER_HS(0x18), &sfab_clk.c },
4891 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004892 { TEST_PER_HS(0x26), &q6sw_clk },
4893 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004894 { TEST_PER_HS(0x2A), &adm0_clk.c },
Tianyi Gou352955d2012-05-18 19:44:01 -07004895 { TEST_PER_HS(0x31), &sata_a_clk.c },
Tianyi Gou6613de52012-01-27 17:57:53 -08004896 { TEST_PER_HS(0x2D), &pcie_phy_ref_clk.c },
4897 { TEST_PER_HS(0x32), &pcie_a_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004898 { TEST_PER_HS(0x34), &ebi1_clk.c },
4899 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004900 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004901
4902 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4903 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4904 { TEST_MM_LS(0x02), &cam1_clk.c },
4905 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004906 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004907 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4908 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4909 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4910 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4911 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4912 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4913 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4914 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4915 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4916 { TEST_MM_LS(0x12), &imem_p_clk.c },
4917 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4918 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4919 { TEST_MM_LS(0x16), &rot_p_clk.c },
4920 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4921 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4922 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4923 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4924 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4925 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4926 { TEST_MM_LS(0x1D), &cam0_clk.c },
4927 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4928 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4929 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4930 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4931 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4932 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4933 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4934 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004935 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004936 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004937
4938 { TEST_MM_HS(0x00), &csi0_clk.c },
4939 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004940 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004941 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4942 { TEST_MM_HS(0x06), &vfe_clk.c },
4943 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4944 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4945 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4946 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4947 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4948 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4949 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4950 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4951 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4952 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4953 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4954 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4955 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4956 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4957 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4958 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4959 { TEST_MM_HS(0x1A), &mdp_clk.c },
4960 { TEST_MM_HS(0x1B), &rot_clk.c },
4961 { TEST_MM_HS(0x1C), &vpe_clk.c },
4962 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4963 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4964 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4965 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4966 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4967 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4968 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4969 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4970 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4971 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4972 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004973 { TEST_MM_HS(0x2D), &csi2_clk.c },
4974 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4975 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4976 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4977 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4978 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004979 { TEST_MM_HS(0x33), &vcap_clk.c },
4980 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004981 { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004982 { TEST_MM_HS(0x35), &vcap_axi_clk.c },
Tianyi Gou51918802012-01-26 14:05:43 -08004983 { TEST_MM_HS(0x36), &rgb_tv_clk.c },
4984 { TEST_MM_HS(0x37), &npl_tv_clk.c },
Patrick Dalye6f489042012-07-11 15:29:15 -07004985 { TEST_MM_HS(0x38), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004986
4987 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4988 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4989 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4990 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4991 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4992 { TEST_LPA(0x14), &pcm_clk.c },
4993 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004994
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004995 { TEST_LPA_HS(0x00), &q6_func_clk },
4996
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004997 { TEST_CPUL2(0x2), &l2_m_clk },
4998 { TEST_CPUL2(0x0), &krait0_m_clk },
4999 { TEST_CPUL2(0x1), &krait1_m_clk },
Tianyi Gou455c13c2012-02-02 16:33:24 -08005000 { TEST_CPUL2(0x4), &krait2_m_clk },
5001 { TEST_CPUL2(0x5), &krait3_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005002};
5003
Matt Wagantallf82f2942012-01-27 13:56:13 -08005004static struct measure_sel *find_measure_sel(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005005{
5006 int i;
5007
5008 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
Matt Wagantallf82f2942012-01-27 13:56:13 -08005009 if (measure_mux[i].c == c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005010 return &measure_mux[i];
5011 return NULL;
5012}
5013
Matt Wagantall8b38f942011-08-02 18:23:18 -07005014static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005015{
5016 int ret = 0;
5017 u32 clk_sel;
5018 struct measure_sel *p;
Matt Wagantallf82f2942012-01-27 13:56:13 -08005019 struct measure_clk *measure = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005020 unsigned long flags;
5021
5022 if (!parent)
5023 return -EINVAL;
5024
5025 p = find_measure_sel(parent);
5026 if (!p)
5027 return -EINVAL;
5028
5029 spin_lock_irqsave(&local_clock_reg_lock, flags);
5030
Matt Wagantall8b38f942011-08-02 18:23:18 -07005031 /*
5032 * Program the test vector, measurement period (sample_ticks)
5033 * and scaling multiplier.
5034 */
Matt Wagantallf82f2942012-01-27 13:56:13 -08005035 measure->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005036 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantallf82f2942012-01-27 13:56:13 -08005037 measure->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005038 switch (p->test_vector >> TEST_TYPE_SHIFT) {
5039 case TEST_TYPE_PER_LS:
5040 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
5041 break;
5042 case TEST_TYPE_PER_HS:
5043 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
5044 break;
5045 case TEST_TYPE_MM_LS:
5046 writel_relaxed(0x4030D97, CLK_TEST_REG);
5047 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
5048 break;
5049 case TEST_TYPE_MM_HS:
5050 writel_relaxed(0x402B800, CLK_TEST_REG);
5051 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
5052 break;
5053 case TEST_TYPE_LPA:
5054 writel_relaxed(0x4030D98, CLK_TEST_REG);
5055 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
5056 LCC_CLK_LS_DEBUG_CFG_REG);
5057 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07005058 case TEST_TYPE_LPA_HS:
5059 writel_relaxed(0x402BC00, CLK_TEST_REG);
5060 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
5061 LCC_CLK_HS_DEBUG_CFG_REG);
5062 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07005063 case TEST_TYPE_CPUL2:
5064 writel_relaxed(0x4030400, CLK_TEST_REG);
5065 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
Matt Wagantallf82f2942012-01-27 13:56:13 -08005066 measure->sample_ticks = 0x4000;
5067 measure->multiplier = 2;
Matt Wagantall8b38f942011-08-02 18:23:18 -07005068 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005069 default:
5070 ret = -EPERM;
5071 }
5072 /* Make sure test vector is set before starting measurements. */
5073 mb();
5074
5075 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
5076
5077 return ret;
5078}
5079
5080/* Sample clock for 'ticks' reference clock ticks. */
5081static u32 run_measurement(unsigned ticks)
5082{
5083 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005084 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
5085
5086 /* Wait for timer to become ready. */
5087 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
5088 cpu_relax();
5089
5090 /* Run measurement and wait for completion. */
5091 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
5092 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
5093 cpu_relax();
5094
5095 /* Stop counters. */
5096 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
5097
5098 /* Return measured ticks. */
5099 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
5100}
5101
5102
5103/* Perform a hardware rate measurement for a given clock.
5104 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07005105static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005106{
5107 unsigned long flags;
5108 u32 pdm_reg_backup, ringosc_reg_backup;
5109 u64 raw_count_short, raw_count_full;
Matt Wagantallf82f2942012-01-27 13:56:13 -08005110 struct measure_clk *measure = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005111 unsigned ret;
5112
Stephen Boyde334aeb2012-01-24 12:17:29 -08005113 ret = clk_prepare_enable(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08005114 if (ret) {
5115 pr_warning("CXO clock failed to enable. Can't measure\n");
5116 return 0;
5117 }
5118
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005119 spin_lock_irqsave(&local_clock_reg_lock, flags);
5120
5121 /* Enable CXO/4 and RINGOSC branch and root. */
5122 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
5123 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
5124 writel_relaxed(0x2898, PDM_CLK_NS_REG);
5125 writel_relaxed(0xA00, RINGOSC_NS_REG);
5126
5127 /*
5128 * The ring oscillator counter will not reset if the measured clock
5129 * is not running. To detect this, run a short measurement before
5130 * the full measurement. If the raw results of the two are the same
5131 * then the clock must be off.
5132 */
5133
5134 /* Run a short measurement. (~1 ms) */
5135 raw_count_short = run_measurement(0x1000);
5136 /* Run a full measurement. (~14 ms) */
Matt Wagantallf82f2942012-01-27 13:56:13 -08005137 raw_count_full = run_measurement(measure->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005138
5139 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
5140 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
5141
5142 /* Return 0 if the clock is off. */
5143 if (raw_count_full == raw_count_short)
5144 ret = 0;
5145 else {
5146 /* Compute rate in Hz. */
5147 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantallf82f2942012-01-27 13:56:13 -08005148 do_div(raw_count_full, ((measure->sample_ticks * 10) + 35));
5149 ret = (raw_count_full * measure->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005150 }
5151
5152 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07005153 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005154 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
5155
Stephen Boyde334aeb2012-01-24 12:17:29 -08005156 clk_disable_unprepare(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08005157
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005158 return ret;
5159}
5160#else /* !CONFIG_DEBUG_FS */
Matt Wagantallf82f2942012-01-27 13:56:13 -08005161static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005162{
5163 return -EINVAL;
5164}
5165
Matt Wagantallf82f2942012-01-27 13:56:13 -08005166static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005167{
5168 return 0;
5169}
5170#endif /* CONFIG_DEBUG_FS */
5171
Matt Wagantallae053222012-05-14 19:42:07 -07005172static struct clk_ops clk_ops_measure = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005173 .set_parent = measure_clk_set_parent,
5174 .get_rate = measure_clk_get_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005175};
5176
Matt Wagantall8b38f942011-08-02 18:23:18 -07005177static struct measure_clk measure_clk = {
5178 .c = {
5179 .dbg_name = "measure_clk",
Matt Wagantallae053222012-05-14 19:42:07 -07005180 .ops = &clk_ops_measure,
Matt Wagantall8b38f942011-08-02 18:23:18 -07005181 CLK_INIT(measure_clk.c),
5182 },
5183 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005184};
5185
Tianyi Goua8b3cce2011-11-08 14:37:26 -08005186static struct clk_lookup msm_clocks_8064[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005187 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5188 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Mohan Pallaka804ca592012-06-14 14:37:38 +05305189 CLK_LOOKUP("pwm_clk", cxo_clk.c, "0-0048"),
Stephen Boyded630b02012-01-26 15:26:47 -08005190 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5191 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5192 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5193 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5194 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Matt Wagantall292aace2012-01-26 19:12:34 -08005195 CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005196 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08005197 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
David Collinsa7d23532012-08-02 10:48:16 -07005198 CLK_LOOKUP("vref_buff", cxo_clk.c, "rpm-regulator"),
Stephen Boyded630b02012-01-26 15:26:47 -08005199 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5200 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5201 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5202 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005203
Matt Wagantalld75f1312012-05-23 16:17:35 -07005204 CLK_LOOKUP("bus_clk", afab_clk.c, ""),
5205 CLK_LOOKUP("bus_clk", afab_a_clk.c, ""),
5206 CLK_LOOKUP("bus_clk", cfpb_clk.c, ""),
5207 CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""),
5208 CLK_LOOKUP("bus_clk", dfab_clk.c, ""),
5209 CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""),
5210 CLK_LOOKUP("mem_clk", ebi1_clk.c, ""),
5211 CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""),
5212 CLK_LOOKUP("bus_clk", mmfab_clk.c, ""),
5213 CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""),
5214 CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""),
5215 CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""),
5216 CLK_LOOKUP("bus_clk", sfab_clk.c, ""),
5217 CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""),
5218 CLK_LOOKUP("bus_clk", sfpb_clk.c, ""),
5219 CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""),
5220
Tianyi Gou21a0e802012-02-04 22:34:10 -08005221 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005222 CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005223 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5224 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5225 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005226 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005227 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5228 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5229 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5230 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5231 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005232 CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005233 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5234 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Pratik Patelf17b1472012-05-25 22:23:52 -07005235 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""),
Pratik Patel3b0ca882012-06-01 16:54:14 -07005236 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tpiu.0"),
5237 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etb.0"),
5238 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel.0"),
5239 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.0"),
5240 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.1"),
5241 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.2"),
5242 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.3"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005243
Tianyi Gou21a0e802012-02-04 22:34:10 -08005244 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005245 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""),
5246 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5247 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005248
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005249 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5250 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5251 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005252 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005253 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5254 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5255 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
5256 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""),
Mayank Rana262e9032012-05-10 15:14:00 -07005257 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005258 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"),
David Keitel3c40fc52012-02-09 17:53:52 -08005259 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005260 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08005261 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08005262 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08005263 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"),
Joel King8f839b92012-04-01 14:37:46 -07005264 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.5"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005265 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5266 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5267 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08005268 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Tianyi Gou05e01102012-02-08 22:15:49 -08005269 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Tianyi Gou43208a02011-09-27 15:35:13 -07005270 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5271 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5272 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5273 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Joel Nider6cbe66a2012-06-26 11:11:59 +03005274 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
5275 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.0"),
5276 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.1"),
5277 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005278 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005279 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5280 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
5281 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005282 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5283 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5284 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005285 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""),
5286 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""),
Tianyi Gou352955d2012-05-18 19:44:01 -07005287 CLK_LOOKUP("src_clk", sata_src_clk.c, ""),
5288 CLK_LOOKUP("core_rxoob_clk", sata_rxoob_clk.c, ""),
5289 CLK_LOOKUP("core_pmalive_clk", sata_pmalive_clk.c, ""),
5290 CLK_LOOKUP("bus_clk", sata_a_clk.c, ""),
5291 CLK_LOOKUP("iface_clk", sata_p_clk.c, ""),
5292 CLK_LOOKUP("slave_iface_clk", sfab_sata_s_p_clk.c, ""),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07005293 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
5294 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
5295 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
5296 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
5297 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
5298 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005299 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005300 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"),
David Keitel3c40fc52012-02-09 17:53:52 -08005301 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005302 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08005303 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08005304 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08005305 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"),
Joel King8f839b92012-04-01 14:37:46 -07005306 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "qup_i2c.5"),
Mayank Rana262e9032012-05-10 15:14:00 -07005307 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Jin Hong4bbbfba2012-02-02 21:48:07 -08005308 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"),
Joel Nider6d7d16c2012-05-30 18:02:42 +03005309 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tspp.0"),
5310 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tspp.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005311 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005312 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05305313 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
5314 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07005315 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5316 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5317 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5318 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06005319 CLK_LOOKUP("iface_clk", pcie_p_clk.c, "msm_pcie"),
5320 CLK_LOOKUP("ref_clk", pcie_phy_ref_clk.c, "msm_pcie"),
5321 CLK_LOOKUP("bus_clk", pcie_a_clk.c, "msm_pcie"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005322 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5323 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005324 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5325 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5326 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5327 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Kevin Chand07220e2012-02-13 15:52:22 -08005328 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005329 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Sreesudhan Ramakrish Ramkumar8002a792012-04-09 17:42:58 -07005330 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar6c6f57c2012-02-21 15:12:44 -08005331 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Kevin Chand07220e2012-02-13 15:52:22 -08005332 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
5333 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5334 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5335 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5336 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5337 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5338 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5339 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5340 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5341 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5342 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5343 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5344 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5345 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5346 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5347 CLK_LOOKUP("csiphy_timer_src_clk",
5348 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5349 CLK_LOOKUP("csiphy_timer_src_clk",
5350 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5351 CLK_LOOKUP("csiphy_timer_src_clk",
5352 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5353 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5354 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5355 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005356 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5357 CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"),
5358 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
5359 CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"),
Tianyi Gou51918802012-01-26 14:05:43 -08005360 CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""),
5361 CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""),
5362
Pu Chen86b4be92011-11-03 17:27:57 -07005363 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005364 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005365 CLK_LOOKUP("bus_clk",
Patrick Dalye6f489042012-07-11 15:29:15 -07005366 gfx3d_axi_clk.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005367 CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005368 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005369 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
5370 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005371 CLK_LOOKUP("core_clk", vcap_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005372 CLK_LOOKUP("core_clk", vcap_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005373 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005374 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005375 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005376 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005377 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5378 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005379 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005380 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005381 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005382 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005383 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005384 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005385 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005386 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005387 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005388 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Matt Wagantall61286312012-02-22 15:55:09 -08005389 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005390 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5391 CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""),
Greg Griscofa47b532011-11-11 10:32:06 -08005392 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005393 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005394 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
Tianyi Gou51918802012-01-26 14:05:43 -08005395 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005396 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005397 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Ujwal Pateld041f982012-03-27 19:51:44 -07005398 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005399 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chand07220e2012-02-13 15:52:22 -08005400 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005401 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chand07220e2012-02-13 15:52:22 -08005402 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005403 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5404 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5405 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5406 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5407 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5408 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5409 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005410 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
5411 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"),
Kevin Chand07220e2012-02-13 15:52:22 -08005412 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5413 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5414 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005415 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5416 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
5417 CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"),
5418 CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"),
Pu Chen86b4be92011-11-03 17:27:57 -07005419 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005420 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005421 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5422 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005423 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005424 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005425 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005426 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005427 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005428 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005429 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005430 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005431 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005432 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005433 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chand07220e2012-02-13 15:52:22 -08005434 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005435 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chanb20742b2012-02-27 15:47:35 -08005436 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall61286312012-02-22 15:55:09 -08005437 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005438
Patrick Lai04baee942012-05-01 14:38:47 -07005439 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c,
5440 "msm-dai-q6-mi2s"),
5441 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c,
5442 "msm-dai-q6-mi2s"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005443 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5444 "msm-dai-q6.1"),
5445 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5446 "msm-dai-q6.1"),
5447 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5448 "msm-dai-q6.5"),
5449 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5450 "msm-dai-q6.5"),
5451 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5452 "msm-dai-q6.16384"),
5453 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5454 "msm-dai-q6.16384"),
5455 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5456 "msm-dai-q6.4"),
5457 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5458 "msm-dai-q6.4"),
5459 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005460 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005461 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005462 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005463 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""),
5464 CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""),
5465 CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""),
5466 CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""),
5467 CLK_LOOKUP("core_clk", rot_axi_clk.c, ""),
5468 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""),
5469 CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
5470 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
5471 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
Patrick Dalye6f489042012-07-11 15:29:15 -07005472 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005473
5474 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5475 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5476 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"),
5477 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"),
5478 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5479 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5480 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5481 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5482 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5483 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5484 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
5485
Manu Gautam5143b252012-01-05 19:25:23 -08005486 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5487 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5488 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5489 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5490 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005491
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005492 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5493 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5494 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5495 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5496 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5497 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5498 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5499 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5500 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
Patrick Dalye6f489042012-07-11 15:29:15 -07005501 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.9"),
5502 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"),
5503
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005504 CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
5505
Deepak Kotur954b1782012-04-24 17:58:19 -07005506 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5507 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5508 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5509 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5510 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005511 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5512 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
5513
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005514 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005515 CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
5516 CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005517
Matt Wagantallc33c1ed2012-07-23 17:19:08 -07005518 CLK_LOOKUP("reset1_clk", dsi1_reset_clk.c, "footswitch-8x60.4"),
5519 CLK_LOOKUP("reset2_clk", dsi2_reset_clk.c, "footswitch-8x60.4"),
Matt Wagantall735e41b2012-07-23 17:18:58 -07005520
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005521 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5522 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5523 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
Tianyi Gou455c13c2012-02-02 16:33:24 -08005524 CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""),
5525 CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005526};
5527
Patrick Dalye6f489042012-07-11 15:29:15 -07005528static struct clk_lookup msm_clocks_8960_common[] __initdata = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005529 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5530 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyded630b02012-01-26 15:26:47 -08005531 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5532 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5533 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5534 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5535 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005536 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08005537 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
David Collinsa7d23532012-08-02 10:48:16 -07005538 CLK_LOOKUP("vref_buff", cxo_clk.c, "rpm-regulator"),
Stephen Boyded630b02012-01-26 15:26:47 -08005539 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5540 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5541 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5542 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005543
Matt Wagantalld75f1312012-05-23 16:17:35 -07005544 CLK_LOOKUP("bus_clk", afab_clk.c, ""),
5545 CLK_LOOKUP("bus_clk", afab_a_clk.c, ""),
5546 CLK_LOOKUP("bus_clk", cfpb_clk.c, ""),
5547 CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""),
5548 CLK_LOOKUP("bus_clk", dfab_clk.c, ""),
5549 CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""),
5550 CLK_LOOKUP("mem_clk", ebi1_clk.c, ""),
5551 CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""),
5552 CLK_LOOKUP("bus_clk", mmfab_clk.c, ""),
5553 CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""),
5554 CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""),
5555 CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""),
5556 CLK_LOOKUP("bus_clk", sfab_clk.c, ""),
5557 CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""),
5558 CLK_LOOKUP("bus_clk", sfpb_clk.c, ""),
5559 CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""),
5560
Matt Wagantallb2710b82011-11-16 19:55:17 -08005561 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005562 CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005563 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5564 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5565 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005566 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005567 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5568 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5569 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5570 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5571 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005572 CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005573 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5574 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Pratik Patelf17b1472012-05-25 22:23:52 -07005575 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""),
Pratik Patel3b0ca882012-06-01 16:54:14 -07005576 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tpiu.0"),
5577 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etb.0"),
5578 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel.0"),
5579 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.0"),
5580 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.1"),
5581 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.2"),
5582 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.3"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005583
5584 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005585 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5586 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5587 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005588
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005589 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5590 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5591 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5592 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5593 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5594 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5595 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
Matt Wagantalle2522372011-08-17 14:52:21 -07005596 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5597 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005598 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
Mayank Rana1f02d952012-07-04 19:11:20 +05305599 /* used on 8960 SGLTE for console */
Stepan Moskovchenko2b4b1cd2012-03-29 18:21:04 -07005600 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"),
Mayank Rana1f02d952012-07-04 19:11:20 +05305601 /* used on 8960 standalone with Atheros Bluetooth */
5602 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hs.2"),
Mayank Ranae009c922012-03-22 03:02:06 +05305603 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005604 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5605 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5606 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005607 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005608 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005609 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5610 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005611 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5612 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5613 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5614 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005615 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005616 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005617 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005618 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005619 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005620 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005621 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005622 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5623 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5624 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5625 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5626 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005627 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005628 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005629 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5630 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005631 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5632 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5633 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5634 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5635 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5636 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005637 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5638 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5639 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5640 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5641 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005642 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005643 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005644 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005645 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005646 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005647 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005648 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005649 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5650 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005651 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5652 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005653 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
Mayank Rana1f02d952012-07-04 19:11:20 +05305654 /* used on 8960 SGLTE for serial console */
Stepan Moskovchenko2b4b1cd2012-03-29 18:21:04 -07005655 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"),
Mayank Rana1f02d952012-07-04 19:11:20 +05305656 /* used on 8960 standalone with Atheros Bluetooth */
5657 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hs.2"),
Mayank Ranae009c922012-03-22 03:02:06 +05305658 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"),
Matt Wagantallac294852011-08-17 15:44:58 -07005659 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005660 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005661 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005662 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
Joel Nider6d7d16c2012-05-30 18:02:42 +03005663 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tspp.0"),
5664 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tspp.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005665 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5666 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005667 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005668 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5669 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5670 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5671 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5672 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005673 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5674 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005675 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5676 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5677 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5678 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Kevin Chan09f4e662011-12-16 08:17:02 -08005679 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5680 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5681 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005682 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -08005683 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005684 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005685 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5686 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005687 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005688 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5689 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005690 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005691 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5692 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005693 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
Kevin Chane12c6672011-10-26 11:55:26 -07005694 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5695 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005696 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5697 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5698 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5699 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5700 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5701 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5702 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Kevin Chanf6216f22011-10-25 18:40:11 -07005703 CLK_LOOKUP("csiphy_timer_src_clk",
5704 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5705 CLK_LOOKUP("csiphy_timer_src_clk",
5706 csiphy_timer_src_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005707 CLK_LOOKUP("csiphy_timer_src_clk",
5708 csiphy_timer_src_clk.c, "msm_csiphy.2"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005709 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5710 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005711 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005712 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5713 CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"),
5714 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
5715 CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005716 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005717 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5718 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005719 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5720 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005721 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Kalyani Oruganti465d1e12012-05-15 10:23:05 -07005722 CLK_LOOKUP("core_clk", jpegd_clk.c, "msm_mercury.0"),
5723 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, "msm_mercury.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005724 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005725 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005726 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005727 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005728 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005729 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005730 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005731 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005732 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5733 CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005734 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005735 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005736 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005737 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
5738 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005739 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005740 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005741 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005742 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005743 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005744 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005745 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005746 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005747 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5748 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5749 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5750 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5751 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5752 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5753 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005754 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
5755 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005756 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5757 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005758 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005759 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5760 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
5761 CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"),
5762 CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005763 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005764 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005765 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5766 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005767 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005768 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005769 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005770 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005771 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005772 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005773 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005774 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005775 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005776 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005777 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005778 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005779 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005780 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005781 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Patrick Lai04baee942012-05-01 14:38:47 -07005782 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c,
5783 "msm-dai-q6-mi2s"),
5784 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c,
5785 "msm-dai-q6-mi2s"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005786 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5787 "msm-dai-q6.1"),
5788 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5789 "msm-dai-q6.1"),
5790 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5791 "msm-dai-q6.5"),
5792 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5793 "msm-dai-q6.5"),
5794 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5795 "msm-dai-q6.16384"),
5796 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5797 "msm-dai-q6.16384"),
5798 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5799 "msm-dai-q6.4"),
5800 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5801 "msm-dai-q6.4"),
5802 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005803 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005804 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005805 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005806 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5807 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5808 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5809 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5810 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5811 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5812 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5813 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5814 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5815 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005816
5817 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5818 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5819 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5820 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5821 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005822 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5823 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005824
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005825 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005826 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005827 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5828 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5829 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5830 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5831 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005832 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005833 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005834 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005835
Matt Wagantalle1a86062011-08-18 17:46:10 -07005836 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005837 CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
5838 CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005839
Matt Wagantallc33c1ed2012-07-23 17:19:08 -07005840 CLK_LOOKUP("reset1_clk", dsi1_reset_clk.c, "footswitch-8x60.4"),
5841 CLK_LOOKUP("reset2_clk", dsi2_reset_clk.c, "footswitch-8x60.4"),
Matt Wagantall735e41b2012-07-23 17:18:58 -07005842
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005843 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5844 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5845 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5846 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5847 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5848 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005849};
5850
Patrick Dalye6f489042012-07-11 15:29:15 -07005851static struct clk_lookup msm_clocks_8960_only[] __initdata = {
5852 CLK_LOOKUP("enc_clk", tv_enc_clk.c, "tvenc.0"),
5853 CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"),
5854 CLK_LOOKUP("iface_clk", tv_enc_p_clk.c, "tvenc.0"),
5855
5856 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
5857 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
5858 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
5859 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
5860 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
5861 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
5862 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
5863 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
5864 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5865 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
5866};
5867
5868static struct clk_lookup msm_clocks_8960ab_only[] __initdata = {
5869 CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),
Joel King9af070b2012-08-19 22:32:14 -07005870 CLK_LOOKUP("core_clk", gfx3d_axi_clk.c, "msm_iommu.10"),
Patrick Dalye6f489042012-07-11 15:29:15 -07005871 CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""),
5872};
5873
5874static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_common)
5875 + ARRAY_SIZE(msm_clocks_8960_only)
5876 + ARRAY_SIZE(msm_clocks_8960ab_only)];
5877
Tianyi Goue3d4f542012-03-15 17:06:45 -07005878static struct clk_lookup msm_clocks_8930[] = {
Stephen Boydbe1a7392012-04-02 20:17:11 -07005879 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005880 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5881 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5882 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5883 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5884 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
5885 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
David Collinsa7d23532012-08-02 10:48:16 -07005886 CLK_LOOKUP("vref_buff", cxo_clk.c, "rpm-regulator"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005887 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5888 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5889 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5890 CLK_LOOKUP("measure", measure_clk.c, "debug"),
5891
Matt Wagantalld75f1312012-05-23 16:17:35 -07005892 CLK_LOOKUP("bus_clk", afab_clk.c, ""),
5893 CLK_LOOKUP("bus_clk", afab_a_clk.c, ""),
5894 CLK_LOOKUP("bus_clk", cfpb_clk.c, ""),
5895 CLK_LOOKUP("bus_clk", cfpb_a_clk.c, ""),
5896 CLK_LOOKUP("bus_clk", dfab_clk.c, ""),
5897 CLK_LOOKUP("bus_clk", dfab_a_clk.c, ""),
5898 CLK_LOOKUP("mem_clk", ebi1_clk.c, ""),
5899 CLK_LOOKUP("mem_clk", ebi1_a_clk.c, ""),
5900 CLK_LOOKUP("bus_clk", mmfab_clk.c, ""),
5901 CLK_LOOKUP("bus_clk", mmfab_a_clk.c, ""),
5902 CLK_LOOKUP("bus_clk", mmfpb_clk.c, ""),
5903 CLK_LOOKUP("bus_clk", mmfpb_a_clk.c, ""),
5904 CLK_LOOKUP("bus_clk", sfab_clk.c, ""),
5905 CLK_LOOKUP("bus_clk", sfab_a_clk.c, ""),
5906 CLK_LOOKUP("bus_clk", sfpb_clk.c, ""),
5907 CLK_LOOKUP("bus_clk", sfpb_a_clk.c, ""),
5908
Tianyi Goue3d4f542012-03-15 17:06:45 -07005909 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005910 CLK_LOOKUP("bus_a_clk", afab_msmbus_a_clk.c, "msm_apps_fab"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005911 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5912 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5913 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
5914 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
5915 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5916 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5917 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5918 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5919 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07005920 CLK_LOOKUP("mem_a_clk", ebi1_msmbus_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005921 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5922 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Pratik Patelf17b1472012-05-25 22:23:52 -07005923 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, ""),
Pratik Patel3b0ca882012-06-01 16:54:14 -07005924 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tpiu.0"),
5925 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etb.0"),
5926 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel.0"),
5927 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.0"),
5928 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.1"),
5929 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.2"),
5930 CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm.3"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005931
5932 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005933 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5934 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5935 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
5936
5937 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5938 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5939 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5940 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5941 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5942 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5943 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
5944 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5945 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5946 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5947 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5948 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5949 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5950 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5951 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
5952 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
5953 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
5954 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5955 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
5956 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5957 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5958 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5959 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
5960 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
5961 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
5962 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
5963 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
5964 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
5965 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
5966 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
5967 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5968 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5969 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5970 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5971 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
5972 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5973 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
5974 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5975 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
5976 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5977 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5978 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5979 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5980 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5981 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
5982 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5983 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5984 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5985 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5986 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
5987 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
5988 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
5989 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
5990 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
5991 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
5992 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
5993 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
5994 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5995 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
5996 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5997 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
5998 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5999 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
6000 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
6001 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
6002 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
6003 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
6004 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
6005 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
6006 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
6007 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
6008 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
6009 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
6010 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
6011 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
6012 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
6013 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
6014 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
6015 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
6016 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
6017 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
6018 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006019 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Hody Hung994f4622012-04-24 10:27:45 -07006020 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
Sreesudhan Ramakrish Ramkumar981c82c2012-04-30 17:31:37 -07006021 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006022 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
6023 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
6024 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
6025 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
6026 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
6027 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
6028 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
6029 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
6030 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
6031 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
6032 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
6033 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
6034 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
6035 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
6036 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
6037 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
6038 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
6039 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
6040 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
6041 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
6042 CLK_LOOKUP("csiphy_timer_src_clk",
6043 csiphy_timer_src_clk.c, "msm_csiphy.0"),
6044 CLK_LOOKUP("csiphy_timer_src_clk",
6045 csiphy_timer_src_clk.c, "msm_csiphy.1"),
6046 CLK_LOOKUP("csiphy_timer_src_clk",
6047 csiphy_timer_src_clk.c, "msm_csiphy.2"),
6048 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
6049 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
6050 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006051 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
6052 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006053 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
6054 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
6055 CLK_LOOKUP("bus_clk",
6056 gfx3d_axi_clk_8930.c, "footswitch-8x60.2"),
6057 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07006058 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
6059 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006060 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006061 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006062 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006063 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006064 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006065 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006066 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
6067 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
6068 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006069 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
6070 CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006071 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006072 CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006073 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
6074 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006075 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
6076 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006077 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006078 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006079 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
6080 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
6081 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
6082 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
6083 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
6084 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
6085 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
6086 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
6087 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
6088 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
6089 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
6090 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
6091 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006092 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006093 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
6094 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
6095 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006096 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
6097 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006098 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
6099 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
6100 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
6101 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07006102 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006103 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
6104 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07006105 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006106 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
6107 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
6108 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
6109 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
6110 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
6111 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
6112 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
6113 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
6114 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
6115 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
6116 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
6117 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
6118 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
6119 "msm-dai-q6.1"),
6120 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
6121 "msm-dai-q6.1"),
6122 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
6123 "msm-dai-q6.5"),
6124 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
6125 "msm-dai-q6.5"),
6126 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
6127 "msm-dai-q6.16384"),
6128 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
6129 "msm-dai-q6.16384"),
6130 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
6131 "msm-dai-q6.4"),
6132 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
6133 "msm-dai-q6.4"),
6134 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
6135 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
6136 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
6137 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
6138 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
6139 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
6140 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
6141 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
6142 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
6143 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
6144 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
6145 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"),
6146 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"),
6147
6148 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
6149 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
6150 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
6151 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
6152 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08006153 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
6154 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006155
6156 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
6157 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
6158 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
6159 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
6160 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
6161 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
6162 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
6163 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
6164 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
6165 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006166
6167 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall33bac7e2012-05-22 14:59:05 -07006168 CLK_LOOKUP("mem_clk", ebi1_acpu_a_clk.c, ""),
6169 CLK_LOOKUP("bus_clk", afab_acpu_a_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07006170
Matt Wagantallc33c1ed2012-07-23 17:19:08 -07006171 CLK_LOOKUP("reset1_clk", dsi1_reset_clk.c, "footswitch-8x60.4"),
Matt Wagantall735e41b2012-07-23 17:18:58 -07006172
Tianyi Goue3d4f542012-03-15 17:06:45 -07006173 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
6174 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
6175 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
6176 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
6177 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
6178 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
6179};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006180/*
6181 * Miscellaneous clock register initializations
6182 */
6183
6184/* Read, modify, then write-back a register. */
6185static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
6186{
6187 uint32_t regval = readl_relaxed(reg);
6188 regval &= ~mask;
6189 regval |= val;
6190 writel_relaxed(regval, reg);
6191}
6192
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006193static struct pll_config_regs pll4_regs __initdata = {
6194 .l_reg = LCC_PLL0_L_VAL_REG,
6195 .m_reg = LCC_PLL0_M_VAL_REG,
6196 .n_reg = LCC_PLL0_N_VAL_REG,
6197 .config_reg = LCC_PLL0_CONFIG_REG,
6198 .mode_reg = LCC_PLL0_MODE_REG,
6199};
Tianyi Gou41515e22011-09-01 19:37:43 -07006200
Matt Wagantall86e03822011-12-12 10:59:24 -08006201static struct pll_config pll4_config_393 __initdata = {
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006202 .l = 0xE,
6203 .m = 0x27A,
6204 .n = 0x465,
6205 .vco_val = 0x0,
6206 .vco_mask = BM(17, 16),
6207 .pre_div_val = 0x0,
6208 .pre_div_mask = BIT(19),
6209 .post_div_val = 0x0,
6210 .post_div_mask = BM(21, 20),
6211 .mn_ena_val = BIT(22),
6212 .mn_ena_mask = BIT(22),
6213 .main_output_val = BIT(23),
6214 .main_output_mask = BIT(23),
6215};
Tianyi Gou41515e22011-09-01 19:37:43 -07006216
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006217static struct pll_config_regs pll15_regs __initdata = {
6218 .l_reg = MM_PLL3_L_VAL_REG,
6219 .m_reg = MM_PLL3_M_VAL_REG,
6220 .n_reg = MM_PLL3_N_VAL_REG,
6221 .config_reg = MM_PLL3_CONFIG_REG,
6222 .mode_reg = MM_PLL3_MODE_REG,
6223};
Tianyi Gou358c3862011-10-18 17:03:41 -07006224
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006225static struct pll_config pll15_config __initdata = {
6226 .l = (0x24 | BVAL(31, 7, 0x620)),
6227 .m = 0x1,
6228 .n = 0x9,
6229 .vco_val = BVAL(17, 16, 0x2),
6230 .vco_mask = BM(17, 16),
6231 .pre_div_val = 0x0,
6232 .pre_div_mask = BIT(19),
6233 .post_div_val = 0x0,
6234 .post_div_mask = BM(21, 20),
6235 .mn_ena_val = BIT(22),
6236 .mn_ena_mask = BIT(22),
6237 .main_output_val = BIT(23),
6238 .main_output_mask = BIT(23),
6239};
Tianyi Gou41515e22011-09-01 19:37:43 -07006240
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006241static struct pll_config_regs pll14_regs __initdata = {
6242 .l_reg = BB_PLL14_L_VAL_REG,
6243 .m_reg = BB_PLL14_M_VAL_REG,
6244 .n_reg = BB_PLL14_N_VAL_REG,
6245 .config_reg = BB_PLL14_CONFIG_REG,
6246 .mode_reg = BB_PLL14_MODE_REG,
6247};
6248
6249static struct pll_config pll14_config __initdata = {
6250 .l = (0x11 | BVAL(31, 7, 0x620)),
6251 .m = 0x7,
6252 .n = 0x9,
6253 .vco_val = 0x0,
6254 .vco_mask = BM(17, 16),
6255 .pre_div_val = 0x0,
6256 .pre_div_mask = BIT(19),
6257 .post_div_val = 0x0,
6258 .post_div_mask = BM(21, 20),
6259 .mn_ena_val = BIT(22),
6260 .mn_ena_mask = BIT(22),
6261 .main_output_val = BIT(23),
6262 .main_output_mask = BIT(23),
6263};
Tianyi Gou41515e22011-09-01 19:37:43 -07006264
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006265static void __init reg_init(void)
6266{
Stephen Boydd471e7a2011-11-19 01:37:39 -08006267 void __iomem *imem_reg;
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006268
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006269 /* Deassert MM SW_RESET_ALL signal. */
6270 writel_relaxed(0, SW_RESET_ALL_REG);
6271
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006272 /*
Tianyi Goue3d4f542012-03-15 17:06:45 -07006273 * Some bits are only used on 8960 or 8064 or 8930 and are marked as
6274 * reserved bits on the other SoCs. Writing to these reserved bits
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006275 * should have no effect.
6276 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08006277 /*
6278 * Initialize MM AHB registers: Enable the FPB clock and disable HW
Patrick Dalye6f489042012-07-11 15:29:15 -07006279 * gating on 8627 and 8960 for all clocks. Also set VFE_AHB's
Stephen Boydd471e7a2011-11-19 01:37:39 -08006280 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
6281 * the clock is halted. The sleep and wake-up delays are set to safe
6282 * values.
6283 */
Patrick Dalye6f489042012-07-11 15:29:15 -07006284 if (cpu_is_msm8627() || cpu_is_msm8960ab()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08006285 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
6286 writel_relaxed(0x000007F9, AHB_EN2_REG);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006287 } else {
David Garibaldif69836a2012-08-17 16:05:22 -07006288 rmwreg(0x40000000, AHB_EN_REG, 0x6C000103);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006289 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
Stephen Boydd471e7a2011-11-19 01:37:39 -08006290 }
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006291
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006292 if (cpu_is_apq8064())
Tianyi Gouf3095ea2012-05-22 14:16:06 -07006293 rmwreg(0x00000001, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006294
6295 /* Deassert all locally-owned MM AHB resets. */
6296 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07006297 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006298
6299 /* Initialize MM AXI registers: Enable HW gating for all clocks that
6300 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
6301 * delays to safe values. */
Patrick Dalye6f489042012-07-11 15:29:15 -07006302 if (cpu_is_msm8960ab() || (cpu_is_msm8960() &&
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006303 SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 3) ||
6304 cpu_is_msm8627()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08006305 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
6306 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006307 } else {
6308 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
6309 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08006310 }
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006311
Matt Wagantall53d968f2011-07-19 13:22:53 -07006312 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006313 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
6314
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006315 if (cpu_is_apq8064())
Tianyi Gouf3095ea2012-05-22 14:16:06 -07006316 rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF);
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006317 if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627())
Tianyi Goue3d4f542012-03-15 17:06:45 -07006318 rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
Patrick Dalye6f489042012-07-11 15:29:15 -07006319 if (cpu_is_msm8960ab())
6320 rmwreg(0x009FE000, MAXI_EN5_REG, 0x01FFE000);
6321
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006322 if (cpu_is_msm8627())
Stephen Boydd471e7a2011-11-19 01:37:39 -08006323 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Patrick Dalye6f489042012-07-11 15:29:15 -07006324 else if (cpu_is_msm8960ab())
6325 rmwreg(0x000001C6, SAXI_EN_REG, 0x00001DF6);
Tianyi Gou33caa5d2012-06-18 12:04:11 -07006326 else
6327 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08006328
6329 /* Enable IMEM's clk_on signal */
6330 imem_reg = ioremap(0x04b00040, 4);
6331 if (imem_reg) {
6332 writel_relaxed(0x3, imem_reg);
6333 iounmap(imem_reg);
6334 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006335
6336 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
6337 * memories retain state even when not clocked. Also, set sleep and
6338 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07006339 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
6340 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
6341 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006342 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07006343 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006344 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006345 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
6346 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
6347 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006348 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
6349 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
6350 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07006351 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07006352 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Patrick Dalye6f489042012-07-11 15:29:15 -07006353 if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()) {
Tianyi Goue3d4f542012-03-15 17:06:45 -07006354 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
6355 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
6356 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
6357 }
Patrick Dalye6f489042012-07-11 15:29:15 -07006358 if (cpu_is_msm8960ab())
6359 rmwreg(0x00000001, DSI2_PIXEL_CC2_REG, 0x00000001);
6360
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006361 if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||
6362 cpu_is_msm8627())
Patrick Dalye6f489042012-07-11 15:29:15 -07006363 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
6364 if (cpu_is_msm8960ab())
6365 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Goue3d4f542012-03-15 17:06:45 -07006366
6367 if (cpu_is_msm8960()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006368 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
6369 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006370 }
6371 if (cpu_is_apq8064()) {
6372 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07006373 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006374 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006375
Tianyi Gou41515e22011-09-01 19:37:43 -07006376 /*
6377 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
6378 * core remain active during halt state of the clk. Also, set sleep
6379 * and wake-up value to max.
6380 */
6381 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006382 if (cpu_is_apq8064()) {
6383 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
6384 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
6385 }
Tianyi Gou41515e22011-09-01 19:37:43 -07006386
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006387 /* De-assert MM AXI resets to all hardware blocks. */
6388 writel_relaxed(0, SW_RESET_AXI_REG);
6389
6390 /* Deassert all MM core resets. */
6391 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07006392 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006393
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006394 /* Enable TSSC and PDM PXO sources. */
6395 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
6396 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
6397
6398 /* Source SLIMBus xo src from slimbus reference clock */
Patrick Dalye6f489042012-07-11 15:29:15 -07006399 if (cpu_is_msm8960ab() || cpu_is_msm8960())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07006400 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006401
6402 /* Source the dsi_byte_clks from the DSI PHY PLLs */
6403 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
Patrick Dalye6f489042012-07-11 15:29:15 -07006404 if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064())
Tianyi Goue3d4f542012-03-15 17:06:45 -07006405 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07006406
Siddhartha Agrawal482459c2012-05-24 15:28:53 -07006407 /* Source the dsi1_esc_clk from the DSI1 PHY PLLs */
6408 rmwreg(0x1, DSI1_ESC_NS_REG, 0x7);
6409
Tianyi Gou352955d2012-05-18 19:44:01 -07006410 /*
6411 * Source the sata_phy_ref_clk from PXO and set predivider of
6412 * sata_pmalive_clk to 1.
6413 */
6414 if (cpu_is_apq8064()) {
Tianyi Gou41515e22011-09-01 19:37:43 -07006415 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
Tianyi Gou352955d2012-05-18 19:44:01 -07006416 rmwreg(0, SATA_PMALIVE_CLK_CTL_REG, 0x3);
6417 }
Tianyi Gou41515e22011-09-01 19:37:43 -07006418
6419 /*
Tianyi Gou05e01102012-02-08 22:15:49 -08006420 * TODO: Programming below PLLs and prng_clk is temporary and
6421 * needs to be removed after bootloaders program them.
Tianyi Gou41515e22011-09-01 19:37:43 -07006422 */
6423 if (cpu_is_apq8064()) {
Tianyi Gou317aa862012-02-06 14:31:07 -08006424 u32 is_pll_enabled;
Tianyi Gou41515e22011-09-01 19:37:43 -07006425
6426 /* Program pxo_src_clk to source from PXO */
6427 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
6428
Tianyi Gou41515e22011-09-01 19:37:43 -07006429 /* Check if PLL14 is active */
6430 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006431 if (!is_pll_enabled)
Tianyi Goudf71f2e2011-10-24 22:25:04 -07006432 /* Ref clk = 27MHz and program pll14 to 480MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006433 configure_pll(&pll14_config, &pll14_regs, 1);
Tianyi Gou621f8742011-09-01 21:45:01 -07006434
Tianyi Gou621f8742011-09-01 21:45:01 -07006435 /* Program PLL15 to 975MHz with ref clk = 27MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006436 configure_pll(&pll15_config, &pll15_regs, 0);
Tianyi Gouc29c3242011-10-12 21:02:15 -07006437
6438 /* Check if PLL4 is active */
6439 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006440 if (!is_pll_enabled)
Tianyi Goudf71f2e2011-10-24 22:25:04 -07006441 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
Matt Wagantall86e03822011-12-12 10:59:24 -08006442 configure_pll(&pll4_config_393, &pll4_regs, 1);
Tianyi Gouc29c3242011-10-12 21:02:15 -07006443
6444 /* Enable PLL4 source on the LPASS Primary PLL Mux */
6445 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou05e01102012-02-08 22:15:49 -08006446
6447 /* Program prng_clk to 64MHz if it isn't configured */
6448 if (!readl_relaxed(PRNG_CLK_NS_REG))
6449 writel_relaxed(0x2B, PRNG_CLK_NS_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07006450 }
Tianyi Gou65c536a2012-03-20 23:20:29 -07006451
6452 /*
6453 * Program PLL15 to 900MHz with ref clk = 27MHz and
6454 * only enable PLL main output.
6455 */
Stepan Moskovchenko0df9bb22012-07-06 18:19:15 -07006456 if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006457 pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
6458 pll15_config.m = 0x1;
6459 pll15_config.n = 0x3;
6460 configure_pll(&pll15_config, &pll15_regs, 0);
6461 /* Disable AUX and BIST outputs */
6462 writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
Tianyi Gou65c536a2012-03-20 23:20:29 -07006463 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006464}
6465
Patrick Dalye6f489042012-07-11 15:29:15 -07006466struct clock_init_data msm8960_clock_init_data __initdata;
Matt Wagantallb64888f2012-04-02 21:35:07 -07006467static void __init msm8960_clock_pre_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006468{
Matt Wagantall86e03822011-12-12 10:59:24 -08006469 /* Initialize clock registers. */
6470 reg_init();
6471
Patrick Daly1a3859f2012-08-27 16:10:26 -07006472 if (cpu_is_apq8064())
Matt Wagantall82feaa12012-07-09 10:54:49 -07006473 vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8064;
Tianyi Goubf3d0b12012-01-23 14:37:28 -08006474
Matt Wagantall86e03822011-12-12 10:59:24 -08006475 /* Detect PLL4 programmed for alternate 491.52MHz clock plan. */
6476 if (readl_relaxed(LCC_PLL0_L_VAL_REG) == 0x12) {
6477 pll4_clk.c.rate = 491520000;
6478 audio_slimbus_clk.freq_tbl = clk_tbl_aif_osr_492;
6479 mi2s_osr_clk.freq_tbl = clk_tbl_aif_osr_492;
6480 codec_i2s_mic_osr_clk.freq_tbl = clk_tbl_aif_osr_492;
6481 spare_i2s_mic_osr_clk.freq_tbl = clk_tbl_aif_osr_492;
6482 codec_i2s_spkr_osr_clk.freq_tbl = clk_tbl_aif_osr_492;
6483 spare_i2s_spkr_osr_clk.freq_tbl = clk_tbl_aif_osr_492;
6484 pcm_clk.freq_tbl = clk_tbl_pcm_492;
6485 }
6486
Patrick Dalye6f489042012-07-11 15:29:15 -07006487 if (cpu_is_msm8960() || cpu_is_msm8960ab())
6488 memcpy(msm_clocks_8960, msm_clocks_8960_common,
6489 sizeof(msm_clocks_8960_common));
6490 if (cpu_is_msm8960ab()) {
6491 pll3_clk.c.rate = 650000000;
6492 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960ab;
6493 gfx3d_clk.c.fmax[VDD_DIG_LOW] = 192000000;
6494 gfx3d_clk.c.fmax[VDD_DIG_NOMINAL] = 325000000;
6495 gfx3d_clk.c.fmax[VDD_DIG_HIGH] = 400000000;
6496 mdp_clk.freq_tbl = clk_tbl_mdp_8960ab;
6497 mdp_clk.c.fmax[VDD_DIG_LOW] = 128000000;
6498 mdp_clk.c.fmax[VDD_DIG_NOMINAL] = 266667000;
6499
6500 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common),
6501 msm_clocks_8960ab_only, sizeof(msm_clocks_8960ab_only));
6502 msm8960_clock_init_data.size -=
6503 ARRAY_SIZE(msm_clocks_8960_only);
Joel King9af070b2012-08-19 22:32:14 -07006504
6505 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Patrick Dalye6f489042012-07-11 15:29:15 -07006506 } else if (cpu_is_msm8960()) {
6507 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common),
6508 msm_clocks_8960_only, sizeof(msm_clocks_8960_only));
6509 msm8960_clock_init_data.size -=
6510 ARRAY_SIZE(msm_clocks_8960ab_only);
6511 }
Tianyi Gou41515e22011-09-01 19:37:43 -07006512 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006513 * Change the freq tables for and voltage requirements for
6514 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07006515 */
6516 if (cpu_is_apq8064()) {
6517 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006518
6519 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
6520 sizeof(gfx3d_clk.c.fmax));
6521 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
6522 sizeof(ijpeg_clk.c.fmax));
6523 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
6524 sizeof(ijpeg_clk.c.fmax));
6525 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
6526 sizeof(tv_src_clk.c.fmax));
6527 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
6528 sizeof(vfe_clk.c.fmax));
6529
Patrick Dalye6f489042012-07-11 15:29:15 -07006530 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Goue3d4f542012-03-15 17:06:45 -07006531 }
6532
6533 /*
6534 * Change the freq tables and voltage requirements for
6535 * clocks which differ between 8960 and 8930.
6536 */
Patrick Dalyebe63c52012-08-07 15:41:30 -07006537 if (cpu_is_msm8930() || cpu_is_msm8627()) {
Tianyi Goue3d4f542012-03-15 17:06:45 -07006538 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930,
6539 sizeof(gfx3d_clk.c.fmax));
Patrick Dalyebe63c52012-08-07 15:41:30 -07006540 } else if (cpu_is_msm8930aa()) {
6541 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930aa,
6542 sizeof(gfx3d_clk.c.fmax));
6543 }
6544 if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627()) {
6545 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
Tianyi Goue3d4f542012-03-15 17:06:45 -07006546 pll15_clk.c.rate = 900000000;
6547 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07006548 }
Stephen Boyd842a1f62012-04-26 19:07:38 -07006549 if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B)
6550 prng_clk.freq_tbl = clk_tbl_prng_64;
Stephen Boyd94625ef2011-07-12 17:06:01 -07006551
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006552 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006553
Vikram Mulukutla681d8682012-03-09 23:56:20 -08006554 clk_ops_local_pll.enable = sr_pll_clk_enable;
Matt Wagantallb64888f2012-04-02 21:35:07 -07006555}
6556
Patrick Daly1a3859f2012-08-27 16:10:26 -07006557static void __init msm8930_pm8917_clock_pre_init(void)
6558{
6559 /* detect pmic8917 from board file, and call this init function */
6560
6561 vdd_dig.set_vdd = set_vdd_dig_8930;
6562 rpm_vreg_dig_8930 = RPM_VREG_ID_PM8917_VDD_DIG_CORNER;
6563 vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8930_pm8917;
6564
6565 msm8960_clock_pre_init();
6566}
6567
6568static void __init msm8930_clock_pre_init(void)
6569{
6570 vdd_dig.set_vdd = set_vdd_dig_8930;
6571 vdd_sr2_hdmi_pll.set_vdd = set_vdd_sr2_hdmi_pll_8930;
6572
6573 msm8960_clock_pre_init();
6574}
6575
Matt Wagantallb64888f2012-04-02 21:35:07 -07006576static void __init msm8960_clock_post_init(void)
6577{
6578 /* Keep PXO on whenever APPS cpu is active */
6579 clk_prepare_enable(&pxo_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006580
Matt Wagantalle655cd72012-04-09 10:15:03 -07006581 /* Reset 3D core while clocked to ensure it resets completely. */
6582 clk_set_rate(&gfx3d_clk.c, 27000000);
6583 clk_prepare_enable(&gfx3d_clk.c);
6584 clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT);
6585 udelay(5);
6586 clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT);
6587 clk_disable_unprepare(&gfx3d_clk.c);
6588
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006589 /* Initialize rates for clocks that only support one. */
6590 clk_set_rate(&pdm_clk.c, 27000000);
Stephen Boyd842a1f62012-04-26 19:07:38 -07006591 clk_set_rate(&prng_clk.c, prng_clk.freq_tbl->freq_hz);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006592 clk_set_rate(&mdp_vsync_clk.c, 27000000);
6593 clk_set_rate(&tsif_ref_clk.c, 105000);
6594 clk_set_rate(&tssc_clk.c, 27000000);
6595 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07006596 if (cpu_is_apq8064()) {
6597 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
6598 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
6599 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006600 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Patrick Dalye6f489042012-07-11 15:29:15 -07006601 if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_msm8930() ||
6602 cpu_is_msm8930aa() || cpu_is_msm8627())
Tianyi Gou41515e22011-09-01 19:37:43 -07006603 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07006604 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
6605 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
6606 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Lena Salman127823f2012-02-14 17:13:53 +02006607 clk_set_rate(&usb_hsic_system_clk.c, 60000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07006608 /*
6609 * Set the CSI rates to a safe default to avoid warnings when
6610 * switching csi pix and rdi clocks.
6611 */
6612 clk_set_rate(&csi0_src_clk.c, 27000000);
6613 clk_set_rate(&csi1_src_clk.c, 27000000);
6614 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006615
6616 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07006617 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006618 * Toggle these clocks on and off to refresh them.
6619 */
Stephen Boyd409b8b42012-04-10 12:12:56 -07006620 clk_prepare_enable(&pdm_clk.c);
6621 clk_disable_unprepare(&pdm_clk.c);
6622 clk_prepare_enable(&tssc_clk.c);
6623 clk_disable_unprepare(&tssc_clk.c);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006624 clk_prepare_enable(&usb_hsic_hsic_clk.c);
6625 clk_disable_unprepare(&usb_hsic_hsic_clk.c);
Stephen Boydd7a143a2012-02-16 17:59:26 -08006626
6627 /*
6628 * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all
6629 * times when Apps CPU is active. This ensures the timer's requirement
6630 * of Krait AHB running 4 times as fast as the timer itself.
6631 */
6632 clk_set_rate(&sfab_tmr_a_clk.c, 54000000);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006633 clk_prepare_enable(&sfab_tmr_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006634}
6635
Stephen Boydbb600ae2011-08-02 20:11:40 -07006636static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006637{
Stephen Boyda3787f32011-09-16 18:55:13 -07006638 int rc;
6639 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07006640 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07006641
6642 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
6643 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
6644 PTR_ERR(mmfpb_a_clk)))
6645 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006646 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07006647 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
6648 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006649 rc = clk_prepare_enable(mmfpb_a_clk);
Stephen Boyda3787f32011-09-16 18:55:13 -07006650 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
6651 return rc;
6652
Stephen Boyd85436132011-09-16 18:55:13 -07006653 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
6654 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
6655 PTR_ERR(cfpb_a_clk)))
6656 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006657 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07006658 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
6659 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006660 rc = clk_prepare_enable(cfpb_a_clk);
Stephen Boyd85436132011-09-16 18:55:13 -07006661 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
6662 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006663
6664 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006665}
Stephen Boydbb600ae2011-08-02 20:11:40 -07006666
6667struct clock_init_data msm8960_clock_init_data __initdata = {
6668 .table = msm_clocks_8960,
6669 .size = ARRAY_SIZE(msm_clocks_8960),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006670 .pre_init = msm8960_clock_pre_init,
6671 .post_init = msm8960_clock_post_init,
Stephen Boydbb600ae2011-08-02 20:11:40 -07006672 .late_init = msm8960_clock_late_init,
6673};
Tianyi Gou41515e22011-09-01 19:37:43 -07006674
6675struct clock_init_data apq8064_clock_init_data __initdata = {
6676 .table = msm_clocks_8064,
6677 .size = ARRAY_SIZE(msm_clocks_8064),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006678 .pre_init = msm8960_clock_pre_init,
6679 .post_init = msm8960_clock_post_init,
Tianyi Gou41515e22011-09-01 19:37:43 -07006680 .late_init = msm8960_clock_late_init,
6681};
Tianyi Goue3d4f542012-03-15 17:06:45 -07006682
6683struct clock_init_data msm8930_clock_init_data __initdata = {
6684 .table = msm_clocks_8930,
6685 .size = ARRAY_SIZE(msm_clocks_8930),
Patrick Daly1a3859f2012-08-27 16:10:26 -07006686 .pre_init = msm8930_clock_pre_init,
6687 .post_init = msm8960_clock_post_init,
6688 .late_init = msm8960_clock_late_init,
6689};
6690
6691struct clock_init_data msm8930_pm8917_clock_init_data __initdata = {
6692 .table = msm_clocks_8930,
6693 .size = ARRAY_SIZE(msm_clocks_8930),
6694 .pre_init = msm8930_pm8917_clock_pre_init,
Matt Wagantallb64888f2012-04-02 21:35:07 -07006695 .post_init = msm8960_clock_post_init,
Tianyi Goue3d4f542012-03-15 17:06:45 -07006696 .late_init = msm8960_clock_late_init,
6697};