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Alan Cox806c35f2006-01-18 17:44:08 -08001/*
2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e7xxx_chips" below for supported chipsets
8 *
9 * Written by Thayne Harbaugh
10 * Based on work by Dan Hollis <goemon at anime dot net> and others.
11 * http://www.anime.net/~goemon/linux-ecc/
12 *
13 * Contributors:
Dave Petersone7ecd892006-03-26 01:38:52 -080014 * Eric Biederman (Linux Networx)
15 * Tom Zimmerman (Linux Networx)
16 * Jim Garlick (Lawrence Livermore National Labs)
Alan Cox806c35f2006-01-18 17:44:08 -080017 * Dave Peterson (Lawrence Livermore National Labs)
18 * That One Guy (Some other place)
19 * Wang Zhenyu (intel.com)
20 *
21 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
22 *
23 */
24
Alan Cox806c35f2006-01-18 17:44:08 -080025#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/pci_ids.h>
Dave Jiangc0d12172007-07-19 01:49:46 -070029#include <linux/edac.h>
Douglas Thompson20bcb7a2007-07-19 01:49:47 -070030#include "edac_core.h"
Alan Cox806c35f2006-01-18 17:44:08 -080031
Michal Marek152ba392011-04-01 12:41:20 +020032#define E7XXX_REVISION " Ver: 2.0.2"
Doug Thompson929a40e2006-07-01 04:35:45 -070033#define EDAC_MOD_STR "e7xxx_edac"
Doug Thompson37f04582006-06-30 01:56:07 -070034
Dave Peterson537fba22006-03-26 01:38:40 -080035#define e7xxx_printk(level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080036 edac_printk(level, "e7xxx", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080037
38#define e7xxx_mc_printk(mci, level, fmt, arg...) \
Dave Petersone7ecd892006-03-26 01:38:52 -080039 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
Dave Peterson537fba22006-03-26 01:38:40 -080040
Alan Cox806c35f2006-01-18 17:44:08 -080041#ifndef PCI_DEVICE_ID_INTEL_7205_0
42#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
43#endif /* PCI_DEVICE_ID_INTEL_7205_0 */
44
45#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
46#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
47#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
48
49#ifndef PCI_DEVICE_ID_INTEL_7500_0
50#define PCI_DEVICE_ID_INTEL_7500_0 0x2540
51#endif /* PCI_DEVICE_ID_INTEL_7500_0 */
52
53#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
54#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
55#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
56
57#ifndef PCI_DEVICE_ID_INTEL_7501_0
58#define PCI_DEVICE_ID_INTEL_7501_0 0x254c
59#endif /* PCI_DEVICE_ID_INTEL_7501_0 */
60
61#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
62#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
63#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
64
65#ifndef PCI_DEVICE_ID_INTEL_7505_0
66#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
67#endif /* PCI_DEVICE_ID_INTEL_7505_0 */
68
69#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
70#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
71#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
72
Alan Cox806c35f2006-01-18 17:44:08 -080073#define E7XXX_NR_CSROWS 8 /* number of csrows */
74#define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */
75
Alan Cox806c35f2006-01-18 17:44:08 -080076/* E7XXX register addresses - device 0 function 0 */
77#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
78#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
79 /*
80 * 31 Device width row 7 0=x8 1=x4
81 * 27 Device width row 6
82 * 23 Device width row 5
83 * 19 Device width row 4
84 * 15 Device width row 3
85 * 11 Device width row 2
86 * 7 Device width row 1
87 * 3 Device width row 0
88 */
89#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
90 /*
91 * 22 Number channels 0=1,1=2
92 * 19:18 DRB Granularity 32/64MB
93 */
94#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
95#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
96#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
97
98/* E7XXX register addresses - device 0 function 1 */
99#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
100#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
101#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
102 /* error address register (32b) */
103 /*
104 * 31:28 Reserved
105 * 27:6 CE address (4k block 33:12)
106 * 5:0 Reserved
107 */
108#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
109 /* error address register (32b) */
110 /*
111 * 31:28 Reserved
112 * 27:6 CE address (4k block 33:12)
113 * 5:0 Reserved
114 */
115#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
116 /* error syndrome register (16b) */
117
118enum e7xxx_chips {
119 E7500 = 0,
120 E7501,
121 E7505,
122 E7205,
123};
124
Alan Cox806c35f2006-01-18 17:44:08 -0800125struct e7xxx_pvt {
126 struct pci_dev *bridge_ck;
127 u32 tolm;
128 u32 remapbase;
129 u32 remaplimit;
130 const struct e7xxx_dev_info *dev_info;
131};
132
Alan Cox806c35f2006-01-18 17:44:08 -0800133struct e7xxx_dev_info {
134 u16 err_dev;
135 const char *ctl_name;
136};
137
Alan Cox806c35f2006-01-18 17:44:08 -0800138struct e7xxx_error_info {
139 u8 dram_ferr;
140 u8 dram_nerr;
141 u32 dram_celog_add;
142 u16 dram_celog_syndrome;
143 u32 dram_uelog_add;
144};
145
Dave Jiang456a2f92007-07-19 01:50:10 -0700146static struct edac_pci_ctl_info *e7xxx_pci;
147
Alan Cox806c35f2006-01-18 17:44:08 -0800148static const struct e7xxx_dev_info e7xxx_devs[] = {
149 [E7500] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700150 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
151 .ctl_name = "E7500"},
Alan Cox806c35f2006-01-18 17:44:08 -0800152 [E7501] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700153 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
154 .ctl_name = "E7501"},
Alan Cox806c35f2006-01-18 17:44:08 -0800155 [E7505] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700156 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
157 .ctl_name = "E7505"},
Alan Cox806c35f2006-01-18 17:44:08 -0800158 [E7205] = {
Douglas Thompson052dfb42007-07-19 01:50:13 -0700159 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
160 .ctl_name = "E7205"},
Alan Cox806c35f2006-01-18 17:44:08 -0800161};
162
Alan Cox806c35f2006-01-18 17:44:08 -0800163/* FIXME - is this valid for both SECDED and S4ECD4ED? */
164static inline int e7xxx_find_channel(u16 syndrome)
165{
Dave Peterson537fba22006-03-26 01:38:40 -0800166 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800167
168 if ((syndrome & 0xff00) == 0)
169 return 0;
Dave Petersone7ecd892006-03-26 01:38:52 -0800170
Alan Cox806c35f2006-01-18 17:44:08 -0800171 if ((syndrome & 0x00ff) == 0)
172 return 1;
Dave Petersone7ecd892006-03-26 01:38:52 -0800173
Alan Cox806c35f2006-01-18 17:44:08 -0800174 if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
175 return 0;
Dave Petersone7ecd892006-03-26 01:38:52 -0800176
Alan Cox806c35f2006-01-18 17:44:08 -0800177 return 1;
178}
179
Dave Petersone7ecd892006-03-26 01:38:52 -0800180static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700181 unsigned long page)
Alan Cox806c35f2006-01-18 17:44:08 -0800182{
183 u32 remap;
Dave Jiang849a4c32007-07-19 01:50:03 -0700184 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
Alan Cox806c35f2006-01-18 17:44:08 -0800185
Dave Peterson537fba22006-03-26 01:38:40 -0800186 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800187
188 if ((page < pvt->tolm) ||
Douglas Thompson052dfb42007-07-19 01:50:13 -0700189 ((page >= 0x100000) && (page < pvt->remapbase)))
Alan Cox806c35f2006-01-18 17:44:08 -0800190 return page;
Dave Petersone7ecd892006-03-26 01:38:52 -0800191
Alan Cox806c35f2006-01-18 17:44:08 -0800192 remap = (page - pvt->tolm) + pvt->remapbase;
Dave Petersone7ecd892006-03-26 01:38:52 -0800193
Alan Cox806c35f2006-01-18 17:44:08 -0800194 if (remap < pvt->remaplimit)
195 return remap;
Dave Petersone7ecd892006-03-26 01:38:52 -0800196
Dave Peterson537fba22006-03-26 01:38:40 -0800197 e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
Alan Cox806c35f2006-01-18 17:44:08 -0800198 return pvt->tolm - 1;
199}
200
Dave Jiang849a4c32007-07-19 01:50:03 -0700201static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800202{
203 u32 error_1b, page;
204 u16 syndrome;
205 int row;
206 int channel;
207
Dave Peterson537fba22006-03-26 01:38:40 -0800208 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800209 /* read the error address */
210 error_1b = info->dram_celog_add;
211 /* FIXME - should use PAGE_SHIFT */
Dave Jiang849a4c32007-07-19 01:50:03 -0700212 page = error_1b >> 6; /* convert the address to 4k page */
Alan Cox806c35f2006-01-18 17:44:08 -0800213 /* read the syndrome */
214 syndrome = info->dram_celog_syndrome;
215 /* FIXME - check for -1 */
216 row = edac_mc_find_csrow_by_page(mci, page);
217 /* convert syndrome to channel */
218 channel = e7xxx_find_channel(syndrome);
Dave Petersone7ecd892006-03-26 01:38:52 -0800219 edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
Alan Cox806c35f2006-01-18 17:44:08 -0800220}
221
Alan Cox806c35f2006-01-18 17:44:08 -0800222static void process_ce_no_info(struct mem_ctl_info *mci)
223{
Dave Peterson537fba22006-03-26 01:38:40 -0800224 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800225 edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
226}
227
Dave Jiang849a4c32007-07-19 01:50:03 -0700228static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800229{
230 u32 error_2b, block_page;
231 int row;
232
Dave Peterson537fba22006-03-26 01:38:40 -0800233 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800234 /* read the error address */
235 error_2b = info->dram_uelog_add;
236 /* FIXME - should use PAGE_SHIFT */
Dave Jiang849a4c32007-07-19 01:50:03 -0700237 block_page = error_2b >> 6; /* convert to 4k address */
Alan Cox806c35f2006-01-18 17:44:08 -0800238 row = edac_mc_find_csrow_by_page(mci, block_page);
239 edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
240}
241
Alan Cox806c35f2006-01-18 17:44:08 -0800242static void process_ue_no_info(struct mem_ctl_info *mci)
243{
Dave Peterson537fba22006-03-26 01:38:40 -0800244 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800245 edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
246}
247
Dave Jiang849a4c32007-07-19 01:50:03 -0700248static void e7xxx_get_error_info(struct mem_ctl_info *mci,
249 struct e7xxx_error_info *info)
Alan Cox806c35f2006-01-18 17:44:08 -0800250{
251 struct e7xxx_pvt *pvt;
252
Dave Jiang849a4c32007-07-19 01:50:03 -0700253 pvt = (struct e7xxx_pvt *)mci->pvt_info;
254 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
255 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
Alan Cox806c35f2006-01-18 17:44:08 -0800256
257 if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
258 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700259 &info->dram_celog_add);
Alan Cox806c35f2006-01-18 17:44:08 -0800260 pci_read_config_word(pvt->bridge_ck,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700261 E7XXX_DRAM_CELOG_SYNDROME,
262 &info->dram_celog_syndrome);
Alan Cox806c35f2006-01-18 17:44:08 -0800263 }
264
265 if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
266 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700267 &info->dram_uelog_add);
Alan Cox806c35f2006-01-18 17:44:08 -0800268
269 if (info->dram_ferr & 3)
Dave Petersone7ecd892006-03-26 01:38:52 -0800270 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
Alan Cox806c35f2006-01-18 17:44:08 -0800271
272 if (info->dram_nerr & 3)
Dave Petersone7ecd892006-03-26 01:38:52 -0800273 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
Alan Cox806c35f2006-01-18 17:44:08 -0800274}
275
Dave Jiang849a4c32007-07-19 01:50:03 -0700276static int e7xxx_process_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700277 struct e7xxx_error_info *info,
278 int handle_errors)
Alan Cox806c35f2006-01-18 17:44:08 -0800279{
280 int error_found;
281
282 error_found = 0;
283
284 /* decode and report errors */
285 if (info->dram_ferr & 1) { /* check first error correctable */
286 error_found = 1;
287
288 if (handle_errors)
289 process_ce(mci, info);
290 }
291
292 if (info->dram_ferr & 2) { /* check first error uncorrectable */
293 error_found = 1;
294
295 if (handle_errors)
296 process_ue(mci, info);
297 }
298
299 if (info->dram_nerr & 1) { /* check next error correctable */
300 error_found = 1;
301
302 if (handle_errors) {
303 if (info->dram_ferr & 1)
304 process_ce_no_info(mci);
305 else
306 process_ce(mci, info);
307 }
308 }
309
310 if (info->dram_nerr & 2) { /* check next error uncorrectable */
311 error_found = 1;
312
313 if (handle_errors) {
314 if (info->dram_ferr & 2)
315 process_ue_no_info(mci);
316 else
317 process_ue(mci, info);
318 }
319 }
320
321 return error_found;
322}
323
Alan Cox806c35f2006-01-18 17:44:08 -0800324static void e7xxx_check(struct mem_ctl_info *mci)
325{
326 struct e7xxx_error_info info;
327
Dave Peterson537fba22006-03-26 01:38:40 -0800328 debugf3("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800329 e7xxx_get_error_info(mci, &info);
330 e7xxx_process_error_info(mci, &info, 1);
331}
332
Doug Thompson13189522006-06-30 01:56:08 -0700333/* Return 1 if dual channel mode is active. Else return 0. */
334static inline int dual_channel_active(u32 drc, int dev_idx)
Alan Cox806c35f2006-01-18 17:44:08 -0800335{
Doug Thompson13189522006-06-30 01:56:08 -0700336 return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
337}
Alan Cox806c35f2006-01-18 17:44:08 -0800338
Doug Thompson13189522006-06-30 01:56:08 -0700339/* Return DRB granularity (0=32mb, 1=64mb). */
340static inline int drb_granularity(u32 drc, int dev_idx)
341{
Alan Cox806c35f2006-01-18 17:44:08 -0800342 /* only e7501 can be single channel */
Doug Thompson13189522006-06-30 01:56:08 -0700343 return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
344}
Alan Cox806c35f2006-01-18 17:44:08 -0800345
Doug Thompson13189522006-06-30 01:56:08 -0700346static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700347 int dev_idx, u32 drc)
Doug Thompson13189522006-06-30 01:56:08 -0700348{
349 unsigned long last_cumul_size;
350 int index;
351 u8 value;
352 u32 dra, cumul_size;
353 int drc_chan, drc_drbg, drc_ddim, mem_dev;
354 struct csrow_info *csrow;
Alan Cox806c35f2006-01-18 17:44:08 -0800355
Alan Cox806c35f2006-01-18 17:44:08 -0800356 pci_read_config_dword(pdev, E7XXX_DRA, &dra);
Doug Thompson13189522006-06-30 01:56:08 -0700357 drc_chan = dual_channel_active(drc, dev_idx);
358 drc_drbg = drb_granularity(drc, dev_idx);
359 drc_ddim = (drc >> 20) & 0x3;
360 last_cumul_size = 0;
Alan Cox806c35f2006-01-18 17:44:08 -0800361
Doug Thompson13189522006-06-30 01:56:08 -0700362 /* The dram row boundary (DRB) reg values are boundary address
Alan Cox806c35f2006-01-18 17:44:08 -0800363 * for each DRAM row with a granularity of 32 or 64MB (single/dual
364 * channel operation). DRB regs are cumulative; therefore DRB7 will
365 * contain the total memory contained in all eight rows.
366 */
Doug Thompson13189522006-06-30 01:56:08 -0700367 for (index = 0; index < mci->nr_csrows; index++) {
Alan Cox806c35f2006-01-18 17:44:08 -0800368 /* mem_dev 0=x8, 1=x4 */
Doug Thompson13189522006-06-30 01:56:08 -0700369 mem_dev = (dra >> (index * 4 + 3)) & 0x1;
370 csrow = &mci->csrows[index];
Alan Cox806c35f2006-01-18 17:44:08 -0800371
Doug Thompson37f04582006-06-30 01:56:07 -0700372 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
Alan Cox806c35f2006-01-18 17:44:08 -0800373 /* convert a 64 or 32 MiB DRB to a page size. */
374 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
Dave Peterson537fba22006-03-26 01:38:40 -0800375 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
376 cumul_size);
Alan Cox806c35f2006-01-18 17:44:08 -0800377 if (cumul_size == last_cumul_size)
Doug Thompson13189522006-06-30 01:56:08 -0700378 continue; /* not populated */
Alan Cox806c35f2006-01-18 17:44:08 -0800379
380 csrow->first_page = last_cumul_size;
381 csrow->last_page = cumul_size - 1;
382 csrow->nr_pages = cumul_size - last_cumul_size;
383 last_cumul_size = cumul_size;
Doug Thompson13189522006-06-30 01:56:08 -0700384 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
385 csrow->mtype = MEM_RDDR; /* only one type supported */
Alan Cox806c35f2006-01-18 17:44:08 -0800386 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
387
388 /*
389 * if single channel or x8 devices then SECDED
390 * if dual channel and x4 then S4ECD4ED
391 */
392 if (drc_ddim) {
393 if (drc_chan && mem_dev) {
394 csrow->edac_mode = EDAC_S4ECD4ED;
395 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
396 } else {
397 csrow->edac_mode = EDAC_SECDED;
398 mci->edac_cap |= EDAC_FLAG_SECDED;
399 }
400 } else
401 csrow->edac_mode = EDAC_NONE;
402 }
Doug Thompson13189522006-06-30 01:56:08 -0700403}
Alan Cox806c35f2006-01-18 17:44:08 -0800404
Doug Thompson13189522006-06-30 01:56:08 -0700405static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
406{
407 u16 pci_data;
408 struct mem_ctl_info *mci = NULL;
409 struct e7xxx_pvt *pvt = NULL;
410 u32 drc;
411 int drc_chan;
412 struct e7xxx_error_info discard;
413
414 debugf0("%s(): mci\n", __func__);
Dave Jiangc0d12172007-07-19 01:49:46 -0700415
Doug Thompson13189522006-06-30 01:56:08 -0700416 pci_read_config_dword(pdev, E7XXX_DRC, &drc);
417
418 drc_chan = dual_channel_active(drc, dev_idx);
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700419 mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1, 0);
Doug Thompson13189522006-06-30 01:56:08 -0700420
421 if (mci == NULL)
422 return -ENOMEM;
423
424 debugf3("%s(): init mci\n", __func__);
425 mci->mtype_cap = MEM_FLAG_RDDR;
426 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
Douglas Thompson052dfb42007-07-19 01:50:13 -0700427 EDAC_FLAG_S4ECD4ED;
Doug Thompson13189522006-06-30 01:56:08 -0700428 /* FIXME - what if different memory types are in different csrows? */
429 mci->mod_name = EDAC_MOD_STR;
430 mci->mod_ver = E7XXX_REVISION;
431 mci->dev = &pdev->dev;
432 debugf3("%s(): init pvt\n", __func__);
Dave Jiang849a4c32007-07-19 01:50:03 -0700433 pvt = (struct e7xxx_pvt *)mci->pvt_info;
Doug Thompson13189522006-06-30 01:56:08 -0700434 pvt->dev_info = &e7xxx_devs[dev_idx];
435 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
Dave Jiang849a4c32007-07-19 01:50:03 -0700436 pvt->dev_info->err_dev, pvt->bridge_ck);
Doug Thompson13189522006-06-30 01:56:08 -0700437
438 if (!pvt->bridge_ck) {
439 e7xxx_printk(KERN_ERR, "error reporting device not found:"
Douglas Thompson052dfb42007-07-19 01:50:13 -0700440 "vendor %x device 0x%x (broken BIOS?)\n",
441 PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
Doug Thompson13189522006-06-30 01:56:08 -0700442 goto fail0;
443 }
444
445 debugf3("%s(): more mci init\n", __func__);
446 mci->ctl_name = pvt->dev_info->ctl_name;
Dave Jiangc4192702007-07-19 01:49:47 -0700447 mci->dev_name = pci_name(pdev);
Doug Thompson13189522006-06-30 01:56:08 -0700448 mci->edac_check = e7xxx_check;
449 mci->ctl_page_to_phys = ctl_page_to_phys;
450 e7xxx_init_csrows(mci, pdev, dev_idx, drc);
Alan Cox806c35f2006-01-18 17:44:08 -0800451 mci->edac_cap |= EDAC_FLAG_NONE;
Dave Peterson537fba22006-03-26 01:38:40 -0800452 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800453 /* load the top of low memory, remap base, and remap limit vars */
Doug Thompson37f04582006-06-30 01:56:07 -0700454 pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800455 pvt->tolm = ((u32) pci_data) << 4;
Doug Thompson37f04582006-06-30 01:56:07 -0700456 pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800457 pvt->remapbase = ((u32) pci_data) << 14;
Doug Thompson37f04582006-06-30 01:56:07 -0700458 pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800459 pvt->remaplimit = ((u32) pci_data) << 14;
Dave Peterson537fba22006-03-26 01:38:40 -0800460 e7xxx_printk(KERN_INFO,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700461 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
462 pvt->remapbase, pvt->remaplimit);
Alan Cox806c35f2006-01-18 17:44:08 -0800463
464 /* clear any pending errors, or initial state bits */
Dave Peterson749ede52006-03-26 01:38:45 -0800465 e7xxx_get_error_info(mci, &discard);
Alan Cox806c35f2006-01-18 17:44:08 -0800466
Doug Thompson2d7bbb92006-06-30 01:56:08 -0700467 /* Here we assume that we will never see multiple instances of this
468 * type of memory controller. The ID is therefore hardcoded to 0.
469 */
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700470 if (edac_mc_add_mc(mci)) {
Dave Peterson537fba22006-03-26 01:38:40 -0800471 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
Doug Thompson13189522006-06-30 01:56:08 -0700472 goto fail1;
Alan Cox806c35f2006-01-18 17:44:08 -0800473 }
474
Dave Jiang456a2f92007-07-19 01:50:10 -0700475 /* allocating generic PCI control info */
476 e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
477 if (!e7xxx_pci) {
478 printk(KERN_WARNING
479 "%s(): Unable to create PCI control\n",
480 __func__);
481 printk(KERN_WARNING
482 "%s(): PCI error report via EDAC not setup\n",
483 __func__);
484 }
485
Alan Cox806c35f2006-01-18 17:44:08 -0800486 /* get this far and it's successful */
Dave Peterson537fba22006-03-26 01:38:40 -0800487 debugf3("%s(): success\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800488 return 0;
489
Douglas Thompson052dfb42007-07-19 01:50:13 -0700490fail1:
Doug Thompson13189522006-06-30 01:56:08 -0700491 pci_dev_put(pvt->bridge_ck);
Alan Cox806c35f2006-01-18 17:44:08 -0800492
Douglas Thompson052dfb42007-07-19 01:50:13 -0700493fail0:
Doug Thompson13189522006-06-30 01:56:08 -0700494 edac_mc_free(mci);
495
496 return -ENODEV;
Alan Cox806c35f2006-01-18 17:44:08 -0800497}
498
499/* returns count (>= 0), or negative on error */
Dave Petersone7ecd892006-03-26 01:38:52 -0800500static int __devinit e7xxx_init_one(struct pci_dev *pdev,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700501 const struct pci_device_id *ent)
Alan Cox806c35f2006-01-18 17:44:08 -0800502{
Dave Peterson537fba22006-03-26 01:38:40 -0800503 debugf0("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800504
505 /* wake up and enable device */
506 return pci_enable_device(pdev) ?
Douglas Thompson052dfb42007-07-19 01:50:13 -0700507 -EIO : e7xxx_probe1(pdev, ent->driver_data);
Alan Cox806c35f2006-01-18 17:44:08 -0800508}
509
Alan Cox806c35f2006-01-18 17:44:08 -0800510static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
511{
512 struct mem_ctl_info *mci;
513 struct e7xxx_pvt *pvt;
514
Dave Peterson537fba22006-03-26 01:38:40 -0800515 debugf0("%s()\n", __func__);
Alan Cox806c35f2006-01-18 17:44:08 -0800516
Dave Jiang456a2f92007-07-19 01:50:10 -0700517 if (e7xxx_pci)
518 edac_pci_release_generic_ctl(e7xxx_pci);
519
Doug Thompson37f04582006-06-30 01:56:07 -0700520 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
Dave Peterson18dbc332006-03-26 01:38:50 -0800521 return;
522
Dave Jiang849a4c32007-07-19 01:50:03 -0700523 pvt = (struct e7xxx_pvt *)mci->pvt_info;
Dave Peterson18dbc332006-03-26 01:38:50 -0800524 pci_dev_put(pvt->bridge_ck);
525 edac_mc_free(mci);
Alan Cox806c35f2006-01-18 17:44:08 -0800526}
527
Alan Cox806c35f2006-01-18 17:44:08 -0800528static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
Dave Petersone7ecd892006-03-26 01:38:52 -0800529 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700530 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
531 E7205},
Dave Petersone7ecd892006-03-26 01:38:52 -0800532 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700533 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
534 E7500},
Dave Petersone7ecd892006-03-26 01:38:52 -0800535 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700536 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
537 E7501},
Dave Petersone7ecd892006-03-26 01:38:52 -0800538 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700539 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
540 E7505},
Dave Petersone7ecd892006-03-26 01:38:52 -0800541 {
Dave Jiang849a4c32007-07-19 01:50:03 -0700542 0,
543 } /* 0 terminated list. */
Alan Cox806c35f2006-01-18 17:44:08 -0800544};
545
546MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
547
Alan Cox806c35f2006-01-18 17:44:08 -0800548static struct pci_driver e7xxx_driver = {
Dave Peterson680cbbb2006-03-26 01:38:41 -0800549 .name = EDAC_MOD_STR,
Alan Cox806c35f2006-01-18 17:44:08 -0800550 .probe = e7xxx_init_one,
551 .remove = __devexit_p(e7xxx_remove_one),
552 .id_table = e7xxx_pci_tbl,
553};
554
Alan Coxda9bb1d2006-01-18 17:44:13 -0800555static int __init e7xxx_init(void)
Alan Cox806c35f2006-01-18 17:44:08 -0800556{
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700557 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
558 opstate_init();
559
Alan Cox806c35f2006-01-18 17:44:08 -0800560 return pci_register_driver(&e7xxx_driver);
561}
562
Alan Cox806c35f2006-01-18 17:44:08 -0800563static void __exit e7xxx_exit(void)
564{
565 pci_unregister_driver(&e7xxx_driver);
566}
567
568module_init(e7xxx_init);
569module_exit(e7xxx_exit);
570
Alan Cox806c35f2006-01-18 17:44:08 -0800571MODULE_LICENSE("GPL");
572MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
Douglas Thompson052dfb42007-07-19 01:50:13 -0700573 "Based on.work by Dan Hollis et al");
Alan Cox806c35f2006-01-18 17:44:08 -0800574MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
Dave Jiangc0d12172007-07-19 01:49:46 -0700575module_param(edac_op_state, int, 0444);
576MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");