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Steve Glendinningfd9abb32008-11-05 00:35:37 +00001/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************/
21#ifndef __SMSC911X_H__
22#define __SMSC911X_H__
23
Steve Glendinningfd9abb32008-11-05 00:35:37 +000024#define TX_FIFO_LOW_THRESHOLD ((u32)1600)
John Faith6cc0e942010-11-01 11:30:08 +000025#define SMSC911X_EEPROM_SIZE ((u32)128)
Steve Glendinningfd9abb32008-11-05 00:35:37 +000026#define USE_DEBUG 0
27
28/* This is the maximum number of packets to be received every
29 * NAPI poll */
30#define SMSC_NAPI_WEIGHT 16
31
32/* implements a PHY loopback test at initialisation time, to ensure a packet
André Goddard Rosaaf901ca2009-11-14 13:09:05 -020033 * can be successfully looped back */
Steve Glendinningfd9abb32008-11-05 00:35:37 +000034#define USE_PHY_WORK_AROUND
35
Steve Glendinningfd9abb32008-11-05 00:35:37 +000036#if USE_DEBUG >= 1
Joe Perchesdffc6b22011-03-25 14:21:22 +000037#define SMSC_WARN(pdata, nlevel, fmt, args...) \
38 netif_warn(pdata, nlevel, (pdata)->dev, \
39 "%s: " fmt "\n", __func__, ##args)
Steve Glendinningfd9abb32008-11-05 00:35:37 +000040#else
Joe Perchesdffc6b22011-03-25 14:21:22 +000041#define SMSC_WARN(pdata, nlevel, fmt, args...) \
42 no_printk(fmt "\n", ##args)
Steve Glendinningfd9abb32008-11-05 00:35:37 +000043#endif
44
45#if USE_DEBUG >= 2
Joe Perchesdffc6b22011-03-25 14:21:22 +000046#define SMSC_TRACE(pdata, nlevel, fmt, args...) \
47 netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)
Steve Glendinningfd9abb32008-11-05 00:35:37 +000048#else
Joe Perchesdffc6b22011-03-25 14:21:22 +000049#define SMSC_TRACE(pdata, nlevel, fmt, args...) \
50 no_printk(fmt "\n", ##args)
Steve Glendinningfd9abb32008-11-05 00:35:37 +000051#endif
52
53#ifdef CONFIG_DEBUG_SPINLOCK
54#define SMSC_ASSERT_MAC_LOCK(pdata) \
55 WARN_ON(!spin_is_locked(&pdata->mac_lock))
56#else
57#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
58#endif /* CONFIG_DEBUG_SPINLOCK */
59
Steve Glendinningfd9abb32008-11-05 00:35:37 +000060/* SMSC911x registers and bitfields */
61#define RX_DATA_FIFO 0x00
62
63#define TX_DATA_FIFO 0x20
64#define TX_CMD_A_ON_COMP_ 0x80000000
65#define TX_CMD_A_BUF_END_ALGN_ 0x03000000
66#define TX_CMD_A_4_BYTE_ALGN_ 0x00000000
67#define TX_CMD_A_16_BYTE_ALGN_ 0x01000000
68#define TX_CMD_A_32_BYTE_ALGN_ 0x02000000
69#define TX_CMD_A_DATA_OFFSET_ 0x001F0000
70#define TX_CMD_A_FIRST_SEG_ 0x00002000
71#define TX_CMD_A_LAST_SEG_ 0x00001000
72#define TX_CMD_A_BUF_SIZE_ 0x000007FF
73#define TX_CMD_B_PKT_TAG_ 0xFFFF0000
74#define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000
75#define TX_CMD_B_DISABLE_PADDING_ 0x00001000
76#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF
77
78#define RX_STATUS_FIFO 0x40
79#define RX_STS_ES_ 0x00008000
Steve Glendinning785b6f92009-03-19 00:24:44 +000080#define RX_STS_LENGTH_ERR_ 0x00001000
Steve Glendinningfd9abb32008-11-05 00:35:37 +000081#define RX_STS_MCAST_ 0x00000400
Steve Glendinning785b6f92009-03-19 00:24:44 +000082#define RX_STS_FRAME_TYPE_ 0x00000020
83#define RX_STS_CRC_ERR_ 0x00000002
Steve Glendinningfd9abb32008-11-05 00:35:37 +000084
85#define RX_STATUS_FIFO_PEEK 0x44
86
87#define TX_STATUS_FIFO 0x48
88#define TX_STS_ES_ 0x00008000
Steve Glendinning785b6f92009-03-19 00:24:44 +000089#define TX_STS_LOST_CARRIER_ 0x00000800
90#define TX_STS_NO_CARRIER_ 0x00000400
91#define TX_STS_LATE_COL_ 0x00000200
92#define TX_STS_EXCESS_COL_ 0x00000100
Steve Glendinningfd9abb32008-11-05 00:35:37 +000093
94#define TX_STATUS_FIFO_PEEK 0x4C
95
96#define ID_REV 0x50
97#define ID_REV_CHIP_ID_ 0xFFFF0000
98#define ID_REV_REV_ID_ 0x0000FFFF
99
100#define INT_CFG 0x54
101#define INT_CFG_INT_DEAS_ 0xFF000000
102#define INT_CFG_INT_DEAS_CLR_ 0x00004000
103#define INT_CFG_INT_DEAS_STS_ 0x00002000
104#define INT_CFG_IRQ_INT_ 0x00001000
105#define INT_CFG_IRQ_EN_ 0x00000100
106#define INT_CFG_IRQ_POL_ 0x00000010
107#define INT_CFG_IRQ_TYPE_ 0x00000001
108
109#define INT_STS 0x58
110#define INT_STS_SW_INT_ 0x80000000
111#define INT_STS_TXSTOP_INT_ 0x02000000
112#define INT_STS_RXSTOP_INT_ 0x01000000
113#define INT_STS_RXDFH_INT_ 0x00800000
114#define INT_STS_RXDF_INT_ 0x00400000
115#define INT_STS_TX_IOC_ 0x00200000
116#define INT_STS_RXD_INT_ 0x00100000
117#define INT_STS_GPT_INT_ 0x00080000
118#define INT_STS_PHY_INT_ 0x00040000
119#define INT_STS_PME_INT_ 0x00020000
120#define INT_STS_TXSO_ 0x00010000
121#define INT_STS_RWT_ 0x00008000
122#define INT_STS_RXE_ 0x00004000
123#define INT_STS_TXE_ 0x00002000
124#define INT_STS_TDFU_ 0x00000800
125#define INT_STS_TDFO_ 0x00000400
126#define INT_STS_TDFA_ 0x00000200
127#define INT_STS_TSFF_ 0x00000100
128#define INT_STS_TSFL_ 0x00000080
129#define INT_STS_RXDF_ 0x00000040
130#define INT_STS_RDFL_ 0x00000020
131#define INT_STS_RSFF_ 0x00000010
132#define INT_STS_RSFL_ 0x00000008
133#define INT_STS_GPIO2_INT_ 0x00000004
134#define INT_STS_GPIO1_INT_ 0x00000002
135#define INT_STS_GPIO0_INT_ 0x00000001
136
137#define INT_EN 0x5C
138#define INT_EN_SW_INT_EN_ 0x80000000
139#define INT_EN_TXSTOP_INT_EN_ 0x02000000
140#define INT_EN_RXSTOP_INT_EN_ 0x01000000
141#define INT_EN_RXDFH_INT_EN_ 0x00800000
142#define INT_EN_TIOC_INT_EN_ 0x00200000
143#define INT_EN_RXD_INT_EN_ 0x00100000
144#define INT_EN_GPT_INT_EN_ 0x00080000
145#define INT_EN_PHY_INT_EN_ 0x00040000
146#define INT_EN_PME_INT_EN_ 0x00020000
147#define INT_EN_TXSO_EN_ 0x00010000
148#define INT_EN_RWT_EN_ 0x00008000
149#define INT_EN_RXE_EN_ 0x00004000
150#define INT_EN_TXE_EN_ 0x00002000
151#define INT_EN_TDFU_EN_ 0x00000800
152#define INT_EN_TDFO_EN_ 0x00000400
153#define INT_EN_TDFA_EN_ 0x00000200
154#define INT_EN_TSFF_EN_ 0x00000100
155#define INT_EN_TSFL_EN_ 0x00000080
156#define INT_EN_RXDF_EN_ 0x00000040
157#define INT_EN_RDFL_EN_ 0x00000020
158#define INT_EN_RSFF_EN_ 0x00000010
159#define INT_EN_RSFL_EN_ 0x00000008
160#define INT_EN_GPIO2_INT_ 0x00000004
161#define INT_EN_GPIO1_INT_ 0x00000002
162#define INT_EN_GPIO0_INT_ 0x00000001
163
164#define BYTE_TEST 0x64
165
166#define FIFO_INT 0x68
167#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000
168#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000
169#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00
170#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF
171
172#define RX_CFG 0x6C
173#define RX_CFG_RX_END_ALGN_ 0xC0000000
174#define RX_CFG_RX_END_ALGN4_ 0x00000000
175#define RX_CFG_RX_END_ALGN16_ 0x40000000
176#define RX_CFG_RX_END_ALGN32_ 0x80000000
177#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000
178#define RX_CFG_RX_DUMP_ 0x00008000
179#define RX_CFG_RXDOFF_ 0x00001F00
180
181#define TX_CFG 0x70
182#define TX_CFG_TXS_DUMP_ 0x00008000
183#define TX_CFG_TXD_DUMP_ 0x00004000
184#define TX_CFG_TXSAO_ 0x00000004
185#define TX_CFG_TX_ON_ 0x00000002
186#define TX_CFG_STOP_TX_ 0x00000001
187
188#define HW_CFG 0x74
189#define HW_CFG_TTM_ 0x00200000
190#define HW_CFG_SF_ 0x00100000
191#define HW_CFG_TX_FIF_SZ_ 0x000F0000
192#define HW_CFG_TR_ 0x00003000
193#define HW_CFG_SRST_ 0x00000001
194
195/* only available on 115/117 */
196#define HW_CFG_PHY_CLK_SEL_ 0x00000060
197#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000
198#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020
199#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040
200#define HW_CFG_SMI_SEL_ 0x00000010
201#define HW_CFG_EXT_PHY_DET_ 0x00000008
202#define HW_CFG_EXT_PHY_EN_ 0x00000004
203#define HW_CFG_SRST_TO_ 0x00000002
204
205/* only available on 116/118 */
206#define HW_CFG_32_16_BIT_MODE_ 0x00000004
207
208#define RX_DP_CTRL 0x78
209#define RX_DP_CTRL_RX_FFWD_ 0x80000000
210
211#define RX_FIFO_INF 0x7C
212#define RX_FIFO_INF_RXSUSED_ 0x00FF0000
213#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF
214
215#define TX_FIFO_INF 0x80
216#define TX_FIFO_INF_TSUSED_ 0x00FF0000
217#define TX_FIFO_INF_TDFREE_ 0x0000FFFF
218
219#define PMT_CTRL 0x84
220#define PMT_CTRL_PM_MODE_ 0x00003000
221#define PMT_CTRL_PM_MODE_D0_ 0x00000000
222#define PMT_CTRL_PM_MODE_D1_ 0x00001000
223#define PMT_CTRL_PM_MODE_D2_ 0x00002000
224#define PMT_CTRL_PM_MODE_D3_ 0x00003000
225#define PMT_CTRL_PHY_RST_ 0x00000400
226#define PMT_CTRL_WOL_EN_ 0x00000200
227#define PMT_CTRL_ED_EN_ 0x00000100
228#define PMT_CTRL_PME_TYPE_ 0x00000040
229#define PMT_CTRL_WUPS_ 0x00000030
230#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000
231#define PMT_CTRL_WUPS_ED_ 0x00000010
232#define PMT_CTRL_WUPS_WOL_ 0x00000020
233#define PMT_CTRL_WUPS_MULTI_ 0x00000030
234#define PMT_CTRL_PME_IND_ 0x00000008
235#define PMT_CTRL_PME_POL_ 0x00000004
236#define PMT_CTRL_PME_EN_ 0x00000002
237#define PMT_CTRL_READY_ 0x00000001
238
239#define GPIO_CFG 0x88
240#define GPIO_CFG_LED3_EN_ 0x40000000
241#define GPIO_CFG_LED2_EN_ 0x20000000
242#define GPIO_CFG_LED1_EN_ 0x10000000
243#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000
244#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000
245#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000
246#define GPIO_CFG_EEPR_EN_ 0x00700000
247#define GPIO_CFG_GPIOBUF2_ 0x00040000
248#define GPIO_CFG_GPIOBUF1_ 0x00020000
249#define GPIO_CFG_GPIOBUF0_ 0x00010000
250#define GPIO_CFG_GPIODIR2_ 0x00000400
251#define GPIO_CFG_GPIODIR1_ 0x00000200
252#define GPIO_CFG_GPIODIR0_ 0x00000100
253#define GPIO_CFG_GPIOD4_ 0x00000020
254#define GPIO_CFG_GPIOD3_ 0x00000010
255#define GPIO_CFG_GPIOD2_ 0x00000004
256#define GPIO_CFG_GPIOD1_ 0x00000002
257#define GPIO_CFG_GPIOD0_ 0x00000001
258
259#define GPT_CFG 0x8C
260#define GPT_CFG_TIMER_EN_ 0x20000000
261#define GPT_CFG_GPT_LOAD_ 0x0000FFFF
262
263#define GPT_CNT 0x90
264#define GPT_CNT_GPT_CNT_ 0x0000FFFF
265
266#define WORD_SWAP 0x98
267
268#define FREE_RUN 0x9C
269
270#define RX_DROP 0xA0
271
272#define MAC_CSR_CMD 0xA4
273#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000
274#define MAC_CSR_CMD_R_NOT_W_ 0x40000000
275#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF
276
277#define MAC_CSR_DATA 0xA8
278
279#define AFC_CFG 0xAC
280#define AFC_CFG_AFC_HI_ 0x00FF0000
281#define AFC_CFG_AFC_LO_ 0x0000FF00
282#define AFC_CFG_BACK_DUR_ 0x000000F0
283#define AFC_CFG_FCMULT_ 0x00000008
284#define AFC_CFG_FCBRD_ 0x00000004
285#define AFC_CFG_FCADD_ 0x00000002
286#define AFC_CFG_FCANY_ 0x00000001
287
288#define E2P_CMD 0xB0
289#define E2P_CMD_EPC_BUSY_ 0x80000000
290#define E2P_CMD_EPC_CMD_ 0x70000000
291#define E2P_CMD_EPC_CMD_READ_ 0x00000000
292#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000
293#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000
294#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000
295#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000
296#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000
297#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000
298#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000
299#define E2P_CMD_EPC_TIMEOUT_ 0x00000200
300#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100
301#define E2P_CMD_EPC_ADDR_ 0x000000FF
302
303#define E2P_DATA 0xB4
304#define E2P_DATA_EEPROM_DATA_ 0x000000FF
305#define LAN_REGISTER_EXTENT 0x00000100
306
307/*
308 * MAC Control and Status Register (Indirect Address)
309 * Offset (through the MAC_CSR CMD and DATA port)
310 */
311#define MAC_CR 0x01
312#define MAC_CR_RXALL_ 0x80000000
313#define MAC_CR_HBDIS_ 0x10000000
314#define MAC_CR_RCVOWN_ 0x00800000
315#define MAC_CR_LOOPBK_ 0x00200000
316#define MAC_CR_FDPX_ 0x00100000
317#define MAC_CR_MCPAS_ 0x00080000
318#define MAC_CR_PRMS_ 0x00040000
319#define MAC_CR_INVFILT_ 0x00020000
320#define MAC_CR_PASSBAD_ 0x00010000
321#define MAC_CR_HFILT_ 0x00008000
322#define MAC_CR_HPFILT_ 0x00002000
323#define MAC_CR_LCOLL_ 0x00001000
324#define MAC_CR_BCAST_ 0x00000800
325#define MAC_CR_DISRTY_ 0x00000400
326#define MAC_CR_PADSTR_ 0x00000100
327#define MAC_CR_BOLMT_MASK_ 0x000000C0
328#define MAC_CR_DFCHK_ 0x00000020
329#define MAC_CR_TXEN_ 0x00000008
330#define MAC_CR_RXEN_ 0x00000004
331
332#define ADDRH 0x02
333
334#define ADDRL 0x03
335
336#define HASHH 0x04
337
338#define HASHL 0x05
339
340#define MII_ACC 0x06
341#define MII_ACC_PHY_ADDR_ 0x0000F800
342#define MII_ACC_MIIRINDA_ 0x000007C0
343#define MII_ACC_MII_WRITE_ 0x00000002
344#define MII_ACC_MII_BUSY_ 0x00000001
345
346#define MII_DATA 0x07
347
348#define FLOW 0x08
349#define FLOW_FCPT_ 0xFFFF0000
350#define FLOW_FCPASS_ 0x00000004
351#define FLOW_FCEN_ 0x00000002
352#define FLOW_FCBSY_ 0x00000001
353
354#define VLAN1 0x09
355
356#define VLAN2 0x0A
357
358#define WUFF 0x0B
359
360#define WUCSR 0x0C
361#define WUCSR_GUE_ 0x00000200
362#define WUCSR_WUFR_ 0x00000040
363#define WUCSR_MPR_ 0x00000020
364#define WUCSR_WAKE_EN_ 0x00000004
365#define WUCSR_MPEN_ 0x00000002
366
367/*
368 * Phy definitions (vendor-specific)
369 */
370#define LAN9118_PHY_ID 0x00C0001C
371
372#define MII_INTSTS 0x1D
373
374#define MII_INTMSK 0x1E
375#define PHY_INTMSK_AN_RCV_ (1 << 1)
376#define PHY_INTMSK_PDFAULT_ (1 << 2)
377#define PHY_INTMSK_AN_ACK_ (1 << 3)
378#define PHY_INTMSK_LNKDOWN_ (1 << 4)
379#define PHY_INTMSK_RFAULT_ (1 << 5)
380#define PHY_INTMSK_AN_COMP_ (1 << 6)
381#define PHY_INTMSK_ENERGYON_ (1 << 7)
382#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \
383 PHY_INTMSK_AN_COMP_ | \
384 PHY_INTMSK_RFAULT_ | \
385 PHY_INTMSK_LNKDOWN_)
386
387#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \
388 ADVERTISE_PAUSE_ASYM)
389
390#define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \
391 LPA_PAUSE_ASYM)
392
Akira Takeuchi62747cd2010-10-27 17:28:58 +0100393/*
394 * Provide hooks to let the arch add to the initialisation procedure
395 * and to override the source of the MAC address.
396 */
397#define SMSC_INITIALIZE() do {} while (0)
398#define smsc_get_mac(dev) smsc911x_read_mac_address((dev))
399
400#ifdef CONFIG_SMSC911X_ARCH_HOOKS
401#include <asm/smsc911x.h>
402#endif
403
Steve Glendinningfd9abb32008-11-05 00:35:37 +0000404#endif /* __SMSC911X_H__ */