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Linus Walleije8689e62010-09-28 15:57:37 +02001/*
2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
4 *
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 *
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +000022 * The full GNU General Public License is in this distribution in the file
23 * called COPYING.
Linus Walleije8689e62010-09-28 15:57:37 +020024 *
25 * Documentation: ARM DDI 0196G == PL080
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +000026 * Documentation: ARM DDI 0218E == PL081
Linus Walleije8689e62010-09-28 15:57:37 +020027 *
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +000028 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
29 * channel.
Linus Walleije8689e62010-09-28 15:57:37 +020030 *
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
36 *
37 * The PL080 has a dual bus master, PL081 has a single master.
38 *
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
41 * Until no data left
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
44 * Clear burst request
45 * Raise terminal count interrupt
46 *
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
50 *
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
53 *
54 * ASSUMES default (little) endianness for DMA transfers
55 *
Russell King - ARM Linux9dc2c202011-01-03 22:33:06 +000056 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
62 * are ignored.
63 *
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
68 *
Linus Walleije8689e62010-09-28 15:57:37 +020069 * Global TODO:
70 * - Break out common code from arch/arm/mach-s3c64xx and share
71 */
Russell King - ARM Linux730404a2011-01-03 22:34:07 +000072#include <linux/amba/bus.h>
Linus Walleije8689e62010-09-28 15:57:37 +020073#include <linux/amba/pl08x.h>
74#include <linux/debugfs.h>
Viresh Kumar0c38d702011-08-05 15:32:28 +053075#include <linux/delay.h>
76#include <linux/device.h>
77#include <linux/dmaengine.h>
78#include <linux/dmapool.h>
Vinod Koul8516f522011-09-02 16:43:44 +053079#include <linux/dma-mapping.h>
Viresh Kumar0c38d702011-08-05 15:32:28 +053080#include <linux/init.h>
81#include <linux/interrupt.h>
82#include <linux/module.h>
Viresh Kumarb7b60182011-08-05 15:32:33 +053083#include <linux/pm_runtime.h>
Linus Walleije8689e62010-09-28 15:57:37 +020084#include <linux/seq_file.h>
Viresh Kumar0c38d702011-08-05 15:32:28 +053085#include <linux/slab.h>
Linus Walleije8689e62010-09-28 15:57:37 +020086#include <asm/hardware/pl080.h>
Linus Walleije8689e62010-09-28 15:57:37 +020087
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000088#include "dmaengine.h"
89
Linus Walleije8689e62010-09-28 15:57:37 +020090#define DRIVER_NAME "pl08xdmac"
91
Russell King - ARM Linux7703eac2011-08-31 09:34:35 +010092static struct amba_driver pl08x_amba_driver;
93
Linus Walleije8689e62010-09-28 15:57:37 +020094/**
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +000095 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
Linus Walleije8689e62010-09-28 15:57:37 +020096 * @channels: the number of channels available in this variant
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +000097 * @dualmaster: whether this version supports dual AHB masters or not.
Linus Walleije8689e62010-09-28 15:57:37 +020098 */
99struct vendor_data {
Linus Walleije8689e62010-09-28 15:57:37 +0200100 u8 channels;
101 bool dualmaster;
102};
103
104/*
105 * PL08X private data structures
Russell King - ARM Linuxe8b5e112011-01-03 22:30:24 +0000106 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
Russell King - ARM Linuxe25761d2011-01-03 22:37:52 +0000107 * start & end do not - their bus bit info is in cctl. Also note that these
108 * are fixed 32-bit quantities.
Linus Walleije8689e62010-09-28 15:57:37 +0200109 */
Russell King - ARM Linux7cb72ad2011-01-03 22:35:28 +0000110struct pl08x_lli {
Russell King - ARM Linuxe25761d2011-01-03 22:37:52 +0000111 u32 src;
112 u32 dst;
Russell King - ARM Linuxbfddfb42011-01-03 22:38:12 +0000113 u32 lli;
Linus Walleije8689e62010-09-28 15:57:37 +0200114 u32 cctl;
115};
116
117/**
118 * struct pl08x_driver_data - the local state holder for the PL08x
119 * @slave: slave engine for this instance
120 * @memcpy: memcpy engine for this instance
121 * @base: virtual memory base (remapped) for the PL08x
122 * @adev: the corresponding AMBA (PrimeCell) bus entry
123 * @vd: vendor data for this PL08x variant
124 * @pd: platform data passed in from the platform/machine
125 * @phy_chans: array of data for the physical channels
126 * @pool: a pool for the LLI descriptors
127 * @pool_ctr: counter of LLIs in the pool
Viresh Kumar3e27ee82011-08-05 15:32:27 +0530128 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
129 * fetches
Russell King - ARM Linux30749cb2011-01-03 22:41:13 +0000130 * @mem_buses: set to indicate memory transfers on AHB2.
Linus Walleije8689e62010-09-28 15:57:37 +0200131 * @lock: a spinlock for this struct
132 */
133struct pl08x_driver_data {
134 struct dma_device slave;
135 struct dma_device memcpy;
136 void __iomem *base;
137 struct amba_device *adev;
Russell King - ARM Linuxf96ca9e2011-01-03 22:35:08 +0000138 const struct vendor_data *vd;
Linus Walleije8689e62010-09-28 15:57:37 +0200139 struct pl08x_platform_data *pd;
140 struct pl08x_phy_chan *phy_chans;
141 struct dma_pool *pool;
142 int pool_ctr;
Russell King - ARM Linux30749cb2011-01-03 22:41:13 +0000143 u8 lli_buses;
144 u8 mem_buses;
Linus Walleije8689e62010-09-28 15:57:37 +0200145 spinlock_t lock;
146};
147
148/*
149 * PL08X specific defines
150 */
151
Linus Walleije8689e62010-09-28 15:57:37 +0200152/* Size (bytes) of each LLI buffer allocated for one transfer */
153# define PL08X_LLI_TSFR_SIZE 0x2000
154
Russell King - ARM Linuxe8b5e112011-01-03 22:30:24 +0000155/* Maximum times we call dma_pool_alloc on this pool without freeing */
Russell King - ARM Linux7cb72ad2011-01-03 22:35:28 +0000156#define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
Linus Walleije8689e62010-09-28 15:57:37 +0200157#define PL08X_ALIGN 8
158
159static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
160{
161 return container_of(chan, struct pl08x_dma_chan, chan);
162}
163
Russell King - ARM Linux501e67e2011-01-03 22:44:57 +0000164static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
165{
166 return container_of(tx, struct pl08x_txd, tx);
167}
168
Linus Walleije8689e62010-09-28 15:57:37 +0200169/*
170 * Physical channel handling
171 */
172
173/* Whether a certain channel is busy or not */
174static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
175{
176 unsigned int val;
177
178 val = readl(ch->base + PL080_CH_CONFIG);
179 return val & PL080_CONFIG_ACTIVE;
180}
181
182/*
183 * Set the initial DMA register values i.e. those for the first LLI
Russell King - ARM Linuxe8b5e112011-01-03 22:30:24 +0000184 * The next LLI pointer and the configuration interrupt bit have
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000185 * been set when the LLIs were constructed. Poke them into the hardware
186 * and start the transfer.
Linus Walleije8689e62010-09-28 15:57:37 +0200187 */
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000188static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
189 struct pl08x_txd *txd)
Linus Walleije8689e62010-09-28 15:57:37 +0200190{
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000191 struct pl08x_driver_data *pl08x = plchan->host;
Linus Walleije8689e62010-09-28 15:57:37 +0200192 struct pl08x_phy_chan *phychan = plchan->phychan;
Russell King - ARM Linux19524d72011-01-03 22:39:13 +0000193 struct pl08x_lli *lli = &txd->llis_va[0];
Russell King - ARM Linux09b3c322011-01-03 22:39:53 +0000194 u32 val;
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000195
196 plchan->at = txd;
Linus Walleije8689e62010-09-28 15:57:37 +0200197
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000198 /* Wait for channel inactive */
199 while (pl08x_phy_channel_busy(phychan))
Russell King - ARM Linux19386b32011-01-03 22:36:29 +0000200 cpu_relax();
Linus Walleije8689e62010-09-28 15:57:37 +0200201
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000202 dev_vdbg(&pl08x->adev->dev,
203 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
Russell King - ARM Linux19524d72011-01-03 22:39:13 +0000204 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
205 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
Russell King - ARM Linux09b3c322011-01-03 22:39:53 +0000206 txd->ccfg);
Linus Walleije8689e62010-09-28 15:57:37 +0200207
Russell King - ARM Linux19524d72011-01-03 22:39:13 +0000208 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
209 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
210 writel(lli->lli, phychan->base + PL080_CH_LLI);
211 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
Russell King - ARM Linux09b3c322011-01-03 22:39:53 +0000212 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +0000213
214 /* Enable the DMA channel */
215 /* Do not access config register until channel shows as disabled */
216 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
217 cpu_relax();
218
219 /* Do not access config register until channel shows as inactive */
220 val = readl(phychan->base + PL080_CH_CONFIG);
221 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
222 val = readl(phychan->base + PL080_CH_CONFIG);
223
224 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
Linus Walleije8689e62010-09-28 15:57:37 +0200225}
226
227/*
Russell King - ARM Linux81796612011-01-27 12:37:44 +0000228 * Pause the channel by setting the HALT bit.
Linus Walleije8689e62010-09-28 15:57:37 +0200229 *
Russell King - ARM Linux81796612011-01-27 12:37:44 +0000230 * For M->P transfers, pause the DMAC first and then stop the peripheral -
231 * the FIFO can only drain if the peripheral is still requesting data.
232 * (note: this can still timeout if the DMAC FIFO never drains of data.)
Linus Walleije8689e62010-09-28 15:57:37 +0200233 *
Russell King - ARM Linux81796612011-01-27 12:37:44 +0000234 * For P->M transfers, disable the peripheral first to stop it filling
235 * the DMAC FIFO, and then pause the DMAC.
Linus Walleije8689e62010-09-28 15:57:37 +0200236 */
237static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
238{
239 u32 val;
Russell King - ARM Linux81796612011-01-27 12:37:44 +0000240 int timeout;
Linus Walleije8689e62010-09-28 15:57:37 +0200241
242 /* Set the HALT bit and wait for the FIFO to drain */
243 val = readl(ch->base + PL080_CH_CONFIG);
244 val |= PL080_CONFIG_HALT;
245 writel(val, ch->base + PL080_CH_CONFIG);
246
247 /* Wait for channel inactive */
Russell King - ARM Linux81796612011-01-27 12:37:44 +0000248 for (timeout = 1000; timeout; timeout--) {
249 if (!pl08x_phy_channel_busy(ch))
250 break;
251 udelay(1);
252 }
253 if (pl08x_phy_channel_busy(ch))
254 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
Linus Walleije8689e62010-09-28 15:57:37 +0200255}
256
257static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
258{
259 u32 val;
260
261 /* Clear the HALT bit */
262 val = readl(ch->base + PL080_CH_CONFIG);
263 val &= ~PL080_CONFIG_HALT;
264 writel(val, ch->base + PL080_CH_CONFIG);
265}
266
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +0000267/*
268 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
269 * clears any pending interrupt status. This should not be used for
270 * an on-going transfer, but as a method of shutting down a channel
271 * (eg, when it's no longer used) or terminating a transfer.
272 */
273static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
274 struct pl08x_phy_chan *ch)
Linus Walleije8689e62010-09-28 15:57:37 +0200275{
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +0000276 u32 val = readl(ch->base + PL080_CH_CONFIG);
Linus Walleije8689e62010-09-28 15:57:37 +0200277
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +0000278 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
279 PL080_CONFIG_TC_IRQ_MASK);
Linus Walleije8689e62010-09-28 15:57:37 +0200280
Linus Walleije8689e62010-09-28 15:57:37 +0200281 writel(val, ch->base + PL080_CH_CONFIG);
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +0000282
283 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
284 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
Linus Walleije8689e62010-09-28 15:57:37 +0200285}
286
287static inline u32 get_bytes_in_cctl(u32 cctl)
288{
289 /* The source width defines the number of bytes */
290 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
291
292 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
293 case PL080_WIDTH_8BIT:
294 break;
295 case PL080_WIDTH_16BIT:
296 bytes *= 2;
297 break;
298 case PL080_WIDTH_32BIT:
299 bytes *= 4;
300 break;
301 }
302 return bytes;
303}
304
305/* The channel should be paused when calling this */
306static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
307{
308 struct pl08x_phy_chan *ch;
Linus Walleije8689e62010-09-28 15:57:37 +0200309 struct pl08x_txd *txd;
310 unsigned long flags;
Russell King - ARM Linuxcace6582011-01-03 22:37:31 +0000311 size_t bytes = 0;
Linus Walleije8689e62010-09-28 15:57:37 +0200312
313 spin_lock_irqsave(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +0200314 ch = plchan->phychan;
315 txd = plchan->at;
316
317 /*
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000318 * Follow the LLIs to get the number of remaining
319 * bytes in the currently active transaction.
Linus Walleije8689e62010-09-28 15:57:37 +0200320 */
321 if (ch && txd) {
Russell King - ARM Linux4c0df6a2011-01-03 22:36:50 +0000322 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
Linus Walleije8689e62010-09-28 15:57:37 +0200323
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000324 /* First get the remaining bytes in the active transfer */
Linus Walleije8689e62010-09-28 15:57:37 +0200325 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
326
327 if (clli) {
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000328 struct pl08x_lli *llis_va = txd->llis_va;
329 dma_addr_t llis_bus = txd->llis_bus;
330 int index;
Linus Walleije8689e62010-09-28 15:57:37 +0200331
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000332 BUG_ON(clli < llis_bus || clli >= llis_bus +
333 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
Linus Walleije8689e62010-09-28 15:57:37 +0200334
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000335 /*
336 * Locate the next LLI - as this is an array,
337 * it's simple maths to find.
338 */
339 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
340
341 for (; index < MAX_NUM_TSFR_LLIS; index++) {
342 bytes += get_bytes_in_cctl(llis_va[index].cctl);
343
Linus Walleije8689e62010-09-28 15:57:37 +0200344 /*
Russell King - ARM Linuxe8b5e112011-01-03 22:30:24 +0000345 * A LLI pointer of 0 terminates the LLI list
Linus Walleije8689e62010-09-28 15:57:37 +0200346 */
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000347 if (!llis_va[index].lli)
348 break;
Linus Walleije8689e62010-09-28 15:57:37 +0200349 }
350 }
351 }
352
353 /* Sum up all queued transactions */
Russell King - ARM Linux15c17232011-01-03 22:44:36 +0000354 if (!list_empty(&plchan->pend_list)) {
Russell King - ARM Linuxdb9f1362011-01-03 22:38:32 +0000355 struct pl08x_txd *txdi;
Russell King - ARM Linux15c17232011-01-03 22:44:36 +0000356 list_for_each_entry(txdi, &plchan->pend_list, node) {
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530357 struct pl08x_sg *dsg;
358 list_for_each_entry(dsg, &txd->dsg_list, node)
359 bytes += dsg->len;
Linus Walleije8689e62010-09-28 15:57:37 +0200360 }
Linus Walleije8689e62010-09-28 15:57:37 +0200361 }
362
363 spin_unlock_irqrestore(&plchan->lock, flags);
364
365 return bytes;
366}
367
368/*
369 * Allocate a physical channel for a virtual channel
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +0000370 *
371 * Try to locate a physical channel to be used for this transfer. If all
372 * are taken return NULL and the requester will have to cope by using
373 * some fallback PIO mode or retrying later.
Linus Walleije8689e62010-09-28 15:57:37 +0200374 */
375static struct pl08x_phy_chan *
376pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
377 struct pl08x_dma_chan *virt_chan)
378{
379 struct pl08x_phy_chan *ch = NULL;
380 unsigned long flags;
381 int i;
382
Linus Walleije8689e62010-09-28 15:57:37 +0200383 for (i = 0; i < pl08x->vd->channels; i++) {
384 ch = &pl08x->phy_chans[i];
385
386 spin_lock_irqsave(&ch->lock, flags);
387
388 if (!ch->serving) {
389 ch->serving = virt_chan;
390 ch->signal = -1;
391 spin_unlock_irqrestore(&ch->lock, flags);
392 break;
393 }
394
395 spin_unlock_irqrestore(&ch->lock, flags);
396 }
397
398 if (i == pl08x->vd->channels) {
399 /* No physical channel available, cope with it */
400 return NULL;
401 }
402
Viresh Kumarb7b60182011-08-05 15:32:33 +0530403 pm_runtime_get_sync(&pl08x->adev->dev);
Linus Walleije8689e62010-09-28 15:57:37 +0200404 return ch;
405}
406
407static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
408 struct pl08x_phy_chan *ch)
409{
410 unsigned long flags;
411
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +0000412 spin_lock_irqsave(&ch->lock, flags);
413
Linus Walleije8689e62010-09-28 15:57:37 +0200414 /* Stop the channel and clear its interrupts */
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +0000415 pl08x_terminate_phy_chan(pl08x, ch);
Linus Walleije8689e62010-09-28 15:57:37 +0200416
Viresh Kumarb7b60182011-08-05 15:32:33 +0530417 pm_runtime_put(&pl08x->adev->dev);
418
Linus Walleije8689e62010-09-28 15:57:37 +0200419 /* Mark it as free */
Linus Walleije8689e62010-09-28 15:57:37 +0200420 ch->serving = NULL;
421 spin_unlock_irqrestore(&ch->lock, flags);
422}
423
424/*
425 * LLI handling
426 */
427
428static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
429{
430 switch (coded) {
431 case PL080_WIDTH_8BIT:
432 return 1;
433 case PL080_WIDTH_16BIT:
434 return 2;
435 case PL080_WIDTH_32BIT:
436 return 4;
437 default:
438 break;
439 }
440 BUG();
441 return 0;
442}
443
444static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
Russell King - ARM Linuxcace6582011-01-03 22:37:31 +0000445 size_t tsize)
Linus Walleije8689e62010-09-28 15:57:37 +0200446{
447 u32 retbits = cctl;
448
Russell King - ARM Linuxe8b5e112011-01-03 22:30:24 +0000449 /* Remove all src, dst and transfer size bits */
Linus Walleije8689e62010-09-28 15:57:37 +0200450 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
451 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
452 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
453
454 /* Then set the bits according to the parameters */
455 switch (srcwidth) {
456 case 1:
457 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
458 break;
459 case 2:
460 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
461 break;
462 case 4:
463 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
464 break;
465 default:
466 BUG();
467 break;
468 }
469
470 switch (dstwidth) {
471 case 1:
472 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
473 break;
474 case 2:
475 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
476 break;
477 case 4:
478 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
479 break;
480 default:
481 BUG();
482 break;
483 }
484
485 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
486 return retbits;
487}
488
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000489struct pl08x_lli_build_data {
490 struct pl08x_txd *txd;
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000491 struct pl08x_bus_data srcbus;
492 struct pl08x_bus_data dstbus;
493 size_t remainder;
Russell King - ARM Linux25c94f72011-07-21 17:11:46 +0100494 u32 lli_bus;
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000495};
496
Linus Walleije8689e62010-09-28 15:57:37 +0200497/*
Viresh Kumar0532e6f2011-08-05 15:32:31 +0530498 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
499 * victim in case src & dest are not similarly aligned. i.e. If after aligning
500 * masters address with width requirements of transfer (by sending few byte by
501 * byte data), slave is still not aligned, then its width will be reduced to
502 * BYTE.
503 * - prefers the destination bus if both available
Viresh Kumar036f05f2011-08-05 15:32:41 +0530504 * - prefers bus with fixed address (i.e. peripheral)
Linus Walleije8689e62010-09-28 15:57:37 +0200505 */
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000506static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
507 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
Linus Walleije8689e62010-09-28 15:57:37 +0200508{
509 if (!(cctl & PL080_CONTROL_DST_INCR)) {
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000510 *mbus = &bd->dstbus;
511 *sbus = &bd->srcbus;
Viresh Kumar036f05f2011-08-05 15:32:41 +0530512 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
513 *mbus = &bd->srcbus;
514 *sbus = &bd->dstbus;
Linus Walleije8689e62010-09-28 15:57:37 +0200515 } else {
Viresh Kumar036f05f2011-08-05 15:32:41 +0530516 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000517 *mbus = &bd->dstbus;
518 *sbus = &bd->srcbus;
Linus Walleije8689e62010-09-28 15:57:37 +0200519 } else {
Viresh Kumar036f05f2011-08-05 15:32:41 +0530520 *mbus = &bd->srcbus;
521 *sbus = &bd->dstbus;
Linus Walleije8689e62010-09-28 15:57:37 +0200522 }
523 }
524}
525
526/*
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +0000527 * Fills in one LLI for a certain transfer descriptor and advance the counter
Linus Walleije8689e62010-09-28 15:57:37 +0200528 */
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000529static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
530 int num_llis, int len, u32 cctl)
Linus Walleije8689e62010-09-28 15:57:37 +0200531{
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000532 struct pl08x_lli *llis_va = bd->txd->llis_va;
533 dma_addr_t llis_bus = bd->txd->llis_bus;
Linus Walleije8689e62010-09-28 15:57:37 +0200534
535 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
536
Russell King - ARM Linux30749cb2011-01-03 22:41:13 +0000537 llis_va[num_llis].cctl = cctl;
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000538 llis_va[num_llis].src = bd->srcbus.addr;
539 llis_va[num_llis].dst = bd->dstbus.addr;
Viresh Kumar3e27ee82011-08-05 15:32:27 +0530540 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
541 sizeof(struct pl08x_lli);
Russell King - ARM Linux25c94f72011-07-21 17:11:46 +0100542 llis_va[num_llis].lli |= bd->lli_bus;
Linus Walleije8689e62010-09-28 15:57:37 +0200543
544 if (cctl & PL080_CONTROL_SRC_INCR)
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000545 bd->srcbus.addr += len;
Linus Walleije8689e62010-09-28 15:57:37 +0200546 if (cctl & PL080_CONTROL_DST_INCR)
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000547 bd->dstbus.addr += len;
Linus Walleije8689e62010-09-28 15:57:37 +0200548
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000549 BUG_ON(bd->remainder < len);
Russell King - ARM Linuxcace6582011-01-03 22:37:31 +0000550
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000551 bd->remainder -= len;
Linus Walleije8689e62010-09-28 15:57:37 +0200552}
553
Viresh Kumar03af5002011-08-05 15:32:39 +0530554static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
555 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
Linus Walleije8689e62010-09-28 15:57:37 +0200556{
Viresh Kumar03af5002011-08-05 15:32:39 +0530557 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
558 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
559 (*total_bytes) += len;
Linus Walleije8689e62010-09-28 15:57:37 +0200560}
561
562/*
563 * This fills in the table of LLIs for the transfer descriptor
564 * Note that we assume we never have to change the burst sizes
565 * Return 0 for error
566 */
567static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
568 struct pl08x_txd *txd)
569{
Linus Walleije8689e62010-09-28 15:57:37 +0200570 struct pl08x_bus_data *mbus, *sbus;
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000571 struct pl08x_lli_build_data bd;
Linus Walleije8689e62010-09-28 15:57:37 +0200572 int num_llis = 0;
Viresh Kumar03af5002011-08-05 15:32:39 +0530573 u32 cctl, early_bytes = 0;
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530574 size_t max_bytes_per_lli, total_bytes;
Russell King - ARM Linux7cb72ad2011-01-03 22:35:28 +0000575 struct pl08x_lli *llis_va;
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530576 struct pl08x_sg *dsg;
Linus Walleije8689e62010-09-28 15:57:37 +0200577
Viresh Kumar3e27ee82011-08-05 15:32:27 +0530578 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
Linus Walleije8689e62010-09-28 15:57:37 +0200579 if (!txd->llis_va) {
580 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
581 return 0;
582 }
583
584 pl08x->pool_ctr++;
585
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000586 bd.txd = txd;
Russell King - ARM Linux25c94f72011-07-21 17:11:46 +0100587 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530588 cctl = txd->cctl;
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000589
Linus Walleije8689e62010-09-28 15:57:37 +0200590 /* Find maximum width of the source bus */
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000591 bd.srcbus.maxwidth =
Linus Walleije8689e62010-09-28 15:57:37 +0200592 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
593 PL080_CONTROL_SWIDTH_SHIFT);
594
595 /* Find maximum width of the destination bus */
Russell King - ARM Linux542361f2011-01-03 22:43:15 +0000596 bd.dstbus.maxwidth =
Linus Walleije8689e62010-09-28 15:57:37 +0200597 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
598 PL080_CONTROL_DWIDTH_SHIFT);
599
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530600 list_for_each_entry(dsg, &txd->dsg_list, node) {
601 total_bytes = 0;
602 cctl = txd->cctl;
Linus Walleije8689e62010-09-28 15:57:37 +0200603
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530604 bd.srcbus.addr = dsg->src_addr;
605 bd.dstbus.addr = dsg->dst_addr;
606 bd.remainder = dsg->len;
607 bd.srcbus.buswidth = bd.srcbus.maxwidth;
608 bd.dstbus.buswidth = bd.dstbus.maxwidth;
Linus Walleije8689e62010-09-28 15:57:37 +0200609
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530610 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
Linus Walleije8689e62010-09-28 15:57:37 +0200611
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530612 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
613 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
614 bd.srcbus.buswidth,
615 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
616 bd.dstbus.buswidth,
617 bd.remainder);
618 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
619 mbus == &bd.srcbus ? "src" : "dst",
620 sbus == &bd.srcbus ? "src" : "dst");
Russell King - ARM Linuxfc74eb72011-07-21 17:12:06 +0100621
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530622 /*
623 * Zero length is only allowed if all these requirements are
624 * met:
625 * - flow controller is peripheral.
626 * - src.addr is aligned to src.width
627 * - dst.addr is aligned to dst.width
628 *
629 * sg_len == 1 should be true, as there can be two cases here:
630 *
631 * - Memory addresses are contiguous and are not scattered.
632 * Here, Only one sg will be passed by user driver, with
633 * memory address and zero length. We pass this to controller
634 * and after the transfer it will receive the last burst
635 * request from peripheral and so transfer finishes.
636 *
637 * - Memory addresses are scattered and are not contiguous.
638 * Here, Obviously as DMA controller doesn't know when a lli's
639 * transfer gets over, it can't load next lli. So in this
640 * case, there has to be an assumption that only one lli is
641 * supported. Thus, we can't have scattered addresses.
642 */
643 if (!bd.remainder) {
644 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
645 PL080_CONFIG_FLOW_CONTROL_SHIFT;
646 if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
Viresh Kumar0a235652011-08-05 15:32:42 +0530647 (fc <= PL080_FLOW_SRC2DST_SRC))) {
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530648 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
649 __func__);
650 return 0;
651 }
Linus Walleije8689e62010-09-28 15:57:37 +0200652
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530653 if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
Julia Lawall880db3f2012-01-12 22:49:29 +0100654 (bd.dstbus.addr % bd.dstbus.buswidth)) {
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530655 dev_err(&pl08x->adev->dev,
656 "%s src & dst address must be aligned to src"
657 " & dst width if peripheral is flow controller",
658 __func__);
659 return 0;
660 }
Linus Walleije8689e62010-09-28 15:57:37 +0200661
Viresh Kumar16a2e7d2011-08-05 15:32:37 +0530662 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530663 bd.dstbus.buswidth, 0);
664 pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
665 break;
Linus Walleije8689e62010-09-28 15:57:37 +0200666 }
667
668 /*
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530669 * Send byte by byte for following cases
670 * - Less than a bus width available
671 * - until master bus is aligned
Linus Walleije8689e62010-09-28 15:57:37 +0200672 */
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530673 if (bd.remainder < mbus->buswidth)
674 early_bytes = bd.remainder;
675 else if ((mbus->addr) % (mbus->buswidth)) {
676 early_bytes = mbus->buswidth - (mbus->addr) %
677 (mbus->buswidth);
678 if ((bd.remainder - early_bytes) < mbus->buswidth)
679 early_bytes = bd.remainder;
Linus Walleije8689e62010-09-28 15:57:37 +0200680 }
Viresh Kumar16a2e7d2011-08-05 15:32:37 +0530681
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530682 if (early_bytes) {
683 dev_vdbg(&pl08x->adev->dev,
684 "%s byte width LLIs (remain 0x%08x)\n",
685 __func__, bd.remainder);
686 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
687 &total_bytes);
688 }
Linus Walleije8689e62010-09-28 15:57:37 +0200689
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530690 if (bd.remainder) {
691 /*
692 * Master now aligned
693 * - if slave is not then we must set its width down
694 */
695 if (sbus->addr % sbus->buswidth) {
696 dev_dbg(&pl08x->adev->dev,
697 "%s set down bus width to one byte\n",
698 __func__);
699
700 sbus->buswidth = 1;
701 }
702
703 /*
704 * Bytes transferred = tsize * src width, not
705 * MIN(buswidths)
706 */
707 max_bytes_per_lli = bd.srcbus.buswidth *
708 PL080_CONTROL_TRANSFER_SIZE_MASK;
709 dev_vdbg(&pl08x->adev->dev,
710 "%s max bytes per lli = %zu\n",
711 __func__, max_bytes_per_lli);
712
713 /*
714 * Make largest possible LLIs until less than one bus
715 * width left
716 */
717 while (bd.remainder > (mbus->buswidth - 1)) {
718 size_t lli_len, tsize, width;
719
720 /*
721 * If enough left try to send max possible,
722 * otherwise try to send the remainder
723 */
724 lli_len = min(bd.remainder, max_bytes_per_lli);
725
726 /*
727 * Check against maximum bus alignment:
728 * Calculate actual transfer size in relation to
729 * bus width an get a maximum remainder of the
730 * highest bus width - 1
731 */
732 width = max(mbus->buswidth, sbus->buswidth);
733 lli_len = (lli_len / width) * width;
734 tsize = lli_len / bd.srcbus.buswidth;
735
736 dev_vdbg(&pl08x->adev->dev,
737 "%s fill lli with single lli chunk of "
738 "size 0x%08zx (remainder 0x%08zx)\n",
739 __func__, lli_len, bd.remainder);
740
741 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
742 bd.dstbus.buswidth, tsize);
743 pl08x_fill_lli_for_desc(&bd, num_llis++,
744 lli_len, cctl);
745 total_bytes += lli_len;
746 }
747
748 /*
749 * Send any odd bytes
750 */
751 if (bd.remainder) {
752 dev_vdbg(&pl08x->adev->dev,
753 "%s align with boundary, send odd bytes (remain %zu)\n",
754 __func__, bd.remainder);
755 prep_byte_width_lli(&bd, &cctl, bd.remainder,
756 num_llis++, &total_bytes);
757 }
758 }
759
760 if (total_bytes != dsg->len) {
761 dev_err(&pl08x->adev->dev,
762 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
763 __func__, total_bytes, dsg->len);
764 return 0;
765 }
766
767 if (num_llis >= MAX_NUM_TSFR_LLIS) {
768 dev_err(&pl08x->adev->dev,
769 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
770 __func__, (u32) MAX_NUM_TSFR_LLIS);
771 return 0;
772 }
Linus Walleije8689e62010-09-28 15:57:37 +0200773 }
Linus Walleije8689e62010-09-28 15:57:37 +0200774
Russell King - ARM Linuxb58b6b52011-01-03 22:34:48 +0000775 llis_va = txd->llis_va;
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +0000776 /* The final LLI terminates the LLI. */
Russell King - ARM Linuxbfddfb42011-01-03 22:38:12 +0000777 llis_va[num_llis - 1].lli = 0;
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +0000778 /* The final LLI element shall also fire an interrupt. */
Russell King - ARM Linuxb58b6b52011-01-03 22:34:48 +0000779 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
Linus Walleije8689e62010-09-28 15:57:37 +0200780
Linus Walleije8689e62010-09-28 15:57:37 +0200781#ifdef VERBOSE_DEBUG
782 {
783 int i;
784
Russell King - ARM Linuxfc74eb72011-07-21 17:12:06 +0100785 dev_vdbg(&pl08x->adev->dev,
786 "%-3s %-9s %-10s %-10s %-10s %s\n",
787 "lli", "", "csrc", "cdst", "clli", "cctl");
Linus Walleije8689e62010-09-28 15:57:37 +0200788 for (i = 0; i < num_llis; i++) {
789 dev_vdbg(&pl08x->adev->dev,
Russell King - ARM Linuxfc74eb72011-07-21 17:12:06 +0100790 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
791 i, &llis_va[i], llis_va[i].src,
792 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
Linus Walleije8689e62010-09-28 15:57:37 +0200793 );
794 }
795 }
796#endif
797
798 return num_llis;
799}
800
801/* You should call this with the struct pl08x lock held */
802static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
803 struct pl08x_txd *txd)
804{
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530805 struct pl08x_sg *dsg, *_dsg;
806
Linus Walleije8689e62010-09-28 15:57:37 +0200807 /* Free the LLI */
Viresh Kumarc1205642011-08-05 15:32:44 +0530808 if (txd->llis_va)
809 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
Linus Walleije8689e62010-09-28 15:57:37 +0200810
811 pl08x->pool_ctr--;
812
Viresh Kumarb7f69d92011-08-05 15:32:43 +0530813 list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
814 list_del(&dsg->node);
815 kfree(dsg);
816 }
817
Linus Walleije8689e62010-09-28 15:57:37 +0200818 kfree(txd);
819}
820
821static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
822 struct pl08x_dma_chan *plchan)
823{
824 struct pl08x_txd *txdi = NULL;
825 struct pl08x_txd *next;
826
Russell King - ARM Linux15c17232011-01-03 22:44:36 +0000827 if (!list_empty(&plchan->pend_list)) {
Linus Walleije8689e62010-09-28 15:57:37 +0200828 list_for_each_entry_safe(txdi,
Russell King - ARM Linux15c17232011-01-03 22:44:36 +0000829 next, &plchan->pend_list, node) {
Linus Walleije8689e62010-09-28 15:57:37 +0200830 list_del(&txdi->node);
831 pl08x_free_txd(pl08x, txdi);
832 }
Linus Walleije8689e62010-09-28 15:57:37 +0200833 }
834}
835
836/*
837 * The DMA ENGINE API
838 */
839static int pl08x_alloc_chan_resources(struct dma_chan *chan)
840{
841 return 0;
842}
843
844static void pl08x_free_chan_resources(struct dma_chan *chan)
845{
846}
847
848/*
849 * This should be called with the channel plchan->lock held
850 */
851static int prep_phy_channel(struct pl08x_dma_chan *plchan,
852 struct pl08x_txd *txd)
853{
854 struct pl08x_driver_data *pl08x = plchan->host;
855 struct pl08x_phy_chan *ch;
856 int ret;
857
858 /* Check if we already have a channel */
Viresh Kumar8f0d30f2011-11-29 12:56:50 +0530859 if (plchan->phychan) {
860 ch = plchan->phychan;
861 goto got_channel;
862 }
Linus Walleije8689e62010-09-28 15:57:37 +0200863
864 ch = pl08x_get_phy_channel(pl08x, plchan);
865 if (!ch) {
866 /* No physical channel available, cope with it */
867 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
868 return -EBUSY;
869 }
870
871 /*
872 * OK we have a physical channel: for memcpy() this is all we
873 * need, but for slaves the physical signals may be muxed!
874 * Can the platform allow us to use this channel?
875 */
Viresh Kumar16ca8102011-08-05 15:32:35 +0530876 if (plchan->slave && pl08x->pd->get_signal) {
Linus Walleije8689e62010-09-28 15:57:37 +0200877 ret = pl08x->pd->get_signal(plchan);
878 if (ret < 0) {
879 dev_dbg(&pl08x->adev->dev,
880 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
881 ch->id, plchan->name);
882 /* Release physical channel & return */
883 pl08x_put_phy_channel(pl08x, ch);
884 return -EBUSY;
885 }
886 ch->signal = ret;
887 }
888
Viresh Kumar8f0d30f2011-11-29 12:56:50 +0530889 plchan->phychan = ch;
Linus Walleije8689e62010-09-28 15:57:37 +0200890 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
891 ch->id,
892 ch->signal,
893 plchan->name);
894
Viresh Kumar8f0d30f2011-11-29 12:56:50 +0530895got_channel:
896 /* Assign the flow control signal to this channel */
897 if (txd->direction == DMA_MEM_TO_DEV)
898 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
899 else if (txd->direction == DMA_DEV_TO_MEM)
900 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
901
Russell King - ARM Linux8087aac2011-01-03 22:45:17 +0000902 plchan->phychan_hold++;
Linus Walleije8689e62010-09-28 15:57:37 +0200903
904 return 0;
905}
906
Russell King - ARM Linux8c8cc2b2011-01-03 22:36:09 +0000907static void release_phy_channel(struct pl08x_dma_chan *plchan)
908{
909 struct pl08x_driver_data *pl08x = plchan->host;
910
911 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
912 pl08x->pd->put_signal(plchan);
913 plchan->phychan->signal = -1;
914 }
915 pl08x_put_phy_channel(pl08x, plchan->phychan);
916 plchan->phychan = NULL;
917}
918
Linus Walleije8689e62010-09-28 15:57:37 +0200919static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
920{
921 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
Russell King - ARM Linux501e67e2011-01-03 22:44:57 +0000922 struct pl08x_txd *txd = to_pl08x_txd(tx);
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +0000923 unsigned long flags;
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000924 dma_cookie_t cookie;
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +0000925
926 spin_lock_irqsave(&plchan->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000927 cookie = dma_cookie_assign(tx);
Russell King - ARM Linux501e67e2011-01-03 22:44:57 +0000928
929 /* Put this onto the pending list */
930 list_add_tail(&txd->node, &plchan->pend_list);
931
932 /*
933 * If there was no physical channel available for this memcpy,
934 * stack the request up and indicate that the channel is waiting
935 * for a free physical channel.
936 */
937 if (!plchan->slave && !plchan->phychan) {
938 /* Do this memcpy whenever there is a channel ready */
939 plchan->state = PL08X_CHAN_WAITING;
940 plchan->waiting = txd;
Russell King - ARM Linux8087aac2011-01-03 22:45:17 +0000941 } else {
942 plchan->phychan_hold--;
Russell King - ARM Linux501e67e2011-01-03 22:44:57 +0000943 }
944
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +0000945 spin_unlock_irqrestore(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +0200946
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000947 return cookie;
Linus Walleije8689e62010-09-28 15:57:37 +0200948}
949
950static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
951 struct dma_chan *chan, unsigned long flags)
952{
953 struct dma_async_tx_descriptor *retval = NULL;
954
955 return retval;
956}
957
958/*
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +0000959 * Code accessing dma_async_is_complete() in a tight loop may give problems.
960 * If slaves are relying on interrupts to signal completion this function
961 * must not be called with interrupts disabled.
Linus Walleije8689e62010-09-28 15:57:37 +0200962 */
Viresh Kumar3e27ee82011-08-05 15:32:27 +0530963static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
964 dma_cookie_t cookie, struct dma_tx_state *txstate)
Linus Walleije8689e62010-09-28 15:57:37 +0200965{
966 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
Linus Walleije8689e62010-09-28 15:57:37 +0200967 enum dma_status ret;
Linus Walleije8689e62010-09-28 15:57:37 +0200968
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000969 ret = dma_cookie_status(chan, cookie, txstate);
970 if (ret == DMA_SUCCESS)
Linus Walleije8689e62010-09-28 15:57:37 +0200971 return ret;
Linus Walleije8689e62010-09-28 15:57:37 +0200972
973 /*
Linus Walleije8689e62010-09-28 15:57:37 +0200974 * This cookie not complete yet
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000975 * Get number of bytes left in the active transactions and queue
Linus Walleije8689e62010-09-28 15:57:37 +0200976 */
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000977 dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
Linus Walleije8689e62010-09-28 15:57:37 +0200978
979 if (plchan->state == PL08X_CHAN_PAUSED)
980 return DMA_PAUSED;
981
982 /* Whether waiting or running, we're in progress */
983 return DMA_IN_PROGRESS;
984}
985
986/* PrimeCell DMA extension */
987struct burst_table {
Russell King - ARM Linux760596c62011-07-21 17:14:08 +0100988 u32 burstwords;
Linus Walleije8689e62010-09-28 15:57:37 +0200989 u32 reg;
990};
991
992static const struct burst_table burst_sizes[] = {
993 {
994 .burstwords = 256,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +0100995 .reg = PL080_BSIZE_256,
Linus Walleije8689e62010-09-28 15:57:37 +0200996 },
997 {
998 .burstwords = 128,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +0100999 .reg = PL080_BSIZE_128,
Linus Walleije8689e62010-09-28 15:57:37 +02001000 },
1001 {
1002 .burstwords = 64,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001003 .reg = PL080_BSIZE_64,
Linus Walleije8689e62010-09-28 15:57:37 +02001004 },
1005 {
1006 .burstwords = 32,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001007 .reg = PL080_BSIZE_32,
Linus Walleije8689e62010-09-28 15:57:37 +02001008 },
1009 {
1010 .burstwords = 16,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001011 .reg = PL080_BSIZE_16,
Linus Walleije8689e62010-09-28 15:57:37 +02001012 },
1013 {
1014 .burstwords = 8,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001015 .reg = PL080_BSIZE_8,
Linus Walleije8689e62010-09-28 15:57:37 +02001016 },
1017 {
1018 .burstwords = 4,
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001019 .reg = PL080_BSIZE_4,
Linus Walleije8689e62010-09-28 15:57:37 +02001020 },
1021 {
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001022 .burstwords = 0,
1023 .reg = PL080_BSIZE_1,
Linus Walleije8689e62010-09-28 15:57:37 +02001024 },
1025};
1026
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001027/*
1028 * Given the source and destination available bus masks, select which
1029 * will be routed to each port. We try to have source and destination
1030 * on separate ports, but always respect the allowable settings.
1031 */
1032static u32 pl08x_select_bus(u8 src, u8 dst)
1033{
1034 u32 cctl = 0;
1035
1036 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1037 cctl |= PL080_CONTROL_DST_AHB2;
1038 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1039 cctl |= PL080_CONTROL_SRC_AHB2;
1040
1041 return cctl;
1042}
1043
Russell King - ARM Linuxf14c4262011-07-21 17:12:47 +01001044static u32 pl08x_cctl(u32 cctl)
1045{
1046 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1047 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1048 PL080_CONTROL_PROT_MASK);
1049
1050 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1051 return cctl | PL080_CONTROL_PROT_SYS;
1052}
1053
Russell King - ARM Linuxaa88cda2011-07-21 17:13:28 +01001054static u32 pl08x_width(enum dma_slave_buswidth width)
1055{
1056 switch (width) {
1057 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1058 return PL080_WIDTH_8BIT;
1059 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1060 return PL080_WIDTH_16BIT;
1061 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1062 return PL080_WIDTH_32BIT;
Vinod Koulf32807f2011-07-25 19:22:01 +05301063 default:
1064 return ~0;
Russell King - ARM Linuxaa88cda2011-07-21 17:13:28 +01001065 }
Russell King - ARM Linuxaa88cda2011-07-21 17:13:28 +01001066}
1067
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001068static u32 pl08x_burst(u32 maxburst)
1069{
1070 int i;
1071
1072 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1073 if (burst_sizes[i].burstwords <= maxburst)
1074 break;
1075
1076 return burst_sizes[i].reg;
1077}
1078
Russell King - ARM Linuxf0fd9442011-01-03 22:45:57 +00001079static int dma_set_runtime_config(struct dma_chan *chan,
1080 struct dma_slave_config *config)
Linus Walleije8689e62010-09-28 15:57:37 +02001081{
1082 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1083 struct pl08x_driver_data *pl08x = plchan->host;
Linus Walleije8689e62010-09-28 15:57:37 +02001084 enum dma_slave_buswidth addr_width;
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001085 u32 width, burst, maxburst;
Linus Walleije8689e62010-09-28 15:57:37 +02001086 u32 cctl = 0;
Linus Walleije8689e62010-09-28 15:57:37 +02001087
Russell King - ARM Linuxb7f75862011-01-03 22:46:17 +00001088 if (!plchan->slave)
1089 return -EINVAL;
1090
Linus Walleije8689e62010-09-28 15:57:37 +02001091 /* Transfer direction */
1092 plchan->runtime_direction = config->direction;
Vinod Kouldb8196d2011-10-13 22:34:23 +05301093 if (config->direction == DMA_MEM_TO_DEV) {
Linus Walleije8689e62010-09-28 15:57:37 +02001094 addr_width = config->dst_addr_width;
1095 maxburst = config->dst_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +05301096 } else if (config->direction == DMA_DEV_TO_MEM) {
Linus Walleije8689e62010-09-28 15:57:37 +02001097 addr_width = config->src_addr_width;
1098 maxburst = config->src_maxburst;
1099 } else {
1100 dev_err(&pl08x->adev->dev,
1101 "bad runtime_config: alien transfer direction\n");
Russell King - ARM Linuxf0fd9442011-01-03 22:45:57 +00001102 return -EINVAL;
Linus Walleije8689e62010-09-28 15:57:37 +02001103 }
1104
Russell King - ARM Linuxaa88cda2011-07-21 17:13:28 +01001105 width = pl08x_width(addr_width);
1106 if (width == ~0) {
Linus Walleije8689e62010-09-28 15:57:37 +02001107 dev_err(&pl08x->adev->dev,
1108 "bad runtime_config: alien address width\n");
Russell King - ARM Linuxf0fd9442011-01-03 22:45:57 +00001109 return -EINVAL;
Linus Walleije8689e62010-09-28 15:57:37 +02001110 }
1111
Russell King - ARM Linuxaa88cda2011-07-21 17:13:28 +01001112 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1113 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1114
Linus Walleije8689e62010-09-28 15:57:37 +02001115 /*
Russell King - ARM Linux4440aac2011-01-03 22:30:44 +00001116 * If this channel will only request single transfers, set this
1117 * down to ONE element. Also select one element if no maxburst
1118 * is specified.
Linus Walleije8689e62010-09-28 15:57:37 +02001119 */
Russell King - ARM Linux760596c62011-07-21 17:14:08 +01001120 if (plchan->cd->single)
1121 maxburst = 1;
1122
1123 burst = pl08x_burst(maxburst);
1124 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1125 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
Linus Walleije8689e62010-09-28 15:57:37 +02001126
Viresh Kumar8c9f7aa2012-02-01 16:12:20 +05301127 plchan->device_fc = config->device_fc;
1128
Vinod Kouldb8196d2011-10-13 22:34:23 +05301129 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
Russell King - ARM Linuxb207b4d2011-07-21 17:12:27 +01001130 plchan->src_addr = config->src_addr;
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001131 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1132 pl08x_select_bus(plchan->cd->periph_buses,
1133 pl08x->mem_buses);
Russell King - ARM Linuxb207b4d2011-07-21 17:12:27 +01001134 } else {
1135 plchan->dst_addr = config->dst_addr;
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001136 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1137 pl08x_select_bus(pl08x->mem_buses,
1138 plchan->cd->periph_buses);
Russell King - ARM Linuxb207b4d2011-07-21 17:12:27 +01001139 }
Russell King - ARM Linuxf0fd9442011-01-03 22:45:57 +00001140
Linus Walleije8689e62010-09-28 15:57:37 +02001141 dev_dbg(&pl08x->adev->dev,
1142 "configured channel %s (%s) for %s, data width %d, "
Russell King - ARM Linux4983a042011-01-03 22:39:33 +00001143 "maxburst %d words, LE, CCTL=0x%08x\n",
Linus Walleije8689e62010-09-28 15:57:37 +02001144 dma_chan_name(chan), plchan->name,
Vinod Kouldb8196d2011-10-13 22:34:23 +05301145 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
Linus Walleije8689e62010-09-28 15:57:37 +02001146 addr_width,
1147 maxburst,
Russell King - ARM Linux4983a042011-01-03 22:39:33 +00001148 cctl);
Russell King - ARM Linuxf0fd9442011-01-03 22:45:57 +00001149
1150 return 0;
Linus Walleije8689e62010-09-28 15:57:37 +02001151}
1152
1153/*
1154 * Slave transactions callback to the slave device to allow
1155 * synchronization of slave DMA signals with the DMAC enable
1156 */
1157static void pl08x_issue_pending(struct dma_chan *chan)
1158{
1159 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
Linus Walleije8689e62010-09-28 15:57:37 +02001160 unsigned long flags;
1161
1162 spin_lock_irqsave(&plchan->lock, flags);
Russell King - ARM Linux9c0bb432011-01-03 22:32:05 +00001163 /* Something is already active, or we're waiting for a channel... */
1164 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1165 spin_unlock_irqrestore(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001166 return;
Russell King - ARM Linux9c0bb432011-01-03 22:32:05 +00001167 }
Linus Walleije8689e62010-09-28 15:57:37 +02001168
1169 /* Take the first element in the queue and execute it */
Russell King - ARM Linux15c17232011-01-03 22:44:36 +00001170 if (!list_empty(&plchan->pend_list)) {
Linus Walleije8689e62010-09-28 15:57:37 +02001171 struct pl08x_txd *next;
1172
Russell King - ARM Linux15c17232011-01-03 22:44:36 +00001173 next = list_first_entry(&plchan->pend_list,
Linus Walleije8689e62010-09-28 15:57:37 +02001174 struct pl08x_txd,
1175 node);
1176 list_del(&next->node);
Linus Walleije8689e62010-09-28 15:57:37 +02001177 plchan->state = PL08X_CHAN_RUNNING;
1178
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +00001179 pl08x_start_txd(plchan, next);
Linus Walleije8689e62010-09-28 15:57:37 +02001180 }
1181
1182 spin_unlock_irqrestore(&plchan->lock, flags);
1183}
1184
1185static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1186 struct pl08x_txd *txd)
1187{
Linus Walleije8689e62010-09-28 15:57:37 +02001188 struct pl08x_driver_data *pl08x = plchan->host;
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +00001189 unsigned long flags;
1190 int num_llis, ret;
Linus Walleije8689e62010-09-28 15:57:37 +02001191
1192 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
Russell King - ARM Linuxdafa7312011-01-03 22:31:45 +00001193 if (!num_llis) {
Viresh Kumar57001a62011-08-05 15:32:45 +05301194 spin_lock_irqsave(&plchan->lock, flags);
1195 pl08x_free_txd(pl08x, txd);
1196 spin_unlock_irqrestore(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001197 return -EINVAL;
Russell King - ARM Linuxdafa7312011-01-03 22:31:45 +00001198 }
Linus Walleije8689e62010-09-28 15:57:37 +02001199
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +00001200 spin_lock_irqsave(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001201
Linus Walleije8689e62010-09-28 15:57:37 +02001202 /*
1203 * See if we already have a physical channel allocated,
1204 * else this is the time to try to get one.
1205 */
1206 ret = prep_phy_channel(plchan, txd);
1207 if (ret) {
1208 /*
Russell King - ARM Linux501e67e2011-01-03 22:44:57 +00001209 * No physical channel was available.
1210 *
1211 * memcpy transfers can be sorted out at submission time.
1212 *
1213 * Slave transfers may have been denied due to platform
1214 * channel muxing restrictions. Since there is no guarantee
1215 * that this will ever be resolved, and the signal must be
1216 * acquired AFTER acquiring the physical channel, we will let
1217 * them be NACK:ed with -EBUSY here. The drivers can retry
1218 * the prep() call if they are eager on doing this using DMA.
Linus Walleije8689e62010-09-28 15:57:37 +02001219 */
1220 if (plchan->slave) {
1221 pl08x_free_txd_list(pl08x, plchan);
Russell King - ARM Linux501e67e2011-01-03 22:44:57 +00001222 pl08x_free_txd(pl08x, txd);
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +00001223 spin_unlock_irqrestore(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001224 return -EBUSY;
1225 }
Linus Walleije8689e62010-09-28 15:57:37 +02001226 } else
1227 /*
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001228 * Else we're all set, paused and ready to roll, status
1229 * will switch to PL08X_CHAN_RUNNING when we call
1230 * issue_pending(). If there is something running on the
1231 * channel already we don't change its state.
Linus Walleije8689e62010-09-28 15:57:37 +02001232 */
1233 if (plchan->state == PL08X_CHAN_IDLE)
1234 plchan->state = PL08X_CHAN_PAUSED;
1235
Russell King - ARM Linuxc370e592011-01-03 22:45:37 +00001236 spin_unlock_irqrestore(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001237
1238 return 0;
1239}
1240
Russell King - ARM Linuxc0428792011-01-03 22:43:56 +00001241static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1242 unsigned long flags)
Russell King - ARM Linuxac3cd202011-01-03 22:35:49 +00001243{
Viresh Kumarb201c112011-08-05 15:32:29 +05301244 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
Russell King - ARM Linuxac3cd202011-01-03 22:35:49 +00001245
1246 if (txd) {
1247 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
Russell King - ARM Linuxc0428792011-01-03 22:43:56 +00001248 txd->tx.flags = flags;
Russell King - ARM Linuxac3cd202011-01-03 22:35:49 +00001249 txd->tx.tx_submit = pl08x_tx_submit;
1250 INIT_LIST_HEAD(&txd->node);
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301251 INIT_LIST_HEAD(&txd->dsg_list);
Russell King - ARM Linux4983a042011-01-03 22:39:33 +00001252
1253 /* Always enable error and terminal interrupts */
1254 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1255 PL080_CONFIG_TC_IRQ_MASK;
Russell King - ARM Linuxac3cd202011-01-03 22:35:49 +00001256 }
1257 return txd;
1258}
1259
Linus Walleije8689e62010-09-28 15:57:37 +02001260/*
1261 * Initialize a descriptor to be used by memcpy submit
1262 */
1263static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1264 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1265 size_t len, unsigned long flags)
1266{
1267 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1268 struct pl08x_driver_data *pl08x = plchan->host;
1269 struct pl08x_txd *txd;
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301270 struct pl08x_sg *dsg;
Linus Walleije8689e62010-09-28 15:57:37 +02001271 int ret;
1272
Russell King - ARM Linuxc0428792011-01-03 22:43:56 +00001273 txd = pl08x_get_txd(plchan, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001274 if (!txd) {
1275 dev_err(&pl08x->adev->dev,
1276 "%s no memory for descriptor\n", __func__);
1277 return NULL;
1278 }
1279
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301280 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1281 if (!dsg) {
1282 pl08x_free_txd(pl08x, txd);
1283 dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
1284 __func__);
1285 return NULL;
1286 }
1287 list_add_tail(&dsg->node, &txd->dsg_list);
1288
Linus Walleije8689e62010-09-28 15:57:37 +02001289 txd->direction = DMA_NONE;
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301290 dsg->src_addr = src;
1291 dsg->dst_addr = dest;
1292 dsg->len = len;
Linus Walleije8689e62010-09-28 15:57:37 +02001293
1294 /* Set platform data for m2m */
Russell King - ARM Linux4983a042011-01-03 22:39:33 +00001295 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
Russell King - ARM Linuxc7da9a52011-01-03 22:40:53 +00001296 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1297 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
Russell King - ARM Linux4983a042011-01-03 22:39:33 +00001298
Linus Walleije8689e62010-09-28 15:57:37 +02001299 /* Both to be incremented or the code will break */
Russell King - ARM Linux70b5ed62011-01-03 22:40:13 +00001300 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
Russell King - ARM Linuxc7da9a52011-01-03 22:40:53 +00001301
Russell King - ARM Linuxc7da9a52011-01-03 22:40:53 +00001302 if (pl08x->vd->dualmaster)
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001303 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1304 pl08x->mem_buses);
Linus Walleije8689e62010-09-28 15:57:37 +02001305
Linus Walleije8689e62010-09-28 15:57:37 +02001306 ret = pl08x_prep_channel_resources(plchan, txd);
1307 if (ret)
1308 return NULL;
Linus Walleije8689e62010-09-28 15:57:37 +02001309
1310 return &txd->tx;
1311}
1312
Russell King - ARM Linux3e2a0372011-01-03 22:32:46 +00001313static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
Linus Walleije8689e62010-09-28 15:57:37 +02001314 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05301315 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05001316 unsigned long flags, void *context)
Linus Walleije8689e62010-09-28 15:57:37 +02001317{
1318 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1319 struct pl08x_driver_data *pl08x = plchan->host;
1320 struct pl08x_txd *txd;
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301321 struct pl08x_sg *dsg;
1322 struct scatterlist *sg;
1323 dma_addr_t slave_addr;
Viresh Kumar0a235652011-08-05 15:32:42 +05301324 int ret, tmp;
Linus Walleije8689e62010-09-28 15:57:37 +02001325
Linus Walleije8689e62010-09-28 15:57:37 +02001326 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301327 __func__, sgl->length, plchan->name);
Linus Walleije8689e62010-09-28 15:57:37 +02001328
Russell King - ARM Linuxc0428792011-01-03 22:43:56 +00001329 txd = pl08x_get_txd(plchan, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001330 if (!txd) {
1331 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1332 return NULL;
1333 }
1334
Linus Walleije8689e62010-09-28 15:57:37 +02001335 if (direction != plchan->runtime_direction)
1336 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1337 "the direction configured for the PrimeCell\n",
1338 __func__);
1339
1340 /*
1341 * Set up addresses, the PrimeCell configured address
1342 * will take precedence since this may configure the
1343 * channel target address dynamically at runtime.
1344 */
1345 txd->direction = direction;
Russell King - ARM Linuxc7da9a52011-01-03 22:40:53 +00001346
Vinod Kouldb8196d2011-10-13 22:34:23 +05301347 if (direction == DMA_MEM_TO_DEV) {
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001348 txd->cctl = plchan->dst_cctl;
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301349 slave_addr = plchan->dst_addr;
Vinod Kouldb8196d2011-10-13 22:34:23 +05301350 } else if (direction == DMA_DEV_TO_MEM) {
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001351 txd->cctl = plchan->src_cctl;
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301352 slave_addr = plchan->src_addr;
Linus Walleije8689e62010-09-28 15:57:37 +02001353 } else {
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301354 pl08x_free_txd(pl08x, txd);
Linus Walleije8689e62010-09-28 15:57:37 +02001355 dev_err(&pl08x->adev->dev,
1356 "%s direction unsupported\n", __func__);
1357 return NULL;
1358 }
Linus Walleije8689e62010-09-28 15:57:37 +02001359
Viresh Kumar8c9f7aa2012-02-01 16:12:20 +05301360 if (plchan->device_fc)
Vinod Kouldb8196d2011-10-13 22:34:23 +05301361 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
Viresh Kumar0a235652011-08-05 15:32:42 +05301362 PL080_FLOW_PER2MEM_PER;
1363 else
Vinod Kouldb8196d2011-10-13 22:34:23 +05301364 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
Viresh Kumar0a235652011-08-05 15:32:42 +05301365 PL080_FLOW_PER2MEM;
1366
1367 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1368
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301369 for_each_sg(sgl, sg, sg_len, tmp) {
1370 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1371 if (!dsg) {
1372 pl08x_free_txd(pl08x, txd);
1373 dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
1374 __func__);
1375 return NULL;
1376 }
1377 list_add_tail(&dsg->node, &txd->dsg_list);
1378
1379 dsg->len = sg_dma_len(sg);
Vinod Kouldb8196d2011-10-13 22:34:23 +05301380 if (direction == DMA_MEM_TO_DEV) {
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301381 dsg->src_addr = sg_phys(sg);
1382 dsg->dst_addr = slave_addr;
1383 } else {
1384 dsg->src_addr = slave_addr;
1385 dsg->dst_addr = sg_phys(sg);
1386 }
1387 }
1388
Linus Walleije8689e62010-09-28 15:57:37 +02001389 ret = pl08x_prep_channel_resources(plchan, txd);
1390 if (ret)
1391 return NULL;
Linus Walleije8689e62010-09-28 15:57:37 +02001392
1393 return &txd->tx;
1394}
1395
1396static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1397 unsigned long arg)
1398{
1399 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1400 struct pl08x_driver_data *pl08x = plchan->host;
1401 unsigned long flags;
1402 int ret = 0;
1403
1404 /* Controls applicable to inactive channels */
1405 if (cmd == DMA_SLAVE_CONFIG) {
Russell King - ARM Linuxf0fd9442011-01-03 22:45:57 +00001406 return dma_set_runtime_config(chan,
1407 (struct dma_slave_config *)arg);
Linus Walleije8689e62010-09-28 15:57:37 +02001408 }
1409
1410 /*
1411 * Anything succeeds on channels with no physical allocation and
1412 * no queued transfers.
1413 */
1414 spin_lock_irqsave(&plchan->lock, flags);
1415 if (!plchan->phychan && !plchan->at) {
1416 spin_unlock_irqrestore(&plchan->lock, flags);
1417 return 0;
1418 }
1419
1420 switch (cmd) {
1421 case DMA_TERMINATE_ALL:
1422 plchan->state = PL08X_CHAN_IDLE;
1423
1424 if (plchan->phychan) {
Russell King - ARM Linuxfb526212011-01-27 12:32:53 +00001425 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
Linus Walleije8689e62010-09-28 15:57:37 +02001426
1427 /*
1428 * Mark physical channel as free and free any slave
1429 * signal
1430 */
Russell King - ARM Linux8c8cc2b2011-01-03 22:36:09 +00001431 release_phy_channel(plchan);
Davide Ciminaghi88c08a32012-04-19 12:20:24 +02001432 plchan->phychan_hold = 0;
Linus Walleije8689e62010-09-28 15:57:37 +02001433 }
Linus Walleije8689e62010-09-28 15:57:37 +02001434 /* Dequeue jobs and free LLIs */
1435 if (plchan->at) {
1436 pl08x_free_txd(pl08x, plchan->at);
1437 plchan->at = NULL;
1438 }
1439 /* Dequeue jobs not yet fired as well */
1440 pl08x_free_txd_list(pl08x, plchan);
1441 break;
1442 case DMA_PAUSE:
1443 pl08x_pause_phy_chan(plchan->phychan);
1444 plchan->state = PL08X_CHAN_PAUSED;
1445 break;
1446 case DMA_RESUME:
1447 pl08x_resume_phy_chan(plchan->phychan);
1448 plchan->state = PL08X_CHAN_RUNNING;
1449 break;
1450 default:
1451 /* Unknown command */
1452 ret = -ENXIO;
1453 break;
1454 }
1455
1456 spin_unlock_irqrestore(&plchan->lock, flags);
1457
1458 return ret;
1459}
1460
1461bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1462{
Russell King - ARM Linux7703eac2011-08-31 09:34:35 +01001463 struct pl08x_dma_chan *plchan;
Linus Walleije8689e62010-09-28 15:57:37 +02001464 char *name = chan_id;
1465
Russell King - ARM Linux7703eac2011-08-31 09:34:35 +01001466 /* Reject channels for devices not bound to this driver */
1467 if (chan->device->dev->driver != &pl08x_amba_driver.drv)
1468 return false;
1469
1470 plchan = to_pl08x_chan(chan);
1471
Linus Walleije8689e62010-09-28 15:57:37 +02001472 /* Check that the channel is not taken! */
1473 if (!strcmp(plchan->name, name))
1474 return true;
1475
1476 return false;
1477}
1478
1479/*
1480 * Just check that the device is there and active
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001481 * TODO: turn this bit on/off depending on the number of physical channels
1482 * actually used, if it is zero... well shut it off. That will save some
1483 * power. Cut the clock at the same time.
Linus Walleije8689e62010-09-28 15:57:37 +02001484 */
1485static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1486{
Viresh Kumar48a59ef2011-08-05 15:32:34 +05301487 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
Linus Walleije8689e62010-09-28 15:57:37 +02001488}
1489
Russell King - ARM Linux3d992e12011-01-03 22:44:16 +00001490static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1491{
1492 struct device *dev = txd->tx.chan->device->dev;
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301493 struct pl08x_sg *dsg;
Russell King - ARM Linux3d992e12011-01-03 22:44:16 +00001494
1495 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1496 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301497 list_for_each_entry(dsg, &txd->dsg_list, node)
1498 dma_unmap_single(dev, dsg->src_addr, dsg->len,
1499 DMA_TO_DEVICE);
1500 else {
1501 list_for_each_entry(dsg, &txd->dsg_list, node)
1502 dma_unmap_page(dev, dsg->src_addr, dsg->len,
1503 DMA_TO_DEVICE);
1504 }
Russell King - ARM Linux3d992e12011-01-03 22:44:16 +00001505 }
1506 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1507 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301508 list_for_each_entry(dsg, &txd->dsg_list, node)
1509 dma_unmap_single(dev, dsg->dst_addr, dsg->len,
1510 DMA_FROM_DEVICE);
Russell King - ARM Linux3d992e12011-01-03 22:44:16 +00001511 else
Viresh Kumarb7f69d92011-08-05 15:32:43 +05301512 list_for_each_entry(dsg, &txd->dsg_list, node)
1513 dma_unmap_page(dev, dsg->dst_addr, dsg->len,
1514 DMA_FROM_DEVICE);
Russell King - ARM Linux3d992e12011-01-03 22:44:16 +00001515 }
1516}
1517
Linus Walleije8689e62010-09-28 15:57:37 +02001518static void pl08x_tasklet(unsigned long data)
1519{
1520 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
Linus Walleije8689e62010-09-28 15:57:37 +02001521 struct pl08x_driver_data *pl08x = plchan->host;
Russell King - ARM Linux858c21c2011-01-03 22:41:34 +00001522 struct pl08x_txd *txd;
Russell King - ARM Linuxbf072af2011-01-03 22:31:24 +00001523 unsigned long flags;
Linus Walleije8689e62010-09-28 15:57:37 +02001524
Russell King - ARM Linuxbf072af2011-01-03 22:31:24 +00001525 spin_lock_irqsave(&plchan->lock, flags);
Linus Walleije8689e62010-09-28 15:57:37 +02001526
Russell King - ARM Linux858c21c2011-01-03 22:41:34 +00001527 txd = plchan->at;
1528 plchan->at = NULL;
1529
1530 if (txd) {
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001531 /* Update last completed */
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +00001532 dma_cookie_complete(&txd->tx);
Linus Walleije8689e62010-09-28 15:57:37 +02001533 }
Russell King - ARM Linux8087aac2011-01-03 22:45:17 +00001534
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001535 /* If a new descriptor is queued, set it up plchan->at is NULL here */
Russell King - ARM Linux15c17232011-01-03 22:44:36 +00001536 if (!list_empty(&plchan->pend_list)) {
Linus Walleije8689e62010-09-28 15:57:37 +02001537 struct pl08x_txd *next;
1538
Russell King - ARM Linux15c17232011-01-03 22:44:36 +00001539 next = list_first_entry(&plchan->pend_list,
Linus Walleije8689e62010-09-28 15:57:37 +02001540 struct pl08x_txd,
1541 node);
1542 list_del(&next->node);
Russell King - ARM Linuxc885bee2011-01-03 22:38:52 +00001543
1544 pl08x_start_txd(plchan, next);
Russell King - ARM Linux8087aac2011-01-03 22:45:17 +00001545 } else if (plchan->phychan_hold) {
1546 /*
1547 * This channel is still in use - we have a new txd being
1548 * prepared and will soon be queued. Don't give up the
1549 * physical channel.
1550 */
Linus Walleije8689e62010-09-28 15:57:37 +02001551 } else {
1552 struct pl08x_dma_chan *waiting = NULL;
1553
1554 /*
1555 * No more jobs, so free up the physical channel
1556 * Free any allocated signal on slave transfers too
1557 */
Russell King - ARM Linux8c8cc2b2011-01-03 22:36:09 +00001558 release_phy_channel(plchan);
Linus Walleije8689e62010-09-28 15:57:37 +02001559 plchan->state = PL08X_CHAN_IDLE;
1560
1561 /*
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001562 * And NOW before anyone else can grab that free:d up
1563 * physical channel, see if there is some memcpy pending
1564 * that seriously needs to start because of being stacked
1565 * up while we were choking the physical channels with data.
Linus Walleije8689e62010-09-28 15:57:37 +02001566 */
1567 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1568 chan.device_node) {
Viresh Kumar3e27ee82011-08-05 15:32:27 +05301569 if (waiting->state == PL08X_CHAN_WAITING &&
1570 waiting->waiting != NULL) {
Linus Walleije8689e62010-09-28 15:57:37 +02001571 int ret;
1572
1573 /* This should REALLY not fail now */
1574 ret = prep_phy_channel(waiting,
1575 waiting->waiting);
1576 BUG_ON(ret);
Russell King - ARM Linux8087aac2011-01-03 22:45:17 +00001577 waiting->phychan_hold--;
Linus Walleije8689e62010-09-28 15:57:37 +02001578 waiting->state = PL08X_CHAN_RUNNING;
1579 waiting->waiting = NULL;
1580 pl08x_issue_pending(&waiting->chan);
1581 break;
1582 }
1583 }
1584 }
1585
Russell King - ARM Linuxbf072af2011-01-03 22:31:24 +00001586 spin_unlock_irqrestore(&plchan->lock, flags);
Russell King - ARM Linux858c21c2011-01-03 22:41:34 +00001587
Russell King - ARM Linux3d992e12011-01-03 22:44:16 +00001588 if (txd) {
1589 dma_async_tx_callback callback = txd->tx.callback;
1590 void *callback_param = txd->tx.callback_param;
1591
1592 /* Don't try to unmap buffers on slave channels */
1593 if (!plchan->slave)
1594 pl08x_unmap_buffers(txd);
1595
1596 /* Free the descriptor */
1597 spin_lock_irqsave(&plchan->lock, flags);
1598 pl08x_free_txd(pl08x, txd);
1599 spin_unlock_irqrestore(&plchan->lock, flags);
1600
1601 /* Callback to signal completion */
1602 if (callback)
1603 callback(callback_param);
1604 }
Linus Walleije8689e62010-09-28 15:57:37 +02001605}
1606
1607static irqreturn_t pl08x_irq(int irq, void *dev)
1608{
1609 struct pl08x_driver_data *pl08x = dev;
Viresh Kumar28da2832011-08-05 15:32:36 +05301610 u32 mask = 0, err, tc, i;
Linus Walleije8689e62010-09-28 15:57:37 +02001611
Viresh Kumar28da2832011-08-05 15:32:36 +05301612 /* check & clear - ERR & TC interrupts */
1613 err = readl(pl08x->base + PL080_ERR_STATUS);
1614 if (err) {
1615 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1616 __func__, err);
1617 writel(err, pl08x->base + PL080_ERR_CLEAR);
Linus Walleije8689e62010-09-28 15:57:37 +02001618 }
Viresh Kumar28da2832011-08-05 15:32:36 +05301619 tc = readl(pl08x->base + PL080_INT_STATUS);
1620 if (tc)
1621 writel(tc, pl08x->base + PL080_TC_CLEAR);
1622
1623 if (!err && !tc)
1624 return IRQ_NONE;
1625
Linus Walleije8689e62010-09-28 15:57:37 +02001626 for (i = 0; i < pl08x->vd->channels; i++) {
Viresh Kumar28da2832011-08-05 15:32:36 +05301627 if (((1 << i) & err) || ((1 << i) & tc)) {
Linus Walleije8689e62010-09-28 15:57:37 +02001628 /* Locate physical channel */
1629 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1630 struct pl08x_dma_chan *plchan = phychan->serving;
1631
Viresh Kumar28da2832011-08-05 15:32:36 +05301632 if (!plchan) {
1633 dev_err(&pl08x->adev->dev,
1634 "%s Error TC interrupt on unused channel: 0x%08x\n",
1635 __func__, i);
1636 continue;
1637 }
1638
Linus Walleije8689e62010-09-28 15:57:37 +02001639 /* Schedule tasklet on this channel */
1640 tasklet_schedule(&plchan->tasklet);
Linus Walleije8689e62010-09-28 15:57:37 +02001641 mask |= (1 << i);
1642 }
1643 }
Linus Walleije8689e62010-09-28 15:57:37 +02001644
1645 return mask ? IRQ_HANDLED : IRQ_NONE;
1646}
1647
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001648static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1649{
1650 u32 cctl = pl08x_cctl(chan->cd->cctl);
1651
1652 chan->slave = true;
1653 chan->name = chan->cd->bus_id;
1654 chan->src_addr = chan->cd->addr;
1655 chan->dst_addr = chan->cd->addr;
1656 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1657 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1658 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1659 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1660}
1661
Linus Walleije8689e62010-09-28 15:57:37 +02001662/*
1663 * Initialise the DMAC memcpy/slave channels.
1664 * Make a local wrapper to hold required data
1665 */
1666static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
Viresh Kumar3e27ee82011-08-05 15:32:27 +05301667 struct dma_device *dmadev, unsigned int channels, bool slave)
Linus Walleije8689e62010-09-28 15:57:37 +02001668{
1669 struct pl08x_dma_chan *chan;
1670 int i;
1671
1672 INIT_LIST_HEAD(&dmadev->channels);
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001673
Linus Walleije8689e62010-09-28 15:57:37 +02001674 /*
1675 * Register as many many memcpy as we have physical channels,
1676 * we won't always be able to use all but the code will have
1677 * to cope with that situation.
1678 */
1679 for (i = 0; i < channels; i++) {
Viresh Kumarb201c112011-08-05 15:32:29 +05301680 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
Linus Walleije8689e62010-09-28 15:57:37 +02001681 if (!chan) {
1682 dev_err(&pl08x->adev->dev,
1683 "%s no memory for channel\n", __func__);
1684 return -ENOMEM;
1685 }
1686
1687 chan->host = pl08x;
1688 chan->state = PL08X_CHAN_IDLE;
1689
1690 if (slave) {
Linus Walleije8689e62010-09-28 15:57:37 +02001691 chan->cd = &pl08x->pd->slave_channels[i];
Russell King - ARM Linux121c8472011-07-21 17:13:48 +01001692 pl08x_dma_slave_init(chan);
Linus Walleije8689e62010-09-28 15:57:37 +02001693 } else {
1694 chan->cd = &pl08x->pd->memcpy_channel;
1695 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1696 if (!chan->name) {
1697 kfree(chan);
1698 return -ENOMEM;
1699 }
1700 }
Russell King - ARM Linuxb58b6b52011-01-03 22:34:48 +00001701 if (chan->cd->circular_buffer) {
1702 dev_err(&pl08x->adev->dev,
1703 "channel %s: circular buffers not supported\n",
1704 chan->name);
1705 kfree(chan);
1706 continue;
1707 }
Viresh Kumar175a5e62011-08-05 15:32:32 +05301708 dev_dbg(&pl08x->adev->dev,
Linus Walleije8689e62010-09-28 15:57:37 +02001709 "initialize virtual channel \"%s\"\n",
1710 chan->name);
1711
1712 chan->chan.device = dmadev;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001713 dma_cookie_init(&chan->chan);
Linus Walleije8689e62010-09-28 15:57:37 +02001714
1715 spin_lock_init(&chan->lock);
Russell King - ARM Linux15c17232011-01-03 22:44:36 +00001716 INIT_LIST_HEAD(&chan->pend_list);
Linus Walleije8689e62010-09-28 15:57:37 +02001717 tasklet_init(&chan->tasklet, pl08x_tasklet,
1718 (unsigned long) chan);
1719
1720 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1721 }
1722 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1723 i, slave ? "slave" : "memcpy");
1724 return i;
1725}
1726
1727static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1728{
1729 struct pl08x_dma_chan *chan = NULL;
1730 struct pl08x_dma_chan *next;
1731
1732 list_for_each_entry_safe(chan,
1733 next, &dmadev->channels, chan.device_node) {
1734 list_del(&chan->chan.device_node);
1735 kfree(chan);
1736 }
1737}
1738
1739#ifdef CONFIG_DEBUG_FS
1740static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1741{
1742 switch (state) {
1743 case PL08X_CHAN_IDLE:
1744 return "idle";
1745 case PL08X_CHAN_RUNNING:
1746 return "running";
1747 case PL08X_CHAN_PAUSED:
1748 return "paused";
1749 case PL08X_CHAN_WAITING:
1750 return "waiting";
1751 default:
1752 break;
1753 }
1754 return "UNKNOWN STATE";
1755}
1756
1757static int pl08x_debugfs_show(struct seq_file *s, void *data)
1758{
1759 struct pl08x_driver_data *pl08x = s->private;
1760 struct pl08x_dma_chan *chan;
1761 struct pl08x_phy_chan *ch;
1762 unsigned long flags;
1763 int i;
1764
1765 seq_printf(s, "PL08x physical channels:\n");
1766 seq_printf(s, "CHANNEL:\tUSER:\n");
1767 seq_printf(s, "--------\t-----\n");
1768 for (i = 0; i < pl08x->vd->channels; i++) {
1769 struct pl08x_dma_chan *virt_chan;
1770
1771 ch = &pl08x->phy_chans[i];
1772
1773 spin_lock_irqsave(&ch->lock, flags);
1774 virt_chan = ch->serving;
1775
1776 seq_printf(s, "%d\t\t%s\n",
1777 ch->id, virt_chan ? virt_chan->name : "(none)");
1778
1779 spin_unlock_irqrestore(&ch->lock, flags);
1780 }
1781
1782 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1783 seq_printf(s, "CHANNEL:\tSTATE:\n");
1784 seq_printf(s, "--------\t------\n");
1785 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
Russell King - ARM Linux3e2a0372011-01-03 22:32:46 +00001786 seq_printf(s, "%s\t\t%s\n", chan->name,
Linus Walleije8689e62010-09-28 15:57:37 +02001787 pl08x_state_str(chan->state));
1788 }
1789
1790 seq_printf(s, "\nPL08x virtual slave channels:\n");
1791 seq_printf(s, "CHANNEL:\tSTATE:\n");
1792 seq_printf(s, "--------\t------\n");
1793 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
Russell King - ARM Linux3e2a0372011-01-03 22:32:46 +00001794 seq_printf(s, "%s\t\t%s\n", chan->name,
Linus Walleije8689e62010-09-28 15:57:37 +02001795 pl08x_state_str(chan->state));
1796 }
1797
1798 return 0;
1799}
1800
1801static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1802{
1803 return single_open(file, pl08x_debugfs_show, inode->i_private);
1804}
1805
1806static const struct file_operations pl08x_debugfs_operations = {
1807 .open = pl08x_debugfs_open,
1808 .read = seq_read,
1809 .llseek = seq_lseek,
1810 .release = single_release,
1811};
1812
1813static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1814{
1815 /* Expose a simple debugfs interface to view all clocks */
Viresh Kumar3e27ee82011-08-05 15:32:27 +05301816 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1817 S_IFREG | S_IRUGO, NULL, pl08x,
1818 &pl08x_debugfs_operations);
Linus Walleije8689e62010-09-28 15:57:37 +02001819}
1820
1821#else
1822static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1823{
1824}
1825#endif
1826
Russell Kingaa25afa2011-02-19 15:55:00 +00001827static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
Linus Walleije8689e62010-09-28 15:57:37 +02001828{
1829 struct pl08x_driver_data *pl08x;
Russell King - ARM Linuxf96ca9e2011-01-03 22:35:08 +00001830 const struct vendor_data *vd = id->data;
Linus Walleije8689e62010-09-28 15:57:37 +02001831 int ret = 0;
1832 int i;
1833
1834 ret = amba_request_regions(adev, NULL);
1835 if (ret)
1836 return ret;
1837
1838 /* Create the driver state holder */
Viresh Kumarb201c112011-08-05 15:32:29 +05301839 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
Linus Walleije8689e62010-09-28 15:57:37 +02001840 if (!pl08x) {
1841 ret = -ENOMEM;
1842 goto out_no_pl08x;
1843 }
1844
Viresh Kumarb7b60182011-08-05 15:32:33 +05301845 pm_runtime_set_active(&adev->dev);
1846 pm_runtime_enable(&adev->dev);
1847
Linus Walleije8689e62010-09-28 15:57:37 +02001848 /* Initialize memcpy engine */
1849 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1850 pl08x->memcpy.dev = &adev->dev;
1851 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1852 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1853 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1854 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1855 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1856 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1857 pl08x->memcpy.device_control = pl08x_control;
1858
1859 /* Initialize slave engine */
1860 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1861 pl08x->slave.dev = &adev->dev;
1862 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1863 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1864 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1865 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1866 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1867 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1868 pl08x->slave.device_control = pl08x_control;
1869
1870 /* Get the platform data */
1871 pl08x->pd = dev_get_platdata(&adev->dev);
1872 if (!pl08x->pd) {
1873 dev_err(&adev->dev, "no platform data supplied\n");
1874 goto out_no_platdata;
1875 }
1876
1877 /* Assign useful pointers to the driver state */
1878 pl08x->adev = adev;
1879 pl08x->vd = vd;
1880
Russell King - ARM Linux30749cb2011-01-03 22:41:13 +00001881 /* By default, AHB1 only. If dualmaster, from platform */
1882 pl08x->lli_buses = PL08X_AHB1;
1883 pl08x->mem_buses = PL08X_AHB1;
1884 if (pl08x->vd->dualmaster) {
1885 pl08x->lli_buses = pl08x->pd->lli_buses;
1886 pl08x->mem_buses = pl08x->pd->mem_buses;
1887 }
1888
Linus Walleije8689e62010-09-28 15:57:37 +02001889 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1890 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1891 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1892 if (!pl08x->pool) {
1893 ret = -ENOMEM;
1894 goto out_no_lli_pool;
1895 }
1896
1897 spin_lock_init(&pl08x->lock);
1898
1899 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1900 if (!pl08x->base) {
1901 ret = -ENOMEM;
1902 goto out_no_ioremap;
1903 }
1904
1905 /* Turn on the PL08x */
1906 pl08x_ensure_on(pl08x);
1907
Russell King - ARM Linux94ae8522011-01-16 20:18:05 +00001908 /* Attach the interrupt handler */
Linus Walleije8689e62010-09-28 15:57:37 +02001909 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1910 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1911
1912 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
Russell King - ARM Linuxb05cd8f2011-01-03 22:33:26 +00001913 DRIVER_NAME, pl08x);
Linus Walleije8689e62010-09-28 15:57:37 +02001914 if (ret) {
1915 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1916 __func__, adev->irq[0]);
1917 goto out_no_irq;
1918 }
1919
1920 /* Initialize physical channels */
Viresh Kumarb201c112011-08-05 15:32:29 +05301921 pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)),
Linus Walleije8689e62010-09-28 15:57:37 +02001922 GFP_KERNEL);
1923 if (!pl08x->phy_chans) {
1924 dev_err(&adev->dev, "%s failed to allocate "
1925 "physical channel holders\n",
1926 __func__);
1927 goto out_no_phychans;
1928 }
1929
1930 for (i = 0; i < vd->channels; i++) {
1931 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1932
1933 ch->id = i;
1934 ch->base = pl08x->base + PL080_Cx_BASE(i);
1935 spin_lock_init(&ch->lock);
1936 ch->serving = NULL;
1937 ch->signal = -1;
Viresh Kumar175a5e62011-08-05 15:32:32 +05301938 dev_dbg(&adev->dev, "physical channel %d is %s\n",
1939 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
Linus Walleije8689e62010-09-28 15:57:37 +02001940 }
1941
1942 /* Register as many memcpy channels as there are physical channels */
1943 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1944 pl08x->vd->channels, false);
1945 if (ret <= 0) {
1946 dev_warn(&pl08x->adev->dev,
1947 "%s failed to enumerate memcpy channels - %d\n",
1948 __func__, ret);
1949 goto out_no_memcpy;
1950 }
1951 pl08x->memcpy.chancnt = ret;
1952
1953 /* Register slave channels */
1954 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
Viresh Kumar3e27ee82011-08-05 15:32:27 +05301955 pl08x->pd->num_slave_channels, true);
Linus Walleije8689e62010-09-28 15:57:37 +02001956 if (ret <= 0) {
1957 dev_warn(&pl08x->adev->dev,
1958 "%s failed to enumerate slave channels - %d\n",
1959 __func__, ret);
1960 goto out_no_slave;
1961 }
1962 pl08x->slave.chancnt = ret;
1963
1964 ret = dma_async_device_register(&pl08x->memcpy);
1965 if (ret) {
1966 dev_warn(&pl08x->adev->dev,
1967 "%s failed to register memcpy as an async device - %d\n",
1968 __func__, ret);
1969 goto out_no_memcpy_reg;
1970 }
1971
1972 ret = dma_async_device_register(&pl08x->slave);
1973 if (ret) {
1974 dev_warn(&pl08x->adev->dev,
1975 "%s failed to register slave as an async device - %d\n",
1976 __func__, ret);
1977 goto out_no_slave_reg;
1978 }
1979
1980 amba_set_drvdata(adev, pl08x);
1981 init_pl08x_debugfs(pl08x);
Russell King - ARM Linuxb05cd8f2011-01-03 22:33:26 +00001982 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1983 amba_part(adev), amba_rev(adev),
1984 (unsigned long long)adev->res.start, adev->irq[0]);
Viresh Kumarb7b60182011-08-05 15:32:33 +05301985
1986 pm_runtime_put(&adev->dev);
Linus Walleije8689e62010-09-28 15:57:37 +02001987 return 0;
1988
1989out_no_slave_reg:
1990 dma_async_device_unregister(&pl08x->memcpy);
1991out_no_memcpy_reg:
1992 pl08x_free_virtual_channels(&pl08x->slave);
1993out_no_slave:
1994 pl08x_free_virtual_channels(&pl08x->memcpy);
1995out_no_memcpy:
1996 kfree(pl08x->phy_chans);
1997out_no_phychans:
1998 free_irq(adev->irq[0], pl08x);
1999out_no_irq:
2000 iounmap(pl08x->base);
2001out_no_ioremap:
2002 dma_pool_destroy(pl08x->pool);
2003out_no_lli_pool:
2004out_no_platdata:
Viresh Kumarb7b60182011-08-05 15:32:33 +05302005 pm_runtime_put(&adev->dev);
2006 pm_runtime_disable(&adev->dev);
2007
Linus Walleije8689e62010-09-28 15:57:37 +02002008 kfree(pl08x);
2009out_no_pl08x:
2010 amba_release_regions(adev);
2011 return ret;
2012}
2013
2014/* PL080 has 8 channels and the PL080 have just 2 */
2015static struct vendor_data vendor_pl080 = {
Linus Walleije8689e62010-09-28 15:57:37 +02002016 .channels = 8,
2017 .dualmaster = true,
2018};
2019
2020static struct vendor_data vendor_pl081 = {
Linus Walleije8689e62010-09-28 15:57:37 +02002021 .channels = 2,
2022 .dualmaster = false,
2023};
2024
2025static struct amba_id pl08x_ids[] = {
2026 /* PL080 */
2027 {
2028 .id = 0x00041080,
2029 .mask = 0x000fffff,
2030 .data = &vendor_pl080,
2031 },
2032 /* PL081 */
2033 {
2034 .id = 0x00041081,
2035 .mask = 0x000fffff,
2036 .data = &vendor_pl081,
2037 },
2038 /* Nomadik 8815 PL080 variant */
2039 {
2040 .id = 0x00280880,
2041 .mask = 0x00ffffff,
2042 .data = &vendor_pl080,
2043 },
2044 { 0, 0 },
2045};
2046
Dave Martin037566d2011-10-05 15:15:20 +01002047MODULE_DEVICE_TABLE(amba, pl08x_ids);
2048
Linus Walleije8689e62010-09-28 15:57:37 +02002049static struct amba_driver pl08x_amba_driver = {
2050 .drv.name = DRIVER_NAME,
2051 .id_table = pl08x_ids,
2052 .probe = pl08x_probe,
2053};
2054
2055static int __init pl08x_init(void)
2056{
2057 int retval;
2058 retval = amba_driver_register(&pl08x_amba_driver);
2059 if (retval)
2060 printk(KERN_WARNING DRIVER_NAME
Russell King - ARM Linuxe8b5e112011-01-03 22:30:24 +00002061 "failed to register as an AMBA device (%d)\n",
Linus Walleije8689e62010-09-28 15:57:37 +02002062 retval);
2063 return retval;
2064}
2065subsys_initcall(pl08x_init);