Marcelo Tosatti | de957c8 | 2005-10-28 17:46:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. |
| 3 | * |
| 4 | * (C) 1999-2000 Magnus Damm <damm@bitsmart.com> |
| 5 | * (C) 2001-2002 Montavista Software, Inc. |
| 6 | * <mlocke@mvista.com> |
| 7 | * |
| 8 | * Support for two slots by Cyclades Corporation |
| 9 | * <oliver.kurth@cyclades.de> |
| 10 | * Further fixes, v2.6 kernel port |
| 11 | * <marcelo.tosatti@cyclades.com> |
| 12 | * |
| 13 | * "The ExCA standard specifies that socket controllers should provide |
| 14 | * two IO and five memory windows per socket, which can be independently |
| 15 | * configured and positioned in the host address space and mapped to |
| 16 | * arbitrary segments of card address space. " - David A Hinds. 1999 |
| 17 | * |
| 18 | * This controller does _not_ meet the ExCA standard. |
| 19 | * |
| 20 | * m8xx pcmcia controller brief info: |
| 21 | * + 8 windows (attrib, mem, i/o) |
| 22 | * + up to two slots (SLOT_A and SLOT_B) |
| 23 | * + inputpins, outputpins, event and mask registers. |
| 24 | * - no offset register. sigh. |
| 25 | * |
| 26 | * Because of the lacking offset register we must map the whole card. |
| 27 | * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. |
| 28 | * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO |
| 29 | * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. |
| 30 | * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. |
| 31 | * They are maximum 64KByte each... |
| 32 | */ |
| 33 | |
| 34 | #include <linux/module.h> |
| 35 | #include <linux/init.h> |
| 36 | #include <linux/types.h> |
| 37 | #include <linux/fcntl.h> |
| 38 | #include <linux/string.h> |
| 39 | |
| 40 | #include <asm/io.h> |
| 41 | #include <asm/bitops.h> |
Marcelo Tosatti | de957c8 | 2005-10-28 17:46:13 -0700 | [diff] [blame] | 42 | #include <asm/system.h> |
| 43 | |
| 44 | #include <linux/kernel.h> |
| 45 | #include <linux/errno.h> |
| 46 | #include <linux/sched.h> |
| 47 | #include <linux/slab.h> |
| 48 | #include <linux/timer.h> |
| 49 | #include <linux/ioport.h> |
| 50 | #include <linux/delay.h> |
| 51 | #include <linux/interrupt.h> |
Marcelo Tosatti | e346315 | 2005-11-05 13:03:32 -0200 | [diff] [blame] | 52 | #include <linux/platform_device.h> |
Marcelo Tosatti | de957c8 | 2005-10-28 17:46:13 -0700 | [diff] [blame] | 53 | |
| 54 | #include <asm/mpc8xx.h> |
| 55 | #include <asm/8xx_immap.h> |
| 56 | #include <asm/irq.h> |
| 57 | |
| 58 | #include <pcmcia/version.h> |
| 59 | #include <pcmcia/cs_types.h> |
| 60 | #include <pcmcia/cs.h> |
| 61 | #include <pcmcia/ss.h> |
| 62 | |
| 63 | #ifdef PCMCIA_DEBUG |
| 64 | static int pc_debug = PCMCIA_DEBUG; |
| 65 | module_param(pc_debug, int, 0); |
| 66 | #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args); |
| 67 | #else |
| 68 | #define dprintk(args...) |
| 69 | #endif |
| 70 | |
| 71 | #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) |
| 72 | #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) |
| 73 | |
| 74 | static const char *version = "Version 0.06, Aug 2005"; |
| 75 | MODULE_LICENSE("Dual MPL/GPL"); |
| 76 | |
| 77 | #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) |
| 78 | |
| 79 | /* The RPX series use SLOT_B */ |
| 80 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) |
| 81 | #define CONFIG_PCMCIA_SLOT_B |
| 82 | #define CONFIG_BD_IS_MHZ |
| 83 | #endif |
| 84 | |
| 85 | /* The ADS board use SLOT_A */ |
| 86 | #ifdef CONFIG_ADS |
| 87 | #define CONFIG_PCMCIA_SLOT_A |
| 88 | #define CONFIG_BD_IS_MHZ |
| 89 | #endif |
| 90 | |
| 91 | /* The FADS series are a mess */ |
| 92 | #ifdef CONFIG_FADS |
| 93 | #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) |
| 94 | #define CONFIG_PCMCIA_SLOT_A |
| 95 | #else |
| 96 | #define CONFIG_PCMCIA_SLOT_B |
| 97 | #endif |
| 98 | #endif |
| 99 | |
| 100 | /* Cyclades ACS uses both slots */ |
| 101 | #ifdef CONFIG_PRxK |
| 102 | #define CONFIG_PCMCIA_SLOT_A |
| 103 | #define CONFIG_PCMCIA_SLOT_B |
| 104 | #endif |
| 105 | |
| 106 | #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ |
| 107 | |
| 108 | #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) |
| 109 | |
| 110 | #define PCMCIA_SOCKETS_NO 2 |
| 111 | /* We have only 8 windows, dualsocket support will be limited. */ |
| 112 | #define PCMCIA_MEM_WIN_NO 2 |
| 113 | #define PCMCIA_IO_WIN_NO 2 |
| 114 | #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" |
| 115 | |
| 116 | #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) |
| 117 | |
| 118 | #define PCMCIA_SOCKETS_NO 1 |
| 119 | /* full support for one slot */ |
| 120 | #define PCMCIA_MEM_WIN_NO 5 |
| 121 | #define PCMCIA_IO_WIN_NO 2 |
| 122 | |
| 123 | /* define _slot_ to be able to optimize macros */ |
| 124 | |
| 125 | #ifdef CONFIG_PCMCIA_SLOT_A |
| 126 | #define _slot_ 0 |
| 127 | #define PCMCIA_SLOT_MSG "SLOT_A" |
| 128 | #else |
| 129 | #define _slot_ 1 |
| 130 | #define PCMCIA_SLOT_MSG "SLOT_B" |
| 131 | #endif |
| 132 | |
| 133 | #else |
| 134 | #error m8xx_pcmcia: Bad configuration! |
| 135 | #endif |
| 136 | |
| 137 | /* ------------------------------------------------------------------------- */ |
| 138 | |
| 139 | #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ |
| 140 | #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ |
| 141 | #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ |
| 142 | |
| 143 | #define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */ |
| 144 | |
| 145 | /* ------------------------------------------------------------------------- */ |
| 146 | |
| 147 | /* 2.4.x and newer has this always in HZ */ |
| 148 | #define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq)) |
| 149 | |
| 150 | static int pcmcia_schlvl = PCMCIA_SCHLVL; |
| 151 | |
| 152 | static spinlock_t events_lock = SPIN_LOCK_UNLOCKED; |
| 153 | |
| 154 | |
| 155 | #define PCMCIA_SOCKET_KEY_5V 1 |
| 156 | #define PCMCIA_SOCKET_KEY_LV 2 |
| 157 | |
| 158 | /* look up table for pgcrx registers */ |
| 159 | static u32 *m8xx_pgcrx[2] = { |
| 160 | &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra, |
| 161 | &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb |
| 162 | }; |
| 163 | |
| 164 | /* |
| 165 | * This structure is used to address each window in the PCMCIA controller. |
| 166 | * |
| 167 | * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly |
| 168 | * after pcmcia_win[n]... |
| 169 | */ |
| 170 | |
| 171 | struct pcmcia_win { |
| 172 | u32 br; |
| 173 | u32 or; |
| 174 | }; |
| 175 | |
| 176 | /* |
| 177 | * For some reason the hardware guys decided to make both slots share |
| 178 | * some registers. |
| 179 | * |
| 180 | * Could someone invent object oriented hardware ? |
| 181 | * |
| 182 | * The macros are used to get the right bit from the registers. |
| 183 | * SLOT_A : slot = 0 |
| 184 | * SLOT_B : slot = 1 |
| 185 | */ |
| 186 | |
| 187 | #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) |
| 188 | #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) |
| 189 | #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) |
| 190 | #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) |
| 191 | |
| 192 | #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) |
| 193 | #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) |
| 194 | #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) |
| 195 | #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) |
| 196 | #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) |
| 197 | #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) |
| 198 | #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) |
| 199 | #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) |
| 200 | #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) |
| 201 | #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) |
| 202 | #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) |
| 203 | |
| 204 | #define M8XX_PCMCIA_POR_VALID 0x00000001 |
| 205 | #define M8XX_PCMCIA_POR_WRPROT 0x00000002 |
| 206 | #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 |
| 207 | #define M8XX_PCMCIA_POR_IO 0x00000018 |
| 208 | #define M8XX_PCMCIA_POR_16BIT 0x00000040 |
| 209 | |
| 210 | #define M8XX_PGCRX(slot) m8xx_pgcrx[slot] |
| 211 | |
| 212 | #define M8XX_PGCRX_CXOE 0x00000080 |
| 213 | #define M8XX_PGCRX_CXRESET 0x00000040 |
| 214 | |
| 215 | /* we keep one lookup table per socket to check flags */ |
| 216 | |
| 217 | #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ |
| 218 | |
| 219 | struct event_table { |
| 220 | u32 regbit; |
| 221 | u32 eventbit; |
| 222 | }; |
| 223 | |
| 224 | struct socket_info { |
| 225 | void (*handler)(void *info, u32 events); |
| 226 | void *info; |
| 227 | |
| 228 | u32 slot; |
| 229 | |
| 230 | socket_state_t state; |
| 231 | struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; |
| 232 | struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; |
| 233 | struct event_table events[PCMCIA_EVENTS_MAX]; |
| 234 | struct pcmcia_socket socket; |
| 235 | }; |
| 236 | |
| 237 | static struct socket_info socket[PCMCIA_SOCKETS_NO]; |
| 238 | |
| 239 | /* |
| 240 | * Search this table to see if the windowsize is |
| 241 | * supported... |
| 242 | */ |
| 243 | |
| 244 | #define M8XX_SIZES_NO 32 |
| 245 | |
| 246 | static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = |
| 247 | { |
| 248 | 0x00000001, 0x00000002, 0x00000008, 0x00000004, |
| 249 | 0x00000080, 0x00000040, 0x00000010, 0x00000020, |
| 250 | 0x00008000, 0x00004000, 0x00001000, 0x00002000, |
| 251 | 0x00000100, 0x00000200, 0x00000800, 0x00000400, |
| 252 | |
| 253 | 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 254 | 0x01000000, 0x02000000, 0xffffffff, 0x04000000, |
| 255 | 0x00010000, 0x00020000, 0x00080000, 0x00040000, |
| 256 | 0x00800000, 0x00400000, 0x00100000, 0x00200000 |
| 257 | }; |
| 258 | |
| 259 | /* ------------------------------------------------------------------------- */ |
| 260 | |
| 261 | static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs); |
| 262 | |
| 263 | #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ |
| 264 | |
| 265 | /* ------------------------------------------------------------------------- */ |
| 266 | /* board specific stuff: */ |
| 267 | /* voltage_set(), hardware_enable() and hardware_disable() */ |
| 268 | /* ------------------------------------------------------------------------- */ |
| 269 | /* RPX Boards from Embedded Planet */ |
| 270 | |
| 271 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) |
| 272 | |
| 273 | /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. |
| 274 | * SYPCR is write once only, therefore must the slowest memory be faster |
| 275 | * than the bus monitor or we will get a machine check due to the bus timeout. |
| 276 | */ |
| 277 | |
| 278 | #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" |
| 279 | |
| 280 | #undef PCMCIA_BMT_LIMIT |
| 281 | #define PCMCIA_BMT_LIMIT (6*8) |
| 282 | |
| 283 | static int voltage_set(int slot, int vcc, int vpp) |
| 284 | { |
| 285 | u32 reg = 0; |
| 286 | |
| 287 | switch(vcc) { |
| 288 | case 0: break; |
| 289 | case 33: |
| 290 | reg |= BCSR1_PCVCTL4; |
| 291 | break; |
| 292 | case 50: |
| 293 | reg |= BCSR1_PCVCTL5; |
| 294 | break; |
| 295 | default: |
| 296 | return 1; |
| 297 | } |
| 298 | |
| 299 | switch(vpp) { |
| 300 | case 0: break; |
| 301 | case 33: |
| 302 | case 50: |
| 303 | if(vcc == vpp) |
| 304 | reg |= BCSR1_PCVCTL6; |
| 305 | else |
| 306 | return 1; |
| 307 | break; |
| 308 | case 120: |
| 309 | reg |= BCSR1_PCVCTL7; |
| 310 | default: |
| 311 | return 1; |
| 312 | } |
| 313 | |
| 314 | if(!((vcc == 50) || (vcc == 0))) |
| 315 | return 1; |
| 316 | |
| 317 | /* first, turn off all power */ |
| 318 | |
| 319 | out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7)); |
| 320 | |
| 321 | /* enable new powersettings */ |
| 322 | |
| 323 | out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg); |
| 324 | |
| 325 | return 0; |
| 326 | } |
| 327 | |
| 328 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V |
| 329 | #define hardware_enable(_slot_) /* No hardware to enable */ |
| 330 | #define hardware_disable(_slot_) /* No hardware to disable */ |
| 331 | |
| 332 | #endif /* CONFIG_RPXCLASSIC */ |
| 333 | |
| 334 | /* FADS Boards from Motorola */ |
| 335 | |
| 336 | #if defined(CONFIG_FADS) |
| 337 | |
| 338 | #define PCMCIA_BOARD_MSG "FADS" |
| 339 | |
| 340 | static int voltage_set(int slot, int vcc, int vpp) |
| 341 | { |
| 342 | u32 reg = 0; |
| 343 | |
| 344 | switch(vcc) { |
| 345 | case 0: |
| 346 | break; |
| 347 | case 33: |
| 348 | reg |= BCSR1_PCCVCC0; |
| 349 | break; |
| 350 | case 50: |
| 351 | reg |= BCSR1_PCCVCC1; |
| 352 | break; |
| 353 | default: |
| 354 | return 1; |
| 355 | } |
| 356 | |
| 357 | switch(vpp) { |
| 358 | case 0: |
| 359 | break; |
| 360 | case 33: |
| 361 | case 50: |
| 362 | if(vcc == vpp) |
| 363 | reg |= BCSR1_PCCVPP1; |
| 364 | else |
| 365 | return 1; |
| 366 | break; |
| 367 | case 120: |
| 368 | if ((vcc == 33) || (vcc == 50)) |
| 369 | reg |= BCSR1_PCCVPP0; |
| 370 | else |
| 371 | return 1; |
| 372 | default: |
| 373 | return 1; |
| 374 | } |
| 375 | |
| 376 | /* first, turn off all power */ |
| 377 | out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); |
| 378 | |
| 379 | /* enable new powersettings */ |
| 380 | out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V |
| 386 | |
| 387 | static void hardware_enable(int slot) |
| 388 | { |
| 389 | out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN); |
| 390 | } |
| 391 | |
| 392 | static void hardware_disable(int slot) |
| 393 | { |
| 394 | out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN); |
| 395 | } |
| 396 | |
| 397 | #endif |
| 398 | |
| 399 | /* ------------------------------------------------------------------------- */ |
| 400 | /* Motorola MBX860 */ |
| 401 | |
| 402 | #if defined(CONFIG_MBX) |
| 403 | |
| 404 | #define PCMCIA_BOARD_MSG "MBX" |
| 405 | |
| 406 | static int voltage_set(int slot, int vcc, int vpp) |
| 407 | { |
| 408 | u8 reg = 0; |
| 409 | |
| 410 | switch(vcc) { |
| 411 | case 0: |
| 412 | break; |
| 413 | case 33: |
| 414 | reg |= CSR2_VCC_33; |
| 415 | break; |
| 416 | case 50: |
| 417 | reg |= CSR2_VCC_50; |
| 418 | break; |
| 419 | default: |
| 420 | return 1; |
| 421 | } |
| 422 | |
| 423 | switch(vpp) { |
| 424 | case 0: |
| 425 | break; |
| 426 | case 33: |
| 427 | case 50: |
| 428 | if(vcc == vpp) |
| 429 | reg |= CSR2_VPP_VCC; |
| 430 | else |
| 431 | return 1; |
| 432 | break; |
| 433 | case 120: |
| 434 | if ((vcc == 33) || (vcc == 50)) |
| 435 | reg |= CSR2_VPP_12; |
| 436 | else |
| 437 | return 1; |
| 438 | default: |
| 439 | return 1; |
| 440 | } |
| 441 | |
| 442 | /* first, turn off all power */ |
| 443 | out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); |
| 444 | |
| 445 | /* enable new powersettings */ |
| 446 | out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg); |
| 447 | |
| 448 | return 0; |
| 449 | } |
| 450 | |
| 451 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V |
| 452 | #define hardware_enable(_slot_) /* No hardware to enable */ |
| 453 | #define hardware_disable(_slot_) /* No hardware to disable */ |
| 454 | |
| 455 | #endif /* CONFIG_MBX */ |
| 456 | |
| 457 | #if defined(CONFIG_PRxK) |
| 458 | #include <asm/cpld.h> |
| 459 | extern volatile fpga_pc_regs *fpga_pc; |
| 460 | |
| 461 | #define PCMCIA_BOARD_MSG "MPC855T" |
| 462 | |
| 463 | static int voltage_set(int slot, int vcc, int vpp) |
| 464 | { |
| 465 | u8 reg = 0; |
| 466 | u8 regread; |
| 467 | cpld_regs *ccpld = get_cpld(); |
| 468 | |
| 469 | switch(vcc) { |
| 470 | case 0: |
| 471 | break; |
| 472 | case 33: |
| 473 | reg |= PCMCIA_VCC_33; |
| 474 | break; |
| 475 | case 50: |
| 476 | reg |= PCMCIA_VCC_50; |
| 477 | break; |
| 478 | default: |
| 479 | return 1; |
| 480 | } |
| 481 | |
| 482 | switch(vpp) { |
| 483 | case 0: |
| 484 | break; |
| 485 | case 33: |
| 486 | case 50: |
| 487 | if(vcc == vpp) |
| 488 | reg |= PCMCIA_VPP_VCC; |
| 489 | else |
| 490 | return 1; |
| 491 | break; |
| 492 | case 120: |
| 493 | if ((vcc == 33) || (vcc == 50)) |
| 494 | reg |= PCMCIA_VPP_12; |
| 495 | else |
| 496 | return 1; |
| 497 | default: |
| 498 | return 1; |
| 499 | } |
| 500 | |
| 501 | reg = reg >> (slot << 2); |
| 502 | regread = in_8(&ccpld->fpga_pc_ctl); |
| 503 | if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { |
| 504 | /* enable new powersettings */ |
| 505 | regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)); |
| 506 | out_8(&ccpld->fpga_pc_ctl, reg | regread); |
| 507 | msleep(100); |
| 508 | } |
| 509 | |
| 510 | return 0; |
| 511 | } |
| 512 | |
| 513 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV |
| 514 | #define hardware_enable(_slot_) /* No hardware to enable */ |
| 515 | #define hardware_disable(_slot_) /* No hardware to disable */ |
| 516 | |
| 517 | #endif /* CONFIG_PRxK */ |
| 518 | |
| 519 | static void m8xx_shutdown(void) |
| 520 | { |
| 521 | u32 m, i; |
| 522 | struct pcmcia_win *w; |
| 523 | |
| 524 | for(i = 0; i < PCMCIA_SOCKETS_NO; i++){ |
| 525 | w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; |
| 526 | |
| 527 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i)); |
| 528 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i)); |
| 529 | |
| 530 | /* turn off interrupt and disable CxOE */ |
| 531 | out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); |
| 532 | |
| 533 | /* turn off memory windows */ |
| 534 | for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) { |
| 535 | out_be32(&w->or, 0); /* set to not valid */ |
| 536 | w++; |
| 537 | } |
| 538 | |
| 539 | /* turn off voltage */ |
| 540 | voltage_set(i, 0, 0); |
| 541 | |
| 542 | /* disable external hardware */ |
| 543 | hardware_disable(i); |
| 544 | } |
| 545 | |
| 546 | free_irq(pcmcia_schlvl, NULL); |
| 547 | } |
| 548 | |
Marcelo Tosatti | de957c8 | 2005-10-28 17:46:13 -0700 | [diff] [blame] | 549 | static struct device_driver m8xx_driver = { |
| 550 | .name = "m8xx-pcmcia", |
| 551 | .bus = &platform_bus_type, |
Marcelo Tosatti | e346315 | 2005-11-05 13:03:32 -0200 | [diff] [blame] | 552 | .suspend = pcmcia_socket_dev_suspend, |
| 553 | .resume = pcmcia_socket_dev_resume, |
Marcelo Tosatti | de957c8 | 2005-10-28 17:46:13 -0700 | [diff] [blame] | 554 | }; |
| 555 | |
| 556 | static struct platform_device m8xx_device = { |
| 557 | .name = "m8xx-pcmcia", |
| 558 | .id = 0, |
| 559 | }; |
| 560 | |
| 561 | static u32 pending_events[PCMCIA_SOCKETS_NO]; |
| 562 | static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED; |
| 563 | |
| 564 | static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs) |
| 565 | { |
| 566 | struct socket_info *s; |
| 567 | struct event_table *e; |
| 568 | unsigned int i, events, pscr, pipr, per; |
| 569 | |
| 570 | dprintk("Interrupt!\n"); |
| 571 | /* get interrupt sources */ |
| 572 | |
| 573 | pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr); |
| 574 | pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr); |
| 575 | per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per); |
| 576 | |
| 577 | for(i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
| 578 | s = &socket[i]; |
| 579 | e = &s->events[0]; |
| 580 | events = 0; |
| 581 | |
| 582 | while(e->regbit) { |
| 583 | if(pscr & e->regbit) |
| 584 | events |= e->eventbit; |
| 585 | |
| 586 | e++; |
| 587 | } |
| 588 | |
| 589 | /* |
| 590 | * report only if both card detect signals are the same |
| 591 | * not too nice done, |
| 592 | * we depend on that CD2 is the bit to the left of CD1... |
| 593 | */ |
| 594 | if(events & SS_DETECT) |
| 595 | if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ |
| 596 | (pipr & M8XX_PCMCIA_CD1(i))) |
| 597 | { |
| 598 | events &= ~SS_DETECT; |
| 599 | } |
| 600 | |
| 601 | #ifdef PCMCIA_GLITCHY_CD |
| 602 | /* |
| 603 | * I've experienced CD problems with my ADS board. |
| 604 | * We make an extra check to see if there was a |
| 605 | * real change of Card detection. |
| 606 | */ |
| 607 | |
| 608 | if((events & SS_DETECT) && |
| 609 | ((pipr & |
| 610 | (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && |
| 611 | (s->state.Vcc | s->state.Vpp)) { |
| 612 | events &= ~SS_DETECT; |
| 613 | /*printk( "CD glitch workaround - CD = 0x%08x!\n", |
| 614 | (pipr & (M8XX_PCMCIA_CD2(i) |
| 615 | | M8XX_PCMCIA_CD1(i))));*/ |
| 616 | } |
| 617 | #endif |
| 618 | |
| 619 | /* call the handler */ |
| 620 | |
| 621 | dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, " |
| 622 | "pipr = 0x%08x\n", |
| 623 | i, events, pscr, pipr); |
| 624 | |
| 625 | if(events) { |
| 626 | spin_lock(&pending_event_lock); |
| 627 | pending_events[i] |= events; |
| 628 | spin_unlock(&pending_event_lock); |
| 629 | /* |
| 630 | * Turn off RDY_L bits in the PER mask on |
| 631 | * CD interrupt receival. |
| 632 | * |
| 633 | * They can generate bad interrupts on the |
| 634 | * ACS4,8,16,32. - marcelo |
| 635 | */ |
| 636 | per &= ~M8XX_PCMCIA_RDY_L(0); |
| 637 | per &= ~M8XX_PCMCIA_RDY_L(1); |
| 638 | |
| 639 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per); |
| 640 | |
| 641 | if (events) |
| 642 | pcmcia_parse_events(&socket[i].socket, events); |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | /* clear the interrupt sources */ |
| 647 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr); |
| 648 | |
| 649 | dprintk("Interrupt done.\n"); |
| 650 | |
| 651 | return IRQ_HANDLED; |
| 652 | } |
| 653 | |
| 654 | static u32 m8xx_get_graycode(u32 size) |
| 655 | { |
| 656 | u32 k; |
| 657 | |
| 658 | for(k = 0; k < M8XX_SIZES_NO; k++) |
| 659 | if(m8xx_size_to_gray[k] == size) |
| 660 | break; |
| 661 | |
| 662 | if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) |
| 663 | k = -1; |
| 664 | |
| 665 | return k; |
| 666 | } |
| 667 | |
| 668 | static u32 m8xx_get_speed(u32 ns, u32 is_io) |
| 669 | { |
| 670 | u32 reg, clocks, psst, psl, psht; |
| 671 | |
| 672 | if(!ns) { |
| 673 | |
| 674 | /* |
| 675 | * We get called with IO maps setup to 0ns |
| 676 | * if not specified by the user. |
| 677 | * They should be 255ns. |
| 678 | */ |
| 679 | |
| 680 | if(is_io) |
| 681 | ns = 255; |
| 682 | else |
| 683 | ns = 100; /* fast memory if 0 */ |
| 684 | } |
| 685 | |
| 686 | /* |
| 687 | * In PSST, PSL, PSHT fields we tell the controller |
| 688 | * timing parameters in CLKOUT clock cycles. |
| 689 | * CLKOUT is the same as GCLK2_50. |
| 690 | */ |
| 691 | |
| 692 | /* how we want to adjust the timing - in percent */ |
| 693 | |
| 694 | #define ADJ 180 /* 80 % longer accesstime - to be sure */ |
| 695 | |
| 696 | clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; |
| 697 | clocks = (clocks * ADJ) / (100*1000); |
| 698 | if(clocks >= PCMCIA_BMT_LIMIT) { |
| 699 | printk( "Max access time limit reached\n"); |
| 700 | clocks = PCMCIA_BMT_LIMIT-1; |
| 701 | } |
| 702 | |
| 703 | psst = clocks / 7; /* setup time */ |
| 704 | psht = clocks / 7; /* hold time */ |
| 705 | psl = (clocks * 5) / 7; /* strobe length */ |
| 706 | |
| 707 | psst += clocks - (psst + psht + psl); |
| 708 | |
| 709 | reg = psst << 12; |
| 710 | reg |= psl << 7; |
| 711 | reg |= psht << 16; |
| 712 | |
| 713 | return reg; |
| 714 | } |
| 715 | |
| 716 | static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) |
| 717 | { |
| 718 | int lsock = container_of(sock, struct socket_info, socket)->slot; |
| 719 | struct socket_info *s = &socket[lsock]; |
| 720 | unsigned int pipr, reg; |
| 721 | |
| 722 | pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr); |
| 723 | |
| 724 | *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) |
| 725 | | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; |
| 726 | *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; |
| 727 | |
| 728 | if (s->state.flags & SS_IOCARD) |
| 729 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; |
| 730 | else { |
| 731 | *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; |
| 732 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; |
| 733 | *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; |
| 734 | } |
| 735 | |
| 736 | if (s->state.Vcc | s->state.Vpp) |
| 737 | *value |= SS_POWERON; |
| 738 | |
| 739 | /* |
| 740 | * Voltage detection: |
| 741 | * This driver only supports 16-Bit pc-cards. |
| 742 | * Cardbus is not handled here. |
| 743 | * |
| 744 | * To determine what voltage to use we must read the VS1 and VS2 pin. |
| 745 | * Depending on what socket type is present, |
| 746 | * different combinations mean different things. |
| 747 | * |
| 748 | * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse |
| 749 | * |
| 750 | * 5V 5V, LV* NC NC 5V only 5V (if available) |
| 751 | * |
| 752 | * 5V 5V, LV* GND NC 5 or 3.3V as low as possible |
| 753 | * |
| 754 | * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible |
| 755 | * |
| 756 | * LV* 5V - - shall not fit into socket |
| 757 | * |
| 758 | * LV* LV* GND NC 3.3V only 3.3V |
| 759 | * |
| 760 | * LV* LV* NC GND x.xV x.xV (if avail.) |
| 761 | * |
| 762 | * LV* LV* GND GND 3.3 or x.xV as low as possible |
| 763 | * |
| 764 | * *LV means Low Voltage |
| 765 | * |
| 766 | * |
| 767 | * That gives us the following table: |
| 768 | * |
| 769 | * Socket VS1 VS2 Voltage |
| 770 | * |
| 771 | * 5V NC NC 5V |
| 772 | * 5V NC GND none (should not be possible) |
| 773 | * 5V GND NC >= 3.3V |
| 774 | * 5V GND GND >= x.xV |
| 775 | * |
| 776 | * LV NC NC 5V (if available) |
| 777 | * LV NC GND x.xV (if available) |
| 778 | * LV GND NC 3.3V |
| 779 | * LV GND GND >= x.xV |
| 780 | * |
| 781 | * So, how do I determine if I have a 5V or a LV |
| 782 | * socket on my board? Look at the socket! |
| 783 | * |
| 784 | * |
| 785 | * Socket with 5V key: |
| 786 | * ++--------------------------------------------+ |
| 787 | * || | |
| 788 | * || || |
| 789 | * || || |
| 790 | * | | |
| 791 | * +---------------------------------------------+ |
| 792 | * |
| 793 | * Socket with LV key: |
| 794 | * ++--------------------------------------------+ |
| 795 | * || | |
| 796 | * | || |
| 797 | * | || |
| 798 | * | | |
| 799 | * +---------------------------------------------+ |
| 800 | * |
| 801 | * |
| 802 | * With other words - LV only cards does not fit |
| 803 | * into the 5V socket! |
| 804 | */ |
| 805 | |
| 806 | /* read out VS1 and VS2 */ |
| 807 | |
| 808 | reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) |
| 809 | >> M8XX_PCMCIA_VS_SHIFT(lsock); |
| 810 | |
| 811 | if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { |
| 812 | switch(reg) { |
| 813 | case 1: |
| 814 | *value |= SS_3VCARD; |
| 815 | break; /* GND, NC - 3.3V only */ |
| 816 | case 2: |
| 817 | *value |= SS_XVCARD; |
| 818 | break; /* NC. GND - x.xV only */ |
| 819 | }; |
| 820 | } |
| 821 | |
| 822 | dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value); |
| 823 | return 0; |
| 824 | } |
| 825 | |
| 826 | static int m8xx_get_socket(struct pcmcia_socket *sock, socket_state_t *state) |
| 827 | { |
| 828 | int lsock = container_of(sock, struct socket_info, socket)->slot; |
| 829 | *state = socket[lsock].state; /* copy the whole structure */ |
| 830 | |
| 831 | dprintk("GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, " |
| 832 | "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags, |
| 833 | state->Vcc, state->Vpp, state->io_irq, state->csc_mask); |
| 834 | return 0; |
| 835 | } |
| 836 | |
| 837 | static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state) |
| 838 | { |
| 839 | int lsock = container_of(sock, struct socket_info, socket)->slot; |
| 840 | struct socket_info *s = &socket[lsock]; |
| 841 | struct event_table *e; |
| 842 | unsigned int reg; |
| 843 | unsigned long flags; |
| 844 | |
| 845 | dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " |
| 846 | "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, |
| 847 | state->Vcc, state->Vpp, state->io_irq, state->csc_mask); |
| 848 | |
| 849 | /* First, set voltage - bail out if invalid */ |
| 850 | if(voltage_set(lsock, state->Vcc, state->Vpp)) |
| 851 | return -EINVAL; |
| 852 | |
| 853 | /* Take care of reset... */ |
| 854 | if(state->flags & SS_RESET) |
| 855 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ |
| 856 | else |
| 857 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); |
| 858 | |
| 859 | /* ... and output enable. */ |
| 860 | |
| 861 | /* The CxOE signal is connected to a 74541 on the ADS. |
| 862 | I guess most other boards used the ADS as a reference. |
| 863 | I tried to control the CxOE signal with SS_OUTPUT_ENA, |
| 864 | but the reset signal seems connected via the 541. |
| 865 | If the CxOE is left high are some signals tristated and |
| 866 | no pullups are present -> the cards act wierd. |
| 867 | So right now the buffers are enabled if the power is on. */ |
| 868 | |
| 869 | if(state->Vcc || state->Vpp) |
| 870 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ |
| 871 | else |
| 872 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); |
| 873 | |
| 874 | /* |
| 875 | * We'd better turn off interrupts before |
| 876 | * we mess with the events-table.. |
| 877 | */ |
| 878 | |
| 879 | spin_lock_irqsave(&events_lock, flags); |
| 880 | |
| 881 | /* |
| 882 | * Play around with the interrupt mask to be able to |
| 883 | * give the events the generic pcmcia driver wants us to. |
| 884 | */ |
| 885 | |
| 886 | e = &s->events[0]; |
| 887 | reg = 0; |
| 888 | |
| 889 | if(state->csc_mask & SS_DETECT) { |
| 890 | e->eventbit = SS_DETECT; |
| 891 | reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) |
| 892 | | M8XX_PCMCIA_CD1(lsock)); |
| 893 | e++; |
| 894 | } |
| 895 | if(state->flags & SS_IOCARD) { |
| 896 | /* |
| 897 | * I/O card |
| 898 | */ |
| 899 | if(state->csc_mask & SS_STSCHG) { |
| 900 | e->eventbit = SS_STSCHG; |
| 901 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); |
| 902 | e++; |
| 903 | } |
| 904 | /* |
| 905 | * If io_irq is non-zero we should enable irq. |
| 906 | */ |
| 907 | if(state->io_irq) { |
| 908 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24); |
| 909 | /* |
| 910 | * Strange thing here: |
| 911 | * The manual does not tell us which interrupt |
| 912 | * the sources generate. |
| 913 | * Anyhow, I found out that RDY_L generates IREQLVL. |
| 914 | * |
| 915 | * We use level triggerd interrupts, and they don't |
| 916 | * have to be cleared in PSCR in the interrupt handler. |
| 917 | */ |
| 918 | reg |= M8XX_PCMCIA_RDY_L(lsock); |
| 919 | } |
| 920 | else |
| 921 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); |
| 922 | } |
| 923 | else { |
| 924 | /* |
| 925 | * Memory card |
| 926 | */ |
| 927 | if(state->csc_mask & SS_BATDEAD) { |
| 928 | e->eventbit = SS_BATDEAD; |
| 929 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); |
| 930 | e++; |
| 931 | } |
| 932 | if(state->csc_mask & SS_BATWARN) { |
| 933 | e->eventbit = SS_BATWARN; |
| 934 | reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); |
| 935 | e++; |
| 936 | } |
| 937 | /* What should I trigger on - low/high,raise,fall? */ |
| 938 | if(state->csc_mask & SS_READY) { |
| 939 | e->eventbit = SS_READY; |
| 940 | reg |= e->regbit = 0; //?? |
| 941 | e++; |
| 942 | } |
| 943 | } |
| 944 | |
| 945 | e->regbit = 0; /* terminate list */ |
| 946 | |
| 947 | /* |
| 948 | * Clear the status changed . |
| 949 | * Port A and Port B share the same port. |
| 950 | * Writing ones will clear the bits. |
| 951 | */ |
| 952 | |
| 953 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg); |
| 954 | |
| 955 | /* |
| 956 | * Write the mask. |
| 957 | * Port A and Port B share the same port. |
| 958 | * Need for read-modify-write. |
| 959 | * Ones will enable the interrupt. |
| 960 | */ |
| 961 | |
| 962 | /* |
| 963 | reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per |
| 964 | & M8XX_PCMCIA_MASK(lsock); |
| 965 | */ |
| 966 | |
| 967 | reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & |
| 968 | (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
| 969 | |
| 970 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg); |
| 971 | |
| 972 | spin_unlock_irqrestore(&events_lock, flags); |
| 973 | |
| 974 | /* copy the struct and modify the copy */ |
| 975 | |
| 976 | s->state = *state; |
| 977 | |
| 978 | return 0; |
| 979 | } |
| 980 | |
| 981 | static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) |
| 982 | { |
| 983 | int lsock = container_of(sock, struct socket_info, socket)->slot; |
| 984 | |
| 985 | struct socket_info *s = &socket[lsock]; |
| 986 | struct pcmcia_win *w; |
| 987 | unsigned int reg, winnr; |
| 988 | |
| 989 | #define M8XX_SIZE (io->stop - io->start + 1) |
| 990 | #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) |
| 991 | |
| 992 | dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, " |
| 993 | "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags, |
| 994 | io->speed, io->start, io->stop); |
| 995 | |
| 996 | if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) |
| 997 | || (io->stop > 0xffff) || (io->stop < io->start)) |
| 998 | return -EINVAL; |
| 999 | |
| 1000 | if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) |
| 1001 | return -EINVAL; |
| 1002 | |
| 1003 | if(io->flags & MAP_ACTIVE) { |
| 1004 | |
| 1005 | dprintk( "io->flags & MAP_ACTIVE\n"); |
| 1006 | |
| 1007 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) |
| 1008 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
| 1009 | |
| 1010 | /* setup registers */ |
| 1011 | |
| 1012 | w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; |
| 1013 | w += winnr; |
| 1014 | |
| 1015 | out_be32(&w->or, 0); /* turn off window first */ |
| 1016 | out_be32(&w->br, M8XX_BASE); |
| 1017 | |
| 1018 | reg <<= 27; |
| 1019 | reg |= M8XX_PCMCIA_POR_IO |(lsock << 2); |
| 1020 | |
| 1021 | reg |= m8xx_get_speed(io->speed, 1); |
| 1022 | |
| 1023 | if(io->flags & MAP_WRPROT) |
| 1024 | reg |= M8XX_PCMCIA_POR_WRPROT; |
| 1025 | |
| 1026 | /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/ |
| 1027 | if(io->flags & MAP_16BIT) |
| 1028 | reg |= M8XX_PCMCIA_POR_16BIT; |
| 1029 | |
| 1030 | if(io->flags & MAP_ACTIVE) |
| 1031 | reg |= M8XX_PCMCIA_POR_VALID; |
| 1032 | |
| 1033 | out_be32(&w->or, reg); |
| 1034 | |
| 1035 | dprintk("Socket %u: Mapped io window %u at %#8.8x, " |
| 1036 | "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); |
| 1037 | } else { |
| 1038 | /* shutdown IO window */ |
| 1039 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) |
| 1040 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
| 1041 | |
| 1042 | /* setup registers */ |
| 1043 | |
| 1044 | w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; |
| 1045 | w += winnr; |
| 1046 | |
| 1047 | out_be32(&w->or, 0); /* turn off window */ |
| 1048 | out_be32(&w->br, 0); /* turn off base address */ |
| 1049 | |
| 1050 | dprintk("Socket %u: Unmapped io window %u at %#8.8x, " |
| 1051 | "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); |
| 1052 | } |
| 1053 | |
| 1054 | /* copy the struct and modify the copy */ |
| 1055 | s->io_win[io->map] = *io; |
| 1056 | s->io_win[io->map].flags &= (MAP_WRPROT |
| 1057 | | MAP_16BIT |
| 1058 | | MAP_ACTIVE); |
| 1059 | dprintk("SetIOMap exit\n"); |
| 1060 | |
| 1061 | return 0; |
| 1062 | } |
| 1063 | |
| 1064 | static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem) |
| 1065 | { |
| 1066 | int lsock = container_of(sock, struct socket_info, socket)->slot; |
| 1067 | struct socket_info *s = &socket[lsock]; |
| 1068 | struct pcmcia_win *w; |
| 1069 | struct pccard_mem_map *old; |
| 1070 | unsigned int reg, winnr; |
| 1071 | |
| 1072 | dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, " |
| 1073 | "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, |
| 1074 | mem->speed, mem->static_start, mem->card_start); |
| 1075 | |
| 1076 | if ((mem->map >= PCMCIA_MEM_WIN_NO) |
| 1077 | // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) |
| 1078 | || (mem->card_start >= 0x04000000) |
| 1079 | || (mem->static_start & 0xfff) /* 4KByte resolution */ |
| 1080 | || (mem->card_start & 0xfff)) |
| 1081 | return -EINVAL; |
| 1082 | |
| 1083 | if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { |
| 1084 | printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); |
| 1085 | return -EINVAL; |
| 1086 | } |
| 1087 | reg <<= 27; |
| 1088 | |
| 1089 | winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; |
| 1090 | |
| 1091 | /* Setup the window in the pcmcia controller */ |
| 1092 | |
| 1093 | w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; |
| 1094 | w += winnr; |
| 1095 | |
| 1096 | reg |= lsock << 2; |
| 1097 | |
| 1098 | reg |= m8xx_get_speed(mem->speed, 0); |
| 1099 | |
| 1100 | if(mem->flags & MAP_ATTRIB) |
| 1101 | reg |= M8XX_PCMCIA_POR_ATTRMEM; |
| 1102 | |
| 1103 | if(mem->flags & MAP_WRPROT) |
| 1104 | reg |= M8XX_PCMCIA_POR_WRPROT; |
| 1105 | |
| 1106 | if(mem->flags & MAP_16BIT) |
| 1107 | reg |= M8XX_PCMCIA_POR_16BIT; |
| 1108 | |
| 1109 | if(mem->flags & MAP_ACTIVE) |
| 1110 | reg |= M8XX_PCMCIA_POR_VALID; |
| 1111 | |
| 1112 | out_be32(&w->or, reg); |
| 1113 | |
| 1114 | dprintk("Socket %u: Mapped memory window %u at %#8.8x, " |
| 1115 | "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); |
| 1116 | |
| 1117 | if(mem->flags & MAP_ACTIVE) { |
| 1118 | /* get the new base address */ |
| 1119 | mem->static_start = PCMCIA_MEM_WIN_BASE + |
| 1120 | (PCMCIA_MEM_WIN_SIZE * winnr) |
| 1121 | + mem->card_start; |
| 1122 | } |
| 1123 | |
| 1124 | dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, " |
| 1125 | "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, |
| 1126 | mem->speed, mem->static_start, mem->card_start); |
| 1127 | |
| 1128 | /* copy the struct and modify the copy */ |
| 1129 | |
| 1130 | old = &s->mem_win[mem->map]; |
| 1131 | |
| 1132 | *old = *mem; |
| 1133 | old->flags &= (MAP_ATTRIB |
| 1134 | | MAP_WRPROT |
| 1135 | | MAP_16BIT |
| 1136 | | MAP_ACTIVE); |
| 1137 | |
| 1138 | return 0; |
| 1139 | } |
| 1140 | |
| 1141 | static int m8xx_sock_init(struct pcmcia_socket *sock) |
| 1142 | { |
| 1143 | int i; |
| 1144 | pccard_io_map io = { 0, 0, 0, 0, 1 }; |
| 1145 | pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; |
| 1146 | |
| 1147 | dprintk( "sock_init(%d)\n", s); |
| 1148 | |
| 1149 | m8xx_set_socket(sock, &dead_socket); |
| 1150 | for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { |
| 1151 | io.map = i; |
| 1152 | m8xx_set_io_map(sock, &io); |
| 1153 | } |
| 1154 | for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { |
| 1155 | mem.map = i; |
| 1156 | m8xx_set_mem_map(sock, &mem); |
| 1157 | } |
| 1158 | |
| 1159 | return 0; |
| 1160 | |
| 1161 | } |
| 1162 | |
| 1163 | static int m8xx_suspend(struct pcmcia_socket *sock) |
| 1164 | { |
| 1165 | return m8xx_set_socket(sock, &dead_socket); |
| 1166 | } |
| 1167 | |
| 1168 | static struct pccard_operations m8xx_services = { |
| 1169 | .init = m8xx_sock_init, |
| 1170 | .suspend = m8xx_suspend, |
| 1171 | .get_status = m8xx_get_status, |
| 1172 | .get_socket = m8xx_get_socket, |
| 1173 | .set_socket = m8xx_set_socket, |
| 1174 | .set_io_map = m8xx_set_io_map, |
| 1175 | .set_mem_map = m8xx_set_mem_map, |
| 1176 | }; |
| 1177 | |
| 1178 | static int __init m8xx_init(void) |
| 1179 | { |
| 1180 | struct pcmcia_win *w; |
| 1181 | unsigned int i,m; |
| 1182 | |
| 1183 | pcmcia_info("%s\n", version); |
| 1184 | |
| 1185 | if (driver_register(&m8xx_driver)) |
| 1186 | return -1; |
| 1187 | |
| 1188 | pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG |
| 1189 | " with IRQ %u.\n", pcmcia_schlvl); |
| 1190 | |
| 1191 | /* Configure Status change interrupt */ |
| 1192 | |
| 1193 | if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0, |
| 1194 | "m8xx_pcmcia", NULL)) { |
| 1195 | pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", |
| 1196 | pcmcia_schlvl); |
| 1197 | return -1; |
| 1198 | } |
| 1199 | |
| 1200 | w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; |
| 1201 | |
| 1202 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, |
| 1203 | M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)); |
| 1204 | |
| 1205 | out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, |
| 1206 | in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & |
| 1207 | ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1))); |
| 1208 | |
| 1209 | /* connect interrupt and disable CxOE */ |
| 1210 | |
| 1211 | out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16)); |
| 1212 | out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16)); |
| 1213 | |
| 1214 | /* intialize the fixed memory windows */ |
| 1215 | |
| 1216 | for(i = 0; i < PCMCIA_SOCKETS_NO; i++){ |
| 1217 | for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) { |
| 1218 | out_be32(&w->br, PCMCIA_MEM_WIN_BASE + |
| 1219 | (PCMCIA_MEM_WIN_SIZE |
| 1220 | * (m + i * PCMCIA_MEM_WIN_NO))); |
| 1221 | |
| 1222 | out_be32(&w->or, 0); /* set to not valid */ |
| 1223 | |
| 1224 | w++; |
| 1225 | } |
| 1226 | } |
| 1227 | |
| 1228 | /* turn off voltage */ |
| 1229 | voltage_set(0, 0, 0); |
| 1230 | voltage_set(1, 0, 0); |
| 1231 | |
| 1232 | /* Enable external hardware */ |
| 1233 | hardware_enable(0); |
| 1234 | hardware_enable(1); |
| 1235 | |
| 1236 | platform_device_register(&m8xx_device); |
| 1237 | |
| 1238 | for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) { |
| 1239 | socket[i].slot = i; |
| 1240 | socket[i].socket.owner = THIS_MODULE; |
| 1241 | socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; |
| 1242 | socket[i].socket.irq_mask = 0x000; |
| 1243 | socket[i].socket.map_size = 0x1000; |
| 1244 | socket[i].socket.io_offset = 0; |
| 1245 | socket[i].socket.pci_irq = i ? 7 : 9; |
| 1246 | socket[i].socket.ops = &m8xx_services; |
| 1247 | socket[i].socket.resource_ops = &pccard_nonstatic_ops; |
| 1248 | socket[i].socket.cb_dev = NULL; |
| 1249 | socket[i].socket.dev.dev = &m8xx_device.dev; |
| 1250 | } |
| 1251 | |
| 1252 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) |
| 1253 | pcmcia_register_socket(&socket[i].socket); |
| 1254 | |
| 1255 | return 0; |
| 1256 | } |
| 1257 | |
| 1258 | static void __exit m8xx_exit(void) |
| 1259 | { |
| 1260 | int i; |
| 1261 | |
| 1262 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) |
| 1263 | pcmcia_unregister_socket(&socket[i].socket); |
| 1264 | |
| 1265 | m8xx_shutdown(); |
| 1266 | |
| 1267 | platform_device_unregister(&m8xx_device); |
| 1268 | driver_unregister(&m8xx_driver); |
| 1269 | } |
| 1270 | |
| 1271 | module_init(m8xx_init); |
| 1272 | module_exit(m8xx_exit); |