Blame - drivers/dma/Kconfig - kernel/msm

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Chris Leech	c13c826	2006-05-23 17:18:44 -0700	[diff] [blame]	1	#
				2	# DMA engine configuration
				3	#
				4
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	5	menuconfig DMADEVICES
Haavard Skinnemoen	6d4f587	2007-11-28 16:21:43 -0800	[diff] [blame]	6	bool "DMA Engine support"
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	7	depends on !HIGHMEM64G && HAS_DMA
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	8	help
Haavard Skinnemoen	6d4f587	2007-11-28 16:21:43 -0800	[diff] [blame]	9	DMA engines can do asynchronous data transfers without
				10	involving the host CPU. Currently, this framework can be
				11	used to offload memory copies in the network stack and
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	12	RAID operations in the MD driver. This menu only presents
				13	DMA Device drivers supported by the configured arch, it may
				14	be empty in some cases.
Chris Leech	c13c826	2006-05-23 17:18:44 -0700	[diff] [blame]	15
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	16	if DMADEVICES
Chris Leech	db21733	2006-06-17 21:24:58 -0700	[diff] [blame]	17
Chris Leech	0bbd5f4	2006-05-23 17:35:34 -0700	[diff] [blame]	18	comment "DMA Devices"
				19
				20	config INTEL_IOATDMA
				21	tristate "Intel I/OAT DMA support"
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	22	depends on PCI && X86
				23	select DMA_ENGINE
				24	select DCA
				25	help
				26	Enable support for the Intel(R) I/OAT DMA engine present
				27	in recent Intel Xeon chipsets.
				28
				29	Say Y here if you have such a chipset.
				30
				31	If unsure, say N.
Dan Williams	c211092	2007-01-02 13:52:26 -0700	[diff] [blame]	32
				33	config INTEL_IOP_ADMA
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	34	tristate "Intel IOP ADMA support"
				35	depends on ARCH_IOP32X \|\| ARCH_IOP33X \|\| ARCH_IOP13XX
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	36	select DMA_ENGINE
				37	help
				38	Enable support for the Intel(R) IOP Series RAID engines.
Dan Williams	c211092	2007-01-02 13:52:26 -0700	[diff] [blame]	39
Haavard Skinnemoen	3bfb1d2	2008-07-08 11:59:42 -0700	[diff] [blame]	40	config DW_DMAC
				41	tristate "Synopsys DesignWare AHB DMA support"
				42	depends on AVR32
				43	select DMA_ENGINE
				44	default y if CPU_AT32AP7000
				45	help
				46	Support the Synopsys DesignWare AHB DMA controller. This
				47	can be integrated in chips such as the Atmel AT32ap7000.
				48
Zhang Wei	173acc7	2008-03-01 07:42:48 -0700	[diff] [blame]	49	config FSL_DMA
Timur Tabi	77cd62e	2008-09-26 17:00:11 -0700	[diff] [blame]	50	tristate "Freescale Elo and Elo Plus DMA support"
				51	depends on FSL_SOC
Zhang Wei	173acc7	2008-03-01 07:42:48 -0700	[diff] [blame]	52	select DMA_ENGINE
				53	---help---
Timur Tabi	77cd62e	2008-09-26 17:00:11 -0700	[diff] [blame]	54	Enable support for the Freescale Elo and Elo Plus DMA controllers.
				55	The Elo is the DMA controller on some 82xx and 83xx parts, and the
				56	Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei	173acc7	2008-03-01 07:42:48 -0700	[diff] [blame]	57
Saeed Bishara	ff7b047	2008-07-08 11:58:36 -0700	[diff] [blame]	58	config MV_XOR
				59	bool "Marvell XOR engine support"
				60	depends on PLAT_ORION
Saeed Bishara	ff7b047	2008-07-08 11:58:36 -0700	[diff] [blame]	61	select DMA_ENGINE
				62	---help---
				63	Enable support for the Marvell XOR engine.
				64
Guennadi Liakhovetski	5296b56	2009-01-19 15:36:21 -0700	[diff] [blame]	65	config MX3_IPU
				66	bool "MX3x Image Processing Unit support"
				67	depends on ARCH_MX3
				68	select DMA_ENGINE
				69	default y
				70	help
				71	If you plan to use the Image Processing unit in the i.MX3x, say
				72	Y here. If unsure, select Y.
				73
				74	config MX3_IPU_IRQS
				75	int "Number of dynamically mapped interrupts for IPU"
				76	depends on MX3_IPU
				77	range 2 137
				78	default 4
				79	help
				80	Out of 137 interrupt sources on i.MX31 IPU only very few are used.
				81	To avoid bloating the irq_desc[] array we allocate a sufficient
				82	number of IRQ slots and map them dynamically to specific sources.
				83
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	84	config DMA_ENGINE
				85	bool
				86
				87	comment "DMA Clients"
				88	depends on DMA_ENGINE
				89
				90	config NET_DMA
				91	bool "Network: TCP receive copy offload"
				92	depends on DMA_ENGINE && NET
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	93	default (INTEL_IOATDMA \|\| FSL_DMA)
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	94	help
				95	This enables the use of DMA engines in the network stack to
				96	offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	97
				98	Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
				99	say N.
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	100
Dan Williams	729b5d1	2009-03-25 09:13:25 -0700	[diff] [blame^]	101	config ASYNC_TX_DMA
				102	bool "Async_tx: Offload support for the async_tx api"
				103	depends on DMA_ENGINE
				104	help
				105	This allows the async_tx api to take advantage of offload engines for
				106	memcpy, memset, xor, and raid6 p+q operations. If your platform has
				107	a dma engine that can perform raid operations and you have enabled
				108	MD_RAID456 say Y.
				109
				110	If unsure, say N.
				111
Haavard Skinnemoen	4a776f0	2008-07-08 11:58:45 -0700	[diff] [blame]	112	config DMATEST
				113	tristate "DMA Test client"
				114	depends on DMA_ENGINE
				115	help
				116	Simple DMA test client. Say N unless you're debugging a
				117	DMA Device driver.
				118
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	119	endif