Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/sh/kernel/io_microdev.c |
| 3 | * |
| 4 | * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) |
| 5 | * Copyright (C) 2003, 2004 SuperH, Inc. |
| 6 | * Copyright (C) 2004 Paul Mundt |
| 7 | * |
| 8 | * SuperH SH4-202 MicroDev board support. |
| 9 | * |
| 10 | * May be copied or modified under the terms of the GNU General Public |
| 11 | * License. See linux/COPYING for more information. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/config.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/pci.h> |
| 17 | #include <linux/wait.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <asm/mach/io.h> |
| 20 | |
| 21 | /* |
| 22 | * we need to have a 'safe' address to re-direct all I/O requests |
| 23 | * that we do not explicitly wish to handle. This safe address |
| 24 | * must have the following properies: |
| 25 | * |
| 26 | * * writes are ignored (no exception) |
| 27 | * * reads are benign (no side-effects) |
| 28 | * * accesses of width 1, 2 and 4-bytes are all valid. |
| 29 | * |
| 30 | * The Processor Version Register (PVR) has these properties. |
| 31 | */ |
| 32 | #define PVR 0xff000030 /* Processor Version Register */ |
| 33 | |
| 34 | |
| 35 | #define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */ |
| 36 | #define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */ |
| 37 | #define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */ |
| 38 | #define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */ |
| 39 | #define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */ |
| 40 | #define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */ |
| 41 | #define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */ |
| 42 | #define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */ |
| 43 | #define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */ |
| 44 | |
| 45 | #define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */ |
| 46 | #define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */ |
| 47 | #define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */ |
| 48 | #define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */ |
| 49 | #define IO_SERIAL_EXTENT 0x10ul |
| 50 | |
| 51 | #define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */ |
| 52 | #define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */ |
| 53 | #define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */ |
| 54 | |
| 55 | #define PORT2ADDR(x) (microdev_isa_port2addr(x)) |
| 56 | |
| 57 | |
| 58 | static inline void delay(void) |
| 59 | { |
| 60 | #if defined(CONFIG_PCI) |
| 61 | /* System board present, just make a dummy SRAM access. (CS0 will be |
| 62 | mapped to PCI memory, probably good to avoid it.) */ |
| 63 | ctrl_inw(0xa6800000); |
| 64 | #else |
| 65 | /* CS0 will be mapped to flash, ROM etc so safe to access it. */ |
| 66 | ctrl_inw(0xa0000000); |
| 67 | #endif |
| 68 | } |
| 69 | |
| 70 | unsigned char microdev_inb(unsigned long port) |
| 71 | { |
| 72 | #ifdef CONFIG_PCI |
| 73 | if (port >= PCIBIOS_MIN_IO) |
| 74 | return microdev_pci_inb(port); |
| 75 | #endif |
| 76 | return *(volatile unsigned char*)PORT2ADDR(port); |
| 77 | } |
| 78 | |
| 79 | unsigned short microdev_inw(unsigned long port) |
| 80 | { |
| 81 | #ifdef CONFIG_PCI |
| 82 | if (port >= PCIBIOS_MIN_IO) |
| 83 | return microdev_pci_inw(port); |
| 84 | #endif |
| 85 | return *(volatile unsigned short*)PORT2ADDR(port); |
| 86 | } |
| 87 | |
| 88 | unsigned int microdev_inl(unsigned long port) |
| 89 | { |
| 90 | #ifdef CONFIG_PCI |
| 91 | if (port >= PCIBIOS_MIN_IO) |
| 92 | return microdev_pci_inl(port); |
| 93 | #endif |
| 94 | return *(volatile unsigned int*)PORT2ADDR(port); |
| 95 | } |
| 96 | |
| 97 | void microdev_outb(unsigned char b, unsigned long port) |
| 98 | { |
| 99 | #ifdef CONFIG_PCI |
| 100 | if (port >= PCIBIOS_MIN_IO) { |
| 101 | microdev_pci_outb(b, port); |
| 102 | return; |
| 103 | } |
| 104 | #endif |
| 105 | |
| 106 | /* |
| 107 | * There is a board feature with the current SH4-202 MicroDev in |
| 108 | * that the 2 byte enables (nBE0 and nBE1) are tied together (and |
| 109 | * to the Chip Select Line (Ethernet_CS)). Due to this conectivity, |
| 110 | * it is not possible to safely perform 8-bit writes to the |
| 111 | * Ethernet registers, as 16-bits will be consumed from the Data |
| 112 | * lines (corrupting the other byte). Hence, this function is |
| 113 | * written to impliment 16-bit read/modify/write for all byte-wide |
| 114 | * acceses. |
| 115 | * |
| 116 | * Note: there is no problem with byte READS (even or odd). |
| 117 | * |
| 118 | * Sean McGoogan - 16th June 2003. |
| 119 | */ |
| 120 | if ((port >= IO_LAN91C111_BASE) && |
| 121 | (port < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { |
| 122 | /* |
| 123 | * Then are trying to perform a byte-write to the |
| 124 | * LAN91C111. This needs special care. |
| 125 | */ |
| 126 | if (port % 2 == 1) { /* is the port odd ? */ |
| 127 | /* unset bit-0, i.e. make even */ |
| 128 | const unsigned long evenPort = port-1; |
| 129 | unsigned short word; |
| 130 | |
| 131 | /* |
| 132 | * do a 16-bit read/write to write to 'port', |
| 133 | * preserving even byte. |
| 134 | * |
| 135 | * Even addresses are bits 0-7 |
| 136 | * Odd addresses are bits 8-15 |
| 137 | */ |
| 138 | word = microdev_inw(evenPort); |
| 139 | word = (word & 0xffu) | (b << 8); |
| 140 | microdev_outw(word, evenPort); |
| 141 | } else { |
| 142 | /* else, we are trying to do an even byte write */ |
| 143 | unsigned short word; |
| 144 | |
| 145 | /* |
| 146 | * do a 16-bit read/write to write to 'port', |
| 147 | * preserving odd byte. |
| 148 | * |
| 149 | * Even addresses are bits 0-7 |
| 150 | * Odd addresses are bits 8-15 |
| 151 | */ |
| 152 | word = microdev_inw(port); |
| 153 | word = (word & 0xff00u) | (b); |
| 154 | microdev_outw(word, port); |
| 155 | } |
| 156 | } else { |
| 157 | *(volatile unsigned char*)PORT2ADDR(port) = b; |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | void microdev_outw(unsigned short b, unsigned long port) |
| 162 | { |
| 163 | #ifdef CONFIG_PCI |
| 164 | if (port >= PCIBIOS_MIN_IO) { |
| 165 | microdev_pci_outw(b, port); |
| 166 | return; |
| 167 | } |
| 168 | #endif |
| 169 | *(volatile unsigned short*)PORT2ADDR(port) = b; |
| 170 | } |
| 171 | |
| 172 | void microdev_outl(unsigned int b, unsigned long port) |
| 173 | { |
| 174 | #ifdef CONFIG_PCI |
| 175 | if (port >= PCIBIOS_MIN_IO) { |
| 176 | microdev_pci_outl(b, port); |
| 177 | return; |
| 178 | } |
| 179 | #endif |
| 180 | *(volatile unsigned int*)PORT2ADDR(port) = b; |
| 181 | } |
| 182 | |
| 183 | unsigned char microdev_inb_p(unsigned long port) |
| 184 | { |
| 185 | unsigned char v = microdev_inb(port); |
| 186 | delay(); |
| 187 | return v; |
| 188 | } |
| 189 | |
| 190 | unsigned short microdev_inw_p(unsigned long port) |
| 191 | { |
| 192 | unsigned short v = microdev_inw(port); |
| 193 | delay(); |
| 194 | return v; |
| 195 | } |
| 196 | |
| 197 | unsigned int microdev_inl_p(unsigned long port) |
| 198 | { |
| 199 | unsigned int v = microdev_inl(port); |
| 200 | delay(); |
| 201 | return v; |
| 202 | } |
| 203 | |
| 204 | void microdev_outb_p(unsigned char b, unsigned long port) |
| 205 | { |
| 206 | microdev_outb(b, port); |
| 207 | delay(); |
| 208 | } |
| 209 | |
| 210 | void microdev_outw_p(unsigned short b, unsigned long port) |
| 211 | { |
| 212 | microdev_outw(b, port); |
| 213 | delay(); |
| 214 | } |
| 215 | |
| 216 | void microdev_outl_p(unsigned int b, unsigned long port) |
| 217 | { |
| 218 | microdev_outl(b, port); |
| 219 | delay(); |
| 220 | } |
| 221 | |
| 222 | void microdev_insb(unsigned long port, void *buffer, unsigned long count) |
| 223 | { |
| 224 | volatile unsigned char *port_addr; |
| 225 | unsigned char *buf = buffer; |
| 226 | |
| 227 | port_addr = (volatile unsigned char *)PORT2ADDR(port); |
| 228 | |
| 229 | while (count--) |
| 230 | *buf++ = *port_addr; |
| 231 | } |
| 232 | |
| 233 | void microdev_insw(unsigned long port, void *buffer, unsigned long count) |
| 234 | { |
| 235 | volatile unsigned short *port_addr; |
| 236 | unsigned short *buf = buffer; |
| 237 | |
| 238 | port_addr = (volatile unsigned short *)PORT2ADDR(port); |
| 239 | |
| 240 | while (count--) |
| 241 | *buf++ = *port_addr; |
| 242 | } |
| 243 | |
| 244 | void microdev_insl(unsigned long port, void *buffer, unsigned long count) |
| 245 | { |
| 246 | volatile unsigned long *port_addr; |
| 247 | unsigned int *buf = buffer; |
| 248 | |
| 249 | port_addr = (volatile unsigned long *)PORT2ADDR(port); |
| 250 | |
| 251 | while (count--) |
| 252 | *buf++ = *port_addr; |
| 253 | } |
| 254 | |
| 255 | void microdev_outsb(unsigned long port, const void *buffer, unsigned long count) |
| 256 | { |
| 257 | volatile unsigned char *port_addr; |
| 258 | const unsigned char *buf = buffer; |
| 259 | |
| 260 | port_addr = (volatile unsigned char *)PORT2ADDR(port); |
| 261 | |
| 262 | while (count--) |
| 263 | *port_addr = *buf++; |
| 264 | } |
| 265 | |
| 266 | void microdev_outsw(unsigned long port, const void *buffer, unsigned long count) |
| 267 | { |
| 268 | volatile unsigned short *port_addr; |
| 269 | const unsigned short *buf = buffer; |
| 270 | |
| 271 | port_addr = (volatile unsigned short *)PORT2ADDR(port); |
| 272 | |
| 273 | while (count--) |
| 274 | *port_addr = *buf++; |
| 275 | } |
| 276 | |
| 277 | void microdev_outsl(unsigned long port, const void *buffer, unsigned long count) |
| 278 | { |
| 279 | volatile unsigned long *port_addr; |
| 280 | const unsigned int *buf = buffer; |
| 281 | |
| 282 | port_addr = (volatile unsigned long *)PORT2ADDR(port); |
| 283 | |
| 284 | while (count--) |
| 285 | *port_addr = *buf++; |
| 286 | } |
| 287 | |
| 288 | /* |
| 289 | * map I/O ports to memory-mapped addresses |
| 290 | */ |
| 291 | unsigned long microdev_isa_port2addr(unsigned long offset) |
| 292 | { |
| 293 | unsigned long result; |
| 294 | |
| 295 | if ((offset >= IO_LAN91C111_BASE) && |
| 296 | (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { |
| 297 | /* |
| 298 | * SMSC LAN91C111 Ethernet chip |
| 299 | */ |
| 300 | result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; |
| 301 | } else if ((offset >= IO_SUPERIO_BASE) && |
| 302 | (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { |
| 303 | /* |
| 304 | * SMSC FDC37C93xAPM SuperIO chip |
| 305 | * |
| 306 | * Configuration Registers |
| 307 | */ |
| 308 | result = IO_SUPERIO_PHYS + (offset << 1); |
| 309 | #if 0 |
| 310 | } else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG || |
| 311 | offset == KBD_STATUS_REG) { |
| 312 | /* |
| 313 | * SMSC FDC37C93xAPM SuperIO chip |
| 314 | * |
| 315 | * PS/2 Keyboard + Mouse (ports 0x60 and 0x64). |
| 316 | */ |
| 317 | result = IO_SUPERIO_PHYS + (offset << 1); |
| 318 | #endif |
| 319 | } else if (((offset >= IO_IDE1_BASE) && |
| 320 | (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || |
| 321 | (offset == IO_IDE1_MISC)) { |
| 322 | /* |
| 323 | * SMSC FDC37C93xAPM SuperIO chip |
| 324 | * |
| 325 | * IDE #1 |
| 326 | */ |
| 327 | result = IO_SUPERIO_PHYS + (offset << 1); |
| 328 | } else if (((offset >= IO_IDE2_BASE) && |
| 329 | (offset < IO_IDE2_BASE + IO_IDE_EXTENT)) || |
| 330 | (offset == IO_IDE2_MISC)) { |
| 331 | /* |
| 332 | * SMSC FDC37C93xAPM SuperIO chip |
| 333 | * |
| 334 | * IDE #2 |
| 335 | */ |
| 336 | result = IO_SUPERIO_PHYS + (offset << 1); |
| 337 | } else if ((offset >= IO_SERIAL1_BASE) && |
| 338 | (offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) { |
| 339 | /* |
| 340 | * SMSC FDC37C93xAPM SuperIO chip |
| 341 | * |
| 342 | * Serial #1 |
| 343 | */ |
| 344 | result = IO_SUPERIO_PHYS + (offset << 1); |
| 345 | } else if ((offset >= IO_SERIAL2_BASE) && |
| 346 | (offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) { |
| 347 | /* |
| 348 | * SMSC FDC37C93xAPM SuperIO chip |
| 349 | * |
| 350 | * Serial #2 |
| 351 | */ |
| 352 | result = IO_SUPERIO_PHYS + (offset << 1); |
| 353 | } else if ((offset >= IO_ISP1161_BASE) && |
| 354 | (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) { |
| 355 | /* |
| 356 | * Philips USB ISP1161x chip |
| 357 | */ |
| 358 | result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE; |
| 359 | } else { |
| 360 | /* |
| 361 | * safe default. |
| 362 | */ |
| 363 | printk("Warning: unexpected port in %s( offset = 0x%lx )\n", |
| 364 | __FUNCTION__, offset); |
| 365 | result = PVR; |
| 366 | } |
| 367 | |
| 368 | return result; |
| 369 | } |
| 370 | |