Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 13 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 14 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 15 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 18 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 19 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 20 | #include <plat/gpio.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 21 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 22 | #include "omap_hwmod_common_data.h" |
| 23 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 24 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 25 | #include "prm-regbits-24xx.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 26 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 27 | /* |
| 28 | * OMAP2420 hardware module integration data |
| 29 | * |
| 30 | * ALl of the data in this section should be autogeneratable from the |
| 31 | * TI hardware database or other technical documentation. Data that |
| 32 | * is driver-specific or driver-kernel integration-specific belongs |
| 33 | * elsewhere. |
| 34 | */ |
| 35 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 36 | static struct omap_hwmod omap2420_mpu_hwmod; |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 37 | static struct omap_hwmod omap2420_iva_hwmod; |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 38 | static struct omap_hwmod omap2420_l3_main_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 39 | static struct omap_hwmod omap2420_l4_core_hwmod; |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 40 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 41 | static struct omap_hwmod omap2420_gpio1_hwmod; |
| 42 | static struct omap_hwmod omap2420_gpio2_hwmod; |
| 43 | static struct omap_hwmod omap2420_gpio3_hwmod; |
| 44 | static struct omap_hwmod omap2420_gpio4_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 45 | |
| 46 | /* L3 -> L4_CORE interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 47 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 48 | .master = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 49 | .slave = &omap2420_l4_core_hwmod, |
| 50 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 51 | }; |
| 52 | |
| 53 | /* MPU -> L3 interface */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 54 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 55 | .master = &omap2420_mpu_hwmod, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 56 | .slave = &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 57 | .user = OCP_USER_MPU, |
| 58 | }; |
| 59 | |
| 60 | /* Slave interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 61 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
| 62 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | /* Master interfaces on the L3 interconnect */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 66 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
| 67 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 71 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 72 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 73 | .class = &l3_hwmod_class, |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 74 | .masters = omap2420_l3_main_masters, |
| 75 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), |
| 76 | .slaves = omap2420_l3_main_slaves, |
| 77 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 79 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | static struct omap_hwmod omap2420_l4_wkup_hwmod; |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 83 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 84 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 85 | static struct omap_hwmod omap2420_uart3_hwmod; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 86 | static struct omap_hwmod omap2420_i2c1_hwmod; |
| 87 | static struct omap_hwmod omap2420_i2c2_hwmod; |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 88 | |
| 89 | /* L4_CORE -> L4_WKUP interface */ |
| 90 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 91 | .master = &omap2420_l4_core_hwmod, |
| 92 | .slave = &omap2420_l4_wkup_hwmod, |
| 93 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 94 | }; |
| 95 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 96 | /* L4 CORE -> UART1 interface */ |
| 97 | static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { |
| 98 | { |
| 99 | .pa_start = OMAP2_UART1_BASE, |
| 100 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, |
| 101 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 102 | }, |
| 103 | }; |
| 104 | |
| 105 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 106 | .master = &omap2420_l4_core_hwmod, |
| 107 | .slave = &omap2420_uart1_hwmod, |
| 108 | .clk = "uart1_ick", |
| 109 | .addr = omap2420_uart1_addr_space, |
| 110 | .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), |
| 111 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 112 | }; |
| 113 | |
| 114 | /* L4 CORE -> UART2 interface */ |
| 115 | static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { |
| 116 | { |
| 117 | .pa_start = OMAP2_UART2_BASE, |
| 118 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, |
| 119 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 124 | .master = &omap2420_l4_core_hwmod, |
| 125 | .slave = &omap2420_uart2_hwmod, |
| 126 | .clk = "uart2_ick", |
| 127 | .addr = omap2420_uart2_addr_space, |
| 128 | .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), |
| 129 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 130 | }; |
| 131 | |
| 132 | /* L4 PER -> UART3 interface */ |
| 133 | static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { |
| 134 | { |
| 135 | .pa_start = OMAP2_UART3_BASE, |
| 136 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, |
| 137 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 138 | }, |
| 139 | }; |
| 140 | |
| 141 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 142 | .master = &omap2420_l4_core_hwmod, |
| 143 | .slave = &omap2420_uart3_hwmod, |
| 144 | .clk = "uart3_ick", |
| 145 | .addr = omap2420_uart3_addr_space, |
| 146 | .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), |
| 147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 148 | }; |
| 149 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 150 | /* I2C IP block address space length (in bytes) */ |
| 151 | #define OMAP2_I2C_AS_LEN 128 |
| 152 | |
| 153 | /* L4 CORE -> I2C1 interface */ |
| 154 | static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { |
| 155 | { |
| 156 | .pa_start = 0x48070000, |
| 157 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, |
| 158 | .flags = ADDR_TYPE_RT, |
| 159 | }, |
| 160 | }; |
| 161 | |
| 162 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 163 | .master = &omap2420_l4_core_hwmod, |
| 164 | .slave = &omap2420_i2c1_hwmod, |
| 165 | .clk = "i2c1_ick", |
| 166 | .addr = omap2420_i2c1_addr_space, |
| 167 | .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), |
| 168 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 169 | }; |
| 170 | |
| 171 | /* L4 CORE -> I2C2 interface */ |
| 172 | static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { |
| 173 | { |
| 174 | .pa_start = 0x48072000, |
| 175 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, |
| 176 | .flags = ADDR_TYPE_RT, |
| 177 | }, |
| 178 | }; |
| 179 | |
| 180 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 181 | .master = &omap2420_l4_core_hwmod, |
| 182 | .slave = &omap2420_i2c2_hwmod, |
| 183 | .clk = "i2c2_ick", |
| 184 | .addr = omap2420_i2c2_addr_space, |
| 185 | .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), |
| 186 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 187 | }; |
| 188 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 189 | /* Slave interfaces on the L4_CORE interconnect */ |
| 190 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 191 | &omap2420_l3_main__l4_core, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 192 | }; |
| 193 | |
| 194 | /* Master interfaces on the L4_CORE interconnect */ |
| 195 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { |
| 196 | &omap2420_l4_core__l4_wkup, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 197 | &omap2_l4_core__uart1, |
| 198 | &omap2_l4_core__uart2, |
| 199 | &omap2_l4_core__uart3, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 200 | &omap2420_l4_core__i2c1, |
| 201 | &omap2420_l4_core__i2c2 |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 202 | }; |
| 203 | |
| 204 | /* L4 CORE */ |
| 205 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 206 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 207 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 208 | .masters = omap2420_l4_core_masters, |
| 209 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), |
| 210 | .slaves = omap2420_l4_core_slaves, |
| 211 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 212 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 213 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | /* Slave interfaces on the L4_WKUP interconnect */ |
| 217 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { |
| 218 | &omap2420_l4_core__l4_wkup, |
| 219 | }; |
| 220 | |
| 221 | /* Master interfaces on the L4_WKUP interconnect */ |
| 222 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { |
| 223 | }; |
| 224 | |
| 225 | /* L4 WKUP */ |
| 226 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 227 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 228 | .class = &l4_hwmod_class, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 229 | .masters = omap2420_l4_wkup_masters, |
| 230 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), |
| 231 | .slaves = omap2420_l4_wkup_slaves, |
| 232 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 233 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 234 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 235 | }; |
| 236 | |
| 237 | /* Master interfaces on the MPU device */ |
| 238 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 239 | &omap2420_mpu__l3_main, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 240 | }; |
| 241 | |
| 242 | /* MPU */ |
| 243 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 244 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 245 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 246 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 247 | .masters = omap2420_mpu_masters, |
| 248 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), |
| 249 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 250 | }; |
| 251 | |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 252 | /* |
| 253 | * IVA1 interface data |
| 254 | */ |
| 255 | |
| 256 | /* IVA <- L3 interface */ |
| 257 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 258 | .master = &omap2420_l3_main_hwmod, |
| 259 | .slave = &omap2420_iva_hwmod, |
| 260 | .clk = "iva1_ifck", |
| 261 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 262 | }; |
| 263 | |
| 264 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { |
| 265 | &omap2420_l3__iva, |
| 266 | }; |
| 267 | |
| 268 | /* |
| 269 | * IVA2 (IVA2) |
| 270 | */ |
| 271 | |
| 272 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 273 | .name = "iva", |
| 274 | .class = &iva_hwmod_class, |
| 275 | .masters = omap2420_iva_masters, |
| 276 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), |
| 277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
| 278 | }; |
| 279 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 280 | /* l4_wkup -> wd_timer2 */ |
| 281 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 282 | { |
| 283 | .pa_start = 0x48022000, |
| 284 | .pa_end = 0x4802207f, |
| 285 | .flags = ADDR_TYPE_RT |
| 286 | }, |
| 287 | }; |
| 288 | |
| 289 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 290 | .master = &omap2420_l4_wkup_hwmod, |
| 291 | .slave = &omap2420_wd_timer2_hwmod, |
| 292 | .clk = "mpu_wdt_ick", |
| 293 | .addr = omap2420_wd_timer2_addrs, |
| 294 | .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), |
| 295 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 296 | }; |
| 297 | |
| 298 | /* |
| 299 | * 'wd_timer' class |
| 300 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 301 | * overflow condition |
| 302 | */ |
| 303 | |
| 304 | static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { |
| 305 | .rev_offs = 0x0000, |
| 306 | .sysc_offs = 0x0010, |
| 307 | .syss_offs = 0x0014, |
| 308 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 309 | SYSC_HAS_AUTOIDLE), |
| 310 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 311 | }; |
| 312 | |
| 313 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
| 314 | .name = "wd_timer", |
| 315 | .sysc = &omap2420_wd_timer_sysc, |
| 316 | }; |
| 317 | |
| 318 | /* wd_timer2 */ |
| 319 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { |
| 320 | &omap2420_l4_wkup__wd_timer2, |
| 321 | }; |
| 322 | |
| 323 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 324 | .name = "wd_timer2", |
| 325 | .class = &omap2420_wd_timer_hwmod_class, |
| 326 | .main_clk = "mpu_wdt_fck", |
| 327 | .prcm = { |
| 328 | .omap2 = { |
| 329 | .prcm_reg_id = 1, |
| 330 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 331 | .module_offs = WKUP_MOD, |
| 332 | .idlest_reg_id = 1, |
| 333 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 334 | }, |
| 335 | }, |
| 336 | .slaves = omap2420_wd_timer2_slaves, |
| 337 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), |
| 338 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 339 | }; |
| 340 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 341 | /* UART */ |
| 342 | |
| 343 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 344 | .rev_offs = 0x50, |
| 345 | .sysc_offs = 0x54, |
| 346 | .syss_offs = 0x58, |
| 347 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 348 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 349 | SYSC_HAS_AUTOIDLE), |
| 350 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 351 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 352 | }; |
| 353 | |
| 354 | static struct omap_hwmod_class uart_class = { |
| 355 | .name = "uart", |
| 356 | .sysc = &uart_sysc, |
| 357 | }; |
| 358 | |
| 359 | /* UART1 */ |
| 360 | |
| 361 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { |
| 362 | { .irq = INT_24XX_UART1_IRQ, }, |
| 363 | }; |
| 364 | |
| 365 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { |
| 366 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, |
| 367 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, |
| 368 | }; |
| 369 | |
| 370 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
| 371 | &omap2_l4_core__uart1, |
| 372 | }; |
| 373 | |
| 374 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 375 | .name = "uart1", |
| 376 | .mpu_irqs = uart1_mpu_irqs, |
| 377 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), |
| 378 | .sdma_reqs = uart1_sdma_reqs, |
| 379 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), |
| 380 | .main_clk = "uart1_fck", |
| 381 | .prcm = { |
| 382 | .omap2 = { |
| 383 | .module_offs = CORE_MOD, |
| 384 | .prcm_reg_id = 1, |
| 385 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 386 | .idlest_reg_id = 1, |
| 387 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 388 | }, |
| 389 | }, |
| 390 | .slaves = omap2420_uart1_slaves, |
| 391 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), |
| 392 | .class = &uart_class, |
| 393 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 394 | }; |
| 395 | |
| 396 | /* UART2 */ |
| 397 | |
| 398 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { |
| 399 | { .irq = INT_24XX_UART2_IRQ, }, |
| 400 | }; |
| 401 | |
| 402 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { |
| 403 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, |
| 404 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, |
| 405 | }; |
| 406 | |
| 407 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
| 408 | &omap2_l4_core__uart2, |
| 409 | }; |
| 410 | |
| 411 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 412 | .name = "uart2", |
| 413 | .mpu_irqs = uart2_mpu_irqs, |
| 414 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), |
| 415 | .sdma_reqs = uart2_sdma_reqs, |
| 416 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), |
| 417 | .main_clk = "uart2_fck", |
| 418 | .prcm = { |
| 419 | .omap2 = { |
| 420 | .module_offs = CORE_MOD, |
| 421 | .prcm_reg_id = 1, |
| 422 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 423 | .idlest_reg_id = 1, |
| 424 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 425 | }, |
| 426 | }, |
| 427 | .slaves = omap2420_uart2_slaves, |
| 428 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), |
| 429 | .class = &uart_class, |
| 430 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 431 | }; |
| 432 | |
| 433 | /* UART3 */ |
| 434 | |
| 435 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { |
| 436 | { .irq = INT_24XX_UART3_IRQ, }, |
| 437 | }; |
| 438 | |
| 439 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { |
| 440 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, |
| 441 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, |
| 442 | }; |
| 443 | |
| 444 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
| 445 | &omap2_l4_core__uart3, |
| 446 | }; |
| 447 | |
| 448 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 449 | .name = "uart3", |
| 450 | .mpu_irqs = uart3_mpu_irqs, |
| 451 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), |
| 452 | .sdma_reqs = uart3_sdma_reqs, |
| 453 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), |
| 454 | .main_clk = "uart3_fck", |
| 455 | .prcm = { |
| 456 | .omap2 = { |
| 457 | .module_offs = CORE_MOD, |
| 458 | .prcm_reg_id = 2, |
| 459 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 460 | .idlest_reg_id = 2, |
| 461 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 462 | }, |
| 463 | }, |
| 464 | .slaves = omap2420_uart3_slaves, |
| 465 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), |
| 466 | .class = &uart_class, |
| 467 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 468 | }; |
| 469 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 470 | /* I2C common */ |
| 471 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 472 | .rev_offs = 0x00, |
| 473 | .sysc_offs = 0x20, |
| 474 | .syss_offs = 0x10, |
| 475 | .sysc_flags = SYSC_HAS_SOFTRESET, |
| 476 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 477 | }; |
| 478 | |
| 479 | static struct omap_hwmod_class i2c_class = { |
| 480 | .name = "i2c", |
| 481 | .sysc = &i2c_sysc, |
| 482 | }; |
| 483 | |
| 484 | static struct omap_i2c_dev_attr i2c_dev_attr; |
| 485 | |
| 486 | /* I2C1 */ |
| 487 | |
| 488 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
| 489 | { .irq = INT_24XX_I2C1_IRQ, }, |
| 490 | }; |
| 491 | |
| 492 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { |
| 493 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, |
| 494 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, |
| 495 | }; |
| 496 | |
| 497 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
| 498 | &omap2420_l4_core__i2c1, |
| 499 | }; |
| 500 | |
| 501 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 502 | .name = "i2c1", |
| 503 | .mpu_irqs = i2c1_mpu_irqs, |
| 504 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), |
| 505 | .sdma_reqs = i2c1_sdma_reqs, |
| 506 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), |
| 507 | .main_clk = "i2c1_fck", |
| 508 | .prcm = { |
| 509 | .omap2 = { |
| 510 | .module_offs = CORE_MOD, |
| 511 | .prcm_reg_id = 1, |
| 512 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 513 | .idlest_reg_id = 1, |
| 514 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 515 | }, |
| 516 | }, |
| 517 | .slaves = omap2420_i2c1_slaves, |
| 518 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), |
| 519 | .class = &i2c_class, |
| 520 | .dev_attr = &i2c_dev_attr, |
| 521 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 522 | .flags = HWMOD_16BIT_REG, |
| 523 | }; |
| 524 | |
| 525 | /* I2C2 */ |
| 526 | |
| 527 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
| 528 | { .irq = INT_24XX_I2C2_IRQ, }, |
| 529 | }; |
| 530 | |
| 531 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { |
| 532 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, |
| 533 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, |
| 534 | }; |
| 535 | |
| 536 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
| 537 | &omap2420_l4_core__i2c2, |
| 538 | }; |
| 539 | |
| 540 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 541 | .name = "i2c2", |
| 542 | .mpu_irqs = i2c2_mpu_irqs, |
| 543 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), |
| 544 | .sdma_reqs = i2c2_sdma_reqs, |
| 545 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), |
| 546 | .main_clk = "i2c2_fck", |
| 547 | .prcm = { |
| 548 | .omap2 = { |
| 549 | .module_offs = CORE_MOD, |
| 550 | .prcm_reg_id = 1, |
| 551 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 552 | .idlest_reg_id = 1, |
| 553 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 554 | }, |
| 555 | }, |
| 556 | .slaves = omap2420_i2c2_slaves, |
| 557 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), |
| 558 | .class = &i2c_class, |
| 559 | .dev_attr = &i2c_dev_attr, |
| 560 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 561 | .flags = HWMOD_16BIT_REG, |
| 562 | }; |
| 563 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 564 | /* l4_wkup -> gpio1 */ |
| 565 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 566 | { |
| 567 | .pa_start = 0x48018000, |
| 568 | .pa_end = 0x480181ff, |
| 569 | .flags = ADDR_TYPE_RT |
| 570 | }, |
| 571 | }; |
| 572 | |
| 573 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
| 574 | .master = &omap2420_l4_wkup_hwmod, |
| 575 | .slave = &omap2420_gpio1_hwmod, |
| 576 | .clk = "gpios_ick", |
| 577 | .addr = omap2420_gpio1_addr_space, |
| 578 | .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), |
| 579 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 580 | }; |
| 581 | |
| 582 | /* l4_wkup -> gpio2 */ |
| 583 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 584 | { |
| 585 | .pa_start = 0x4801a000, |
| 586 | .pa_end = 0x4801a1ff, |
| 587 | .flags = ADDR_TYPE_RT |
| 588 | }, |
| 589 | }; |
| 590 | |
| 591 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
| 592 | .master = &omap2420_l4_wkup_hwmod, |
| 593 | .slave = &omap2420_gpio2_hwmod, |
| 594 | .clk = "gpios_ick", |
| 595 | .addr = omap2420_gpio2_addr_space, |
| 596 | .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), |
| 597 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 598 | }; |
| 599 | |
| 600 | /* l4_wkup -> gpio3 */ |
| 601 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 602 | { |
| 603 | .pa_start = 0x4801c000, |
| 604 | .pa_end = 0x4801c1ff, |
| 605 | .flags = ADDR_TYPE_RT |
| 606 | }, |
| 607 | }; |
| 608 | |
| 609 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
| 610 | .master = &omap2420_l4_wkup_hwmod, |
| 611 | .slave = &omap2420_gpio3_hwmod, |
| 612 | .clk = "gpios_ick", |
| 613 | .addr = omap2420_gpio3_addr_space, |
| 614 | .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), |
| 615 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 616 | }; |
| 617 | |
| 618 | /* l4_wkup -> gpio4 */ |
| 619 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 620 | { |
| 621 | .pa_start = 0x4801e000, |
| 622 | .pa_end = 0x4801e1ff, |
| 623 | .flags = ADDR_TYPE_RT |
| 624 | }, |
| 625 | }; |
| 626 | |
| 627 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
| 628 | .master = &omap2420_l4_wkup_hwmod, |
| 629 | .slave = &omap2420_gpio4_hwmod, |
| 630 | .clk = "gpios_ick", |
| 631 | .addr = omap2420_gpio4_addr_space, |
| 632 | .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), |
| 633 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 634 | }; |
| 635 | |
| 636 | /* gpio dev_attr */ |
| 637 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 638 | .bank_width = 32, |
| 639 | .dbck_flag = false, |
| 640 | }; |
| 641 | |
| 642 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { |
| 643 | .rev_offs = 0x0000, |
| 644 | .sysc_offs = 0x0010, |
| 645 | .syss_offs = 0x0014, |
| 646 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 647 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 648 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 649 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 650 | }; |
| 651 | |
| 652 | /* |
| 653 | * 'gpio' class |
| 654 | * general purpose io module |
| 655 | */ |
| 656 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { |
| 657 | .name = "gpio", |
| 658 | .sysc = &omap242x_gpio_sysc, |
| 659 | .rev = 0, |
| 660 | }; |
| 661 | |
| 662 | /* gpio1 */ |
| 663 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { |
| 664 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ |
| 665 | }; |
| 666 | |
| 667 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { |
| 668 | &omap2420_l4_wkup__gpio1, |
| 669 | }; |
| 670 | |
| 671 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
| 672 | .name = "gpio1", |
| 673 | .mpu_irqs = omap242x_gpio1_irqs, |
| 674 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), |
| 675 | .main_clk = "gpios_fck", |
| 676 | .prcm = { |
| 677 | .omap2 = { |
| 678 | .prcm_reg_id = 1, |
| 679 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 680 | .module_offs = WKUP_MOD, |
| 681 | .idlest_reg_id = 1, |
| 682 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 683 | }, |
| 684 | }, |
| 685 | .slaves = omap2420_gpio1_slaves, |
| 686 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), |
| 687 | .class = &omap242x_gpio_hwmod_class, |
| 688 | .dev_attr = &gpio_dev_attr, |
| 689 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 690 | }; |
| 691 | |
| 692 | /* gpio2 */ |
| 693 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { |
| 694 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ |
| 695 | }; |
| 696 | |
| 697 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { |
| 698 | &omap2420_l4_wkup__gpio2, |
| 699 | }; |
| 700 | |
| 701 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
| 702 | .name = "gpio2", |
| 703 | .mpu_irqs = omap242x_gpio2_irqs, |
| 704 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), |
| 705 | .main_clk = "gpios_fck", |
| 706 | .prcm = { |
| 707 | .omap2 = { |
| 708 | .prcm_reg_id = 1, |
| 709 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 710 | .module_offs = WKUP_MOD, |
| 711 | .idlest_reg_id = 1, |
| 712 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 713 | }, |
| 714 | }, |
| 715 | .slaves = omap2420_gpio2_slaves, |
| 716 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), |
| 717 | .class = &omap242x_gpio_hwmod_class, |
| 718 | .dev_attr = &gpio_dev_attr, |
| 719 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 720 | }; |
| 721 | |
| 722 | /* gpio3 */ |
| 723 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { |
| 724 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ |
| 725 | }; |
| 726 | |
| 727 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { |
| 728 | &omap2420_l4_wkup__gpio3, |
| 729 | }; |
| 730 | |
| 731 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
| 732 | .name = "gpio3", |
| 733 | .mpu_irqs = omap242x_gpio3_irqs, |
| 734 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), |
| 735 | .main_clk = "gpios_fck", |
| 736 | .prcm = { |
| 737 | .omap2 = { |
| 738 | .prcm_reg_id = 1, |
| 739 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 740 | .module_offs = WKUP_MOD, |
| 741 | .idlest_reg_id = 1, |
| 742 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 743 | }, |
| 744 | }, |
| 745 | .slaves = omap2420_gpio3_slaves, |
| 746 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), |
| 747 | .class = &omap242x_gpio_hwmod_class, |
| 748 | .dev_attr = &gpio_dev_attr, |
| 749 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 750 | }; |
| 751 | |
| 752 | /* gpio4 */ |
| 753 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { |
| 754 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ |
| 755 | }; |
| 756 | |
| 757 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { |
| 758 | &omap2420_l4_wkup__gpio4, |
| 759 | }; |
| 760 | |
| 761 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
| 762 | .name = "gpio4", |
| 763 | .mpu_irqs = omap242x_gpio4_irqs, |
| 764 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), |
| 765 | .main_clk = "gpios_fck", |
| 766 | .prcm = { |
| 767 | .omap2 = { |
| 768 | .prcm_reg_id = 1, |
| 769 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 770 | .module_offs = WKUP_MOD, |
| 771 | .idlest_reg_id = 1, |
| 772 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 773 | }, |
| 774 | }, |
| 775 | .slaves = omap2420_gpio4_slaves, |
| 776 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), |
| 777 | .class = &omap242x_gpio_hwmod_class, |
| 778 | .dev_attr = &gpio_dev_attr, |
| 779 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 780 | }; |
| 781 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 782 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 783 | &omap2420_l3_main_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 784 | &omap2420_l4_core_hwmod, |
| 785 | &omap2420_l4_wkup_hwmod, |
| 786 | &omap2420_mpu_hwmod, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 787 | &omap2420_iva_hwmod, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 788 | &omap2420_wd_timer2_hwmod, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 789 | &omap2420_uart1_hwmod, |
| 790 | &omap2420_uart2_hwmod, |
| 791 | &omap2420_uart3_hwmod, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 792 | &omap2420_i2c1_hwmod, |
| 793 | &omap2420_i2c2_hwmod, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 794 | |
| 795 | /* gpio class */ |
| 796 | &omap2420_gpio1_hwmod, |
| 797 | &omap2420_gpio2_hwmod, |
| 798 | &omap2420_gpio3_hwmod, |
| 799 | &omap2420_gpio4_hwmod, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 800 | NULL, |
| 801 | }; |
| 802 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 803 | int __init omap2420_hwmod_init(void) |
| 804 | { |
| 805 | return omap_hwmod_init(omap2420_hwmods); |
| 806 | } |