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Abhijeet Dharmapurikarfb4a2f82012-08-23 14:36:59 -07001/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
Joel Nidere5de00e2012-07-03 10:58:10 +030018#include <linux/gpio.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/clkdev.h>
Hemant Kumard86c4882012-01-24 19:39:37 -080020#include <linux/dma-mapping.h>
Pratik Patel1746b8f2012-06-02 21:11:41 -070021#include <linux/coresight.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070022#include <mach/irqs-8064.h>
23#include <mach/board.h>
24#include <mach/msm_iomap.h>
Yan He06913ce2011-08-26 16:33:46 -070025#include <mach/usbdiag.h>
26#include <mach/msm_sps.h>
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -070027#include <mach/dma.h>
Jin Hongd3024e62012-02-09 16:13:32 -080028#include <mach/msm_dsps.h>
Matt Wagantall33d01f52012-02-23 23:27:44 -080029#include <mach/clk-provider.h>
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -080030#include <sound/msm-dai-q6.h>
31#include <sound/apr_audio.h>
Joel Nidere5de00e2012-07-03 10:58:10 +030032#include <mach/msm_tsif.h>
Joel Nider50b50fa2012-08-05 14:17:29 +030033#include <mach/msm_tspp.h>
Gagan Mac8a7a5d32011-11-11 16:43:06 -070034#include <mach/msm_bus_board.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060035#include <mach/rpm.h>
Joel Kingdacbc822012-01-25 13:30:57 -080036#include <mach/mdm2.h>
Eric Holmberg023d25c2012-03-01 12:27:55 -070037#include <mach/msm_smd.h>
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -070038#include <mach/msm_dcvs.h>
Laura Abbott532b2df2012-04-12 10:53:48 -070039#include <mach/msm_rtb.h>
Mitchel Humpherysa67e37f2012-09-06 11:35:39 -070040#include <linux/msm_ion.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070041#include "clock.h"
42#include "devices.h"
Matt Wagantall1875d322012-02-22 16:11:33 -080043#include "footswitch.h"
Jeff Ohlstein7e668552011-10-06 16:17:25 -070044#include "msm_watchdog.h"
Praveen Chidambaram78499012011-11-01 17:15:17 -060045#include "rpm_stats.h"
46#include "rpm_log.h"
Subhash Jadavani909e04f2012-04-12 10:52:50 +053047#include <mach/mpm.h>
Laura Abbott0577d7b2012-04-17 11:14:30 -070048#include <mach/iommu_domains.h>
Laura Abbott93a4a352012-05-25 09:26:35 -070049#include <mach/msm_cache_dump.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070050
51/* Address of GSBI blocks */
Stepan Moskovchenko2701a442011-08-19 13:47:22 -070052#define MSM_GSBI1_PHYS 0x12440000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070053#define MSM_GSBI3_PHYS 0x16200000
Harini Jayaramanc4c58692011-07-19 14:50:10 -060054#define MSM_GSBI4_PHYS 0x16300000
55#define MSM_GSBI5_PHYS 0x1A200000
56#define MSM_GSBI6_PHYS 0x16500000
57#define MSM_GSBI7_PHYS 0x16600000
58
Kenneth Heitke748593a2011-07-15 15:45:11 -060059/* GSBI UART devices */
Stepan Moskovchenko2701a442011-08-19 13:47:22 -070060#define MSM_UART1DM_PHYS (MSM_GSBI1_PHYS + 0x10000)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070061#define MSM_UART3DM_PHYS (MSM_GSBI3_PHYS + 0x40000)
Mayank Rana262e9032012-05-10 15:14:00 -070062#define MSM_UART6DM_PHYS (MSM_GSBI6_PHYS + 0x40000)
Jin Hong4bbbfba2012-02-02 21:48:07 -080063#define MSM_UART7DM_PHYS (MSM_GSBI7_PHYS + 0x40000)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064
Harini Jayaramanc4c58692011-07-19 14:50:10 -060065/* GSBI QUP devices */
David Keitel3c40fc52012-02-09 17:53:52 -080066#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x20000)
Harini Jayaramanc4c58692011-07-19 14:50:10 -060067#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
68#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
69#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
70#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
71#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
72#define MSM_QUP_SIZE SZ_4K
73
Kenneth Heitke36920d32011-07-20 16:44:30 -060074/* Address of SSBI CMD */
75#define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000
76#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
77#define MSM_PMIC_SSBI_SIZE SZ_4K
Harini Jayaramanc4c58692011-07-19 14:50:10 -060078
Hemant Kumarcaa09092011-07-30 00:26:33 -070079/* Address of HS USBOTG1 */
Hemant Kumard86c4882012-01-24 19:39:37 -080080#define MSM_HSUSB1_PHYS 0x12500000
81#define MSM_HSUSB1_SIZE SZ_4K
Hemant Kumarcaa09092011-07-30 00:26:33 -070082
Manu Gautam91223e02011-11-08 15:27:22 +053083/* Address of HS USB3 */
84#define MSM_HSUSB3_PHYS 0x12520000
85#define MSM_HSUSB3_SIZE SZ_4K
86
Hemant Kumar1d66e1c2012-02-13 15:24:59 -080087/* Address of HS USB4 */
88#define MSM_HSUSB4_PHYS 0x12530000
89#define MSM_HSUSB4_SIZE SZ_4K
90
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -060091/* Address of PCIE20 PARF */
92#define PCIE20_PARF_PHYS 0x1b600000
93#define PCIE20_PARF_SIZE SZ_128
94
95/* Address of PCIE20 ELBI */
96#define PCIE20_ELBI_PHYS 0x1b502000
97#define PCIE20_ELBI_SIZE SZ_256
98
99/* Address of PCIE20 */
100#define PCIE20_PHYS 0x1b500000
101#define PCIE20_SIZE SZ_4K
Anji Jonnala6c2b6852012-09-21 13:34:44 +0530102#define MSM8064_PC_CNTR_PHYS (APQ8064_IMEM_PHYS + 0x664)
103#define MSM8064_PC_CNTR_SIZE 0x40
Anji Jonnala93129922012-10-09 20:57:53 +0530104#define MSM8064_RPM_MASTER_STATS_BASE 0x10BB00
Anji Jonnala6c2b6852012-09-21 13:34:44 +0530105
106static struct resource msm8064_resources_pccntr[] = {
107 {
108 .start = MSM8064_PC_CNTR_PHYS,
109 .end = MSM8064_PC_CNTR_PHYS + MSM8064_PC_CNTR_SIZE,
110 .flags = IORESOURCE_MEM,
111 },
112};
113
114struct platform_device msm8064_pc_cntr = {
115 .name = "pc-cntr",
116 .id = -1,
117 .num_resources = ARRAY_SIZE(msm8064_resources_pccntr),
118 .resource = msm8064_resources_pccntr,
119};
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -0600120
Jeff Ohlstein7e668552011-10-06 16:17:25 -0700121static struct msm_watchdog_pdata msm_watchdog_pdata = {
122 .pet_time = 10000,
123 .bark_time = 11000,
124 .has_secure = true,
Joel Kinge7ca6f72012-02-09 20:51:25 -0800125 .needs_expired_enable = true,
Rohit Vaswanic77e4a62012-08-09 18:10:28 -0700126 .base = MSM_TMR0_BASE + WDT0_OFFSET,
127};
128
129static struct resource msm_watchdog_resources[] = {
130 {
131 .start = WDT0_ACCSCSSNBARK_INT,
132 .end = WDT0_ACCSCSSNBARK_INT,
133 .flags = IORESOURCE_IRQ,
134 },
Jeff Ohlstein7e668552011-10-06 16:17:25 -0700135};
136
137struct platform_device msm8064_device_watchdog = {
138 .name = "msm_watchdog",
139 .id = -1,
140 .dev = {
141 .platform_data = &msm_watchdog_pdata,
142 },
Rohit Vaswanic77e4a62012-08-09 18:10:28 -0700143 .num_resources = ARRAY_SIZE(msm_watchdog_resources),
144 .resource = msm_watchdog_resources,
Jeff Ohlstein7e668552011-10-06 16:17:25 -0700145};
146
Joel King0581896d2011-07-19 16:43:28 -0700147static struct resource msm_dmov_resource[] = {
148 {
Jeff Ohlstein4af72692011-11-07 15:59:17 -0800149 .start = ADM_0_SCSS_1_IRQ,
Joel King0581896d2011-07-19 16:43:28 -0700150 .flags = IORESOURCE_IRQ,
151 },
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700152 {
Jeff Ohlstein4af72692011-11-07 15:59:17 -0800153 .start = 0x18320000,
154 .end = 0x18320000 + SZ_1M - 1,
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700155 .flags = IORESOURCE_MEM,
156 },
157};
158
159static struct msm_dmov_pdata msm_dmov_pdata = {
Jeff Ohlstein4af72692011-11-07 15:59:17 -0800160 .sd = 1,
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700161 .sd_size = 0x800,
Joel King0581896d2011-07-19 16:43:28 -0700162};
163
Stepan Moskovchenkodf13d342011-08-03 19:01:25 -0700164struct platform_device apq8064_device_dmov = {
Joel King0581896d2011-07-19 16:43:28 -0700165 .name = "msm_dmov",
166 .id = -1,
167 .resource = msm_dmov_resource,
168 .num_resources = ARRAY_SIZE(msm_dmov_resource),
Jeff Ohlstein905f1ce2011-09-07 18:50:18 -0700169 .dev = {
170 .platform_data = &msm_dmov_pdata,
171 },
Joel King0581896d2011-07-19 16:43:28 -0700172};
173
Stepan Moskovchenko2701a442011-08-19 13:47:22 -0700174static struct resource resources_uart_gsbi1[] = {
175 {
176 .start = APQ8064_GSBI1_UARTDM_IRQ,
177 .end = APQ8064_GSBI1_UARTDM_IRQ,
178 .flags = IORESOURCE_IRQ,
179 },
180 {
181 .start = MSM_UART1DM_PHYS,
182 .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
183 .name = "uartdm_resource",
184 .flags = IORESOURCE_MEM,
185 },
186 {
187 .start = MSM_GSBI1_PHYS,
188 .end = MSM_GSBI1_PHYS + PAGE_SIZE - 1,
189 .name = "gsbi_resource",
190 .flags = IORESOURCE_MEM,
191 },
192};
193
194struct platform_device apq8064_device_uart_gsbi1 = {
195 .name = "msm_serial_hsl",
Jin Hong4bbbfba2012-02-02 21:48:07 -0800196 .id = 1,
Stepan Moskovchenko2701a442011-08-19 13:47:22 -0700197 .num_resources = ARRAY_SIZE(resources_uart_gsbi1),
198 .resource = resources_uart_gsbi1,
199};
200
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700201static struct resource resources_uart_gsbi3[] = {
202 {
203 .start = GSBI3_UARTDM_IRQ,
204 .end = GSBI3_UARTDM_IRQ,
205 .flags = IORESOURCE_IRQ,
206 },
207 {
208 .start = MSM_UART3DM_PHYS,
209 .end = MSM_UART3DM_PHYS + PAGE_SIZE - 1,
210 .name = "uartdm_resource",
211 .flags = IORESOURCE_MEM,
212 },
213 {
214 .start = MSM_GSBI3_PHYS,
215 .end = MSM_GSBI3_PHYS + PAGE_SIZE - 1,
216 .name = "gsbi_resource",
217 .flags = IORESOURCE_MEM,
218 },
219};
220
221struct platform_device apq8064_device_uart_gsbi3 = {
222 .name = "msm_serial_hsl",
223 .id = 0,
224 .num_resources = ARRAY_SIZE(resources_uart_gsbi3),
225 .resource = resources_uart_gsbi3,
226};
227
Jing Lin04601f92012-02-05 15:36:07 -0800228static struct resource resources_qup_i2c_gsbi3[] = {
229 {
230 .name = "gsbi_qup_i2c_addr",
231 .start = MSM_GSBI3_PHYS,
232 .end = MSM_GSBI3_PHYS + 4 - 1,
233 .flags = IORESOURCE_MEM,
234 },
235 {
236 .name = "qup_phys_addr",
237 .start = MSM_GSBI3_QUP_PHYS,
238 .end = MSM_GSBI3_QUP_PHYS + MSM_QUP_SIZE - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 {
242 .name = "qup_err_intr",
243 .start = GSBI3_QUP_IRQ,
244 .end = GSBI3_QUP_IRQ,
245 .flags = IORESOURCE_IRQ,
246 },
247 {
248 .name = "i2c_clk",
249 .start = 9,
250 .end = 9,
251 .flags = IORESOURCE_IO,
252 },
253 {
254 .name = "i2c_sda",
255 .start = 8,
256 .end = 8,
257 .flags = IORESOURCE_IO,
258 },
259};
260
David Keitel3c40fc52012-02-09 17:53:52 -0800261static struct resource resources_qup_i2c_gsbi1[] = {
262 {
263 .name = "gsbi_qup_i2c_addr",
264 .start = MSM_GSBI1_PHYS,
265 .end = MSM_GSBI1_PHYS + 4 - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 {
269 .name = "qup_phys_addr",
270 .start = MSM_GSBI1_QUP_PHYS,
271 .end = MSM_GSBI1_QUP_PHYS + MSM_QUP_SIZE - 1,
272 .flags = IORESOURCE_MEM,
273 },
274 {
275 .name = "qup_err_intr",
276 .start = APQ8064_GSBI1_QUP_IRQ,
277 .end = APQ8064_GSBI1_QUP_IRQ,
278 .flags = IORESOURCE_IRQ,
279 },
280 {
281 .name = "i2c_clk",
282 .start = 21,
283 .end = 21,
284 .flags = IORESOURCE_IO,
285 },
286 {
287 .name = "i2c_sda",
288 .start = 20,
289 .end = 20,
290 .flags = IORESOURCE_IO,
291 },
292};
293
294struct platform_device apq8064_device_qup_i2c_gsbi1 = {
295 .name = "qup_i2c",
296 .id = 0,
297 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi1),
298 .resource = resources_qup_i2c_gsbi1,
299};
300
Jing Lin04601f92012-02-05 15:36:07 -0800301struct platform_device apq8064_device_qup_i2c_gsbi3 = {
302 .name = "qup_i2c",
303 .id = 3,
304 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi3),
305 .resource = resources_qup_i2c_gsbi3,
306};
307
Kenneth Heitke748593a2011-07-15 15:45:11 -0600308static struct resource resources_qup_i2c_gsbi4[] = {
309 {
310 .name = "gsbi_qup_i2c_addr",
311 .start = MSM_GSBI4_PHYS,
Harini Jayaramane1554a92011-09-15 14:43:02 -0600312 .end = MSM_GSBI4_PHYS + 4 - 1,
Kenneth Heitke748593a2011-07-15 15:45:11 -0600313 .flags = IORESOURCE_MEM,
314 },
315 {
316 .name = "qup_phys_addr",
317 .start = MSM_GSBI4_QUP_PHYS,
Harini Jayaramane1554a92011-09-15 14:43:02 -0600318 .end = MSM_GSBI4_QUP_PHYS + MSM_QUP_SIZE - 1,
Kenneth Heitke748593a2011-07-15 15:45:11 -0600319 .flags = IORESOURCE_MEM,
320 },
321 {
322 .name = "qup_err_intr",
323 .start = GSBI4_QUP_IRQ,
324 .end = GSBI4_QUP_IRQ,
325 .flags = IORESOURCE_IRQ,
326 },
Kevin Chand07220e2012-02-13 15:52:22 -0800327 {
328 .name = "i2c_clk",
329 .start = 11,
330 .end = 11,
331 .flags = IORESOURCE_IO,
332 },
333 {
334 .name = "i2c_sda",
335 .start = 10,
336 .end = 10,
337 .flags = IORESOURCE_IO,
338 },
Kenneth Heitke748593a2011-07-15 15:45:11 -0600339};
340
341struct platform_device apq8064_device_qup_i2c_gsbi4 = {
342 .name = "qup_i2c",
343 .id = 4,
344 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4),
345 .resource = resources_qup_i2c_gsbi4,
346};
347
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700348static struct resource resources_qup_spi_gsbi5[] = {
349 {
350 .name = "spi_base",
351 .start = MSM_GSBI5_QUP_PHYS,
352 .end = MSM_GSBI5_QUP_PHYS + SZ_4K - 1,
353 .flags = IORESOURCE_MEM,
354 },
355 {
356 .name = "gsbi_base",
357 .start = MSM_GSBI5_PHYS,
358 .end = MSM_GSBI5_PHYS + 4 - 1,
359 .flags = IORESOURCE_MEM,
360 },
361 {
362 .name = "spi_irq_in",
363 .start = GSBI5_QUP_IRQ,
364 .end = GSBI5_QUP_IRQ,
365 .flags = IORESOURCE_IRQ,
366 },
367};
368
369struct platform_device apq8064_device_qup_spi_gsbi5 = {
370 .name = "spi_qsd",
371 .id = 0,
372 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi5),
373 .resource = resources_qup_spi_gsbi5,
374};
375
Bar Weinerf82c5872012-10-23 14:31:26 +0200376static struct resource resources_qup_spi_gsbi6[] = {
377 {
378 .name = "spi_base",
379 .start = MSM_GSBI6_QUP_PHYS,
380 .end = MSM_GSBI6_QUP_PHYS + SZ_4K - 1,
381 .flags = IORESOURCE_MEM,
382 },
383 {
384 .name = "gsbi_base",
385 .start = MSM_GSBI6_PHYS,
386 .end = MSM_GSBI6_PHYS + 4 - 1,
387 .flags = IORESOURCE_MEM,
388 },
389 {
390 .name = "spi_irq_in",
391 .start = GSBI6_QUP_IRQ,
392 .end = GSBI6_QUP_IRQ,
393 .flags = IORESOURCE_IRQ,
394 },
395 {
396 .name = "spi_clk",
397 .start = 17,
398 .end = 17,
399 .flags = IORESOURCE_IO,
400 },
401 {
402 .name = "spi_miso",
403 .start = 15,
404 .end = 15,
405 .flags = IORESOURCE_IO,
406 },
407 {
408 .name = "spi_mosi",
409 .start = 14,
410 .end = 14,
411 .flags = IORESOURCE_IO,
412 },
413 {
414 .name = "spi_cs",
415 .start = 16,
416 .end = 16,
417 .flags = IORESOURCE_IO,
418 }
419};
420
421struct platform_device mpq8064_device_qup_spi_gsbi6 = {
422 .name = "spi_qsd",
423 .id = 1,
424 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi6),
425 .resource = resources_qup_spi_gsbi6,
426};
427
Joel King8f839b92012-04-01 14:37:46 -0700428static struct resource resources_qup_i2c_gsbi5[] = {
429 {
430 .name = "gsbi_qup_i2c_addr",
431 .start = MSM_GSBI5_PHYS,
432 .end = MSM_GSBI5_PHYS + 4 - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 {
436 .name = "qup_phys_addr",
437 .start = MSM_GSBI5_QUP_PHYS,
438 .end = MSM_GSBI5_QUP_PHYS + MSM_QUP_SIZE - 1,
439 .flags = IORESOURCE_MEM,
440 },
441 {
442 .name = "qup_err_intr",
443 .start = GSBI5_QUP_IRQ,
444 .end = GSBI5_QUP_IRQ,
445 .flags = IORESOURCE_IRQ,
446 },
447 {
448 .name = "i2c_clk",
449 .start = 54,
450 .end = 54,
451 .flags = IORESOURCE_IO,
452 },
453 {
454 .name = "i2c_sda",
455 .start = 53,
456 .end = 53,
457 .flags = IORESOURCE_IO,
458 },
459};
460
461struct platform_device mpq8064_device_qup_i2c_gsbi5 = {
462 .name = "qup_i2c",
463 .id = 5,
464 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi5),
465 .resource = resources_qup_i2c_gsbi5,
466};
467
Mayank Rana262e9032012-05-10 15:14:00 -0700468/* GSBI 6 used into UARTDM Mode */
469static struct resource msm_uart_dm6_resources[] = {
470 {
471 .start = MSM_UART6DM_PHYS,
472 .end = MSM_UART6DM_PHYS + PAGE_SIZE - 1,
473 .name = "uartdm_resource",
474 .flags = IORESOURCE_MEM,
475 },
476 {
477 .start = GSBI6_UARTDM_IRQ,
478 .end = GSBI6_UARTDM_IRQ,
479 .flags = IORESOURCE_IRQ,
480 },
481 {
482 .start = MSM_GSBI6_PHYS,
483 .end = MSM_GSBI6_PHYS + 4 - 1,
484 .name = "gsbi_resource",
485 .flags = IORESOURCE_MEM,
486 },
487 {
488 .start = DMOV_MPQ8064_HSUART_GSBI6_TX_CHAN,
489 .end = DMOV_MPQ8064_HSUART_GSBI6_RX_CHAN,
490 .name = "uartdm_channels",
491 .flags = IORESOURCE_DMA,
492 },
493 {
494 .start = DMOV_MPQ8064_HSUART_GSBI6_TX_CRCI,
495 .end = DMOV_MPQ8064_HSUART_GSBI6_RX_CRCI,
496 .name = "uartdm_crci",
497 .flags = IORESOURCE_DMA,
498 },
499};
500static u64 msm_uart_dm6_dma_mask = DMA_BIT_MASK(32);
501struct platform_device mpq8064_device_uartdm_gsbi6 = {
502 .name = "msm_serial_hs",
503 .id = 0,
504 .num_resources = ARRAY_SIZE(msm_uart_dm6_resources),
505 .resource = msm_uart_dm6_resources,
506 .dev = {
507 .dma_mask = &msm_uart_dm6_dma_mask,
508 .coherent_dma_mask = DMA_BIT_MASK(32),
509 },
510};
511
Jin Hong4bbbfba2012-02-02 21:48:07 -0800512static struct resource resources_uart_gsbi7[] = {
513 {
514 .start = GSBI7_UARTDM_IRQ,
515 .end = GSBI7_UARTDM_IRQ,
516 .flags = IORESOURCE_IRQ,
517 },
518 {
519 .start = MSM_UART7DM_PHYS,
520 .end = MSM_UART7DM_PHYS + PAGE_SIZE - 1,
521 .name = "uartdm_resource",
522 .flags = IORESOURCE_MEM,
523 },
524 {
525 .start = MSM_GSBI7_PHYS,
526 .end = MSM_GSBI7_PHYS + PAGE_SIZE - 1,
527 .name = "gsbi_resource",
528 .flags = IORESOURCE_MEM,
529 },
530};
531
532struct platform_device apq8064_device_uart_gsbi7 = {
533 .name = "msm_serial_hsl",
534 .id = 0,
535 .num_resources = ARRAY_SIZE(resources_uart_gsbi7),
536 .resource = resources_uart_gsbi7,
537};
538
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800539struct platform_device apq_pcm = {
540 .name = "msm-pcm-dsp",
541 .id = -1,
542};
543
544struct platform_device apq_pcm_routing = {
545 .name = "msm-pcm-routing",
546 .id = -1,
547};
548
549struct platform_device apq_cpudai0 = {
550 .name = "msm-dai-q6",
551 .id = 0x4000,
552};
553
554struct platform_device apq_cpudai1 = {
555 .name = "msm-dai-q6",
556 .id = 0x4001,
557};
Santosh Mardieff9a742012-04-09 23:23:39 +0530558struct platform_device mpq_cpudai_sec_i2s_rx = {
559 .name = "msm-dai-q6",
560 .id = 4,
561};
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800562struct platform_device apq_cpudai_hdmi_rx = {
Swaminathan Sathappanfd9dbad2012-02-15 16:56:44 -0800563 .name = "msm-dai-q6-hdmi",
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800564 .id = 8,
565};
566
567struct platform_device apq_cpudai_bt_rx = {
568 .name = "msm-dai-q6",
569 .id = 0x3000,
570};
571
572struct platform_device apq_cpudai_bt_tx = {
573 .name = "msm-dai-q6",
574 .id = 0x3001,
575};
576
577struct platform_device apq_cpudai_fm_rx = {
578 .name = "msm-dai-q6",
579 .id = 0x3004,
580};
581
582struct platform_device apq_cpudai_fm_tx = {
583 .name = "msm-dai-q6",
584 .id = 0x3005,
585};
586
Helen Zeng8f925502012-03-05 16:50:17 -0800587struct platform_device apq_cpudai_slim_4_rx = {
588 .name = "msm-dai-q6",
589 .id = 0x4008,
590};
591
592struct platform_device apq_cpudai_slim_4_tx = {
593 .name = "msm-dai-q6",
594 .id = 0x4009,
595};
596
Aviral Guptabfa97882012-10-16 12:15:59 +0530597struct platform_device mpq_cpudai_pseudo = {
598 .name = "msm-dai-q6",
599 .id = 0x8001,
600};
Joel Nidere5de00e2012-07-03 10:58:10 +0300601#define MSM_TSIF0_PHYS (0x18200000)
602#define MSM_TSIF1_PHYS (0x18201000)
603#define MSM_TSIF_SIZE (0x200)
604
605#define TSIF_0_CLK GPIO_CFG(55, 1, GPIO_CFG_INPUT, \
606 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
607#define TSIF_0_EN GPIO_CFG(56, 1, GPIO_CFG_INPUT, \
608 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
609#define TSIF_0_DATA GPIO_CFG(57, 1, GPIO_CFG_INPUT, \
610 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
611#define TSIF_0_SYNC GPIO_CFG(62, 1, GPIO_CFG_INPUT, \
612 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
613#define TSIF_1_CLK GPIO_CFG(59, 1, GPIO_CFG_INPUT, \
614 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
615#define TSIF_1_EN GPIO_CFG(60, 1, GPIO_CFG_INPUT, \
616 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
617#define TSIF_1_DATA GPIO_CFG(61, 1, GPIO_CFG_INPUT, \
618 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
619#define TSIF_1_SYNC GPIO_CFG(58, 1, GPIO_CFG_INPUT, \
620 GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
621
622static const struct msm_gpio tsif0_gpios[] = {
623 { .gpio_cfg = TSIF_0_CLK, .label = "tsif_clk", },
624 { .gpio_cfg = TSIF_0_EN, .label = "tsif_en", },
625 { .gpio_cfg = TSIF_0_DATA, .label = "tsif_data", },
626 { .gpio_cfg = TSIF_0_SYNC, .label = "tsif_sync", },
627};
628
629static const struct msm_gpio tsif1_gpios[] = {
630 { .gpio_cfg = TSIF_1_CLK, .label = "tsif_clk", },
631 { .gpio_cfg = TSIF_1_EN, .label = "tsif_en", },
632 { .gpio_cfg = TSIF_1_DATA, .label = "tsif_data", },
633 { .gpio_cfg = TSIF_1_SYNC, .label = "tsif_sync", },
634};
635
636struct msm_tsif_platform_data tsif1_8064_platform_data = {
637 .num_gpios = ARRAY_SIZE(tsif1_gpios),
638 .gpios = tsif1_gpios,
639 .tsif_pclk = "iface_clk",
640 .tsif_ref_clk = "ref_clk",
641};
642
643struct resource tsif1_8064_resources[] = {
644 [0] = {
645 .flags = IORESOURCE_IRQ,
646 .start = TSIF2_IRQ,
647 .end = TSIF2_IRQ,
648 },
649 [1] = {
650 .flags = IORESOURCE_MEM,
651 .start = MSM_TSIF1_PHYS,
652 .end = MSM_TSIF1_PHYS + MSM_TSIF_SIZE - 1,
653 },
654 [2] = {
655 .flags = IORESOURCE_DMA,
656 .start = DMOV8064_TSIF_CHAN,
657 .end = DMOV8064_TSIF_CRCI,
658 },
659};
660
661struct msm_tsif_platform_data tsif0_8064_platform_data = {
662 .num_gpios = ARRAY_SIZE(tsif0_gpios),
663 .gpios = tsif0_gpios,
664 .tsif_pclk = "iface_clk",
665 .tsif_ref_clk = "ref_clk",
666};
667
668struct resource tsif0_8064_resources[] = {
669 [0] = {
670 .flags = IORESOURCE_IRQ,
671 .start = TSIF1_IRQ,
672 .end = TSIF1_IRQ,
673 },
674 [1] = {
675 .flags = IORESOURCE_MEM,
676 .start = MSM_TSIF0_PHYS,
677 .end = MSM_TSIF0_PHYS + MSM_TSIF_SIZE - 1,
678 },
679 [2] = {
680 .flags = IORESOURCE_DMA,
681 .start = DMOV_TSIF_CHAN,
682 .end = DMOV_TSIF_CRCI,
683 },
684};
685
686struct platform_device msm_8064_device_tsif[2] = {
687 {
688 .name = "msm_tsif",
689 .id = 0,
690 .num_resources = ARRAY_SIZE(tsif0_8064_resources),
691 .resource = tsif0_8064_resources,
692 .dev = {
693 .platform_data = &tsif0_8064_platform_data
694 },
695 },
696 {
697 .name = "msm_tsif",
698 .id = 1,
699 .num_resources = ARRAY_SIZE(tsif1_8064_resources),
700 .resource = tsif1_8064_resources,
701 .dev = {
702 .platform_data = &tsif1_8064_platform_data
703 },
704 }
705};
706
Joel Nider50b50fa2012-08-05 14:17:29 +0300707#define MSM_TSPP_PHYS (0x18202000)
708#define MSM_TSPP_SIZE (0x1000)
709#define MSM_TSPP_BAM_PHYS (0x18204000)
710#define MSM_TSPP_BAM_SIZE (0x2000)
711
712static const struct msm_gpio tspp_gpios[] = {
713 { .gpio_cfg = TSIF_0_CLK, .label = "tsif_clk", },
714 { .gpio_cfg = TSIF_0_EN, .label = "tsif_en", },
715 { .gpio_cfg = TSIF_0_DATA, .label = "tsif_data", },
716 { .gpio_cfg = TSIF_0_SYNC, .label = "tsif_sync", },
717 { .gpio_cfg = TSIF_1_CLK, .label = "tsif_clk", },
718 { .gpio_cfg = TSIF_1_EN, .label = "tsif_en", },
719 { .gpio_cfg = TSIF_1_DATA, .label = "tsif_data", },
720 { .gpio_cfg = TSIF_1_SYNC, .label = "tsif_sync", },
721};
722
723static struct resource tspp_resources[] = {
724 [0] = {
725 .flags = IORESOURCE_IRQ,
726 .start = TSIF_TSPP_IRQ,
727 .end = TSIF1_IRQ,
728 },
729 [1] = {
730 .flags = IORESOURCE_MEM,
731 .start = MSM_TSIF0_PHYS,
732 .end = MSM_TSIF0_PHYS + MSM_TSIF_SIZE - 1,
733 },
734 [2] = {
735 .flags = IORESOURCE_MEM,
736 .start = MSM_TSIF1_PHYS,
737 .end = MSM_TSIF1_PHYS + MSM_TSIF_SIZE - 1,
738 },
739 [3] = {
740 .flags = IORESOURCE_MEM,
741 .start = MSM_TSPP_PHYS,
742 .end = MSM_TSPP_PHYS + MSM_TSPP_SIZE - 1,
743 },
744 [4] = {
745 .flags = IORESOURCE_MEM,
746 .start = MSM_TSPP_BAM_PHYS,
747 .end = MSM_TSPP_BAM_PHYS + MSM_TSPP_BAM_SIZE - 1,
748 },
749};
750
751static struct msm_tspp_platform_data tspp_platform_data = {
752 .num_gpios = ARRAY_SIZE(tspp_gpios),
753 .gpios = tspp_gpios,
754 .tsif_pclk = "iface_clk",
755 .tsif_ref_clk = "ref_clk",
756};
757
758struct platform_device msm_8064_device_tspp = {
759 .name = "msm_tspp",
760 .id = 0,
761 .num_resources = ARRAY_SIZE(tspp_resources),
762 .resource = tspp_resources,
763 .dev = {
764 .platform_data = &tspp_platform_data
765 },
766};
767
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800768/*
769 * Machine specific data for AUX PCM Interface
770 * which the driver will be unware of.
771 */
Kiran Kandi5f4ab692012-02-23 11:23:56 -0800772struct msm_dai_auxpcm_pdata apq_auxpcm_pdata = {
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800773 .clk = "pcm_clk",
Kuirong Wang547a9982012-05-04 18:29:11 -0700774 .mode_8k = {
775 .mode = AFE_PCM_CFG_MODE_PCM,
776 .sync = AFE_PCM_CFG_SYNC_INT,
777 .frame = AFE_PCM_CFG_FRM_256BPF,
778 .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD,
779 .slot = 0,
780 .data = AFE_PCM_CFG_CDATAOE_MASTER,
781 .pcm_clk_rate = 2048000,
782 },
783 .mode_16k = {
784 .mode = AFE_PCM_CFG_MODE_PCM,
785 .sync = AFE_PCM_CFG_SYNC_INT,
786 .frame = AFE_PCM_CFG_FRM_256BPF,
787 .quant = AFE_PCM_CFG_QUANT_LINEAR_NOPAD,
788 .slot = 0,
789 .data = AFE_PCM_CFG_CDATAOE_MASTER,
790 .pcm_clk_rate = 4096000,
791 }
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800792};
793
794struct platform_device apq_cpudai_auxpcm_rx = {
795 .name = "msm-dai-q6",
796 .id = 2,
797 .dev = {
Kiran Kandi5f4ab692012-02-23 11:23:56 -0800798 .platform_data = &apq_auxpcm_pdata,
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800799 },
800};
801
802struct platform_device apq_cpudai_auxpcm_tx = {
803 .name = "msm-dai-q6",
804 .id = 3,
Kiran Kandi5f4ab692012-02-23 11:23:56 -0800805 .dev = {
806 .platform_data = &apq_auxpcm_pdata,
807 },
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800808};
809
Patrick Lai04baee942012-05-01 14:38:47 -0700810struct msm_mi2s_pdata mpq_mi2s_tx_data = {
811 .rx_sd_lines = 0,
812 .tx_sd_lines = MSM_MI2S_SD0 | MSM_MI2S_SD1 | MSM_MI2S_SD2 |
813 MSM_MI2S_SD3,
Kuirong Wangf23f8c52012-03-31 12:34:51 -0700814};
815
816struct platform_device mpq_cpudai_mi2s_tx = {
Patrick Lai04baee942012-05-01 14:38:47 -0700817 .name = "msm-dai-q6-mi2s",
818 .id = -1, /*MI2S_TX */
Kuirong Wangf23f8c52012-03-31 12:34:51 -0700819 .dev = {
820 .platform_data = &mpq_mi2s_tx_data,
821 },
822};
823
Kuirong Wangf8c5e142012-06-21 16:17:32 -0700824struct msm_mi2s_pdata apq_mi2s_data = {
825 .rx_sd_lines = MSM_MI2S_SD0,
826 .tx_sd_lines = MSM_MI2S_SD3,
827};
828
829struct platform_device apq_cpudai_mi2s = {
830 .name = "msm-dai-q6-mi2s",
831 .id = -1,
832 .dev = {
833 .platform_data = &apq_mi2s_data,
834 },
835};
836
837struct platform_device apq_cpudai_i2s_rx = {
838 .name = "msm-dai-q6",
839 .id = PRIMARY_I2S_RX,
840};
841
842struct platform_device apq_cpudai_i2s_tx = {
843 .name = "msm-dai-q6",
844 .id = PRIMARY_I2S_TX,
845};
846
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800847struct platform_device apq_cpu_fe = {
848 .name = "msm-dai-fe",
849 .id = -1,
850};
851
852struct platform_device apq_stub_codec = {
853 .name = "msm-stub-codec",
854 .id = 1,
855};
856
857struct platform_device apq_voice = {
858 .name = "msm-pcm-voice",
859 .id = -1,
860};
861
862struct platform_device apq_voip = {
863 .name = "msm-voip-dsp",
864 .id = -1,
865};
866
867struct platform_device apq_lpa_pcm = {
868 .name = "msm-pcm-lpa",
869 .id = -1,
870};
871
Krishnankutty Kolathappilly4374e332012-03-18 22:27:30 -0700872struct platform_device apq_compr_dsp = {
873 .name = "msm-compr-dsp",
874 .id = -1,
875};
876
877struct platform_device apq_multi_ch_pcm = {
878 .name = "msm-multi-ch-pcm-dsp",
879 .id = -1,
880};
881
Jayasena Sangaraboina99bf09c2012-07-17 12:03:08 -0700882struct platform_device apq_lowlatency_pcm = {
883 .name = "msm-lowlatency-pcm-dsp",
884 .id = -1,
885};
886
Bharath Ramachandramurthyb8e797f2011-11-30 12:08:42 -0800887struct platform_device apq_pcm_hostless = {
888 .name = "msm-pcm-hostless",
889 .id = -1,
890};
891
892struct platform_device apq_cpudai_afe_01_rx = {
893 .name = "msm-dai-q6",
894 .id = 0xE0,
895};
896
897struct platform_device apq_cpudai_afe_01_tx = {
898 .name = "msm-dai-q6",
899 .id = 0xF0,
900};
901
902struct platform_device apq_cpudai_afe_02_rx = {
903 .name = "msm-dai-q6",
904 .id = 0xF1,
905};
906
907struct platform_device apq_cpudai_afe_02_tx = {
908 .name = "msm-dai-q6",
909 .id = 0xE1,
910};
911
912struct platform_device apq_pcm_afe = {
913 .name = "msm-pcm-afe",
914 .id = -1,
915};
916
Neema Shetty8427c262012-02-16 11:23:43 -0800917struct platform_device apq_cpudai_stub = {
918 .name = "msm-dai-stub",
919 .id = -1,
920};
921
Neema Shetty3c9d2862012-03-11 01:25:32 -0800922struct platform_device apq_cpudai_slimbus_1_rx = {
923 .name = "msm-dai-q6",
924 .id = 0x4002,
925};
926
927struct platform_device apq_cpudai_slimbus_1_tx = {
928 .name = "msm-dai-q6",
929 .id = 0x4003,
930};
931
Kiran Kandi97fe19d2012-05-20 22:34:04 -0700932struct platform_device apq_cpudai_slimbus_2_rx = {
933 .name = "msm-dai-q6",
934 .id = 0x4004,
935};
936
Kiran Kandi1e6371d2012-03-29 11:48:57 -0700937struct platform_device apq_cpudai_slimbus_2_tx = {
938 .name = "msm-dai-q6",
939 .id = 0x4005,
940};
941
Neema Shettyc9d86c32012-05-09 12:01:39 -0700942struct platform_device apq_cpudai_slimbus_3_rx = {
943 .name = "msm-dai-q6",
944 .id = 0x4006,
945};
946
Helen Zeng38c3c962012-05-17 14:56:20 -0700947struct platform_device apq_cpudai_slimbus_3_tx = {
948 .name = "msm-dai-q6",
949 .id = 0x4007,
950};
951
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700952static struct resource resources_ssbi_pmic1[] = {
953 {
954 .start = MSM_PMIC1_SSBI_CMD_PHYS,
955 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
956 .flags = IORESOURCE_MEM,
957 },
958};
959
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600960#define LPASS_SLIMBUS_PHYS 0x28080000
961#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
Swaminathan Sathappan2316e082012-02-03 14:07:17 -0800962#define LPASS_SLIMBUS_SLEW (MSM8960_TLMM_PHYS + 0x207C)
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600963/* Board info for the slimbus slave device */
964static struct resource slimbus_res[] = {
965 {
966 .start = LPASS_SLIMBUS_PHYS,
967 .end = LPASS_SLIMBUS_PHYS + 8191,
968 .flags = IORESOURCE_MEM,
969 .name = "slimbus_physical",
970 },
971 {
972 .start = LPASS_SLIMBUS_BAM_PHYS,
973 .end = LPASS_SLIMBUS_BAM_PHYS + 8191,
974 .flags = IORESOURCE_MEM,
975 .name = "slimbus_bam_physical",
976 },
977 {
Swaminathan Sathappan2316e082012-02-03 14:07:17 -0800978 .start = LPASS_SLIMBUS_SLEW,
979 .end = LPASS_SLIMBUS_SLEW + 4 - 1,
980 .flags = IORESOURCE_MEM,
981 .name = "slimbus_slew_reg",
982 },
983 {
Sagar Dharia8bdcdaf2011-09-16 16:01:15 -0600984 .start = SLIMBUS0_CORE_EE1_IRQ,
985 .end = SLIMBUS0_CORE_EE1_IRQ,
986 .flags = IORESOURCE_IRQ,
987 .name = "slimbus_irq",
988 },
989 {
990 .start = SLIMBUS0_BAM_EE1_IRQ,
991 .end = SLIMBUS0_BAM_EE1_IRQ,
992 .flags = IORESOURCE_IRQ,
993 .name = "slimbus_bam_irq",
994 },
995};
996
997struct platform_device apq8064_slim_ctrl = {
998 .name = "msm_slim_ctrl",
999 .id = 1,
1000 .num_resources = ARRAY_SIZE(slimbus_res),
1001 .resource = slimbus_res,
1002 .dev = {
1003 .coherent_dma_mask = 0xffffffffULL,
1004 },
1005};
1006
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001007struct platform_device apq8064_device_ssbi_pmic1 = {
1008 .name = "msm_ssbi",
1009 .id = 0,
1010 .resource = resources_ssbi_pmic1,
1011 .num_resources = ARRAY_SIZE(resources_ssbi_pmic1),
1012};
1013
1014static struct resource resources_ssbi_pmic2[] = {
1015 {
1016 .start = MSM_PMIC2_SSBI_CMD_PHYS,
1017 .end = MSM_PMIC2_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
1018 .flags = IORESOURCE_MEM,
1019 },
1020};
1021
1022struct platform_device apq8064_device_ssbi_pmic2 = {
1023 .name = "msm_ssbi",
1024 .id = 1,
1025 .resource = resources_ssbi_pmic2,
1026 .num_resources = ARRAY_SIZE(resources_ssbi_pmic2),
1027};
1028
1029static struct resource resources_otg[] = {
1030 {
Hemant Kumard86c4882012-01-24 19:39:37 -08001031 .start = MSM_HSUSB1_PHYS,
1032 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001033 .flags = IORESOURCE_MEM,
1034 },
1035 {
1036 .start = USB1_HS_IRQ,
1037 .end = USB1_HS_IRQ,
1038 .flags = IORESOURCE_IRQ,
1039 },
1040};
1041
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -07001042struct platform_device apq8064_device_otg = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001043 .name = "msm_otg",
1044 .id = -1,
1045 .num_resources = ARRAY_SIZE(resources_otg),
1046 .resource = resources_otg,
1047 .dev = {
1048 .coherent_dma_mask = 0xffffffff,
1049 },
1050};
1051
1052static struct resource resources_hsusb[] = {
1053 {
Hemant Kumard86c4882012-01-24 19:39:37 -08001054 .start = MSM_HSUSB1_PHYS,
1055 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001056 .flags = IORESOURCE_MEM,
1057 },
1058 {
1059 .start = USB1_HS_IRQ,
1060 .end = USB1_HS_IRQ,
1061 .flags = IORESOURCE_IRQ,
1062 },
1063};
1064
Stepan Moskovchenko14aa6492011-08-08 15:15:01 -07001065struct platform_device apq8064_device_gadget_peripheral = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001066 .name = "msm_hsusb",
1067 .id = -1,
1068 .num_resources = ARRAY_SIZE(resources_hsusb),
1069 .resource = resources_hsusb,
1070 .dev = {
1071 .coherent_dma_mask = 0xffffffff,
1072 },
1073};
1074
Hemant Kumard86c4882012-01-24 19:39:37 -08001075static struct resource resources_hsusb_host[] = {
1076 {
1077 .start = MSM_HSUSB1_PHYS,
1078 .end = MSM_HSUSB1_PHYS + MSM_HSUSB1_SIZE - 1,
1079 .flags = IORESOURCE_MEM,
1080 },
1081 {
1082 .start = USB1_HS_IRQ,
1083 .end = USB1_HS_IRQ,
1084 .flags = IORESOURCE_IRQ,
1085 },
1086};
1087
Hemant Kumara945b472012-01-25 15:08:06 -08001088static struct resource resources_hsic_host[] = {
1089 {
1090 .start = 0x12510000,
1091 .end = 0x12510000 + SZ_4K - 1,
1092 .flags = IORESOURCE_MEM,
1093 },
1094 {
1095 .start = USB2_HSIC_IRQ,
1096 .end = USB2_HSIC_IRQ,
1097 .flags = IORESOURCE_IRQ,
1098 },
1099 {
1100 .start = MSM_GPIO_TO_INT(49),
1101 .end = MSM_GPIO_TO_INT(49),
1102 .name = "peripheral_status_irq",
1103 .flags = IORESOURCE_IRQ,
1104 },
Vamsi Krishna6921cbe2012-02-21 18:34:43 -08001105 {
Hemant Kumar6fd65032012-05-23 13:02:24 -07001106 .start = 47,
1107 .end = 47,
1108 .name = "wakeup",
1109 .flags = IORESOURCE_IO,
Vamsi Krishna6921cbe2012-02-21 18:34:43 -08001110 },
Hemant Kumara945b472012-01-25 15:08:06 -08001111};
1112
Hemant Kumard86c4882012-01-24 19:39:37 -08001113static u64 dma_mask = DMA_BIT_MASK(32);
1114struct platform_device apq8064_device_hsusb_host = {
1115 .name = "msm_hsusb_host",
1116 .id = -1,
1117 .num_resources = ARRAY_SIZE(resources_hsusb_host),
1118 .resource = resources_hsusb_host,
1119 .dev = {
1120 .dma_mask = &dma_mask,
1121 .coherent_dma_mask = 0xffffffff,
1122 },
1123};
1124
Hemant Kumara945b472012-01-25 15:08:06 -08001125struct platform_device apq8064_device_hsic_host = {
1126 .name = "msm_hsic_host",
1127 .id = -1,
1128 .num_resources = ARRAY_SIZE(resources_hsic_host),
1129 .resource = resources_hsic_host,
1130 .dev = {
1131 .dma_mask = &dma_mask,
1132 .coherent_dma_mask = DMA_BIT_MASK(32),
1133 },
1134};
1135
Manu Gautam91223e02011-11-08 15:27:22 +05301136static struct resource resources_ehci_host3[] = {
1137{
1138 .start = MSM_HSUSB3_PHYS,
1139 .end = MSM_HSUSB3_PHYS + MSM_HSUSB3_SIZE - 1,
1140 .flags = IORESOURCE_MEM,
1141 },
1142 {
1143 .start = USB3_HS_IRQ,
1144 .end = USB3_HS_IRQ,
1145 .flags = IORESOURCE_IRQ,
1146 },
1147};
1148
1149struct platform_device apq8064_device_ehci_host3 = {
1150 .name = "msm_ehci_host",
1151 .id = 0,
1152 .num_resources = ARRAY_SIZE(resources_ehci_host3),
1153 .resource = resources_ehci_host3,
1154 .dev = {
1155 .dma_mask = &dma_mask,
1156 .coherent_dma_mask = 0xffffffff,
1157 },
1158};
1159
Hemant Kumar1d66e1c2012-02-13 15:24:59 -08001160static struct resource resources_ehci_host4[] = {
1161{
1162 .start = MSM_HSUSB4_PHYS,
1163 .end = MSM_HSUSB4_PHYS + MSM_HSUSB4_SIZE - 1,
1164 .flags = IORESOURCE_MEM,
1165 },
1166 {
1167 .start = USB4_HS_IRQ,
1168 .end = USB4_HS_IRQ,
1169 .flags = IORESOURCE_IRQ,
1170 },
1171};
1172
1173struct platform_device apq8064_device_ehci_host4 = {
1174 .name = "msm_ehci_host",
1175 .id = 1,
1176 .num_resources = ARRAY_SIZE(resources_ehci_host4),
1177 .resource = resources_ehci_host4,
1178 .dev = {
1179 .dma_mask = &dma_mask,
1180 .coherent_dma_mask = 0xffffffff,
1181 },
1182};
1183
Matt Wagantallf5cc3892012-06-07 19:47:02 -07001184struct platform_device apq8064_device_acpuclk = {
1185 .name = "acpuclk-8064",
1186 .id = -1,
1187};
1188
Ramesh Masavarapuf31ff242012-05-10 18:55:21 -07001189#define SHARED_IMEM_TZ_BASE 0x2a03f720
1190static struct resource tzlog_resources[] = {
1191 {
1192 .start = SHARED_IMEM_TZ_BASE,
1193 .end = SHARED_IMEM_TZ_BASE + SZ_4K - 1,
1194 .flags = IORESOURCE_MEM,
1195 },
1196};
1197
1198struct platform_device apq_device_tz_log = {
1199 .name = "tz_log",
1200 .id = 0,
1201 .num_resources = ARRAY_SIZE(tzlog_resources),
1202 .resource = tzlog_resources,
1203};
1204
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001205/* MSM Video core device */
1206#ifdef CONFIG_MSM_BUS_SCALING
1207static struct msm_bus_vectors vidc_init_vectors[] = {
1208 {
1209 .src = MSM_BUS_MASTER_VIDEO_ENC,
1210 .dst = MSM_BUS_SLAVE_EBI_CH0,
1211 .ab = 0,
1212 .ib = 0,
1213 },
1214 {
1215 .src = MSM_BUS_MASTER_VIDEO_DEC,
1216 .dst = MSM_BUS_SLAVE_EBI_CH0,
1217 .ab = 0,
1218 .ib = 0,
1219 },
1220 {
1221 .src = MSM_BUS_MASTER_AMPSS_M0,
1222 .dst = MSM_BUS_SLAVE_EBI_CH0,
1223 .ab = 0,
1224 .ib = 0,
1225 },
1226 {
1227 .src = MSM_BUS_MASTER_AMPSS_M0,
1228 .dst = MSM_BUS_SLAVE_EBI_CH0,
1229 .ab = 0,
1230 .ib = 0,
1231 },
1232};
1233static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
1234 {
1235 .src = MSM_BUS_MASTER_VIDEO_ENC,
1236 .dst = MSM_BUS_SLAVE_EBI_CH0,
1237 .ab = 54525952,
1238 .ib = 436207616,
1239 },
1240 {
1241 .src = MSM_BUS_MASTER_VIDEO_DEC,
1242 .dst = MSM_BUS_SLAVE_EBI_CH0,
1243 .ab = 72351744,
1244 .ib = 289406976,
1245 },
1246 {
1247 .src = MSM_BUS_MASTER_AMPSS_M0,
1248 .dst = MSM_BUS_SLAVE_EBI_CH0,
1249 .ab = 500000,
1250 .ib = 1000000,
1251 },
1252 {
1253 .src = MSM_BUS_MASTER_AMPSS_M0,
1254 .dst = MSM_BUS_SLAVE_EBI_CH0,
1255 .ab = 500000,
1256 .ib = 1000000,
1257 },
1258};
1259static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
1260 {
1261 .src = MSM_BUS_MASTER_VIDEO_ENC,
1262 .dst = MSM_BUS_SLAVE_EBI_CH0,
1263 .ab = 40894464,
1264 .ib = 327155712,
1265 },
1266 {
1267 .src = MSM_BUS_MASTER_VIDEO_DEC,
1268 .dst = MSM_BUS_SLAVE_EBI_CH0,
1269 .ab = 48234496,
1270 .ib = 192937984,
1271 },
1272 {
1273 .src = MSM_BUS_MASTER_AMPSS_M0,
1274 .dst = MSM_BUS_SLAVE_EBI_CH0,
1275 .ab = 500000,
1276 .ib = 2000000,
1277 },
1278 {
1279 .src = MSM_BUS_MASTER_AMPSS_M0,
1280 .dst = MSM_BUS_SLAVE_EBI_CH0,
1281 .ab = 500000,
1282 .ib = 2000000,
1283 },
1284};
1285static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
1286 {
1287 .src = MSM_BUS_MASTER_VIDEO_ENC,
1288 .dst = MSM_BUS_SLAVE_EBI_CH0,
1289 .ab = 163577856,
1290 .ib = 1308622848,
1291 },
1292 {
1293 .src = MSM_BUS_MASTER_VIDEO_DEC,
1294 .dst = MSM_BUS_SLAVE_EBI_CH0,
1295 .ab = 219152384,
1296 .ib = 876609536,
1297 },
1298 {
1299 .src = MSM_BUS_MASTER_AMPSS_M0,
1300 .dst = MSM_BUS_SLAVE_EBI_CH0,
1301 .ab = 1750000,
1302 .ib = 3500000,
1303 },
1304 {
1305 .src = MSM_BUS_MASTER_AMPSS_M0,
1306 .dst = MSM_BUS_SLAVE_EBI_CH0,
1307 .ab = 1750000,
1308 .ib = 3500000,
1309 },
1310};
1311static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
1312 {
1313 .src = MSM_BUS_MASTER_VIDEO_ENC,
1314 .dst = MSM_BUS_SLAVE_EBI_CH0,
1315 .ab = 121634816,
1316 .ib = 973078528,
1317 },
1318 {
1319 .src = MSM_BUS_MASTER_VIDEO_DEC,
1320 .dst = MSM_BUS_SLAVE_EBI_CH0,
1321 .ab = 155189248,
1322 .ib = 620756992,
1323 },
1324 {
1325 .src = MSM_BUS_MASTER_AMPSS_M0,
1326 .dst = MSM_BUS_SLAVE_EBI_CH0,
1327 .ab = 1750000,
1328 .ib = 7000000,
1329 },
1330 {
1331 .src = MSM_BUS_MASTER_AMPSS_M0,
1332 .dst = MSM_BUS_SLAVE_EBI_CH0,
1333 .ab = 1750000,
1334 .ib = 7000000,
1335 },
1336};
1337static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
1338 {
1339 .src = MSM_BUS_MASTER_VIDEO_ENC,
1340 .dst = MSM_BUS_SLAVE_EBI_CH0,
1341 .ab = 372244480,
1342 .ib = 2560000000U,
1343 },
1344 {
1345 .src = MSM_BUS_MASTER_VIDEO_DEC,
1346 .dst = MSM_BUS_SLAVE_EBI_CH0,
1347 .ab = 501219328,
1348 .ib = 2560000000U,
1349 },
1350 {
1351 .src = MSM_BUS_MASTER_AMPSS_M0,
1352 .dst = MSM_BUS_SLAVE_EBI_CH0,
1353 .ab = 2500000,
1354 .ib = 5000000,
1355 },
1356 {
1357 .src = MSM_BUS_MASTER_AMPSS_M0,
1358 .dst = MSM_BUS_SLAVE_EBI_CH0,
1359 .ab = 2500000,
1360 .ib = 5000000,
1361 },
1362};
1363static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
1364 {
1365 .src = MSM_BUS_MASTER_VIDEO_ENC,
1366 .dst = MSM_BUS_SLAVE_EBI_CH0,
1367 .ab = 222298112,
1368 .ib = 2560000000U,
1369 },
1370 {
1371 .src = MSM_BUS_MASTER_VIDEO_DEC,
1372 .dst = MSM_BUS_SLAVE_EBI_CH0,
1373 .ab = 330301440,
1374 .ib = 2560000000U,
1375 },
1376 {
1377 .src = MSM_BUS_MASTER_AMPSS_M0,
1378 .dst = MSM_BUS_SLAVE_EBI_CH0,
1379 .ab = 2500000,
1380 .ib = 700000000,
1381 },
1382 {
1383 .src = MSM_BUS_MASTER_AMPSS_M0,
1384 .dst = MSM_BUS_SLAVE_EBI_CH0,
1385 .ab = 2500000,
1386 .ib = 10000000,
1387 },
1388};
1389
Arun Menon152c3c72012-06-20 11:50:08 -07001390static struct msm_bus_vectors vidc_venc_1080p_turbo_vectors[] = {
1391 {
1392 .src = MSM_BUS_MASTER_VIDEO_ENC,
1393 .dst = MSM_BUS_SLAVE_EBI_CH0,
1394 .ab = 222298112,
1395 .ib = 3522000000U,
1396 },
1397 {
1398 .src = MSM_BUS_MASTER_VIDEO_DEC,
1399 .dst = MSM_BUS_SLAVE_EBI_CH0,
1400 .ab = 330301440,
1401 .ib = 3522000000U,
1402 },
1403 {
1404 .src = MSM_BUS_MASTER_AMPSS_M0,
1405 .dst = MSM_BUS_SLAVE_EBI_CH0,
1406 .ab = 2500000,
1407 .ib = 700000000,
1408 },
1409 {
1410 .src = MSM_BUS_MASTER_AMPSS_M0,
1411 .dst = MSM_BUS_SLAVE_EBI_CH0,
1412 .ab = 2500000,
1413 .ib = 10000000,
1414 },
1415};
1416static struct msm_bus_vectors vidc_vdec_1080p_turbo_vectors[] = {
1417 {
1418 .src = MSM_BUS_MASTER_VIDEO_ENC,
1419 .dst = MSM_BUS_SLAVE_EBI_CH0,
1420 .ab = 222298112,
1421 .ib = 3522000000U,
1422 },
1423 {
1424 .src = MSM_BUS_MASTER_VIDEO_DEC,
1425 .dst = MSM_BUS_SLAVE_EBI_CH0,
1426 .ab = 330301440,
1427 .ib = 3522000000U,
1428 },
1429 {
1430 .src = MSM_BUS_MASTER_AMPSS_M0,
1431 .dst = MSM_BUS_SLAVE_EBI_CH0,
1432 .ab = 2500000,
1433 .ib = 700000000,
1434 },
1435 {
1436 .src = MSM_BUS_MASTER_AMPSS_M0,
1437 .dst = MSM_BUS_SLAVE_EBI_CH0,
1438 .ab = 2500000,
1439 .ib = 10000000,
1440 },
1441};
1442
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001443static struct msm_bus_paths vidc_bus_client_config[] = {
1444 {
1445 ARRAY_SIZE(vidc_init_vectors),
1446 vidc_init_vectors,
1447 },
1448 {
1449 ARRAY_SIZE(vidc_venc_vga_vectors),
1450 vidc_venc_vga_vectors,
1451 },
1452 {
1453 ARRAY_SIZE(vidc_vdec_vga_vectors),
1454 vidc_vdec_vga_vectors,
1455 },
1456 {
1457 ARRAY_SIZE(vidc_venc_720p_vectors),
1458 vidc_venc_720p_vectors,
1459 },
1460 {
1461 ARRAY_SIZE(vidc_vdec_720p_vectors),
1462 vidc_vdec_720p_vectors,
1463 },
1464 {
1465 ARRAY_SIZE(vidc_venc_1080p_vectors),
1466 vidc_venc_1080p_vectors,
1467 },
1468 {
1469 ARRAY_SIZE(vidc_vdec_1080p_vectors),
1470 vidc_vdec_1080p_vectors,
1471 },
Arun Menon152c3c72012-06-20 11:50:08 -07001472 {
1473 ARRAY_SIZE(vidc_venc_1080p_turbo_vectors),
1474 vidc_venc_1080p_turbo_vectors,
1475 },
1476 {
1477 ARRAY_SIZE(vidc_vdec_1080p_turbo_vectors),
1478 vidc_vdec_1080p_turbo_vectors,
1479 },
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001480};
1481
1482static struct msm_bus_scale_pdata vidc_bus_client_data = {
1483 vidc_bus_client_config,
1484 ARRAY_SIZE(vidc_bus_client_config),
1485 .name = "vidc",
1486};
1487#endif
1488
1489
1490#define APQ8064_VIDC_BASE_PHYS 0x04400000
1491#define APQ8064_VIDC_BASE_SIZE 0x00100000
1492
1493static struct resource apq8064_device_vidc_resources[] = {
1494 {
1495 .start = APQ8064_VIDC_BASE_PHYS,
1496 .end = APQ8064_VIDC_BASE_PHYS + APQ8064_VIDC_BASE_SIZE - 1,
1497 .flags = IORESOURCE_MEM,
1498 },
1499 {
1500 .start = VCODEC_IRQ,
1501 .end = VCODEC_IRQ,
1502 .flags = IORESOURCE_IRQ,
1503 },
1504};
1505
1506struct msm_vidc_platform_data apq8064_vidc_platform_data = {
1507#ifdef CONFIG_MSM_BUS_SCALING
1508 .vidc_bus_client_pdata = &vidc_bus_client_data,
1509#endif
1510#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
1511 .memtype = ION_CP_MM_HEAP_ID,
1512 .enable_ion = 1,
Deepak kotureda295a2012-05-10 19:49:46 -07001513 .cp_enabled = 1,
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001514#else
1515 .memtype = MEMTYPE_EBI1,
1516 .enable_ion = 0,
1517#endif
1518 .disable_dmx = 0,
1519 .disable_fullhd = 0,
Mohan Kumar Gubbihalli Lachma Naiked9dc912012-03-01 19:11:14 -08001520 .cont_mode_dpb_count = 18,
Riaz Rahaman84f8c682012-05-30 13:32:10 +05301521 .fw_addr = 0x9fe00000,
Mohan Kumar Gubbihalli Lachma Naik7f72edd2012-02-06 17:26:47 -08001522};
1523
1524struct platform_device apq8064_msm_device_vidc = {
1525 .name = "msm_vidc",
1526 .id = 0,
1527 .num_resources = ARRAY_SIZE(apq8064_device_vidc_resources),
1528 .resource = apq8064_device_vidc_resources,
1529 .dev = {
1530 .platform_data = &apq8064_vidc_platform_data,
1531 },
1532};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001533#define MSM_SDC1_BASE 0x12400000
1534#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
1535#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
1536#define MSM_SDC2_BASE 0x12140000
1537#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
1538#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
1539#define MSM_SDC3_BASE 0x12180000
1540#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
1541#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
1542#define MSM_SDC4_BASE 0x121C0000
1543#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
1544#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
1545
1546static struct resource resources_sdc1[] = {
1547 {
1548 .name = "core_mem",
1549 .flags = IORESOURCE_MEM,
1550 .start = MSM_SDC1_BASE,
1551 .end = MSM_SDC1_DML_BASE - 1,
1552 },
1553 {
1554 .name = "core_irq",
1555 .flags = IORESOURCE_IRQ,
1556 .start = SDC1_IRQ_0,
1557 .end = SDC1_IRQ_0
1558 },
1559#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1560 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301561 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001562 .start = MSM_SDC1_DML_BASE,
1563 .end = MSM_SDC1_BAM_BASE - 1,
1564 .flags = IORESOURCE_MEM,
1565 },
1566 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301567 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001568 .start = MSM_SDC1_BAM_BASE,
1569 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
1570 .flags = IORESOURCE_MEM,
1571 },
1572 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301573 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001574 .start = SDC1_BAM_IRQ,
1575 .end = SDC1_BAM_IRQ,
1576 .flags = IORESOURCE_IRQ,
1577 },
1578#endif
1579};
1580
1581static struct resource resources_sdc2[] = {
1582 {
1583 .name = "core_mem",
1584 .flags = IORESOURCE_MEM,
1585 .start = MSM_SDC2_BASE,
1586 .end = MSM_SDC2_DML_BASE - 1,
1587 },
1588 {
1589 .name = "core_irq",
1590 .flags = IORESOURCE_IRQ,
1591 .start = SDC2_IRQ_0,
1592 .end = SDC2_IRQ_0
1593 },
1594#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1595 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301596 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001597 .start = MSM_SDC2_DML_BASE,
1598 .end = MSM_SDC2_BAM_BASE - 1,
1599 .flags = IORESOURCE_MEM,
1600 },
1601 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301602 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001603 .start = MSM_SDC2_BAM_BASE,
1604 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
1605 .flags = IORESOURCE_MEM,
1606 },
1607 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301608 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001609 .start = SDC2_BAM_IRQ,
1610 .end = SDC2_BAM_IRQ,
1611 .flags = IORESOURCE_IRQ,
1612 },
1613#endif
1614};
1615
1616static struct resource resources_sdc3[] = {
1617 {
1618 .name = "core_mem",
1619 .flags = IORESOURCE_MEM,
1620 .start = MSM_SDC3_BASE,
1621 .end = MSM_SDC3_DML_BASE - 1,
1622 },
1623 {
1624 .name = "core_irq",
1625 .flags = IORESOURCE_IRQ,
1626 .start = SDC3_IRQ_0,
1627 .end = SDC3_IRQ_0
1628 },
1629#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1630 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301631 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001632 .start = MSM_SDC3_DML_BASE,
1633 .end = MSM_SDC3_BAM_BASE - 1,
1634 .flags = IORESOURCE_MEM,
1635 },
1636 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301637 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001638 .start = MSM_SDC3_BAM_BASE,
1639 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
1640 .flags = IORESOURCE_MEM,
1641 },
1642 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301643 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001644 .start = SDC3_BAM_IRQ,
1645 .end = SDC3_BAM_IRQ,
1646 .flags = IORESOURCE_IRQ,
1647 },
1648#endif
1649};
1650
1651static struct resource resources_sdc4[] = {
1652 {
1653 .name = "core_mem",
1654 .flags = IORESOURCE_MEM,
1655 .start = MSM_SDC4_BASE,
1656 .end = MSM_SDC4_DML_BASE - 1,
1657 },
1658 {
1659 .name = "core_irq",
1660 .flags = IORESOURCE_IRQ,
1661 .start = SDC4_IRQ_0,
1662 .end = SDC4_IRQ_0
1663 },
1664#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
1665 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301666 .name = "dml_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001667 .start = MSM_SDC4_DML_BASE,
1668 .end = MSM_SDC4_BAM_BASE - 1,
1669 .flags = IORESOURCE_MEM,
1670 },
1671 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301672 .name = "bam_mem",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001673 .start = MSM_SDC4_BAM_BASE,
1674 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
1675 .flags = IORESOURCE_MEM,
1676 },
1677 {
Sujit Reddy Thumma1dfac2c2012-07-30 10:15:39 +05301678 .name = "bam_irq",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001679 .start = SDC4_BAM_IRQ,
1680 .end = SDC4_BAM_IRQ,
1681 .flags = IORESOURCE_IRQ,
1682 },
1683#endif
1684};
1685
1686struct platform_device apq8064_device_sdc1 = {
1687 .name = "msm_sdcc",
1688 .id = 1,
1689 .num_resources = ARRAY_SIZE(resources_sdc1),
1690 .resource = resources_sdc1,
1691 .dev = {
1692 .coherent_dma_mask = 0xffffffff,
1693 },
1694};
1695
1696struct platform_device apq8064_device_sdc2 = {
1697 .name = "msm_sdcc",
1698 .id = 2,
1699 .num_resources = ARRAY_SIZE(resources_sdc2),
1700 .resource = resources_sdc2,
1701 .dev = {
1702 .coherent_dma_mask = 0xffffffff,
1703 },
1704};
1705
1706struct platform_device apq8064_device_sdc3 = {
1707 .name = "msm_sdcc",
1708 .id = 3,
1709 .num_resources = ARRAY_SIZE(resources_sdc3),
1710 .resource = resources_sdc3,
1711 .dev = {
1712 .coherent_dma_mask = 0xffffffff,
1713 },
1714};
1715
1716struct platform_device apq8064_device_sdc4 = {
1717 .name = "msm_sdcc",
1718 .id = 4,
1719 .num_resources = ARRAY_SIZE(resources_sdc4),
1720 .resource = resources_sdc4,
1721 .dev = {
1722 .coherent_dma_mask = 0xffffffff,
1723 },
1724};
1725
1726static struct platform_device *apq8064_sdcc_devices[] __initdata = {
1727 &apq8064_device_sdc1,
1728 &apq8064_device_sdc2,
1729 &apq8064_device_sdc3,
1730 &apq8064_device_sdc4,
1731};
1732
1733int __init apq8064_add_sdcc(unsigned int controller,
1734 struct mmc_platform_data *plat)
1735{
1736 struct platform_device *pdev;
1737
1738 if (!plat)
1739 return 0;
1740 if (controller < 1 || controller > 4)
1741 return -EINVAL;
1742
1743 pdev = apq8064_sdcc_devices[controller-1];
1744 pdev->dev.platform_data = plat;
1745 return platform_device_register(pdev);
1746}
1747
Yan He06913ce2011-08-26 16:33:46 -07001748static struct resource resources_sps[] = {
1749 {
1750 .name = "pipe_mem",
1751 .start = 0x12800000,
1752 .end = 0x12800000 + 0x4000 - 1,
1753 .flags = IORESOURCE_MEM,
1754 },
1755 {
1756 .name = "bamdma_dma",
1757 .start = 0x12240000,
1758 .end = 0x12240000 + 0x1000 - 1,
1759 .flags = IORESOURCE_MEM,
1760 },
1761 {
1762 .name = "bamdma_bam",
1763 .start = 0x12244000,
1764 .end = 0x12244000 + 0x4000 - 1,
1765 .flags = IORESOURCE_MEM,
1766 },
1767 {
1768 .name = "bamdma_irq",
1769 .start = SPS_BAM_DMA_IRQ,
1770 .end = SPS_BAM_DMA_IRQ,
1771 .flags = IORESOURCE_IRQ,
1772 },
1773};
1774
Gagan Mac8a7a5d32011-11-11 16:43:06 -07001775struct platform_device msm_bus_8064_sys_fabric = {
1776 .name = "msm_bus_fabric",
1777 .id = MSM_BUS_FAB_SYSTEM,
1778};
1779struct platform_device msm_bus_8064_apps_fabric = {
1780 .name = "msm_bus_fabric",
1781 .id = MSM_BUS_FAB_APPSS,
1782};
1783struct platform_device msm_bus_8064_mm_fabric = {
1784 .name = "msm_bus_fabric",
1785 .id = MSM_BUS_FAB_MMSS,
1786};
1787struct platform_device msm_bus_8064_sys_fpb = {
1788 .name = "msm_bus_fabric",
1789 .id = MSM_BUS_FAB_SYSTEM_FPB,
1790};
1791struct platform_device msm_bus_8064_cpss_fpb = {
1792 .name = "msm_bus_fabric",
1793 .id = MSM_BUS_FAB_CPSS_FPB,
1794};
1795
Yan He06913ce2011-08-26 16:33:46 -07001796static struct msm_sps_platform_data msm_sps_pdata = {
1797 .bamdma_restricted_pipes = 0x06,
1798};
1799
1800struct platform_device msm_device_sps_apq8064 = {
1801 .name = "msm_sps",
1802 .id = -1,
1803 .num_resources = ARRAY_SIZE(resources_sps),
1804 .resource = resources_sps,
1805 .dev.platform_data = &msm_sps_pdata,
1806};
1807
Eric Holmberg023d25c2012-03-01 12:27:55 -07001808static struct resource smd_resource[] = {
1809 {
1810 .name = "a9_m2a_0",
1811 .start = INT_A9_M2A_0,
1812 .flags = IORESOURCE_IRQ,
1813 },
1814 {
1815 .name = "a9_m2a_5",
1816 .start = INT_A9_M2A_5,
1817 .flags = IORESOURCE_IRQ,
1818 },
1819 {
1820 .name = "adsp_a11",
1821 .start = INT_ADSP_A11,
1822 .flags = IORESOURCE_IRQ,
1823 },
1824 {
1825 .name = "adsp_a11_smsm",
1826 .start = INT_ADSP_A11_SMSM,
1827 .flags = IORESOURCE_IRQ,
1828 },
1829 {
1830 .name = "dsps_a11",
1831 .start = INT_DSPS_A11,
1832 .flags = IORESOURCE_IRQ,
1833 },
1834 {
1835 .name = "dsps_a11_smsm",
1836 .start = INT_DSPS_A11_SMSM,
1837 .flags = IORESOURCE_IRQ,
1838 },
1839 {
1840 .name = "wcnss_a11",
1841 .start = INT_WCNSS_A11,
1842 .flags = IORESOURCE_IRQ,
1843 },
1844 {
1845 .name = "wcnss_a11_smsm",
1846 .start = INT_WCNSS_A11_SMSM,
1847 .flags = IORESOURCE_IRQ,
1848 },
1849};
1850
1851static struct smd_subsystem_config smd_config_list[] = {
1852 {
1853 .irq_config_id = SMD_MODEM,
1854 .subsys_name = "gss",
1855 .edge = SMD_APPS_MODEM,
1856
1857 .smd_int.irq_name = "a9_m2a_0",
1858 .smd_int.flags = IRQF_TRIGGER_RISING,
1859 .smd_int.irq_id = -1,
1860 .smd_int.device_name = "smd_dev",
1861 .smd_int.dev_id = 0,
1862 .smd_int.out_bit_pos = 1 << 3,
1863 .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1864 .smd_int.out_offset = 0x8,
1865
1866 .smsm_int.irq_name = "a9_m2a_5",
1867 .smsm_int.flags = IRQF_TRIGGER_RISING,
1868 .smsm_int.irq_id = -1,
1869 .smsm_int.device_name = "smd_smsm",
1870 .smsm_int.dev_id = 0,
1871 .smsm_int.out_bit_pos = 1 << 4,
1872 .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1873 .smsm_int.out_offset = 0x8,
1874 },
1875 {
1876 .irq_config_id = SMD_Q6,
Stephen Boyd77db8bb2012-06-27 15:15:16 -07001877 .subsys_name = "adsp",
Eric Holmberg023d25c2012-03-01 12:27:55 -07001878 .edge = SMD_APPS_QDSP,
1879
1880 .smd_int.irq_name = "adsp_a11",
1881 .smd_int.flags = IRQF_TRIGGER_RISING,
1882 .smd_int.irq_id = -1,
1883 .smd_int.device_name = "smd_dev",
1884 .smd_int.dev_id = 0,
1885 .smd_int.out_bit_pos = 1 << 15,
1886 .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1887 .smd_int.out_offset = 0x8,
1888
1889 .smsm_int.irq_name = "adsp_a11_smsm",
1890 .smsm_int.flags = IRQF_TRIGGER_RISING,
1891 .smsm_int.irq_id = -1,
1892 .smsm_int.device_name = "smd_smsm",
1893 .smsm_int.dev_id = 0,
1894 .smsm_int.out_bit_pos = 1 << 14,
1895 .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1896 .smsm_int.out_offset = 0x8,
1897 },
1898 {
1899 .irq_config_id = SMD_DSPS,
1900 .subsys_name = "dsps",
1901 .edge = SMD_APPS_DSPS,
1902
1903 .smd_int.irq_name = "dsps_a11",
1904 .smd_int.flags = IRQF_TRIGGER_RISING,
1905 .smd_int.irq_id = -1,
1906 .smd_int.device_name = "smd_dev",
1907 .smd_int.dev_id = 0,
1908 .smd_int.out_bit_pos = 1,
1909 .smd_int.out_base = (void __iomem *)MSM_SIC_NON_SECURE_BASE,
1910 .smd_int.out_offset = 0x4080,
1911
1912 .smsm_int.irq_name = "dsps_a11_smsm",
1913 .smsm_int.flags = IRQF_TRIGGER_RISING,
1914 .smsm_int.irq_id = -1,
1915 .smsm_int.device_name = "smd_smsm",
1916 .smsm_int.dev_id = 0,
1917 .smsm_int.out_bit_pos = 1,
1918 .smsm_int.out_base = (void __iomem *)MSM_SIC_NON_SECURE_BASE,
1919 .smsm_int.out_offset = 0x4094,
1920 },
1921 {
1922 .irq_config_id = SMD_WCNSS,
1923 .subsys_name = "wcnss",
1924 .edge = SMD_APPS_WCNSS,
1925
1926 .smd_int.irq_name = "wcnss_a11",
1927 .smd_int.flags = IRQF_TRIGGER_RISING,
1928 .smd_int.irq_id = -1,
1929 .smd_int.device_name = "smd_dev",
1930 .smd_int.dev_id = 0,
1931 .smd_int.out_bit_pos = 1 << 25,
1932 .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1933 .smd_int.out_offset = 0x8,
1934
1935 .smsm_int.irq_name = "wcnss_a11_smsm",
1936 .smsm_int.flags = IRQF_TRIGGER_RISING,
1937 .smsm_int.irq_id = -1,
1938 .smsm_int.device_name = "smd_smsm",
1939 .smsm_int.dev_id = 0,
1940 .smsm_int.out_bit_pos = 1 << 23,
1941 .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
1942 .smsm_int.out_offset = 0x8,
1943 },
1944};
1945
Eric Holmberg2bb6ccd2012-03-13 13:05:14 -06001946static struct smd_subsystem_restart_config smd_ssr_config = {
1947 .disable_smsm_reset_handshake = 1,
1948};
1949
Eric Holmberg023d25c2012-03-01 12:27:55 -07001950static struct smd_platform smd_platform_data = {
1951 .num_ss_configs = ARRAY_SIZE(smd_config_list),
1952 .smd_ss_configs = smd_config_list,
Eric Holmberg2bb6ccd2012-03-13 13:05:14 -06001953 .smd_ssr_config = &smd_ssr_config,
Eric Holmberg023d25c2012-03-01 12:27:55 -07001954};
1955
Jeff Hugo0c0f5e92011-09-28 13:55:45 -06001956struct platform_device msm_device_smd_apq8064 = {
1957 .name = "msm_smd",
1958 .id = -1,
Eric Holmberg023d25c2012-03-01 12:27:55 -07001959 .resource = smd_resource,
1960 .num_resources = ARRAY_SIZE(smd_resource),
1961 .dev = {
1962 .platform_data = &smd_platform_data,
1963 },
Jeff Hugo0c0f5e92011-09-28 13:55:45 -06001964};
1965
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001966static struct resource resources_msm_pcie[] = {
1967 {
Niranjana Vishwanathapura68210ff2012-06-24 18:03:49 -06001968 .name = "pcie_parf",
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001969 .start = PCIE20_PARF_PHYS,
1970 .end = PCIE20_PARF_PHYS + PCIE20_PARF_SIZE - 1,
1971 .flags = IORESOURCE_MEM,
1972 },
1973 {
Niranjana Vishwanathapura68210ff2012-06-24 18:03:49 -06001974 .name = "pcie_elbi",
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001975 .start = PCIE20_ELBI_PHYS,
1976 .end = PCIE20_ELBI_PHYS + PCIE20_ELBI_SIZE - 1,
1977 .flags = IORESOURCE_MEM,
1978 },
1979 {
1980 .name = "pcie20",
1981 .start = PCIE20_PHYS,
1982 .end = PCIE20_PHYS + PCIE20_SIZE - 1,
1983 .flags = IORESOURCE_MEM,
1984 },
Niranjana Vishwanathapura06f89332012-05-03 17:11:13 -06001985};
1986
1987struct platform_device msm_device_pcie = {
1988 .name = "msm_pcie",
1989 .id = -1,
1990 .num_resources = ARRAY_SIZE(resources_msm_pcie),
1991 .resource = resources_msm_pcie,
1992};
1993
Ramesh Masavarapuf46be1b2011-11-03 11:13:41 -07001994#ifdef CONFIG_HW_RANDOM_MSM
1995/* PRNG device */
1996#define MSM_PRNG_PHYS 0x1A500000
1997static struct resource rng_resources = {
1998 .flags = IORESOURCE_MEM,
1999 .start = MSM_PRNG_PHYS,
2000 .end = MSM_PRNG_PHYS + SZ_512 - 1,
2001};
2002
2003struct platform_device apq8064_device_rng = {
2004 .name = "msm_rng",
2005 .id = 0,
2006 .num_resources = 1,
2007 .resource = &rng_resources,
2008};
2009#endif
2010
Matt Wagantall292aace2012-01-26 19:12:34 -08002011static struct resource msm_gss_resources[] = {
2012 {
2013 .start = 0x10000000,
2014 .end = 0x10000000 + SZ_256 - 1,
2015 .flags = IORESOURCE_MEM,
2016 },
Matt Wagantall19ac4fd2012-02-03 20:18:23 -08002017 {
2018 .start = 0x10008000,
2019 .end = 0x10008000 + SZ_256 - 1,
2020 .flags = IORESOURCE_MEM,
2021 },
Stephen Boydd86214b2012-05-10 15:26:35 -07002022 {
2023 .start = GSS_A5_WDOG_EXPIRED,
2024 .end = GSS_A5_WDOG_EXPIRED,
2025 .flags = IORESOURCE_IRQ,
2026 },
Matt Wagantall292aace2012-01-26 19:12:34 -08002027};
2028
2029struct platform_device msm_gss = {
2030 .name = "pil_gss",
2031 .id = -1,
2032 .num_resources = ARRAY_SIZE(msm_gss_resources),
2033 .resource = msm_gss_resources,
2034};
2035
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07002036static struct fs_driver_data gfx3d_fs_data = {
2037 .clks = (struct fs_clk_data[]){
2038 { .name = "core_clk", .reset_rate = 27000000 },
2039 { .name = "iface_clk" },
2040 { .name = "bus_clk" },
2041 { 0 }
2042 },
2043 .bus_port0 = MSM_BUS_MASTER_GRAPHICS_3D,
2044 .bus_port1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1,
Matt Wagantall1875d322012-02-22 16:11:33 -08002045};
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07002046
2047static struct fs_driver_data ijpeg_fs_data = {
2048 .clks = (struct fs_clk_data[]){
2049 { .name = "core_clk" },
2050 { .name = "iface_clk" },
2051 { .name = "bus_clk" },
2052 { 0 }
2053 },
2054 .bus_port0 = MSM_BUS_MASTER_JPEG_ENC,
2055};
2056
Nagamalleswararao Ganji6db8c512012-05-24 20:26:23 -07002057static struct fs_driver_data mdp_fs_data = {
2058 .clks = (struct fs_clk_data[]){
2059 { .name = "core_clk" },
2060 { .name = "iface_clk" },
2061 { .name = "bus_clk" },
2062 { .name = "vsync_clk" },
2063 { .name = "lut_clk" },
2064 { .name = "tv_src_clk" },
2065 { .name = "tv_clk" },
Matt Wagantallc33c1ed2012-07-23 17:19:08 -07002066 { .name = "reset1_clk" },
2067 { .name = "reset2_clk" },
Nagamalleswararao Ganji6db8c512012-05-24 20:26:23 -07002068 { 0 }
2069 },
2070 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
2071 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
2072};
2073
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07002074static struct fs_driver_data rot_fs_data = {
2075 .clks = (struct fs_clk_data[]){
2076 { .name = "core_clk" },
2077 { .name = "iface_clk" },
2078 { .name = "bus_clk" },
2079 { 0 }
2080 },
2081 .bus_port0 = MSM_BUS_MASTER_ROTATOR,
2082};
2083
2084static struct fs_driver_data ved_fs_data = {
2085 .clks = (struct fs_clk_data[]){
2086 { .name = "core_clk" },
2087 { .name = "iface_clk" },
2088 { .name = "bus_clk" },
2089 { 0 }
2090 },
2091 .bus_port0 = MSM_BUS_MASTER_VIDEO_ENC,
2092 .bus_port1 = MSM_BUS_MASTER_VIDEO_DEC,
2093};
2094
2095static struct fs_driver_data vfe_fs_data = {
2096 .clks = (struct fs_clk_data[]){
2097 { .name = "core_clk" },
2098 { .name = "iface_clk" },
2099 { .name = "bus_clk" },
2100 { 0 }
2101 },
2102 .bus_port0 = MSM_BUS_MASTER_VFE,
2103};
2104
2105static struct fs_driver_data vpe_fs_data = {
2106 .clks = (struct fs_clk_data[]){
2107 { .name = "core_clk" },
2108 { .name = "iface_clk" },
2109 { .name = "bus_clk" },
2110 { 0 }
2111 },
2112 .bus_port0 = MSM_BUS_MASTER_VPE,
2113};
2114
2115static struct fs_driver_data vcap_fs_data = {
2116 .clks = (struct fs_clk_data[]){
2117 { .name = "core_clk" },
2118 { .name = "iface_clk" },
2119 { .name = "bus_clk" },
2120 { 0 },
2121 },
2122 .bus_port0 = MSM_BUS_MASTER_VIDEO_CAP,
2123};
2124
2125struct platform_device *apq8064_footswitch[] __initdata = {
Nagamalleswararao Ganji6db8c512012-05-24 20:26:23 -07002126 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data),
Matt Wagantall316f2fc2012-05-03 20:41:42 -07002127 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
Matt Wagantalle4454b82012-05-03 20:48:01 -07002128 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
Kiran Kumar H Nfa18a032012-06-25 14:34:18 -07002129 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
2130 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
Matt Wagantalld6fbf232012-05-03 20:09:28 -07002131 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
Matt Wagantall5e46aac2012-05-03 20:20:18 -07002132 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
Matt Wagantall3cd5b3d2012-05-03 20:35:20 -07002133 FS_8X60(FS_VCAP, "vdd", "msm_vcap.0", &vcap_fs_data),
Matt Wagantall1f65d9d2012-04-25 14:24:20 -07002134};
2135unsigned apq8064_num_footswitch __initdata = ARRAY_SIZE(apq8064_footswitch);
Matt Wagantall1875d322012-02-22 16:11:33 -08002136
Praveen Chidambaram78499012011-11-01 17:15:17 -06002137struct msm_rpm_platform_data apq8064_rpm_data __initdata = {
2138 .reg_base_addrs = {
2139 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
2140 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
2141 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
2142 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
2143 },
2144 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
Stephen Boydf61255e2012-02-24 14:31:09 -08002145 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
Praveen Chidambarame396ce62012-03-30 11:15:57 -06002146 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
Praveen Chidambaram78499012011-11-01 17:15:17 -06002147 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
2148 .ipc_rpm_val = 4,
2149 .target_id = {
2150 MSM_RPM_MAP(8064, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
2151 MSM_RPM_MAP(8064, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
2152 MSM_RPM_MAP(8064, INVALIDATE_0, INVALIDATE, 8),
2153 MSM_RPM_MAP(8064, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
2154 MSM_RPM_MAP(8064, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
2155 MSM_RPM_MAP(8064, RPM_CTL, RPM_CTL, 1),
2156 MSM_RPM_MAP(8064, CXO_CLK, CXO_CLK, 1),
2157 MSM_RPM_MAP(8064, PXO_CLK, PXO_CLK, 1),
2158 MSM_RPM_MAP(8064, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
2159 MSM_RPM_MAP(8064, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
2160 MSM_RPM_MAP(8064, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
2161 MSM_RPM_MAP(8064, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
2162 MSM_RPM_MAP(8064, SFPB_CLK, SFPB_CLK, 1),
2163 MSM_RPM_MAP(8064, CFPB_CLK, CFPB_CLK, 1),
2164 MSM_RPM_MAP(8064, MMFPB_CLK, MMFPB_CLK, 1),
2165 MSM_RPM_MAP(8064, EBI1_CLK, EBI1_CLK, 1),
2166 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_HALT_0,
2167 APPS_FABRIC_CFG_HALT, 2),
2168 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_CLKMOD_0,
2169 APPS_FABRIC_CFG_CLKMOD, 3),
2170 MSM_RPM_MAP(8064, APPS_FABRIC_CFG_IOCTL,
2171 APPS_FABRIC_CFG_IOCTL, 1),
2172 MSM_RPM_MAP(8064, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
2173 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_HALT_0,
2174 SYS_FABRIC_CFG_HALT, 2),
2175 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_CLKMOD_0,
2176 SYS_FABRIC_CFG_CLKMOD, 3),
2177 MSM_RPM_MAP(8064, SYS_FABRIC_CFG_IOCTL,
2178 SYS_FABRIC_CFG_IOCTL, 1),
2179 MSM_RPM_MAP(8064, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 30),
2180 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_HALT_0,
2181 MMSS_FABRIC_CFG_HALT, 2),
2182 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_CLKMOD_0,
2183 MMSS_FABRIC_CFG_CLKMOD, 3),
2184 MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_IOCTL,
2185 MMSS_FABRIC_CFG_IOCTL, 1),
2186 MSM_RPM_MAP(8064, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 21),
2187 MSM_RPM_MAP(8064, PM8921_S1_0, PM8921_S1, 2),
2188 MSM_RPM_MAP(8064, PM8921_S2_0, PM8921_S2, 2),
2189 MSM_RPM_MAP(8064, PM8921_S3_0, PM8921_S3, 2),
2190 MSM_RPM_MAP(8064, PM8921_S4_0, PM8921_S4, 2),
2191 MSM_RPM_MAP(8064, PM8921_S5_0, PM8921_S5, 2),
2192 MSM_RPM_MAP(8064, PM8921_S6_0, PM8921_S6, 2),
2193 MSM_RPM_MAP(8064, PM8921_S7_0, PM8921_S7, 2),
2194 MSM_RPM_MAP(8064, PM8921_S8_0, PM8921_S8, 2),
2195 MSM_RPM_MAP(8064, PM8921_L1_0, PM8921_L1, 2),
2196 MSM_RPM_MAP(8064, PM8921_L2_0, PM8921_L2, 2),
2197 MSM_RPM_MAP(8064, PM8921_L3_0, PM8921_L3, 2),
2198 MSM_RPM_MAP(8064, PM8921_L4_0, PM8921_L4, 2),
2199 MSM_RPM_MAP(8064, PM8921_L5_0, PM8921_L5, 2),
2200 MSM_RPM_MAP(8064, PM8921_L6_0, PM8921_L6, 2),
2201 MSM_RPM_MAP(8064, PM8921_L7_0, PM8921_L7, 2),
2202 MSM_RPM_MAP(8064, PM8921_L8_0, PM8921_L8, 2),
2203 MSM_RPM_MAP(8064, PM8921_L9_0, PM8921_L9, 2),
2204 MSM_RPM_MAP(8064, PM8921_L10_0, PM8921_L10, 2),
2205 MSM_RPM_MAP(8064, PM8921_L11_0, PM8921_L11, 2),
2206 MSM_RPM_MAP(8064, PM8921_L12_0, PM8921_L12, 2),
2207 MSM_RPM_MAP(8064, PM8921_L13_0, PM8921_L13, 2),
2208 MSM_RPM_MAP(8064, PM8921_L14_0, PM8921_L14, 2),
2209 MSM_RPM_MAP(8064, PM8921_L15_0, PM8921_L15, 2),
2210 MSM_RPM_MAP(8064, PM8921_L16_0, PM8921_L16, 2),
2211 MSM_RPM_MAP(8064, PM8921_L17_0, PM8921_L17, 2),
2212 MSM_RPM_MAP(8064, PM8921_L18_0, PM8921_L18, 2),
2213 MSM_RPM_MAP(8064, PM8921_L19_0, PM8921_L19, 2),
2214 MSM_RPM_MAP(8064, PM8921_L20_0, PM8921_L20, 2),
2215 MSM_RPM_MAP(8064, PM8921_L21_0, PM8921_L21, 2),
2216 MSM_RPM_MAP(8064, PM8921_L22_0, PM8921_L22, 2),
2217 MSM_RPM_MAP(8064, PM8921_L23_0, PM8921_L23, 2),
2218 MSM_RPM_MAP(8064, PM8921_L24_0, PM8921_L24, 2),
2219 MSM_RPM_MAP(8064, PM8921_L25_0, PM8921_L25, 2),
2220 MSM_RPM_MAP(8064, PM8921_L26_0, PM8921_L26, 2),
2221 MSM_RPM_MAP(8064, PM8921_L27_0, PM8921_L27, 2),
2222 MSM_RPM_MAP(8064, PM8921_L28_0, PM8921_L28, 2),
2223 MSM_RPM_MAP(8064, PM8921_L29_0, PM8921_L29, 2),
2224 MSM_RPM_MAP(8064, PM8921_CLK1_0, PM8921_CLK1, 2),
2225 MSM_RPM_MAP(8064, PM8921_CLK2_0, PM8921_CLK2, 2),
2226 MSM_RPM_MAP(8064, PM8921_LVS1, PM8921_LVS1, 1),
2227 MSM_RPM_MAP(8064, PM8921_LVS2, PM8921_LVS2, 1),
2228 MSM_RPM_MAP(8064, PM8921_LVS3, PM8921_LVS3, 1),
2229 MSM_RPM_MAP(8064, PM8921_LVS4, PM8921_LVS4, 1),
2230 MSM_RPM_MAP(8064, PM8921_LVS5, PM8921_LVS5, 1),
2231 MSM_RPM_MAP(8064, PM8921_LVS6, PM8921_LVS6, 1),
2232 MSM_RPM_MAP(8064, PM8921_LVS7, PM8921_LVS7, 1),
2233 MSM_RPM_MAP(8064, PM8821_S1_0, PM8821_S1, 2),
2234 MSM_RPM_MAP(8064, PM8821_S2_0, PM8821_S2, 2),
2235 MSM_RPM_MAP(8064, PM8821_L1_0, PM8821_L1, 2),
2236 MSM_RPM_MAP(8064, NCP_0, NCP, 2),
2237 MSM_RPM_MAP(8064, CXO_BUFFERS, CXO_BUFFERS, 1),
2238 MSM_RPM_MAP(8064, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
2239 MSM_RPM_MAP(8064, HDMI_SWITCH, HDMI_SWITCH, 1),
2240 MSM_RPM_MAP(8064, DDR_DMM_0, DDR_DMM, 2),
2241 MSM_RPM_MAP(8064, QDSS_CLK, QDSS_CLK, 1),
Joel Kingef390842012-05-23 16:42:48 -07002242 MSM_RPM_MAP(8064, VDDMIN_GPIO, VDDMIN_GPIO, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -06002243 },
2244 .target_status = {
2245 MSM_RPM_STATUS_ID_MAP(8064, VERSION_MAJOR),
2246 MSM_RPM_STATUS_ID_MAP(8064, VERSION_MINOR),
2247 MSM_RPM_STATUS_ID_MAP(8064, VERSION_BUILD),
2248 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_0),
2249 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_1),
2250 MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_2),
2251 MSM_RPM_STATUS_ID_MAP(8064, RESERVED_SUPPORTED_RESOURCES_0),
2252 MSM_RPM_STATUS_ID_MAP(8064, SEQUENCE),
2253 MSM_RPM_STATUS_ID_MAP(8064, RPM_CTL),
2254 MSM_RPM_STATUS_ID_MAP(8064, CXO_CLK),
2255 MSM_RPM_STATUS_ID_MAP(8064, PXO_CLK),
2256 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CLK),
2257 MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_CLK),
2258 MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_CLK),
2259 MSM_RPM_STATUS_ID_MAP(8064, DAYTONA_FABRIC_CLK),
2260 MSM_RPM_STATUS_ID_MAP(8064, SFPB_CLK),
2261 MSM_RPM_STATUS_ID_MAP(8064, CFPB_CLK),
2262 MSM_RPM_STATUS_ID_MAP(8064, MMFPB_CLK),
2263 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CLK),
2264 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_HALT),
2265 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_CLKMOD),
2266 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_IOCTL),
2267 MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_ARB),
2268 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_HALT),
2269 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_CLKMOD),
2270 MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_IOCTL),
2271 MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_ARB),
2272 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_HALT),
2273 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_CLKMOD),
2274 MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_IOCTL),
2275 MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_ARB),
2276 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_0),
2277 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_1),
2278 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_0),
2279 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_1),
2280 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_0),
2281 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_1),
2282 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_0),
2283 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_1),
2284 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_0),
2285 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_1),
2286 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_0),
2287 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_1),
2288 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_0),
2289 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_1),
2290 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_0),
2291 MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_1),
2292 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_0),
2293 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_1),
2294 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_0),
2295 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_1),
2296 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_0),
2297 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_1),
2298 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_0),
2299 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_1),
2300 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_0),
2301 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_1),
2302 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_0),
2303 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_1),
2304 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_0),
2305 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_1),
2306 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_0),
2307 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_1),
2308 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_0),
2309 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_1),
2310 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_0),
2311 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_1),
2312 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_0),
2313 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_1),
2314 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_0),
2315 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_1),
2316 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_0),
2317 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_1),
2318 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_0),
2319 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_1),
2320 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_0),
2321 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_1),
2322 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_0),
2323 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_1),
2324 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_0),
2325 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_1),
2326 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_0),
2327 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_1),
2328 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_0),
2329 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_1),
2330 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_0),
2331 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_1),
2332 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_0),
2333 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_1),
2334 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_0),
2335 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_1),
2336 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_0),
2337 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_1),
2338 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_0),
2339 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_1),
2340 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_0),
2341 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_1),
2342 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_0),
2343 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_1),
2344 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_0),
2345 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_1),
2346 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_0),
2347 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_1),
2348 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_0),
2349 MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_1),
2350 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_0),
2351 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_1),
2352 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_0),
2353 MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_1),
2354 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS1),
2355 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS2),
2356 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS3),
2357 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS4),
2358 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS5),
2359 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS6),
2360 MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS7),
2361 MSM_RPM_STATUS_ID_MAP(8064, NCP_0),
2362 MSM_RPM_STATUS_ID_MAP(8064, NCP_1),
2363 MSM_RPM_STATUS_ID_MAP(8064, CXO_BUFFERS),
2364 MSM_RPM_STATUS_ID_MAP(8064, USB_OTG_SWITCH),
2365 MSM_RPM_STATUS_ID_MAP(8064, HDMI_SWITCH),
2366 MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_0),
2367 MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_1),
2368 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH0_RANGE),
2369 MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH1_RANGE),
2370 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_0),
2371 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_1),
2372 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_0),
2373 MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_1),
2374 MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_0),
2375 MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_1),
Joel Kingef390842012-05-23 16:42:48 -07002376 MSM_RPM_STATUS_ID_MAP(8064, VDDMIN_GPIO),
Praveen Chidambaram78499012011-11-01 17:15:17 -06002377 },
2378 .target_ctrl_id = {
2379 MSM_RPM_CTRL_MAP(8064, VERSION_MAJOR),
2380 MSM_RPM_CTRL_MAP(8064, VERSION_MINOR),
2381 MSM_RPM_CTRL_MAP(8064, VERSION_BUILD),
2382 MSM_RPM_CTRL_MAP(8064, REQ_CTX_0),
2383 MSM_RPM_CTRL_MAP(8064, REQ_SEL_0),
2384 MSM_RPM_CTRL_MAP(8064, ACK_CTX_0),
2385 MSM_RPM_CTRL_MAP(8064, ACK_SEL_0),
2386 },
2387 .sel_invalidate = MSM_RPM_8064_SEL_INVALIDATE,
2388 .sel_notification = MSM_RPM_8064_SEL_NOTIFICATION,
2389 .sel_last = MSM_RPM_8064_SEL_LAST,
2390 .ver = {3, 0, 0},
2391};
2392
2393struct platform_device apq8064_rpm_device = {
2394 .name = "msm_rpm",
2395 .id = -1,
2396};
2397
2398static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
Anji Jonnala660b4e42012-09-18 19:20:21 +05302399 .phys_addr_base = 0x0010DD04,
2400 .phys_size = SZ_256,
Praveen Chidambaram78499012011-11-01 17:15:17 -06002401};
2402
2403struct platform_device apq8064_rpm_stat_device = {
2404 .name = "msm_rpm_stat",
2405 .id = -1,
2406 .dev = {
2407 .platform_data = &msm_rpm_stat_pdata,
2408 },
2409};
2410
Anji Jonnala93129922012-10-09 20:57:53 +05302411static struct resource resources_rpm_master_stats[] = {
2412 {
2413 .start = MSM8064_RPM_MASTER_STATS_BASE,
2414 .end = MSM8064_RPM_MASTER_STATS_BASE + SZ_256,
2415 .flags = IORESOURCE_MEM,
2416 },
2417};
2418
2419static char *master_names[] = {
2420 "KPSS",
2421 "MPSS",
2422 "LPASS",
2423 "RIVA",
2424 "DSPS",
2425};
2426
2427static struct msm_rpm_master_stats_platform_data msm_rpm_master_stat_pdata = {
2428 .masters = master_names,
2429 .nomasters = ARRAY_SIZE(master_names),
2430};
2431
2432struct platform_device apq8064_rpm_master_stat_device = {
2433 .name = "msm_rpm_master_stat",
2434 .id = -1,
2435 .num_resources = ARRAY_SIZE(resources_rpm_master_stats),
2436 .resource = resources_rpm_master_stats,
2437 .dev = {
2438 .platform_data = &msm_rpm_master_stat_pdata,
2439 },
2440};
2441
Praveen Chidambaram78499012011-11-01 17:15:17 -06002442static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
2443 .phys_addr_base = 0x0010C000,
2444 .reg_offsets = {
2445 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
2446 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
2447 },
2448 .phys_size = SZ_8K,
2449 .log_len = 4096, /* log's buffer length in bytes */
2450 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
2451};
2452
2453struct platform_device apq8064_rpm_log_device = {
2454 .name = "msm_rpm_log",
2455 .id = -1,
2456 .dev = {
2457 .platform_data = &msm_rpm_log_pdata,
2458 },
2459};
2460
Jin Hongd3024e62012-02-09 16:13:32 -08002461/* Sensors DSPS platform data */
2462
Jin Hongd3024e62012-02-09 16:13:32 -08002463static struct dsps_clk_info dsps_clks[] = {};
2464static struct dsps_regulator_info dsps_regs[] = {};
2465
2466/*
2467 * Note: GPIOs field is intialized in run-time at the function
2468 * apq8064_init_dsps().
2469 */
2470
Stephen Boydf169b4b2012-05-10 17:55:55 -07002471#define PPSS_REG_PHYS_BASE 0x12080000
2472
Jin Hongd3024e62012-02-09 16:13:32 -08002473struct msm_dsps_platform_data msm_dsps_pdata_8064 = {
2474 .clks = dsps_clks,
2475 .clks_num = ARRAY_SIZE(dsps_clks),
2476 .gpios = NULL,
2477 .gpios_num = 0,
2478 .regs = dsps_regs,
2479 .regs_num = ARRAY_SIZE(dsps_regs),
2480 .dsps_pwr_ctl_en = 1,
2481 .signature = DSPS_SIGNATURE,
2482};
2483
2484static struct resource msm_dsps_resources[] = {
2485 {
2486 .start = PPSS_REG_PHYS_BASE,
2487 .end = PPSS_REG_PHYS_BASE + SZ_8K - 1,
2488 .name = "ppss_reg",
2489 .flags = IORESOURCE_MEM,
2490 },
Jin Hongd3024e62012-02-09 16:13:32 -08002491};
2492
2493struct platform_device msm_dsps_device_8064 = {
2494 .name = "msm_dsps",
2495 .id = 0,
2496 .num_resources = ARRAY_SIZE(msm_dsps_resources),
2497 .resource = msm_dsps_resources,
2498 .dev.platform_data = &msm_dsps_pdata_8064,
2499};
2500
Praveen Chidambaram78499012011-11-01 17:15:17 -06002501#ifdef CONFIG_MSM_MPM
2502static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
2503 [1] = MSM_GPIO_TO_INT(26),
2504 [2] = MSM_GPIO_TO_INT(88),
2505 [4] = MSM_GPIO_TO_INT(73),
2506 [5] = MSM_GPIO_TO_INT(74),
2507 [6] = MSM_GPIO_TO_INT(75),
2508 [7] = MSM_GPIO_TO_INT(76),
2509 [8] = MSM_GPIO_TO_INT(77),
2510 [9] = MSM_GPIO_TO_INT(36),
2511 [10] = MSM_GPIO_TO_INT(84),
2512 [11] = MSM_GPIO_TO_INT(7),
2513 [12] = MSM_GPIO_TO_INT(11),
2514 [13] = MSM_GPIO_TO_INT(52),
2515 [14] = MSM_GPIO_TO_INT(15),
2516 [15] = MSM_GPIO_TO_INT(83),
2517 [16] = USB3_HS_IRQ,
2518 [19] = MSM_GPIO_TO_INT(61),
2519 [20] = MSM_GPIO_TO_INT(58),
2520 [23] = MSM_GPIO_TO_INT(65),
2521 [24] = MSM_GPIO_TO_INT(63),
2522 [25] = USB1_HS_IRQ,
2523 [27] = HDMI_IRQ,
2524 [29] = MSM_GPIO_TO_INT(22),
2525 [30] = MSM_GPIO_TO_INT(72),
2526 [31] = USB4_HS_IRQ,
2527 [33] = MSM_GPIO_TO_INT(44),
2528 [34] = MSM_GPIO_TO_INT(39),
2529 [35] = MSM_GPIO_TO_INT(19),
2530 [36] = MSM_GPIO_TO_INT(23),
2531 [37] = MSM_GPIO_TO_INT(41),
2532 [38] = MSM_GPIO_TO_INT(30),
2533 [41] = MSM_GPIO_TO_INT(42),
2534 [42] = MSM_GPIO_TO_INT(56),
2535 [43] = MSM_GPIO_TO_INT(55),
2536 [44] = MSM_GPIO_TO_INT(50),
2537 [45] = MSM_GPIO_TO_INT(49),
2538 [46] = MSM_GPIO_TO_INT(47),
2539 [47] = MSM_GPIO_TO_INT(45),
2540 [48] = MSM_GPIO_TO_INT(38),
2541 [49] = MSM_GPIO_TO_INT(34),
2542 [50] = MSM_GPIO_TO_INT(32),
2543 [51] = MSM_GPIO_TO_INT(29),
2544 [52] = MSM_GPIO_TO_INT(18),
2545 [53] = MSM_GPIO_TO_INT(10),
2546 [54] = MSM_GPIO_TO_INT(81),
2547 [55] = MSM_GPIO_TO_INT(6),
2548};
2549
2550static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
2551 TLMM_MSM_SUMMARY_IRQ,
2552 RPM_APCC_CPU0_GP_HIGH_IRQ,
2553 RPM_APCC_CPU0_GP_MEDIUM_IRQ,
2554 RPM_APCC_CPU0_GP_LOW_IRQ,
2555 RPM_APCC_CPU0_WAKE_UP_IRQ,
2556 RPM_APCC_CPU1_GP_HIGH_IRQ,
2557 RPM_APCC_CPU1_GP_MEDIUM_IRQ,
2558 RPM_APCC_CPU1_GP_LOW_IRQ,
2559 RPM_APCC_CPU1_WAKE_UP_IRQ,
2560 MSS_TO_APPS_IRQ_0,
2561 MSS_TO_APPS_IRQ_1,
2562 MSS_TO_APPS_IRQ_2,
2563 MSS_TO_APPS_IRQ_3,
2564 MSS_TO_APPS_IRQ_4,
2565 MSS_TO_APPS_IRQ_5,
2566 MSS_TO_APPS_IRQ_6,
2567 MSS_TO_APPS_IRQ_7,
2568 MSS_TO_APPS_IRQ_8,
2569 MSS_TO_APPS_IRQ_9,
2570 LPASS_SCSS_GP_LOW_IRQ,
2571 LPASS_SCSS_GP_MEDIUM_IRQ,
2572 LPASS_SCSS_GP_HIGH_IRQ,
2573 SPS_MTI_30,
2574 SPS_MTI_31,
2575 RIVA_APSS_SPARE_IRQ,
2576 RIVA_APPS_WLAN_SMSM_IRQ,
2577 RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
2578 RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
Chandra Ramachandran59851722012-07-23 11:19:48 -07002579 PM8821_SEC_IRQ_N,
Praveen Chidambaram78499012011-11-01 17:15:17 -06002580};
2581
2582struct msm_mpm_device_data apq8064_mpm_dev_data __initdata = {
2583 .irqs_m2a = msm_mpm_irqs_m2a,
2584 .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
2585 .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
2586 .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
2587 .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
2588 .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
2589 .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
2590 .mpm_apps_ipc_val = BIT(1),
2591 .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
2592
2593};
2594#endif
Joel Kingdacbc822012-01-25 13:30:57 -08002595
Joel King14fe7fa2012-05-27 14:26:11 -07002596/* AP2MDM_SOFT_RESET is implemented by the PON_RESET_N gpio */
Joel Kingdacbc822012-01-25 13:30:57 -08002597#define MDM2AP_ERRFATAL 19
2598#define AP2MDM_ERRFATAL 18
2599#define MDM2AP_STATUS 49
2600#define AP2MDM_STATUS 48
Joel King14fe7fa2012-05-27 14:26:11 -07002601#define AP2MDM_SOFT_RESET 27
Ameya Thakure155ece2012-07-09 12:08:37 -07002602#define I2S_AP2MDM_SOFT_RESET 0
Vamsi Krishna9e307cd2012-04-11 13:15:36 -07002603#define AP2MDM_WAKEUP 35
Ameya Thakure155ece2012-07-09 12:08:37 -07002604#define I2S_AP2MDM_WAKEUP 44
Vamsi Krishnac6dcd5e2012-05-09 15:38:01 -07002605#define MDM2AP_PBLRDY 46
Ameya Thakure155ece2012-07-09 12:08:37 -07002606#define I2S_MDM2AP_PBLRDY 81
Joel Kingdacbc822012-01-25 13:30:57 -08002607
2608static struct resource mdm_resources[] = {
2609 {
2610 .start = MDM2AP_ERRFATAL,
2611 .end = MDM2AP_ERRFATAL,
2612 .name = "MDM2AP_ERRFATAL",
2613 .flags = IORESOURCE_IO,
2614 },
2615 {
2616 .start = AP2MDM_ERRFATAL,
2617 .end = AP2MDM_ERRFATAL,
2618 .name = "AP2MDM_ERRFATAL",
2619 .flags = IORESOURCE_IO,
2620 },
2621 {
2622 .start = MDM2AP_STATUS,
2623 .end = MDM2AP_STATUS,
2624 .name = "MDM2AP_STATUS",
2625 .flags = IORESOURCE_IO,
2626 },
2627 {
2628 .start = AP2MDM_STATUS,
2629 .end = AP2MDM_STATUS,
2630 .name = "AP2MDM_STATUS",
2631 .flags = IORESOURCE_IO,
2632 },
2633 {
Joel King14fe7fa2012-05-27 14:26:11 -07002634 .start = AP2MDM_SOFT_RESET,
2635 .end = AP2MDM_SOFT_RESET,
2636 .name = "AP2MDM_SOFT_RESET",
Joel Kingdacbc822012-01-25 13:30:57 -08002637 .flags = IORESOURCE_IO,
2638 },
Vamsi Krishna9e307cd2012-04-11 13:15:36 -07002639 {
2640 .start = AP2MDM_WAKEUP,
2641 .end = AP2MDM_WAKEUP,
2642 .name = "AP2MDM_WAKEUP",
2643 .flags = IORESOURCE_IO,
2644 },
Vamsi Krishnac6dcd5e2012-05-09 15:38:01 -07002645 {
2646 .start = MDM2AP_PBLRDY,
2647 .end = MDM2AP_PBLRDY,
2648 .name = "MDM2AP_PBLRDY",
2649 .flags = IORESOURCE_IO,
2650 },
Joel Kingdacbc822012-01-25 13:30:57 -08002651};
2652
Ameya Thakure155ece2012-07-09 12:08:37 -07002653static struct resource i2s_mdm_resources[] = {
2654 {
2655 .start = MDM2AP_ERRFATAL,
2656 .end = MDM2AP_ERRFATAL,
2657 .name = "MDM2AP_ERRFATAL",
2658 .flags = IORESOURCE_IO,
2659 },
2660 {
2661 .start = AP2MDM_ERRFATAL,
2662 .end = AP2MDM_ERRFATAL,
2663 .name = "AP2MDM_ERRFATAL",
2664 .flags = IORESOURCE_IO,
2665 },
2666 {
2667 .start = MDM2AP_STATUS,
2668 .end = MDM2AP_STATUS,
2669 .name = "MDM2AP_STATUS",
2670 .flags = IORESOURCE_IO,
2671 },
2672 {
2673 .start = AP2MDM_STATUS,
2674 .end = AP2MDM_STATUS,
2675 .name = "AP2MDM_STATUS",
2676 .flags = IORESOURCE_IO,
2677 },
2678 {
2679 .start = I2S_AP2MDM_SOFT_RESET,
2680 .end = I2S_AP2MDM_SOFT_RESET,
2681 .name = "AP2MDM_SOFT_RESET",
2682 .flags = IORESOURCE_IO,
2683 },
2684 {
2685 .start = I2S_AP2MDM_WAKEUP,
2686 .end = I2S_AP2MDM_WAKEUP,
2687 .name = "AP2MDM_WAKEUP",
2688 .flags = IORESOURCE_IO,
2689 },
2690 {
2691 .start = I2S_MDM2AP_PBLRDY,
2692 .end = I2S_MDM2AP_PBLRDY,
2693 .name = "MDM2AP_PBLRDY",
2694 .flags = IORESOURCE_IO,
2695 },
2696};
2697
Joel Kingdacbc822012-01-25 13:30:57 -08002698struct platform_device mdm_8064_device = {
2699 .name = "mdm2_modem",
2700 .id = -1,
2701 .num_resources = ARRAY_SIZE(mdm_resources),
2702 .resource = mdm_resources,
2703};
Praveen Chidambaram8ea3dcd2011-12-07 14:46:31 -07002704
Ameya Thakure155ece2012-07-09 12:08:37 -07002705struct platform_device i2s_mdm_8064_device = {
2706 .name = "mdm2_modem",
2707 .id = -1,
2708 .num_resources = ARRAY_SIZE(i2s_mdm_resources),
2709 .resource = i2s_mdm_resources,
2710};
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002711
2712static struct msm_dcvs_freq_entry apq8064_freq[] = {
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -07002713 { 384000, 900, 0, 0, 0},
2714 { 594000, 950, 0, 0, 0},
2715 { 702000, 975, 0, 0, 0},
2716 {1026000, 1075, 0, 0, 0},
2717 {1242000, 1150, 0, 100, 100},
2718 {1458000, 1188, 0, 100, 100},
2719 {1512000, 1200, 1, 100, 100},
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002720};
2721
2722static struct msm_dcvs_core_info apq8064_core_info = {
Abhijeet Dharmapurikar80add422012-09-13 11:11:54 -07002723 .freq_tbl = &apq8064_freq[0],
2724 .num_cores = 4,
2725 .sensors = (int[]){7, 8, 9, 10},
2726 .thermal_poll_ms = 60000,
2727 .core_param = {
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -07002728 .core_type = MSM_DCVS_CORE_TYPE_CPU,
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002729 },
Abhijeet Dharmapurikar80add422012-09-13 11:11:54 -07002730 .algo_param = {
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -07002731 .disable_pc_threshold = 1458000,
2732 .em_win_size_min_us = 100000,
2733 .em_win_size_max_us = 300000,
2734 .em_max_util_pct = 97,
2735 .group_id = 1,
2736 .max_freq_chg_time_us = 100000,
2737 .slack_mode_dynamic = 0,
2738 .slack_weight_thresh_pct = 3,
2739 .slack_time_min_us = 45000,
2740 .slack_time_max_us = 45000,
2741 .ss_iobusy_conv = 100,
2742 .ss_win_size_min_us = 1000000,
2743 .ss_win_size_max_us = 1000000,
2744 .ss_util_pct = 95,
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002745 },
Abhijeet Dharmapurikar80add422012-09-13 11:11:54 -07002746 .energy_coeffs = {
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -07002747 .active_coeff_a = 336,
2748 .active_coeff_b = 0,
2749 .active_coeff_c = 0,
2750
2751 .leakage_coeff_a = -17720,
2752 .leakage_coeff_b = 37,
2753 .leakage_coeff_c = 3329,
2754 .leakage_coeff_d = -277,
2755 },
Abhijeet Dharmapurikar80add422012-09-13 11:11:54 -07002756 .power_param = {
Abhijeet Dharmapurikar44451662012-08-23 18:58:44 -07002757 .current_temp = 25,
2758 .num_freq = ARRAY_SIZE(apq8064_freq),
2759 }
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002760};
2761
Abhijeet Dharmapurikarc1ed66c2012-09-10 16:03:39 -07002762#define APQ8064_LPM_LATENCY 1000 /* >100 usec for WFI */
2763
2764static struct msm_gov_platform_data gov_platform_data = {
2765 .info = &apq8064_core_info,
2766 .latency = APQ8064_LPM_LATENCY,
2767};
2768
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002769struct platform_device apq8064_msm_gov_device = {
2770 .name = "msm_dcvs_gov",
2771 .id = -1,
2772 .dev = {
Abhijeet Dharmapurikarc1ed66c2012-09-10 16:03:39 -07002773 .platform_data = &gov_platform_data,
Praveen Chidambaram5c8adf22012-02-23 18:44:37 -07002774 },
2775};
Stepan Moskovchenko28662c52012-03-01 12:48:45 -08002776
Abhijeet Dharmapurikarfb4a2f82012-08-23 14:36:59 -07002777static struct msm_mpd_algo_param apq8064_mpd_algo_param = {
2778 .em_win_size_min_us = 10000,
2779 .em_win_size_max_us = 100000,
2780 .em_max_util_pct = 90,
2781 .online_util_pct_min = 60,
2782 .slack_time_min_us = 50000,
2783 .slack_time_max_us = 100000,
2784};
2785
2786struct platform_device apq8064_msm_mpd_device = {
2787 .name = "msm_mpdecision",
2788 .id = -1,
2789 .dev = {
2790 .platform_data = &apq8064_mpd_algo_param,
2791 },
2792};
2793
Terence Hampson2e1705f2012-04-11 19:55:29 -04002794#ifdef CONFIG_MSM_VCAP
2795#define VCAP_HW_BASE 0x05900000
2796
2797static struct msm_bus_vectors vcap_init_vectors[] = {
2798 {
2799 .src = MSM_BUS_MASTER_VIDEO_CAP,
2800 .dst = MSM_BUS_SLAVE_EBI_CH0,
2801 .ab = 0,
2802 .ib = 0,
2803 },
2804};
2805
Terence Hampson2e1705f2012-04-11 19:55:29 -04002806static struct msm_bus_vectors vcap_480_vectors[] = {
2807 {
2808 .src = MSM_BUS_MASTER_VIDEO_CAP,
2809 .dst = MSM_BUS_SLAVE_EBI_CH0,
Terence Hampson779dc762012-06-07 15:59:27 -04002810 .ab = 480 * 720 * 3 * 60,
2811 .ib = 480 * 720 * 3 * 60 * 1.5,
2812 },
2813};
2814
2815static struct msm_bus_vectors vcap_576_vectors[] = {
2816 {
2817 .src = MSM_BUS_MASTER_VIDEO_CAP,
2818 .dst = MSM_BUS_SLAVE_EBI_CH0,
2819 .ab = 576 * 720 * 3 * 60,
2820 .ib = 576 * 720 * 3 * 60 * 1.5,
Terence Hampson2e1705f2012-04-11 19:55:29 -04002821 },
2822};
2823
2824static struct msm_bus_vectors vcap_720_vectors[] = {
2825 {
2826 .src = MSM_BUS_MASTER_VIDEO_CAP,
2827 .dst = MSM_BUS_SLAVE_EBI_CH0,
Terence Hampson35a1ff02012-04-25 17:07:18 -04002828 .ab = 1280 * 720 * 3 * 60,
2829 .ib = 1280 * 720 * 3 * 60 * 1.5,
Terence Hampson2e1705f2012-04-11 19:55:29 -04002830 },
2831};
2832
2833static struct msm_bus_vectors vcap_1080_vectors[] = {
2834 {
2835 .src = MSM_BUS_MASTER_VIDEO_CAP,
2836 .dst = MSM_BUS_SLAVE_EBI_CH0,
Terence Hampsonf51f6e62012-08-29 11:02:17 -04002837 .ab = 1920 * 1080 * 10 * 60,
2838 .ib = 1920 * 1080 * 10 * 60 * 1.5,
Terence Hampson2e1705f2012-04-11 19:55:29 -04002839 },
2840};
2841
2842static struct msm_bus_paths vcap_bus_usecases[] = {
2843 {
2844 ARRAY_SIZE(vcap_init_vectors),
2845 vcap_init_vectors,
2846 },
2847 {
2848 ARRAY_SIZE(vcap_480_vectors),
2849 vcap_480_vectors,
2850 },
2851 {
Terence Hampson779dc762012-06-07 15:59:27 -04002852 ARRAY_SIZE(vcap_576_vectors),
2853 vcap_576_vectors,
2854 },
2855 {
Terence Hampson2e1705f2012-04-11 19:55:29 -04002856 ARRAY_SIZE(vcap_720_vectors),
2857 vcap_720_vectors,
2858 },
2859 {
2860 ARRAY_SIZE(vcap_1080_vectors),
2861 vcap_1080_vectors,
2862 },
2863};
2864
2865static struct msm_bus_scale_pdata vcap_axi_client_pdata = {
2866 vcap_bus_usecases,
2867 ARRAY_SIZE(vcap_bus_usecases),
2868};
2869
2870static struct resource msm_vcap_resources[] = {
2871 {
2872 .name = "vcap",
2873 .start = VCAP_HW_BASE,
2874 .end = VCAP_HW_BASE + SZ_1M - 1,
2875 .flags = IORESOURCE_MEM,
2876 },
2877 {
Terence Hampsonaeb793e2012-05-11 11:41:16 -04002878 .name = "vc_irq",
Terence Hampson2e1705f2012-04-11 19:55:29 -04002879 .start = VCAP_VC,
2880 .end = VCAP_VC,
2881 .flags = IORESOURCE_IRQ,
2882 },
Terence Hampsonaeb793e2012-05-11 11:41:16 -04002883 {
2884 .name = "vp_irq",
2885 .start = VCAP_VP,
2886 .end = VCAP_VP,
2887 .flags = IORESOURCE_IRQ,
2888 },
Terence Hampson2e1705f2012-04-11 19:55:29 -04002889};
2890
2891static unsigned vcap_gpios[] = {
2892 2, 3, 4, 5, 6, 7, 8, 9, 10,
2893 11, 12, 13, 18, 19, 20, 21,
2894 22, 23, 24, 25, 26, 80, 82,
2895 83, 84, 85, 86, 87,
2896};
2897
2898static struct vcap_platform_data vcap_pdata = {
2899 .gpios = vcap_gpios,
2900 .num_gpios = ARRAY_SIZE(vcap_gpios),
2901 .bus_client_pdata = &vcap_axi_client_pdata
2902};
2903
2904struct platform_device msm8064_device_vcap = {
2905 .name = "msm_vcap",
2906 .id = 0,
2907 .resource = msm_vcap_resources,
2908 .num_resources = ARRAY_SIZE(msm_vcap_resources),
2909 .dev = {
2910 .platform_data = &vcap_pdata,
2911 },
2912};
2913#endif
2914
Stepan Moskovchenko28662c52012-03-01 12:48:45 -08002915static struct resource msm_cache_erp_resources[] = {
2916 {
2917 .name = "l1_irq",
2918 .start = SC_SICCPUXEXTFAULTIRPTREQ,
2919 .flags = IORESOURCE_IRQ,
2920 },
2921 {
2922 .name = "l2_irq",
2923 .start = APCC_QGICL2IRPTREQ,
2924 .flags = IORESOURCE_IRQ,
2925 }
2926};
2927
2928struct platform_device apq8064_device_cache_erp = {
2929 .name = "msm_cache_erp",
2930 .id = -1,
2931 .num_resources = ARRAY_SIZE(msm_cache_erp_resources),
2932 .resource = msm_cache_erp_resources,
2933};
Pratik Patel212ab362012-03-16 12:30:07 -07002934
Pratik Patel3b0ca882012-06-01 16:54:14 -07002935#define CORESIGHT_PHYS_BASE 0x01A00000
2936#define CORESIGHT_FUNNEL_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x4000)
2937#define CORESIGHT_ETM2_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1E000)
2938#define CORESIGHT_ETM3_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1F000)
Pratik Patel212ab362012-03-16 12:30:07 -07002939
Pratik Patel3b0ca882012-06-01 16:54:14 -07002940static struct resource coresight_funnel_resources[] = {
Pratik Patel212ab362012-03-16 12:30:07 -07002941 {
Pratik Patel3b0ca882012-06-01 16:54:14 -07002942 .start = CORESIGHT_FUNNEL_PHYS_BASE,
2943 .end = CORESIGHT_FUNNEL_PHYS_BASE + SZ_4K - 1,
Pratik Patel212ab362012-03-16 12:30:07 -07002944 .flags = IORESOURCE_MEM,
2945 },
2946};
2947
Pratik Patel3b0ca882012-06-01 16:54:14 -07002948static const int coresight_funnel_outports[] = { 0, 1 };
2949static const int coresight_funnel_child_ids[] = { 0, 1 };
2950static const int coresight_funnel_child_ports[] = { 0, 0 };
2951
2952static struct coresight_platform_data coresight_funnel_pdata = {
2953 .id = 2,
2954 .name = "coresight-funnel",
Pratik Patel0480dc62012-09-06 09:41:49 -07002955 .nr_inports = 8,
Pratik Patel3b0ca882012-06-01 16:54:14 -07002956 .outports = coresight_funnel_outports,
2957 .child_ids = coresight_funnel_child_ids,
2958 .child_ports = coresight_funnel_child_ports,
2959 .nr_outports = ARRAY_SIZE(coresight_funnel_outports),
2960};
2961
2962struct platform_device apq8064_coresight_funnel_device = {
2963 .name = "coresight-funnel",
Pratik Patel212ab362012-03-16 12:30:07 -07002964 .id = 0,
Pratik Patel3b0ca882012-06-01 16:54:14 -07002965 .num_resources = ARRAY_SIZE(coresight_funnel_resources),
2966 .resource = coresight_funnel_resources,
2967 .dev = {
2968 .platform_data = &coresight_funnel_pdata,
2969 },
2970};
2971
2972static struct resource coresight_etm2_resources[] = {
2973 {
2974 .start = CORESIGHT_ETM2_PHYS_BASE,
2975 .end = CORESIGHT_ETM2_PHYS_BASE + SZ_4K - 1,
2976 .flags = IORESOURCE_MEM,
2977 },
2978};
2979
2980static const int coresight_etm2_outports[] = { 0 };
2981static const int coresight_etm2_child_ids[] = { 2 };
2982static const int coresight_etm2_child_ports[] = { 4 };
2983
2984static struct coresight_platform_data coresight_etm2_pdata = {
2985 .id = 6,
2986 .name = "coresight-etm2",
Pratik Patel0480dc62012-09-06 09:41:49 -07002987 .nr_inports = 0,
Pratik Patel3b0ca882012-06-01 16:54:14 -07002988 .outports = coresight_etm2_outports,
2989 .child_ids = coresight_etm2_child_ids,
2990 .child_ports = coresight_etm2_child_ports,
2991 .nr_outports = ARRAY_SIZE(coresight_etm2_outports),
2992};
2993
2994struct platform_device coresight_etm2_device = {
2995 .name = "coresight-etm",
2996 .id = 2,
2997 .num_resources = ARRAY_SIZE(coresight_etm2_resources),
2998 .resource = coresight_etm2_resources,
2999 .dev = {
3000 .platform_data = &coresight_etm2_pdata,
3001 },
3002};
3003
3004static struct resource coresight_etm3_resources[] = {
3005 {
3006 .start = CORESIGHT_ETM3_PHYS_BASE,
3007 .end = CORESIGHT_ETM3_PHYS_BASE + SZ_4K - 1,
3008 .flags = IORESOURCE_MEM,
3009 },
3010};
3011
3012static const int coresight_etm3_outports[] = { 0 };
3013static const int coresight_etm3_child_ids[] = { 2 };
3014static const int coresight_etm3_child_ports[] = { 5 };
3015
3016static struct coresight_platform_data coresight_etm3_pdata = {
3017 .id = 7,
3018 .name = "coresight-etm3",
Pratik Patel0480dc62012-09-06 09:41:49 -07003019 .nr_inports = 0,
Pratik Patel3b0ca882012-06-01 16:54:14 -07003020 .outports = coresight_etm3_outports,
3021 .child_ids = coresight_etm3_child_ids,
3022 .child_ports = coresight_etm3_child_ports,
3023 .nr_outports = ARRAY_SIZE(coresight_etm3_outports),
3024};
3025
3026struct platform_device coresight_etm3_device = {
3027 .name = "coresight-etm",
3028 .id = 3,
3029 .num_resources = ARRAY_SIZE(coresight_etm3_resources),
3030 .resource = coresight_etm3_resources,
3031 .dev = {
3032 .platform_data = &coresight_etm3_pdata,
3033 },
Pratik Patel212ab362012-03-16 12:30:07 -07003034};
Laura Abbott0577d7b2012-04-17 11:14:30 -07003035
3036struct msm_iommu_domain_name apq8064_iommu_ctx_names[] = {
3037 /* Camera */
3038 {
Laura Abbott0577d7b2012-04-17 11:14:30 -07003039 .name = "ijpeg_src",
3040 .domain = CAMERA_DOMAIN,
3041 },
3042 /* Camera */
3043 {
3044 .name = "ijpeg_dst",
3045 .domain = CAMERA_DOMAIN,
3046 },
3047 /* Camera */
3048 {
3049 .name = "jpegd_src",
3050 .domain = CAMERA_DOMAIN,
3051 },
3052 /* Camera */
3053 {
3054 .name = "jpegd_dst",
3055 .domain = CAMERA_DOMAIN,
3056 },
Olav Hauganef95ae32012-05-15 09:50:30 -07003057 /* Rotator src*/
Laura Abbott0577d7b2012-04-17 11:14:30 -07003058 {
3059 .name = "rot_src",
Olav Hauganef95ae32012-05-15 09:50:30 -07003060 .domain = ROTATOR_SRC_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07003061 },
Olav Hauganef95ae32012-05-15 09:50:30 -07003062 /* Rotator dst */
Laura Abbott0577d7b2012-04-17 11:14:30 -07003063 {
3064 .name = "rot_dst",
Olav Hauganef95ae32012-05-15 09:50:30 -07003065 .domain = ROTATOR_DST_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07003066 },
3067 /* Video */
3068 {
3069 .name = "vcodec_a_mm1",
3070 .domain = VIDEO_DOMAIN,
3071 },
3072 /* Video */
3073 {
3074 .name = "vcodec_b_mm2",
3075 .domain = VIDEO_DOMAIN,
3076 },
3077 /* Video */
3078 {
3079 .name = "vcodec_a_stream",
3080 .domain = VIDEO_DOMAIN,
3081 },
3082};
3083
3084static struct mem_pool apq8064_video_pools[] = {
3085 /*
3086 * Video hardware has the following requirements:
3087 * 1. All video addresses used by the video hardware must be at a higher
3088 * address than video firmware address.
3089 * 2. Video hardware can only access a range of 256MB from the base of
3090 * the video firmware.
3091 */
3092 [VIDEO_FIRMWARE_POOL] =
3093 /* Low addresses, intended for video firmware */
3094 {
3095 .paddr = SZ_128K,
3096 .size = SZ_16M - SZ_128K,
3097 },
3098 [VIDEO_MAIN_POOL] =
3099 /* Main video pool */
3100 {
3101 .paddr = SZ_16M,
3102 .size = SZ_256M - SZ_16M,
3103 },
3104 [GEN_POOL] =
3105 /* Remaining address space up to 2G */
3106 {
3107 .paddr = SZ_256M,
3108 .size = SZ_2G - SZ_256M,
3109 },
3110};
3111
3112static struct mem_pool apq8064_camera_pools[] = {
3113 [GEN_POOL] =
3114 /* One address space for camera */
3115 {
3116 .paddr = SZ_128K,
3117 .size = SZ_2G - SZ_128K,
3118 },
3119};
3120
Olav Hauganef95ae32012-05-15 09:50:30 -07003121static struct mem_pool apq8064_display_read_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07003122 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07003123 /* One address space for display reads */
Laura Abbott0577d7b2012-04-17 11:14:30 -07003124 {
3125 .paddr = SZ_128K,
3126 .size = SZ_2G - SZ_128K,
3127 },
3128};
3129
Olav Hauganef95ae32012-05-15 09:50:30 -07003130static struct mem_pool apq8064_display_write_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07003131 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07003132 /* One address space for display writes */
3133 {
3134 .paddr = SZ_128K,
3135 .size = SZ_2G - SZ_128K,
3136 },
3137};
3138
3139static struct mem_pool apq8064_rotator_src_pools[] = {
3140 [GEN_POOL] =
3141 /* One address space for rotator src */
3142 {
3143 .paddr = SZ_128K,
3144 .size = SZ_2G - SZ_128K,
3145 },
3146};
3147
3148static struct mem_pool apq8064_rotator_dst_pools[] = {
3149 [GEN_POOL] =
3150 /* One address space for rotator dst */
Laura Abbott0577d7b2012-04-17 11:14:30 -07003151 {
3152 .paddr = SZ_128K,
3153 .size = SZ_2G - SZ_128K,
3154 },
3155};
3156
3157static struct msm_iommu_domain apq8064_iommu_domains[] = {
3158 [VIDEO_DOMAIN] = {
3159 .iova_pools = apq8064_video_pools,
3160 .npools = ARRAY_SIZE(apq8064_video_pools),
3161 },
3162 [CAMERA_DOMAIN] = {
3163 .iova_pools = apq8064_camera_pools,
3164 .npools = ARRAY_SIZE(apq8064_camera_pools),
3165 },
Olav Hauganef95ae32012-05-15 09:50:30 -07003166 [DISPLAY_READ_DOMAIN] = {
3167 .iova_pools = apq8064_display_read_pools,
3168 .npools = ARRAY_SIZE(apq8064_display_read_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07003169 },
Olav Hauganef95ae32012-05-15 09:50:30 -07003170 [DISPLAY_WRITE_DOMAIN] = {
3171 .iova_pools = apq8064_display_write_pools,
3172 .npools = ARRAY_SIZE(apq8064_display_write_pools),
3173 },
3174 [ROTATOR_SRC_DOMAIN] = {
3175 .iova_pools = apq8064_rotator_src_pools,
3176 .npools = ARRAY_SIZE(apq8064_rotator_src_pools),
3177 },
3178 [ROTATOR_DST_DOMAIN] = {
3179 .iova_pools = apq8064_rotator_dst_pools,
3180 .npools = ARRAY_SIZE(apq8064_rotator_dst_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07003181 },
3182};
3183
3184struct iommu_domains_pdata apq8064_iommu_domain_pdata = {
3185 .domains = apq8064_iommu_domains,
3186 .ndomains = ARRAY_SIZE(apq8064_iommu_domains),
3187 .domain_names = apq8064_iommu_ctx_names,
3188 .nnames = ARRAY_SIZE(apq8064_iommu_ctx_names),
3189 .domain_alloc_flags = 0,
3190};
3191
3192struct platform_device apq8064_iommu_domain_device = {
3193 .name = "iommu_domains",
3194 .id = -1,
3195 .dev = {
3196 .platform_data = &apq8064_iommu_domain_pdata,
Laura Abbott532b2df2012-04-12 10:53:48 -07003197 }
3198};
3199
3200struct msm_rtb_platform_data apq8064_rtb_pdata = {
3201 .size = SZ_1M,
3202};
3203
3204static int __init msm_rtb_set_buffer_size(char *p)
3205{
3206 int s;
3207
3208 s = memparse(p, NULL);
3209 apq8064_rtb_pdata.size = ALIGN(s, SZ_4K);
3210 return 0;
3211}
3212early_param("msm_rtb_size", msm_rtb_set_buffer_size);
3213
3214struct platform_device apq8064_rtb_device = {
3215 .name = "msm_rtb",
3216 .id = -1,
3217 .dev = {
3218 .platform_data = &apq8064_rtb_pdata,
Laura Abbott0577d7b2012-04-17 11:14:30 -07003219 },
3220};
Laura Abbott93a4a352012-05-25 09:26:35 -07003221
3222#define APQ8064_L1_SIZE SZ_1M
3223/*
3224 * The actual L2 size is smaller but we need a larger buffer
3225 * size to store other dump information
3226 */
3227#define APQ8064_L2_SIZE SZ_8M
3228
3229struct msm_cache_dump_platform_data apq8064_cache_dump_pdata = {
3230 .l2_size = APQ8064_L2_SIZE,
3231 .l1_size = APQ8064_L1_SIZE,
3232};
3233
3234struct platform_device apq8064_cache_dump_device = {
3235 .name = "msm_cache_dump",
3236 .id = -1,
3237 .dev = {
3238 .platform_data = &apq8064_cache_dump_pdata,
3239 },
3240};