Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm / 784a90c0a7d8f5aa94b6c7d295ad44ae8e045aa3 / . / arch / arm / mach-imx / pm-imx5.c
blob: 3d57b5d429fe753ba5066570ec037ef5560ad6c7 [file] [log] [blame]
Sascha Hauer784a90c2011-11-07 12:36:48 +0100[diff] [blame^]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include <linux/suspend.h>
12#include <linux/clk.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <asm/cacheflush.h>
16#include <asm/tlbflush.h>
17#include <mach/common.h>
18#include <mach/hardware.h>
19#include "crm-regs-imx5.h"
20
21static struct clk *gpc_dvfs_clk;
22
23/*
24 * set cpu low power mode before WFI instruction. This function is called
25 * mx5 because it can be used for mx50, mx51, and mx53.
26 */
27void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
28{
29 u32 plat_lpc, arm_srpgcr, ccm_clpcr;
30 u32 empgc0, empgc1;
31 int stop_mode = 0;
32
33 /* always allow platform to issue a deep sleep mode request */
34 plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
35 ~(MXC_CORTEXA8_PLAT_LPC_DSM);
36 ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
37 arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
38 empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
39 empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
40
41 switch (mode) {
42 case WAIT_CLOCKED:
43 break;
44 case WAIT_UNCLOCKED:
45 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
46 break;
47 case WAIT_UNCLOCKED_POWER_OFF:
48 case STOP_POWER_OFF:
49 plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
50 | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
51 if (mode == WAIT_UNCLOCKED_POWER_OFF) {
52 ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
53 ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
54 ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
55 stop_mode = 0;
56 } else {
57 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
58 ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
59 ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
60 ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
61 stop_mode = 1;
62 }
63 arm_srpgcr |= MXC_SRPGCR_PCR;
64
65 if (tzic_enable_wake(1) != 0)
66 return;
67 break;
68 case STOP_POWER_ON:
69 ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
70 break;
71 default:
72 printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
73 return;
74 }
75
76 __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
77 __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
78 __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
79
80 /* Enable NEON SRPG for all but MX50TO1.0. */
81 if (mx50_revision() != IMX_CHIP_REVISION_1_0)
82 __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
83
84 if (stop_mode) {
85 empgc0 |= MXC_SRPGCR_PCR;
86 empgc1 |= MXC_SRPGCR_PCR;
87
88 __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
89 __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
90 }
91}
92
93static int mx5_suspend_prepare(void)
94{
95 return clk_enable(gpc_dvfs_clk);
96}
97
98static int mx5_suspend_enter(suspend_state_t state)
99{
100 switch (state) {
101 case PM_SUSPEND_MEM:
102 mx5_cpu_lp_set(STOP_POWER_OFF);
103 break;
104 case PM_SUSPEND_STANDBY:
105 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
106 break;
107 default:
108 return -EINVAL;
109 }
110
111 if (state == PM_SUSPEND_MEM) {
112 local_flush_tlb_all();
113 flush_cache_all();
114
115 /*clear the EMPGC0/1 bits */
116 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
117 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
118 }
119 cpu_do_idle();
120 return 0;
121}
122
123static void mx5_suspend_finish(void)
124{
125 clk_disable(gpc_dvfs_clk);
126}
127
128static int mx5_pm_valid(suspend_state_t state)
129{
130 return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
131}
132
133static const struct platform_suspend_ops mx5_suspend_ops = {
134 .valid = mx5_pm_valid,
135 .prepare = mx5_suspend_prepare,
136 .enter = mx5_suspend_enter,
137 .finish = mx5_suspend_finish,
138};
139
140static int __init mx5_pm_init(void)
141{
142 if (!cpu_is_mx51() && !cpu_is_mx53())
143 return 0;
144
145 if (gpc_dvfs_clk == NULL)
146 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
147
148 if (!IS_ERR(gpc_dvfs_clk)) {
149 if (cpu_is_mx51())
150 suspend_set_ops(&mx5_suspend_ops);
151 } else
152 return -EPERM;
153
154 return 0;
155}
156device_initcall(mx5_pm_init);