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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Hirokazu Takata3264f972007-08-01 21:09:31 +09002 * linux/arch/m32r/platforms/usrv/setup.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Setup routines for MITSUBISHI uServer
5 *
6 * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto
8 */
9
Linus Torvalds1da177e2005-04-16 15:20:36 -070010#include <linux/irq.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/system.h>
15#include <asm/m32r.h>
16#include <asm/io.h>
17
18#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
19
Linus Torvalds1da177e2005-04-16 15:20:36 -070020icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
21
22static void disable_mappi_irq(unsigned int irq)
23{
24 unsigned long port, data;
25
26 port = irq2port(irq);
27 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
28 outl(data, port);
29}
30
31static void enable_mappi_irq(unsigned int irq)
32{
33 unsigned long port, data;
34
35 port = irq2port(irq);
36 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
37 outl(data, port);
38}
39
40static void mask_and_ack_mappi(unsigned int irq)
41{
42 disable_mappi_irq(irq);
43}
44
45static void end_mappi_irq(unsigned int irq)
46{
47 enable_mappi_irq(irq);
48}
49
50static unsigned int startup_mappi_irq(unsigned int irq)
51{
52 enable_mappi_irq(irq);
53 return 0;
54}
55
56static void shutdown_mappi_irq(unsigned int irq)
57{
58 unsigned long port;
59
60 port = irq2port(irq);
61 outl(M32R_ICUCR_ILEVEL7, port);
62}
63
Thomas Gleixner189e91f2009-06-16 15:33:26 -070064static struct irq_chip mappi_irq_type =
Linus Torvalds1da177e2005-04-16 15:20:36 -070065{
Thomas Gleixnerd1ea13c2010-09-23 18:40:07 +020066 .name = "M32700-IRQ",
Hirokazu Takata6f973b02005-06-21 17:16:13 -070067 .startup = startup_mappi_irq,
68 .shutdown = shutdown_mappi_irq,
69 .enable = enable_mappi_irq,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_mappi_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -070073};
74
75/*
76 * Interrupt Control Unit of PLD on M32700UT (Level 2)
77 */
78#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
79#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
80 (((x) - 1) * sizeof(unsigned short)))
81
82typedef struct {
83 unsigned short icucr; /* ICU Control Register */
84} pld_icu_data_t;
85
86static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
87
88static void disable_m32700ut_pld_irq(unsigned int irq)
89{
90 unsigned long port, data;
91 unsigned int pldirq;
92
93 pldirq = irq2pldirq(irq);
94 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
96 outw(data, port);
97}
98
99static void enable_m32700ut_pld_irq(unsigned int irq)
100{
101 unsigned long port, data;
102 unsigned int pldirq;
103
104 pldirq = irq2pldirq(irq);
105 port = pldirq2port(pldirq);
106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
107 outw(data, port);
108}
109
110static void mask_and_ack_m32700ut_pld(unsigned int irq)
111{
112 disable_m32700ut_pld_irq(irq);
113}
114
115static void end_m32700ut_pld_irq(unsigned int irq)
116{
117 enable_m32700ut_pld_irq(irq);
118 end_mappi_irq(M32R_IRQ_INT1);
119}
120
121static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
122{
123 enable_m32700ut_pld_irq(irq);
124 return 0;
125}
126
127static void shutdown_m32700ut_pld_irq(unsigned int irq)
128{
129 unsigned long port;
130 unsigned int pldirq;
131
132 pldirq = irq2pldirq(irq);
133 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port);
135}
136
Thomas Gleixner189e91f2009-06-16 15:33:26 -0700137static struct irq_chip m32700ut_pld_irq_type =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138{
Thomas Gleixnerd1ea13c2010-09-23 18:40:07 +0200139 .name = "USRV-PLD-IRQ",
Hirokazu Takata6f973b02005-06-21 17:16:13 -0700140 .startup = startup_m32700ut_pld_irq,
141 .shutdown = shutdown_m32700ut_pld_irq,
142 .enable = enable_m32700ut_pld_irq,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146};
147
148void __init init_IRQ(void)
149{
150 static int once = 0;
151 int i;
152
153 if (once)
154 return;
155 else
156 once++;
157
158 /* MFT2 : system timer */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200159 set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
161 disable_mappi_irq(M32R_IRQ_MFT2);
162
163#if defined(CONFIG_SERIAL_M32R_SIO)
164 /* SIO0_R : uart receive data */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200165 set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
167 disable_mappi_irq(M32R_IRQ_SIO0_R);
168
169 /* SIO0_S : uart send data */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200170 set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
172 disable_mappi_irq(M32R_IRQ_SIO0_S);
173
174 /* SIO1_R : uart receive data */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200175 set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
177 disable_mappi_irq(M32R_IRQ_SIO1_R);
178
179 /* SIO1_S : uart send data */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200180 set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
182 disable_mappi_irq(M32R_IRQ_SIO1_S);
183#endif /* CONFIG_SERIAL_M32R_SIO */
184
185 /* INT#67-#71: CFC#0 IREQ on PLD */
Hirokazu Takata3264f972007-08-01 21:09:31 +0900186 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
Thomas Gleixner863018a2010-09-22 19:13:16 +0200187 set_irq_chip(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
189 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
190 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
191 }
192
193#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
194 /* INT#76: 16552D#0 IREQ on PLD */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200195 set_irq_chip(PLD_IRQ_UART0, &m32700ut_pld_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
197 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
198 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
199
200 /* INT#77: 16552D#1 IREQ on PLD */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200201 set_irq_chip(PLD_IRQ_UART1, &m32700ut_pld_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
203 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
204 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
205#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
206
207#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
208 /* INT#80: AK4524 IREQ on PLD */
Thomas Gleixner863018a2010-09-22 19:13:16 +0200209 set_irq_chip(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
211 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
212 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
213#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
214
215 /*
216 * INT1# is used for UART, MMC, CF Controller in FPGA.
217 * We enable it here.
218 */
219 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
220 enable_mappi_irq(M32R_IRQ_INT1);
221}