Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-ixp4xx/common.c |
| 3 | * |
| 4 | * Generic code shared across all IXP4XX platforms |
| 5 | * |
| 6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> |
| 7 | * |
| 8 | * Copyright 2002 (c) Intel Corporation |
| 9 | * Copyright 2003-2004 (c) MontaVista, Software, Inc. |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. |
| 14 | */ |
| 15 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/mm.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/serial.h> |
| 20 | #include <linux/sched.h> |
| 21 | #include <linux/tty.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <linux/serial_core.h> |
| 24 | #include <linux/bootmem.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/bitops.h> |
| 27 | #include <linux/time.h> |
| 28 | #include <linux/timex.h> |
Kevin Hilman | 84904d0 | 2006-09-22 00:58:57 +0100 | [diff] [blame] | 29 | #include <linux/clocksource.h> |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 30 | #include <linux/clockchips.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
Milan Svoboda | e520a36 | 2006-12-01 11:36:41 +0100 | [diff] [blame] | 32 | #include <asm/arch/udc.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | #include <asm/hardware.h> |
| 34 | #include <asm/uaccess.h> |
| 35 | #include <asm/io.h> |
| 36 | #include <asm/pgtable.h> |
| 37 | #include <asm/page.h> |
| 38 | #include <asm/irq.h> |
| 39 | |
| 40 | #include <asm/mach/map.h> |
| 41 | #include <asm/mach/irq.h> |
| 42 | #include <asm/mach/time.h> |
| 43 | |
Kevin Hilman | f9a8ca1 | 2006-12-06 00:45:07 +0100 | [diff] [blame] | 44 | static int __init ixp4xx_clocksource_init(void); |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 45 | static int __init ixp4xx_clockevent_init(void); |
| 46 | static struct clock_event_device clockevent_ixp4xx; |
Kevin Hilman | f9a8ca1 | 2006-12-06 00:45:07 +0100 | [diff] [blame] | 47 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | /************************************************************************* |
| 49 | * IXP4xx chipset I/O mapping |
| 50 | *************************************************************************/ |
| 51 | static struct map_desc ixp4xx_io_desc[] __initdata = { |
| 52 | { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ |
| 53 | .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, |
Deepak Saxena | 87fe04b | 2005-10-28 15:18:59 +0100 | [diff] [blame] | 54 | .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | .length = IXP4XX_PERIPHERAL_REGION_SIZE, |
| 56 | .type = MT_DEVICE |
| 57 | }, { /* Expansion Bus Config Registers */ |
| 58 | .virtual = IXP4XX_EXP_CFG_BASE_VIRT, |
Deepak Saxena | 87fe04b | 2005-10-28 15:18:59 +0100 | [diff] [blame] | 59 | .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | .length = IXP4XX_EXP_CFG_REGION_SIZE, |
| 61 | .type = MT_DEVICE |
| 62 | }, { /* PCI Registers */ |
| 63 | .virtual = IXP4XX_PCI_CFG_BASE_VIRT, |
Deepak Saxena | 87fe04b | 2005-10-28 15:18:59 +0100 | [diff] [blame] | 64 | .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | .length = IXP4XX_PCI_CFG_REGION_SIZE, |
| 66 | .type = MT_DEVICE |
Deepak Saxena | 5932ae3 | 2005-06-24 20:54:35 +0100 | [diff] [blame] | 67 | }, |
| 68 | #ifdef CONFIG_DEBUG_LL |
| 69 | { /* Debug UART mapping */ |
| 70 | .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, |
Deepak Saxena | 87fe04b | 2005-10-28 15:18:59 +0100 | [diff] [blame] | 71 | .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), |
Deepak Saxena | 5932ae3 | 2005-06-24 20:54:35 +0100 | [diff] [blame] | 72 | .length = IXP4XX_DEBUG_UART_REGION_SIZE, |
| 73 | .type = MT_DEVICE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | } |
Deepak Saxena | 5932ae3 | 2005-06-24 20:54:35 +0100 | [diff] [blame] | 75 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | void __init ixp4xx_map_io(void) |
| 79 | { |
| 80 | iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); |
| 81 | } |
| 82 | |
| 83 | |
| 84 | /************************************************************************* |
| 85 | * IXP4xx chipset IRQ handling |
| 86 | * |
| 87 | * TODO: GPIO IRQs should be marked invalid until the user of the IRQ |
| 88 | * (be it PCI or something else) configures that GPIO line |
| 89 | * as an IRQ. |
| 90 | **************************************************************************/ |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 91 | enum ixp4xx_irq_type { |
| 92 | IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE |
| 93 | }; |
| 94 | |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 95 | /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */ |
| 96 | static unsigned long long ixp4xx_irq_edge = 0; |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * IRQ -> GPIO mapping table |
| 100 | */ |
Lennert Buytenhek | 6cc1b65 | 2006-04-20 21:24:38 +0100 | [diff] [blame] | 101 | static signed char irq2gpio[32] = { |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 102 | -1, -1, -1, -1, -1, -1, 0, 1, |
| 103 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 104 | -1, -1, -1, 2, 3, 4, 5, 6, |
| 105 | 7, 8, 9, 10, 11, 12, -1, -1, |
| 106 | }; |
| 107 | |
Milan Svoboda | 25735d1 | 2007-03-21 14:04:08 +0100 | [diff] [blame] | 108 | int gpio_to_irq(int gpio) |
| 109 | { |
| 110 | int irq; |
| 111 | |
| 112 | for (irq = 0; irq < 32; irq++) { |
| 113 | if (irq2gpio[irq] == gpio) |
| 114 | return irq; |
| 115 | } |
| 116 | return -EINVAL; |
| 117 | } |
| 118 | EXPORT_SYMBOL(gpio_to_irq); |
| 119 | |
| 120 | int irq_to_gpio(int irq) |
| 121 | { |
| 122 | int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL; |
| 123 | |
| 124 | if (gpio == -1) |
| 125 | return -EINVAL; |
| 126 | |
| 127 | return gpio; |
| 128 | } |
| 129 | EXPORT_SYMBOL(irq_to_gpio); |
| 130 | |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 131 | static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) |
| 132 | { |
| 133 | int line = irq2gpio[irq]; |
| 134 | u32 int_style; |
| 135 | enum ixp4xx_irq_type irq_type; |
| 136 | volatile u32 *int_reg; |
| 137 | |
| 138 | /* |
| 139 | * Only for GPIO IRQs |
| 140 | */ |
| 141 | if (line < 0) |
| 142 | return -EINVAL; |
| 143 | |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 144 | switch (type){ |
| 145 | case IRQT_BOTHEDGE: |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 146 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; |
| 147 | irq_type = IXP4XX_IRQ_EDGE; |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 148 | break; |
| 149 | case IRQT_RISING: |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 150 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; |
| 151 | irq_type = IXP4XX_IRQ_EDGE; |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 152 | break; |
| 153 | case IRQT_FALLING: |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 154 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; |
| 155 | irq_type = IXP4XX_IRQ_EDGE; |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 156 | break; |
| 157 | case IRQT_HIGH: |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 158 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; |
| 159 | irq_type = IXP4XX_IRQ_LEVEL; |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 160 | break; |
| 161 | case IRQT_LOW: |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 162 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; |
| 163 | irq_type = IXP4XX_IRQ_LEVEL; |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 164 | break; |
| 165 | default: |
David Vrabel | 6132f9e | 2005-09-26 19:52:56 +0100 | [diff] [blame] | 166 | return -EINVAL; |
Mårten Wikström | 06e4479 | 2006-02-22 22:27:23 +0000 | [diff] [blame] | 167 | } |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 168 | |
| 169 | if (irq_type == IXP4XX_IRQ_EDGE) |
| 170 | ixp4xx_irq_edge |= (1 << irq); |
| 171 | else |
| 172 | ixp4xx_irq_edge &= ~(1 << irq); |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 173 | |
| 174 | if (line >= 8) { /* pins 8-15 */ |
| 175 | line -= 8; |
| 176 | int_reg = IXP4XX_GPIO_GPIT2R; |
| 177 | } else { /* pins 0-7 */ |
| 178 | int_reg = IXP4XX_GPIO_GPIT1R; |
| 179 | } |
| 180 | |
| 181 | /* Clear the style for the appropriate pin */ |
| 182 | *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << |
| 183 | (line * IXP4XX_GPIO_STYLE_SIZE)); |
| 184 | |
Deepak Saxena | f7e8bbb8 | 2006-01-04 17:17:10 +0000 | [diff] [blame] | 185 | *IXP4XX_GPIO_GPISR = (1 << line); |
| 186 | |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 187 | /* Set the new style */ |
| 188 | *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); |
David Vrabel | 6132f9e | 2005-09-26 19:52:56 +0100 | [diff] [blame] | 189 | |
Alessandro Zummo | 73deb7d | 2006-03-20 17:10:12 +0000 | [diff] [blame] | 190 | /* Configure the line as an input */ |
Tim Harvey | 5c9b912 | 2007-07-14 11:15:05 +0200 | [diff] [blame] | 191 | gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN); |
Alessandro Zummo | 73deb7d | 2006-03-20 17:10:12 +0000 | [diff] [blame] | 192 | |
David Vrabel | 6132f9e | 2005-09-26 19:52:56 +0100 | [diff] [blame] | 193 | return 0; |
Deepak Saxena | bdf82b5 | 2005-08-29 22:46:30 +0100 | [diff] [blame] | 194 | } |
| 195 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | static void ixp4xx_irq_mask(unsigned int irq) |
| 197 | { |
Ruslan V. Sushko | 45fba08 | 2007-04-06 15:00:31 +0100 | [diff] [blame] | 198 | if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | *IXP4XX_ICMR2 &= ~(1 << (irq - 32)); |
| 200 | else |
| 201 | *IXP4XX_ICMR &= ~(1 << irq); |
| 202 | } |
| 203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | static void ixp4xx_irq_ack(unsigned int irq) |
| 205 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | int line = (irq < 32) ? irq2gpio[irq] : -1; |
| 207 | |
| 208 | if (line >= 0) |
Deepak Saxena | f7e8bbb8 | 2006-01-04 17:17:10 +0000 | [diff] [blame] | 209 | *IXP4XX_GPIO_GPISR = (1 << line); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /* |
| 213 | * Level triggered interrupts on GPIO lines can only be cleared when the |
| 214 | * interrupt condition disappears. |
| 215 | */ |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 216 | static void ixp4xx_irq_unmask(unsigned int irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 217 | { |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 218 | if (!(ixp4xx_irq_edge & (1 << irq))) |
| 219 | ixp4xx_irq_ack(irq); |
| 220 | |
Ruslan V. Sushko | 45fba08 | 2007-04-06 15:00:31 +0100 | [diff] [blame] | 221 | if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 222 | *IXP4XX_ICMR2 |= (1 << (irq - 32)); |
| 223 | else |
| 224 | *IXP4XX_ICMR |= (1 << irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 225 | } |
| 226 | |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 227 | static struct irq_chip ixp4xx_irq_chip = { |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 228 | .name = "IXP4xx", |
Russell King | 2be863c | 2005-09-06 23:13:17 +0100 | [diff] [blame] | 229 | .ack = ixp4xx_irq_ack, |
| 230 | .mask = ixp4xx_irq_mask, |
| 231 | .unmask = ixp4xx_irq_unmask, |
| 232 | .set_type = ixp4xx_set_irq_type, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | }; |
| 234 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | void __init ixp4xx_init_irq(void) |
| 236 | { |
| 237 | int i = 0; |
| 238 | |
| 239 | /* Route all sources to IRQ instead of FIQ */ |
| 240 | *IXP4XX_ICLR = 0x0; |
| 241 | |
| 242 | /* Disable all interrupt */ |
| 243 | *IXP4XX_ICMR = 0x0; |
| 244 | |
Ruslan V. Sushko | 45fba08 | 2007-04-06 15:00:31 +0100 | [diff] [blame] | 245 | if (cpu_is_ixp46x() || cpu_is_ixp43x()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 246 | /* Route upper 32 sources to IRQ instead of FIQ */ |
| 247 | *IXP4XX_ICLR2 = 0x00; |
| 248 | |
| 249 | /* Disable upper 32 interrupts */ |
| 250 | *IXP4XX_ICMR2 = 0x00; |
| 251 | } |
| 252 | |
| 253 | /* Default to all level triggered */ |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 254 | for(i = 0; i < NR_IRQS; i++) { |
| 255 | set_irq_chip(i, &ixp4xx_irq_chip); |
Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame] | 256 | set_irq_handler(i, handle_level_irq); |
Kevin Hilman | 984d115 | 2006-11-03 01:47:20 +0100 | [diff] [blame] | 257 | set_irq_flags(i, IRQF_VALID); |
| 258 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | |
| 262 | /************************************************************************* |
| 263 | * IXP4xx timer tick |
| 264 | * We use OS timer1 on the CPU for the timer tick and the timestamp |
| 265 | * counter as a source of real clock ticks to account for missed jiffies. |
| 266 | *************************************************************************/ |
| 267 | |
Linus Torvalds | 0cd61b6 | 2006-10-06 10:53:39 -0700 | [diff] [blame] | 268 | static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | { |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 270 | struct clock_event_device *evt = &clockevent_ixp4xx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | |
| 272 | /* Clear Pending Interrupt by writing '1' to it */ |
| 273 | *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; |
| 274 | |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 275 | evt->event_handler(evt); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | |
| 277 | return IRQ_HANDLED; |
| 278 | } |
| 279 | |
| 280 | static struct irqaction ixp4xx_timer_irq = { |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 281 | .name = "timer1", |
Bernhard Walle | b30faba | 2007-05-08 00:35:39 -0700 | [diff] [blame] | 282 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
Russell King | 09b8b5f | 2005-06-26 17:06:36 +0100 | [diff] [blame] | 283 | .handler = ixp4xx_timer_interrupt, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | }; |
| 285 | |
Michael-Luke Jones | 435c5da | 2007-05-23 22:38:45 +0100 | [diff] [blame] | 286 | void __init ixp4xx_timer_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | { |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 288 | /* Reset/disable counter */ |
| 289 | *IXP4XX_OSRT1 = 0; |
| 290 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | /* Clear Pending Interrupt by writing '1' to it */ |
| 292 | *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND; |
| 293 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | /* Reset time-stamp counter */ |
| 295 | *IXP4XX_OSTS = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
| 297 | /* Connect the interrupt handler and enable the interrupt */ |
| 298 | setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq); |
Kevin Hilman | f9a8ca1 | 2006-12-06 00:45:07 +0100 | [diff] [blame] | 299 | |
| 300 | ixp4xx_clocksource_init(); |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 301 | ixp4xx_clockevent_init(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | struct sys_timer ixp4xx_timer = { |
| 305 | .init = ixp4xx_timer_init, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | }; |
| 307 | |
Milan Svoboda | e520a36 | 2006-12-01 11:36:41 +0100 | [diff] [blame] | 308 | static struct pxa2xx_udc_mach_info ixp4xx_udc_info; |
| 309 | |
| 310 | void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info) |
| 311 | { |
| 312 | memcpy(&ixp4xx_udc_info, info, sizeof *info); |
| 313 | } |
| 314 | |
| 315 | static struct resource ixp4xx_udc_resources[] = { |
| 316 | [0] = { |
| 317 | .start = 0xc800b000, |
| 318 | .end = 0xc800bfff, |
| 319 | .flags = IORESOURCE_MEM, |
| 320 | }, |
| 321 | [1] = { |
| 322 | .start = IRQ_IXP4XX_USB, |
| 323 | .end = IRQ_IXP4XX_USB, |
| 324 | .flags = IORESOURCE_IRQ, |
| 325 | }, |
| 326 | }; |
| 327 | |
| 328 | /* |
Philipp Zabel | 7a85762 | 2008-06-22 23:36:39 +0100 | [diff] [blame^] | 329 | * USB device controller. The IXP4xx uses the same controller as PXA25X, |
Milan Svoboda | e520a36 | 2006-12-01 11:36:41 +0100 | [diff] [blame] | 330 | * so we just use the same device. |
| 331 | */ |
| 332 | static struct platform_device ixp4xx_udc_device = { |
Philipp Zabel | 7a85762 | 2008-06-22 23:36:39 +0100 | [diff] [blame^] | 333 | .name = "pxa25x-udc", |
Milan Svoboda | e520a36 | 2006-12-01 11:36:41 +0100 | [diff] [blame] | 334 | .id = -1, |
| 335 | .num_resources = 2, |
| 336 | .resource = ixp4xx_udc_resources, |
| 337 | .dev = { |
| 338 | .platform_data = &ixp4xx_udc_info, |
| 339 | }, |
| 340 | }; |
| 341 | |
| 342 | static struct platform_device *ixp4xx_devices[] __initdata = { |
| 343 | &ixp4xx_udc_device, |
| 344 | }; |
| 345 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 346 | static struct resource ixp46x_i2c_resources[] = { |
| 347 | [0] = { |
| 348 | .start = 0xc8011000, |
| 349 | .end = 0xc801101c, |
| 350 | .flags = IORESOURCE_MEM, |
| 351 | }, |
| 352 | [1] = { |
| 353 | .start = IRQ_IXP4XX_I2C, |
| 354 | .end = IRQ_IXP4XX_I2C, |
| 355 | .flags = IORESOURCE_IRQ |
| 356 | } |
| 357 | }; |
| 358 | |
| 359 | /* |
| 360 | * I2C controller. The IXP46x uses the same block as the IOP3xx, so |
| 361 | * we just use the same device name. |
| 362 | */ |
| 363 | static struct platform_device ixp46x_i2c_controller = { |
| 364 | .name = "IOP3xx-I2C", |
| 365 | .id = 0, |
| 366 | .num_resources = 2, |
| 367 | .resource = ixp46x_i2c_resources |
| 368 | }; |
| 369 | |
| 370 | static struct platform_device *ixp46x_devices[] __initdata = { |
| 371 | &ixp46x_i2c_controller |
| 372 | }; |
| 373 | |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 374 | unsigned long ixp4xx_exp_bus_size; |
David Vrabel | 1e74c89 | 2006-01-18 22:46:43 +0000 | [diff] [blame] | 375 | EXPORT_SYMBOL(ixp4xx_exp_bus_size); |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 376 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | void __init ixp4xx_sys_init(void) |
| 378 | { |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 379 | ixp4xx_exp_bus_size = SZ_16M; |
| 380 | |
Milan Svoboda | e520a36 | 2006-12-01 11:36:41 +0100 | [diff] [blame] | 381 | platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); |
| 382 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | if (cpu_is_ixp46x()) { |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 384 | int region; |
| 385 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | platform_add_devices(ixp46x_devices, |
| 387 | ARRAY_SIZE(ixp46x_devices)); |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 388 | |
| 389 | for (region = 0; region < 7; region++) { |
| 390 | if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) { |
| 391 | ixp4xx_exp_bus_size = SZ_32M; |
| 392 | break; |
| 393 | } |
| 394 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | } |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 396 | |
David Vrabel | 1e74c89 | 2006-01-18 22:46:43 +0000 | [diff] [blame] | 397 | printk("IXP4xx: Using %luMiB expansion bus window size\n", |
Deepak Saxena | 54e269e | 2006-01-05 20:59:29 +0000 | [diff] [blame] | 398 | ixp4xx_exp_bus_size >> 20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | } |
| 400 | |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 401 | /* |
| 402 | * clocksource |
| 403 | */ |
Kevin Hilman | 84904d0 | 2006-09-22 00:58:57 +0100 | [diff] [blame] | 404 | cycle_t ixp4xx_get_cycles(void) |
| 405 | { |
| 406 | return *IXP4XX_OSTS; |
| 407 | } |
| 408 | |
| 409 | static struct clocksource clocksource_ixp4xx = { |
| 410 | .name = "OSTS", |
| 411 | .rating = 200, |
| 412 | .read = ixp4xx_get_cycles, |
| 413 | .mask = CLOCKSOURCE_MASK(32), |
| 414 | .shift = 20, |
Thomas Gleixner | c66699a | 2007-02-16 01:27:37 -0800 | [diff] [blame] | 415 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
Kevin Hilman | 84904d0 | 2006-09-22 00:58:57 +0100 | [diff] [blame] | 416 | }; |
| 417 | |
| 418 | unsigned long ixp4xx_timer_freq = FREQ; |
| 419 | static int __init ixp4xx_clocksource_init(void) |
| 420 | { |
| 421 | clocksource_ixp4xx.mult = |
| 422 | clocksource_hz2mult(ixp4xx_timer_freq, |
| 423 | clocksource_ixp4xx.shift); |
| 424 | clocksource_register(&clocksource_ixp4xx); |
| 425 | |
| 426 | return 0; |
| 427 | } |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 428 | |
| 429 | /* |
| 430 | * clockevents |
| 431 | */ |
| 432 | static int ixp4xx_set_next_event(unsigned long evt, |
| 433 | struct clock_event_device *unused) |
| 434 | { |
| 435 | unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK; |
| 436 | |
| 437 | *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts; |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | static void ixp4xx_set_mode(enum clock_event_mode mode, |
| 443 | struct clock_event_device *evt) |
| 444 | { |
Kevin Hilman | 553876c | 2007-12-12 00:32:58 +0100 | [diff] [blame] | 445 | unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK; |
| 446 | unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK; |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 447 | |
| 448 | switch (mode) { |
| 449 | case CLOCK_EVT_MODE_PERIODIC: |
| 450 | osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK; |
| 451 | opts = IXP4XX_OST_ENABLE; |
| 452 | break; |
| 453 | case CLOCK_EVT_MODE_ONESHOT: |
| 454 | /* period set by 'set next_event' */ |
| 455 | osrt = 0; |
| 456 | opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT; |
| 457 | break; |
| 458 | case CLOCK_EVT_MODE_SHUTDOWN: |
Kevin Hilman | 553876c | 2007-12-12 00:32:58 +0100 | [diff] [blame] | 459 | opts &= ~IXP4XX_OST_ENABLE; |
| 460 | break; |
| 461 | case CLOCK_EVT_MODE_RESUME: |
| 462 | opts |= IXP4XX_OST_ENABLE; |
| 463 | break; |
Kevin Hilman | e32f150 | 2007-03-08 20:23:59 +0100 | [diff] [blame] | 464 | case CLOCK_EVT_MODE_UNUSED: |
| 465 | default: |
| 466 | osrt = opts = 0; |
| 467 | break; |
| 468 | } |
| 469 | |
| 470 | *IXP4XX_OSRT1 = osrt | opts; |
| 471 | } |
| 472 | |
| 473 | static struct clock_event_device clockevent_ixp4xx = { |
| 474 | .name = "ixp4xx timer1", |
| 475 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 476 | .rating = 200, |
| 477 | .shift = 24, |
| 478 | .set_mode = ixp4xx_set_mode, |
| 479 | .set_next_event = ixp4xx_set_next_event, |
| 480 | }; |
| 481 | |
| 482 | static int __init ixp4xx_clockevent_init(void) |
| 483 | { |
| 484 | clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC, |
| 485 | clockevent_ixp4xx.shift); |
| 486 | clockevent_ixp4xx.max_delta_ns = |
| 487 | clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx); |
| 488 | clockevent_ixp4xx.min_delta_ns = |
| 489 | clockevent_delta2ns(0xf, &clockevent_ixp4xx); |
| 490 | clockevent_ixp4xx.cpumask = cpumask_of_cpu(0); |
| 491 | |
| 492 | clockevents_register_device(&clockevent_ixp4xx); |
| 493 | return 0; |
| 494 | } |