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Arnd Bergmann67207b92005-11-15 15:53:48 -05001/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
Arnd Bergmann88ced032005-12-16 22:43:46 +010025#ifdef __KERNEL__
26
Arnd Bergmann67207b92005-11-15 15:53:48 -050027#include <linux/workqueue.h>
Jeremy Kerr1d640932006-06-19 20:33:19 +020028#include <linux/sysdev.h>
Arnd Bergmann67207b92005-11-15 15:53:48 -050029
Arnd Bergmannaeb01372006-01-04 20:31:32 +010030#define LS_SIZE (256 * 1024)
Mark Nutter5473af02005-11-15 15:53:49 -050031#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flags indicating progress during context switch. */
Arnd Bergmann8837d922006-01-04 20:31:28 +0100102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
Arnd Bergmann67207b92005-11-15 15:53:48 -0500104
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500105struct spu_context;
106struct spu_runqueue;
Ishizaki Kouc9868fe2007-02-02 16:45:33 +0900107struct device_node;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500108
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000109enum spu_utilization_state {
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000110 SPU_UTIL_USER,
Andre Detsch27ec41d2007-07-20 21:39:33 +0200111 SPU_UTIL_SYSTEM,
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000112 SPU_UTIL_IOWAIT,
Andre Detsch27ec41d2007-07-20 21:39:33 +0200113 SPU_UTIL_IDLE_LOADED,
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000114 SPU_UTIL_MAX
115};
116
Arnd Bergmann67207b92005-11-15 15:53:48 -0500117struct spu {
Jeremy Kerrc61c27d2006-07-12 15:39:54 +1000118 const char *name;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500119 unsigned long local_store_phys;
120 u8 *local_store;
Mark Nutter6df10a82006-03-23 00:00:12 +0100121 unsigned long problem_phys;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500122 struct spu_problem __iomem *problem;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500123 struct spu_priv2 __iomem *priv2;
Arnd Bergmannaa6d5b22007-07-20 21:39:44 +0200124 struct list_head cbe_list;
Christian Kraffte570beb2006-10-24 18:31:23 +0200125 struct list_head full_list;
Christoph Hellwig486acd42007-07-20 21:39:54 +0200126 enum { SPU_FREE, SPU_USED } alloc_state;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500127 int number;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000128 unsigned int irqs[3];
Arnd Bergmann67207b92005-11-15 15:53:48 -0500129 u32 node;
Mark Nutter5473af02005-11-15 15:53:49 -0500130 u64 flags;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500131 u64 dar;
132 u64 dsisr;
Masato Noguchib7f90a42007-09-07 18:28:27 +1000133 u64 class_0_pending;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500134 size_t ls_size;
135 unsigned int slb_replace;
136 struct mm_struct *mm;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500137 struct spu_context *ctx;
138 struct spu_runqueue *rq;
Arnd Bergmann2a911f02005-12-05 22:52:26 -0500139 unsigned long long timestamp;
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500140 pid_t pid;
Bob Nelson14748552007-07-20 21:39:53 +0200141 pid_t tgid;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500142 spinlock_t register_lock;
143
Arnd Bergmann8b3d6662005-11-15 15:53:52 -0500144 void (* wbox_callback)(struct spu *spu);
145 void (* ibox_callback)(struct spu *spu);
Arnd Bergmann51104592005-12-05 22:52:25 -0500146 void (* stop_callback)(struct spu *spu);
Arnd Bergmanna33a7d72006-03-23 00:00:11 +0100147 void (* mfc_callback)(struct spu *spu);
Arnd Bergmann9add11d2006-10-04 17:26:14 +0200148 void (* dma_callback)(struct spu *spu, int type);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500149
150 char irq_c0[8];
151 char irq_c1[8];
152 char irq_c2[8];
Jeremy Kerr1d640932006-06-19 20:33:19 +0200153
Ishizaki Kouc9868fe2007-02-02 16:45:33 +0900154 u64 spe_id;
155
Geoff Levande28b0032006-11-23 00:46:49 +0100156 void* pdata; /* platform private data */
Ishizaki Kouc9868fe2007-02-02 16:45:33 +0900157
158 /* of based platforms only */
159 struct device_node *devnode;
160
161 /* native only */
162 struct spu_priv1 __iomem *priv1;
163
164 /* beat only */
165 u64 shadow_int_mask_RW[3];
166
Jeremy Kerr1d640932006-06-19 20:33:19 +0200167 struct sys_device sysdev;
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000168
Arnd Bergmann9d92af62007-07-20 21:39:45 +0200169 int has_mem_affinity;
170 struct list_head aff_list;
171
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000172 struct {
173 /* protected by interrupt reentrancy */
Andre Detsch27ec41d2007-07-20 21:39:33 +0200174 enum spu_utilization_state util_state;
175 unsigned long long tstamp;
176 unsigned long long times[SPU_UTIL_MAX];
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000177 unsigned long long vol_ctx_switch;
178 unsigned long long invol_ctx_switch;
179 unsigned long long min_flt;
180 unsigned long long maj_flt;
181 unsigned long long hash_flt;
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000182 unsigned long long slb_flt;
183 unsigned long long class2_intr;
Christoph Hellwigfe2f8962007-06-29 10:58:07 +1000184 unsigned long long libassist;
Christoph Hellwige9f8a0b2007-06-29 10:58:03 +1000185 } stats;
Arnd Bergmann67207b92005-11-15 15:53:48 -0500186};
187
Arnd Bergmannaa6d5b22007-07-20 21:39:44 +0200188struct cbe_spu_info {
Christoph Hellwig486acd42007-07-20 21:39:54 +0200189 struct mutex list_mutex;
Arnd Bergmannaa6d5b22007-07-20 21:39:44 +0200190 struct list_head spus;
Arnd Bergmannaa6d5b22007-07-20 21:39:44 +0200191 int n_spus;
Christoph Hellwig486acd42007-07-20 21:39:54 +0200192 int nr_active;
Arnd Bergmannaa6d5b22007-07-20 21:39:44 +0200193 atomic_t reserved_spus;
194};
195
196extern struct cbe_spu_info cbe_spu_info[];
197
Christoph Hellwig486acd42007-07-20 21:39:54 +0200198void spu_init_channels(struct spu *spu);
Arnd Bergmann51104592005-12-05 22:52:25 -0500199int spu_irq_class_0_bottom(struct spu *spu);
200int spu_irq_class_1_bottom(struct spu *spu);
Arnd Bergmann2fb9d202006-01-05 14:05:29 +0000201void spu_irq_setaffinity(struct spu *spu, int cpu);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500202
Andre Detsch8d2655e2007-07-20 21:39:27 +0200203#ifdef CONFIG_KEXEC
204void crash_register_spus(struct list_head *list);
205#else
206static inline void crash_register_spus(struct list_head *list)
207{
208}
209#endif
210
Benjamin Herrenschmidt94b2a432007-03-10 00:05:37 +0100211extern void spu_invalidate_slbs(struct spu *spu);
212extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
213
214/* Calls from the memory management to the SPU */
215struct mm_struct;
216extern void spu_flush_all_slbs(struct mm_struct *mm);
217
Bob Nelson14748552007-07-20 21:39:53 +0200218/* This interface allows a profiler (e.g., OProfile) to store a ref
219 * to spu context information that it creates. This caching technique
220 * avoids the need to recreate this information after a save/restore operation.
221 *
222 * Assumes the caller has already incremented the ref count to
223 * profile_info; then spu_context_destroy must call kref_put
224 * on prof_info_kref.
225 */
226void spu_set_profile_private_kref(struct spu_context *ctx,
227 struct kref *prof_info_kref,
228 void ( * prof_info_release) (struct kref *kref));
229
230void *spu_get_profile_private_kref(struct spu_context *ctx);
231
Arnd Bergmann2dd14932006-03-23 00:00:09 +0100232/* system callbacks from the SPU */
233struct spu_syscall_block {
234 u64 nr_ret;
235 u64 parm[6];
236};
237extern long spu_sys_callback(struct spu_syscall_block *s);
238
239/* syscalls implemented in spufs */
Arnd Bergmannf1fa16e2006-12-19 15:32:42 +0100240struct file;
Jeremy Kerr98f06972007-09-19 14:38:12 +1000241struct spufs_calls {
Jeremy Kerr4ec3c3d2007-09-19 14:38:12 +1000242 long (*create_thread)(const char __user *name,
Arnd Bergmann8e68e2f2007-07-20 21:39:47 +0200243 unsigned int flags, mode_t mode,
244 struct file *neighbor);
Jeremy Kerr4ec3c3d2007-09-19 14:38:12 +1000245 long (*spu_run)(struct file *filp, __u32 __user *unpc,
Arnd Bergmann67207b92005-11-15 15:53:48 -0500246 __u32 __user *ustatus);
Michael Ellerman48cad412007-09-19 14:38:12 +1000247 int (*coredump_extra_notes_size)(void);
Michael Ellerman7af14432007-09-19 14:38:12 +1000248 int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
Dwayne Grant McConnellbf1ab972006-11-23 00:46:37 +0100249 struct module *owner;
250};
251
Arnd Bergmann9add11d2006-10-04 17:26:14 +0200252/* return status from spu_run, same as in libspe */
253#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
254#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
255#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
256#define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
257#define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
258
259/*
260 * Flags for sys_spu_create.
261 */
262#define SPU_CREATE_EVENTS_ENABLED 0x0001
Arnd Bergmann62632032006-10-04 17:26:15 +0200263#define SPU_CREATE_GANG 0x0002
Mark Nutter5737edd2006-10-24 18:31:16 +0200264#define SPU_CREATE_NOSCHED 0x0004
265#define SPU_CREATE_ISOLATE 0x0008
Arnd Bergmann8e68e2f2007-07-20 21:39:47 +0200266#define SPU_CREATE_AFFINITY_SPU 0x0010
267#define SPU_CREATE_AFFINITY_MEM 0x0020
Arnd Bergmann62632032006-10-04 17:26:15 +0200268
Arnd Bergmann8e68e2f2007-07-20 21:39:47 +0200269#define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */
Arnd Bergmann62632032006-10-04 17:26:15 +0200270
Arnd Bergmann9add11d2006-10-04 17:26:14 +0200271
Arnd Bergmann67207b92005-11-15 15:53:48 -0500272int register_spu_syscalls(struct spufs_calls *calls);
273void unregister_spu_syscalls(struct spufs_calls *calls);
Arnd Bergmann67207b92005-11-15 15:53:48 -0500274
Christian Kraffte570beb2006-10-24 18:31:23 +0200275int spu_add_sysdev_attr(struct sysdev_attribute *attr);
276void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
277
278int spu_add_sysdev_attr_group(struct attribute_group *attrs);
279void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
280
Arnd Bergmann67207b92005-11-15 15:53:48 -0500281
282/*
Arnd Bergmann86767272006-10-04 17:26:21 +0200283 * Notifier blocks:
284 *
285 * oprofile can get notified when a context switch is performed
286 * on an spe. The notifer function that gets called is passed
287 * a pointer to the SPU structure as well as the object-id that
288 * identifies the binary running on that SPU now.
289 *
290 * For a context save, the object-id that is passed is zero,
291 * identifying that the kernel will run from that moment on.
292 *
293 * For a context restore, the object-id is the value written
294 * to object-id spufs file from user space and the notifer
295 * function can assume that spu->ctx is valid.
296 */
Arnd Bergmannf1fa16e2006-12-19 15:32:42 +0100297struct notifier_block;
Arnd Bergmann86767272006-10-04 17:26:21 +0200298int spu_switch_event_register(struct notifier_block * n);
299int spu_switch_event_unregister(struct notifier_block * n);
300
301/*
Arnd Bergmann67207b92005-11-15 15:53:48 -0500302 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
303 */
304
305union mfc_tag_size_class_cmd {
306 struct {
307 u16 mfc_size;
308 u16 mfc_tag;
309 u8 pad;
310 u8 mfc_rclassid;
311 u16 mfc_cmd;
312 } u;
313 struct {
314 u32 mfc_size_tag32;
315 u32 mfc_class_cmd32;
316 } by32;
317 u64 all64;
318};
319
320struct mfc_cq_sr {
321 u64 mfc_cq_data0_RW;
322 u64 mfc_cq_data1_RW;
323 u64 mfc_cq_data2_RW;
324 u64 mfc_cq_data3_RW;
325};
326
327struct spu_problem {
328#define MS_SYNC_PENDING 1L
329 u64 spc_mssync_RW; /* 0x0000 */
330 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
331
332 /* DMA Area */
333 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
334 u32 mfc_lsa_W; /* 0x3004 */
335 u64 mfc_ea_W; /* 0x3008 */
336 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
337 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
338 u32 dma_qstatus_R; /* 0x3104 */
339 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
340 u32 dma_querytype_RW; /* 0x3204 */
341 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
342 u32 dma_querymask_RW; /* 0x321c */
343 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
344 u32 dma_tagstatus_R; /* 0x322c */
345#define DMA_TAGSTATUS_INTR_ANY 1u
346#define DMA_TAGSTATUS_INTR_ALL 2u
347 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
348
349 /* SPU Control Area */
350 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
351 u32 pu_mb_R; /* 0x4004 */
352 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
353 u32 spu_mb_W; /* 0x400c */
354 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
355 u32 mb_stat_R; /* 0x4014 */
356 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
357 u32 spu_runcntl_RW; /* 0x401c */
358#define SPU_RUNCNTL_STOP 0L
359#define SPU_RUNCNTL_RUNNABLE 1L
Mark Nutter5737edd2006-10-24 18:31:16 +0200360#define SPU_RUNCNTL_ISOLATE 2L
Arnd Bergmann67207b92005-11-15 15:53:48 -0500361 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
362 u32 spu_status_R; /* 0x4024 */
363#define SPU_STOP_STATUS_SHIFT 16
364#define SPU_STATUS_STOPPED 0x0
365#define SPU_STATUS_RUNNING 0x1
366#define SPU_STATUS_STOPPED_BY_STOP 0x2
367#define SPU_STATUS_STOPPED_BY_HALT 0x4
368#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
369#define SPU_STATUS_SINGLE_STEP 0x10
370#define SPU_STATUS_INVALID_INSTR 0x20
371#define SPU_STATUS_INVALID_CH 0x40
372#define SPU_STATUS_ISOLATED_STATE 0x80
arnd@arndb.deeb758ce2006-10-24 18:31:17 +0200373#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
374#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
Arnd Bergmann67207b92005-11-15 15:53:48 -0500375 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
376 u32 spu_spe_R; /* 0x402c */
377 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
378 u32 spu_npc_RW; /* 0x4034 */
379 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
380
381 /* Signal Notification Area */
382 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
383 u32 signal_notify1; /* 0x1400c */
384 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
385 u32 signal_notify2; /* 0x1c00c */
386} __attribute__ ((aligned(0x20000)));
387
388/* SPU Privilege 2 State Area */
389struct spu_priv2 {
390 /* MFC Registers */
391 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
392
393 /* SLB Management Registers */
394 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
395 u64 slb_index_W; /* 0x1108 */
396#define SLB_INDEX_MASK 0x7L
397 u64 slb_esid_RW; /* 0x1110 */
398 u64 slb_vsid_RW; /* 0x1118 */
399#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
400#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
401#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
402#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
403#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
404#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
405#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
406#define SLB_VSID_4K_PAGE (0x0 << 8)
407#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
408#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
409#define SLB_VSID_CLASS_MASK (0x1ull << 7)
410#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
411 u64 slb_invalidate_entry_W; /* 0x1120 */
412 u64 slb_invalidate_all_W; /* 0x1128 */
413 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
414
415 /* Context Save / Restore Area */
416 struct mfc_cq_sr spuq[16]; /* 0x2000 */
417 struct mfc_cq_sr puq[8]; /* 0x2200 */
418 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
419
420 /* MFC Control */
421 u64 mfc_control_RW; /* 0x3000 */
422#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
423#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
424#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
Kazunori Asayama49776d32007-07-20 21:39:30 +0200425#define MFC_CNTL_SUSPEND_MASK (1ull << 4)
Arnd Bergmann67207b92005-11-15 15:53:48 -0500426#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
427#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
428#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
429#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
430#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
431#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
432#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
433#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
434#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
435#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
436#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
437#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
438#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
439#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
440#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
441#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
442#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
443#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
444#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
445 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
446
447 /* Interrupt Mailbox */
448 u64 puint_mb_R; /* 0x4000 */
449 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
450
451 /* SPU Control */
452 u64 spu_privcntl_RW; /* 0x4040 */
453#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
454#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
455#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
456#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
457#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
458#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
459#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
460#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
461 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
462 u64 spu_lslr_RW; /* 0x4058 */
463 u64 spu_chnlcntptr_RW; /* 0x4060 */
464 u64 spu_chnlcnt_RW; /* 0x4068 */
465 u64 spu_chnldata_RW; /* 0x4070 */
466 u64 spu_cfg_RW; /* 0x4078 */
467 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
468
469 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
470 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
471 u64 spu_tag_status_query_RW; /* 0x5008 */
472#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
473#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
474 u64 spu_cmd_buf1_RW; /* 0x5010 */
475#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
476#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
477 u64 spu_cmd_buf2_RW; /* 0x5018 */
478#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
479#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
480#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
481 u64 spu_atomic_status_RW; /* 0x5020 */
482} __attribute__ ((aligned(0x20000)));
483
484/* SPU Privilege 1 State Area */
485struct spu_priv1 {
486 /* Control and Configuration Area */
487 u64 mfc_sr1_RW; /* 0x000 */
488#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
489#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
490#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
491#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
492#define MFC_STATE1_RELOCATE_MASK 0x10ull
493#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
Sebastian Siewiorbe703172007-06-29 10:57:50 +1000494#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
Arnd Bergmann67207b92005-11-15 15:53:48 -0500495 u64 mfc_lpid_RW; /* 0x008 */
496 u64 spu_idr_RW; /* 0x010 */
497 u64 mfc_vr_RO; /* 0x018 */
498#define MFC_VERSION_BITS (0xffff << 16)
499#define MFC_REVISION_BITS (0xffff)
500#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
501#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
502 u64 spu_vr_RO; /* 0x020 */
503#define SPU_VERSION_BITS (0xffff << 16)
504#define SPU_REVISION_BITS (0xffff)
505#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
506#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
507 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
508
Arnd Bergmann67207b92005-11-15 15:53:48 -0500509 /* Interrupt Area */
Arnd Bergmannf0831ac2006-01-04 20:31:30 +0100510 u64 int_mask_RW[3]; /* 0x100 */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500511#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
512#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
513#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
514#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
Arnd Bergmann67207b92005-11-15 15:53:48 -0500515#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
516#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
517#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
518#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
Arnd Bergmann67207b92005-11-15 15:53:48 -0500519#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
520#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
521#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
522#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
523 u8 pad_0x118_0x140[0x28]; /* 0x118 */
Arnd Bergmannf0831ac2006-01-04 20:31:30 +0100524 u64 int_stat_RW[3]; /* 0x140 */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500525 u8 pad_0x158_0x180[0x28]; /* 0x158 */
526 u64 int_route_RW; /* 0x180 */
527
528 /* Interrupt Routing */
529 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
530
531 /* Atomic Unit Control Area */
532 u64 mfc_atomic_flush_RW; /* 0x200 */
533#define mfc_atomic_flush_enable 0x1L
534 u8 pad_0x208_0x280[0x78]; /* 0x208 */
535 u64 resource_allocation_groupID_RW; /* 0x280 */
536 u64 resource_allocation_enable_RW; /* 0x288 */
537 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
538
539 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
540
541 u64 smf_sbi_signal_sel; /* 0x3c8 */
542#define smf_sbi_mask_lsb 56
543#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
544#define smf_sbi_mask (0x301LL << smf_sbi_shift)
545#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
546#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
547#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
548#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
549 u64 smf_ato_signal_sel; /* 0x3d0 */
550#define smf_ato_mask_lsb 35
551#define smf_ato_shift (63 - smf_ato_mask_lsb)
552#define smf_ato_mask (0x3LL << smf_ato_shift)
553#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
554#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
555 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
556
557 /* TLB Management Registers */
558 u64 mfc_sdr_RW; /* 0x400 */
559 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
560 u64 tlb_index_hint_RO; /* 0x500 */
561 u64 tlb_index_W; /* 0x508 */
562 u64 tlb_vpn_RW; /* 0x510 */
563 u64 tlb_rpn_RW; /* 0x518 */
564 u8 pad_0x520_0x540[0x20]; /* 0x520 */
565 u64 tlb_invalidate_entry_W; /* 0x540 */
566 u64 tlb_invalidate_all_W; /* 0x548 */
567 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
568
569 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
570 u64 smm_hid; /* 0x580 */
571#define PAGE_SIZE_MASK 0xf000000000000000ull
572#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
573 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
574
575 /* MFC Status/Control Area */
576 u64 mfc_accr_RW; /* 0x600 */
577#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
578#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
579#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
580#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
581 u8 pad_0x608_0x610[0x8]; /* 0x608 */
582 u64 mfc_dsisr_RW; /* 0x610 */
583#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
584#define MFC_DSISR_ACCESS_DENIED (1 << 27)
585#define MFC_DSISR_ATOMIC (1 << 26)
586#define MFC_DSISR_ACCESS_PUT (1 << 25)
587#define MFC_DSISR_ADDR_MATCH (1 << 22)
588#define MFC_DSISR_LS (1 << 17)
589#define MFC_DSISR_L (1 << 16)
590#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
591 u8 pad_0x618_0x620[0x8]; /* 0x618 */
592 u64 mfc_dar_RW; /* 0x620 */
593 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
594
595 /* Replacement Management Table (RMT) Area */
596 u64 rmt_index_RW; /* 0x700 */
597 u8 pad_0x708_0x710[0x8]; /* 0x708 */
598 u64 rmt_data1_RW; /* 0x710 */
599 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
600
601 /* Control/Configuration Registers */
602 u64 mfc_dsir_R; /* 0x800 */
603#define MFC_DSIR_Q (1 << 31)
604#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
605 u64 mfc_lsacr_RW; /* 0x808 */
606#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
607#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
608 u64 mfc_lscrr_R; /* 0x810 */
609#define MFC_LSCRR_Q (1 << 31)
610#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
611#define MFC_LSCRR_QI_SHIFT 32
612#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
613 u8 pad_0x818_0x820[0x8]; /* 0x818 */
614 u64 mfc_tclass_id_RW; /* 0x820 */
615#define MFC_TCLASS_ID_ENABLE (1L << 0L)
616#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
617#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
618#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
619#define MFC_TCLASS_QUOTA_2_SHIFT 8L
620#define MFC_TCLASS_QUOTA_1_SHIFT 16L
621#define MFC_TCLASS_QUOTA_0_SHIFT 24L
622#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
623#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
624#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
625 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
626
627 /* Real Mode Support Registers */
628 u64 mfc_rm_boundary; /* 0x900 */
629 u8 pad_0x908_0x938[0x30]; /* 0x908 */
630 u64 smf_dma_signal_sel; /* 0x938 */
631#define mfc_dma1_mask_lsb 41
632#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
633#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
634#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
635#define mfc_dma2_mask_lsb 43
636#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
637#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
638#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
639 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
640 u64 smm_signal_sel; /* 0xa38 */
641#define smm_sig_mask_lsb 12
642#define smm_sig_shift (63 - smm_sig_mask_lsb)
643#define smm_sig_mask (0x3LL << smm_sig_shift)
644#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
645#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
646 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
647
648 /* DMA Command Error Area */
649 u64 mfc_cer_R; /* 0xc00 */
650#define MFC_CER_Q (1 << 31)
651#define MFC_CER_SPU_QUEUE MFC_CER_Q
652 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
653
654 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
655 /* DMA Command Error Area */
656 u64 spu_ecc_cntl_RW; /* 0x1000 */
657#define SPU_ECC_CNTL_E (1ull << 0ull)
658#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
659#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
660#define SPU_ECC_CNTL_S (1ull << 1ull)
661#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
662#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
663#define SPU_ECC_CNTL_B (1ull << 2ull)
664#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
665#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
666#define SPU_ECC_CNTL_I_SHIFT 3ull
667#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
668#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
669#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
670#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
671#define SPU_ECC_CNTL_D (1ull << 5ull)
672#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
673#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
674 u64 spu_ecc_stat_RW; /* 0x1008 */
675#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
676#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
677#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
678#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
679#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
680#define SPU_ECC_DATA_ERROR (1ull << 5ul)
681#define SPU_ECC_DMA_ERROR (1ull << 6ul)
682#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
683 u64 spu_ecc_addr_RW; /* 0x1010 */
684 u64 spu_err_mask_RW; /* 0x1018 */
685#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
686#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
687 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
688
689 /* SPU Debug-Trace Bus (DTB) Selection Registers */
690 u64 spu_trig0_sel; /* 0x1028 */
691 u64 spu_trig1_sel; /* 0x1030 */
692 u64 spu_trig2_sel; /* 0x1038 */
693 u64 spu_trig3_sel; /* 0x1040 */
694 u64 spu_trace_sel; /* 0x1048 */
695#define spu_trace_sel_mask 0x1f1fLL
696#define spu_trace_sel_bus0_bits 0x1000LL
697#define spu_trace_sel_bus2_bits 0x0010LL
698 u64 spu_event0_sel; /* 0x1050 */
699 u64 spu_event1_sel; /* 0x1058 */
700 u64 spu_event2_sel; /* 0x1060 */
701 u64 spu_event3_sel; /* 0x1068 */
702 u64 spu_trace_cntl; /* 0x1070 */
703} __attribute__ ((aligned(0x2000)));
704
Arnd Bergmann88ced032005-12-16 22:43:46 +0100705#endif /* __KERNEL__ */
Arnd Bergmann67207b92005-11-15 15:53:48 -0500706#endif