Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef _ASM_M32R_SYSTEM_H |
| 2 | #define _ASM_M32R_SYSTEM_H |
| 3 | |
| 4 | /* |
| 5 | * This file is subject to the terms and conditions of the GNU General Public |
| 6 | * License. See the file "COPYING" in the main directory of this archive |
| 7 | * for more details. |
| 8 | * |
Hirokazu Takata | 4127272 | 2006-04-18 22:21:38 -0700 | [diff] [blame] | 9 | * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto |
| 10 | * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | */ |
| 12 | |
Al Viro | b4e1ded | 2007-05-15 20:37:00 +0100 | [diff] [blame] | 13 | #include <linux/compiler.h> |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 14 | #include <asm/assembler.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
| 16 | #ifdef __KERNEL__ |
| 17 | |
| 18 | /* |
| 19 | * switch_to(prev, next) should switch from task `prev' to `next' |
| 20 | * `prev' will never be the same as `next'. |
| 21 | * |
Ingo Molnar | 36c8b58 | 2006-07-03 00:25:41 -0700 | [diff] [blame] | 22 | * `next' and `prev' should be struct task_struct, but it isn't always defined |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | */ |
| 24 | |
Hirokazu Takata | 43c09ce | 2007-05-10 22:22:25 -0700 | [diff] [blame] | 25 | #if defined(CONFIG_FRAME_POINTER) || \ |
| 26 | !defined(CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER) |
| 27 | #define M32R_PUSH_FP " push fp\n" |
| 28 | #define M32R_POP_FP " pop fp\n" |
| 29 | #else |
| 30 | #define M32R_PUSH_FP "" |
| 31 | #define M32R_POP_FP "" |
| 32 | #endif |
| 33 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #define switch_to(prev, next, last) do { \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | __asm__ __volatile__ ( \ |
Hirokazu Takata | 4127272 | 2006-04-18 22:21:38 -0700 | [diff] [blame] | 36 | " seth lr, #high(1f) \n" \ |
| 37 | " or3 lr, lr, #low(1f) \n" \ |
| 38 | " st lr, @%4 ; store old LR \n" \ |
| 39 | " ld lr, @%5 ; load new LR \n" \ |
Hirokazu Takata | 43c09ce | 2007-05-10 22:22:25 -0700 | [diff] [blame] | 40 | M32R_PUSH_FP \ |
Hirokazu Takata | 4127272 | 2006-04-18 22:21:38 -0700 | [diff] [blame] | 41 | " st sp, @%2 ; store old SP \n" \ |
| 42 | " ld sp, @%3 ; load new SP \n" \ |
| 43 | " push %1 ; store `prev' on new stack \n" \ |
| 44 | " jmp lr \n" \ |
| 45 | " .fillinsn \n" \ |
| 46 | "1: \n" \ |
| 47 | " pop %0 ; restore `__last' from new stack \n" \ |
Hirokazu Takata | 43c09ce | 2007-05-10 22:22:25 -0700 | [diff] [blame] | 48 | M32R_POP_FP \ |
Hirokazu Takata | 4127272 | 2006-04-18 22:21:38 -0700 | [diff] [blame] | 49 | : "=r" (last) \ |
| 50 | : "0" (prev), \ |
| 51 | "r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \ |
| 52 | "r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \ |
| 53 | : "memory", "lr" \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | ); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | } while(0) |
| 56 | |
| 57 | /* Interrupt Control */ |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 58 | #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | #define local_irq_enable() \ |
| 60 | __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") |
| 61 | #define local_irq_disable() \ |
| 62 | __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 63 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | static inline void local_irq_enable(void) |
| 65 | { |
| 66 | unsigned long tmpreg; |
| 67 | __asm__ __volatile__( |
| 68 | "mvfc %0, psw; \n\t" |
| 69 | "or3 %0, %0, #0x0040; \n\t" |
| 70 | "mvtc %0, psw; \n\t" |
| 71 | : "=&r" (tmpreg) : : "cbit", "memory"); |
| 72 | } |
| 73 | |
| 74 | static inline void local_irq_disable(void) |
| 75 | { |
| 76 | unsigned long tmpreg0, tmpreg1; |
| 77 | __asm__ __volatile__( |
| 78 | "ld24 %0, #0 ; Use 32-bit insn. \n\t" |
| 79 | "mvfc %1, psw ; No interrupt can be accepted here. \n\t" |
| 80 | "mvtc %0, psw \n\t" |
| 81 | "and3 %0, %1, #0xffbf \n\t" |
| 82 | "mvtc %0, psw \n\t" |
| 83 | : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); |
| 84 | } |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 85 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | #define local_save_flags(x) \ |
| 88 | __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) |
| 89 | |
| 90 | #define local_irq_restore(x) \ |
| 91 | __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ |
| 92 | : "r" (x) : "cbit", "memory") |
| 93 | |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 94 | #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | #define local_irq_save(x) \ |
| 96 | __asm__ __volatile__( \ |
| 97 | "mvfc %0, psw; \n\t" \ |
| 98 | "clrpsw #0x40 -> nop; \n\t" \ |
| 99 | : "=r" (x) : /* no input */ : "memory") |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 100 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | #define local_irq_save(x) \ |
| 102 | ({ \ |
| 103 | unsigned long tmpreg; \ |
| 104 | __asm__ __volatile__( \ |
| 105 | "ld24 %1, #0 \n\t" \ |
| 106 | "mvfc %0, psw \n\t" \ |
| 107 | "mvtc %1, psw \n\t" \ |
| 108 | "and3 %1, %0, #0xffbf \n\t" \ |
| 109 | "mvtc %1, psw \n\t" \ |
| 110 | : "=r" (x), "=&r" (tmpreg) \ |
| 111 | : : "cbit", "memory"); \ |
| 112 | }) |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 113 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
| 115 | #define irqs_disabled() \ |
| 116 | ({ \ |
| 117 | unsigned long flags; \ |
| 118 | local_save_flags(flags); \ |
| 119 | !(flags & 0x40); \ |
| 120 | }) |
| 121 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | #define nop() __asm__ __volatile__ ("nop" : : ) |
| 123 | |
Mathieu Desnoyers | 7b631c2 | 2008-02-07 00:16:17 -0800 | [diff] [blame^] | 124 | #define xchg(ptr, x) \ |
| 125 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) |
| 126 | #define xchg_local(ptr, x) \ |
| 127 | ((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \ |
| 128 | sizeof(*(ptr)))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | #ifdef CONFIG_SMP |
| 131 | extern void __xchg_called_with_bad_pointer(void); |
| 132 | #endif |
| 133 | |
| 134 | #ifdef CONFIG_CHIP_M32700_TS1 |
| 135 | #define DCACHE_CLEAR(reg0, reg1, addr) \ |
| 136 | "seth "reg1", #high(dcache_dummy); \n\t" \ |
| 137 | "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \ |
| 138 | "lock "reg0", @"reg1"; \n\t" \ |
| 139 | "add3 "reg0", "addr", #0x1000; \n\t" \ |
| 140 | "ld "reg0", @"reg0"; \n\t" \ |
| 141 | "add3 "reg0", "addr", #0x2000; \n\t" \ |
| 142 | "ld "reg0", @"reg0"; \n\t" \ |
| 143 | "unlock "reg0", @"reg1"; \n\t" |
Robert P. J. Day | beb7dd8 | 2007-05-09 07:14:03 +0200 | [diff] [blame] | 144 | /* FIXME: This workaround code cannot handle kernel modules |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | * correctly under SMP environment. |
| 146 | */ |
| 147 | #else /* CONFIG_CHIP_M32700_TS1 */ |
| 148 | #define DCACHE_CLEAR(reg0, reg1, addr) |
| 149 | #endif /* CONFIG_CHIP_M32700_TS1 */ |
| 150 | |
Al Viro | b4e1ded | 2007-05-15 20:37:00 +0100 | [diff] [blame] | 151 | static __always_inline unsigned long |
Mathieu Desnoyers | 7b631c2 | 2008-02-07 00:16:17 -0800 | [diff] [blame^] | 152 | __xchg(unsigned long x, volatile void *ptr, int size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | { |
| 154 | unsigned long flags; |
| 155 | unsigned long tmp = 0; |
| 156 | |
| 157 | local_irq_save(flags); |
| 158 | |
| 159 | switch (size) { |
| 160 | #ifndef CONFIG_SMP |
| 161 | case 1: |
| 162 | __asm__ __volatile__ ( |
| 163 | "ldb %0, @%2 \n\t" |
| 164 | "stb %1, @%2 \n\t" |
| 165 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); |
| 166 | break; |
| 167 | case 2: |
| 168 | __asm__ __volatile__ ( |
| 169 | "ldh %0, @%2 \n\t" |
| 170 | "sth %1, @%2 \n\t" |
| 171 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); |
| 172 | break; |
| 173 | case 4: |
| 174 | __asm__ __volatile__ ( |
| 175 | "ld %0, @%2 \n\t" |
| 176 | "st %1, @%2 \n\t" |
| 177 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); |
| 178 | break; |
| 179 | #else /* CONFIG_SMP */ |
| 180 | case 4: |
| 181 | __asm__ __volatile__ ( |
| 182 | DCACHE_CLEAR("%0", "r4", "%2") |
| 183 | "lock %0, @%2; \n\t" |
| 184 | "unlock %1, @%2; \n\t" |
| 185 | : "=&r" (tmp) : "r" (x), "r" (ptr) |
| 186 | : "memory" |
| 187 | #ifdef CONFIG_CHIP_M32700_TS1 |
| 188 | , "r4" |
| 189 | #endif /* CONFIG_CHIP_M32700_TS1 */ |
| 190 | ); |
| 191 | break; |
| 192 | default: |
| 193 | __xchg_called_with_bad_pointer(); |
| 194 | #endif /* CONFIG_SMP */ |
| 195 | } |
| 196 | |
| 197 | local_irq_restore(flags); |
| 198 | |
| 199 | return (tmp); |
| 200 | } |
| 201 | |
Mathieu Desnoyers | 7b631c2 | 2008-02-07 00:16:17 -0800 | [diff] [blame^] | 202 | static __always_inline unsigned long |
| 203 | __xchg_local(unsigned long x, volatile void *ptr, int size) |
| 204 | { |
| 205 | unsigned long flags; |
| 206 | unsigned long tmp = 0; |
| 207 | |
| 208 | local_irq_save(flags); |
| 209 | |
| 210 | switch (size) { |
| 211 | case 1: |
| 212 | __asm__ __volatile__ ( |
| 213 | "ldb %0, @%2 \n\t" |
| 214 | "stb %1, @%2 \n\t" |
| 215 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); |
| 216 | break; |
| 217 | case 2: |
| 218 | __asm__ __volatile__ ( |
| 219 | "ldh %0, @%2 \n\t" |
| 220 | "sth %1, @%2 \n\t" |
| 221 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); |
| 222 | break; |
| 223 | case 4: |
| 224 | __asm__ __volatile__ ( |
| 225 | "ld %0, @%2 \n\t" |
| 226 | "st %1, @%2 \n\t" |
| 227 | : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory"); |
| 228 | break; |
| 229 | default: |
| 230 | __xchg_called_with_bad_pointer(); |
| 231 | } |
| 232 | |
| 233 | local_irq_restore(flags); |
| 234 | |
| 235 | return (tmp); |
| 236 | } |
| 237 | |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 238 | #define __HAVE_ARCH_CMPXCHG 1 |
| 239 | |
Hirokazu Takata | 4127272 | 2006-04-18 22:21:38 -0700 | [diff] [blame] | 240 | static inline unsigned long |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 241 | __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new) |
| 242 | { |
| 243 | unsigned long flags; |
| 244 | unsigned int retval; |
| 245 | |
| 246 | local_irq_save(flags); |
| 247 | __asm__ __volatile__ ( |
| 248 | DCACHE_CLEAR("%0", "r4", "%1") |
| 249 | M32R_LOCK" %0, @%1; \n" |
| 250 | " bne %0, %2, 1f; \n" |
| 251 | M32R_UNLOCK" %3, @%1; \n" |
| 252 | " bra 2f; \n" |
| 253 | " .fillinsn \n" |
| 254 | "1:" |
Hirokazu Takata | b04ec26 | 2006-02-20 18:28:15 -0800 | [diff] [blame] | 255 | M32R_UNLOCK" %0, @%1; \n" |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 256 | " .fillinsn \n" |
| 257 | "2:" |
| 258 | : "=&r" (retval) |
| 259 | : "r" (p), "r" (old), "r" (new) |
| 260 | : "cbit", "memory" |
| 261 | #ifdef CONFIG_CHIP_M32700_TS1 |
| 262 | , "r4" |
| 263 | #endif /* CONFIG_CHIP_M32700_TS1 */ |
| 264 | ); |
| 265 | local_irq_restore(flags); |
| 266 | |
| 267 | return retval; |
| 268 | } |
| 269 | |
Mathieu Desnoyers | 7b631c2 | 2008-02-07 00:16:17 -0800 | [diff] [blame^] | 270 | static inline unsigned long |
| 271 | __cmpxchg_local_u32(volatile unsigned int *p, unsigned int old, |
| 272 | unsigned int new) |
| 273 | { |
| 274 | unsigned long flags; |
| 275 | unsigned int retval; |
| 276 | |
| 277 | local_irq_save(flags); |
| 278 | __asm__ __volatile__ ( |
| 279 | DCACHE_CLEAR("%0", "r4", "%1") |
| 280 | "ld %0, @%1; \n" |
| 281 | " bne %0, %2, 1f; \n" |
| 282 | "st %3, @%1; \n" |
| 283 | " bra 2f; \n" |
| 284 | " .fillinsn \n" |
| 285 | "1:" |
| 286 | "st %0, @%1; \n" |
| 287 | " .fillinsn \n" |
| 288 | "2:" |
| 289 | : "=&r" (retval) |
| 290 | : "r" (p), "r" (old), "r" (new) |
| 291 | : "cbit", "memory" |
| 292 | #ifdef CONFIG_CHIP_M32700_TS1 |
| 293 | , "r4" |
| 294 | #endif /* CONFIG_CHIP_M32700_TS1 */ |
| 295 | ); |
| 296 | local_irq_restore(flags); |
| 297 | |
| 298 | return retval; |
| 299 | } |
| 300 | |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 301 | /* This function doesn't exist, so you'll get a linker error |
| 302 | if something tries to do an invalid cmpxchg(). */ |
| 303 | extern void __cmpxchg_called_with_bad_pointer(void); |
| 304 | |
Hirokazu Takata | 4127272 | 2006-04-18 22:21:38 -0700 | [diff] [blame] | 305 | static inline unsigned long |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 306 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) |
| 307 | { |
| 308 | switch (size) { |
| 309 | case 4: |
| 310 | return __cmpxchg_u32(ptr, old, new); |
| 311 | #if 0 /* we don't have __cmpxchg_u64 */ |
| 312 | case 8: |
| 313 | return __cmpxchg_u64(ptr, old, new); |
| 314 | #endif /* 0 */ |
| 315 | } |
| 316 | __cmpxchg_called_with_bad_pointer(); |
| 317 | return old; |
| 318 | } |
| 319 | |
Mathieu Desnoyers | 7b631c2 | 2008-02-07 00:16:17 -0800 | [diff] [blame^] | 320 | #define cmpxchg(ptr, o, n) \ |
| 321 | ((__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)(o), \ |
| 322 | (unsigned long)(n), sizeof(*(ptr)))) |
| 323 | |
| 324 | #include <asm-generic/cmpxchg-local.h> |
| 325 | |
| 326 | static inline unsigned long __cmpxchg_local(volatile void *ptr, |
| 327 | unsigned long old, |
| 328 | unsigned long new, int size) |
| 329 | { |
| 330 | switch (size) { |
| 331 | case 4: |
| 332 | return __cmpxchg_local_u32(ptr, old, new); |
| 333 | default: |
| 334 | return __cmpxchg_local_generic(ptr, old, new, size); |
| 335 | } |
| 336 | |
| 337 | return old; |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make |
| 342 | * them available. |
| 343 | */ |
| 344 | #define cmpxchg_local(ptr, o, n) \ |
| 345 | ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ |
| 346 | (unsigned long)(n), sizeof(*(ptr)))) |
| 347 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) |
Hirokazu Takata | 0332db5 | 2005-11-28 13:43:59 -0800 | [diff] [blame] | 348 | |
| 349 | #endif /* __KERNEL__ */ |
| 350 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | /* |
| 352 | * Memory barrier. |
| 353 | * |
| 354 | * mb() prevents loads and stores being reordered across this point. |
| 355 | * rmb() prevents loads being reordered across this point. |
| 356 | * wmb() prevents stores being reordered across this point. |
| 357 | */ |
| 358 | #define mb() barrier() |
| 359 | #define rmb() mb() |
| 360 | #define wmb() mb() |
| 361 | |
| 362 | /** |
| 363 | * read_barrier_depends - Flush all pending reads that subsequents reads |
| 364 | * depend on. |
| 365 | * |
| 366 | * No data-dependent reads from memory-like regions are ever reordered |
| 367 | * over this barrier. All reads preceding this primitive are guaranteed |
| 368 | * to access memory (but not necessarily other CPUs' caches) before any |
| 369 | * reads following this primitive that depend on the data return by |
| 370 | * any of the preceding reads. This primitive is much lighter weight than |
| 371 | * rmb() on most CPUs, and is never heavier weight than is |
| 372 | * rmb(). |
| 373 | * |
| 374 | * These ordering constraints are respected by both the local CPU |
| 375 | * and the compiler. |
| 376 | * |
| 377 | * Ordering is not guaranteed by anything other than these primitives, |
| 378 | * not even by data dependencies. See the documentation for |
| 379 | * memory_barrier() for examples and URLs to more information. |
| 380 | * |
| 381 | * For example, the following code would force ordering (the initial |
| 382 | * value of "a" is zero, "b" is one, and "p" is "&a"): |
| 383 | * |
| 384 | * <programlisting> |
| 385 | * CPU 0 CPU 1 |
| 386 | * |
| 387 | * b = 2; |
| 388 | * memory_barrier(); |
| 389 | * p = &b; q = p; |
| 390 | * read_barrier_depends(); |
| 391 | * d = *q; |
| 392 | * </programlisting> |
| 393 | * |
| 394 | * |
| 395 | * because the read of "*q" depends on the read of "p" and these |
| 396 | * two reads are separated by a read_barrier_depends(). However, |
| 397 | * the following code, with the same initial values for "a" and "b": |
| 398 | * |
| 399 | * <programlisting> |
| 400 | * CPU 0 CPU 1 |
| 401 | * |
| 402 | * a = 2; |
| 403 | * memory_barrier(); |
| 404 | * b = 3; y = b; |
| 405 | * read_barrier_depends(); |
| 406 | * x = a; |
| 407 | * </programlisting> |
| 408 | * |
| 409 | * does not enforce ordering, since there is no data dependency between |
| 410 | * the read of "a" and the read of "b". Therefore, on some CPUs, such |
| 411 | * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() |
Andreas Mohr | d6e05ed | 2006-06-26 18:35:02 +0200 | [diff] [blame] | 412 | * in cases like this where there are no data dependencies. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | **/ |
| 414 | |
| 415 | #define read_barrier_depends() do { } while (0) |
| 416 | |
| 417 | #ifdef CONFIG_SMP |
| 418 | #define smp_mb() mb() |
| 419 | #define smp_rmb() rmb() |
| 420 | #define smp_wmb() wmb() |
| 421 | #define smp_read_barrier_depends() read_barrier_depends() |
Hirokazu Takata | a27f311 | 2006-09-27 01:50:24 -0700 | [diff] [blame] | 422 | #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | #else |
| 424 | #define smp_mb() barrier() |
| 425 | #define smp_rmb() barrier() |
| 426 | #define smp_wmb() barrier() |
| 427 | #define smp_read_barrier_depends() do { } while (0) |
Hirokazu Takata | a27f311 | 2006-09-27 01:50:24 -0700 | [diff] [blame] | 428 | #define set_mb(var, value) do { var = value; barrier(); } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | #endif |
| 430 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | #define arch_align_stack(x) (x) |
| 432 | |
Hirokazu Takata | fabb626 | 2007-02-10 01:43:40 -0800 | [diff] [blame] | 433 | #endif /* _ASM_M32R_SYSTEM_H */ |