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gerrit-public.fairphone.software / kernel / msm / 7d061402590efc37d553a9155dbf41277675c179 / . / drivers / scsi / mpt2sas / mpi / mpi2.h
blob: 8be75e65f76301a95fe6f7f77a4ad82c4cc92ce3 [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
Kashyap, Desai31b7f2e2010-03-17 16:28:04 +0530[diff] [blame]2 * Copyright (c) 2000-2010 LSI Corporation.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame^]11 * mpi2.h Version: 02.00.16
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
58 * Index register.
59 * Added function code for Host Based Discovery Action.
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame^]64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]66 * --------------------------------------------------------------------------
67 */
68
69#ifndef MPI2_H
70#define MPI2_H
71
72
73/*****************************************************************************
74*
75* MPI Version Definitions
76*
77*****************************************************************************/
78
79#define MPI2_VERSION_MAJOR (0x02)
80#define MPI2_VERSION_MINOR (0x00)
81#define MPI2_VERSION_MAJOR_MASK (0xFF00)
82#define MPI2_VERSION_MAJOR_SHIFT (8)
83#define MPI2_VERSION_MINOR_MASK (0x00FF)
84#define MPI2_VERSION_MINOR_SHIFT (0)
85#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
86 MPI2_VERSION_MINOR)
87
88#define MPI2_VERSION_02_00 (0x0200)
89
90/* versioning for this MPI header set */
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame^]91#define MPI2_HEADER_VERSION_UNIT (0x10)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]92#define MPI2_HEADER_VERSION_DEV (0x00)
93#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
94#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
95#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
96#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
97#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
98
99
100/*****************************************************************************
101*
102* IOC State Definitions
103*
104*****************************************************************************/
105
106#define MPI2_IOC_STATE_RESET (0x00000000)
107#define MPI2_IOC_STATE_READY (0x10000000)
108#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
109#define MPI2_IOC_STATE_FAULT (0x40000000)
110
111#define MPI2_IOC_STATE_MASK (0xF0000000)
112#define MPI2_IOC_STATE_SHIFT (28)
113
114/* Fault state range for prodcut specific codes */
115#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
116#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
117
118
119/*****************************************************************************
120*
121* System Interface Register Definitions
122*
123*****************************************************************************/
124
125typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
126{
127 U32 Doorbell; /* 0x00 */
128 U32 WriteSequence; /* 0x04 */
129 U32 HostDiagnostic; /* 0x08 */
130 U32 Reserved1; /* 0x0C */
131 U32 DiagRWData; /* 0x10 */
132 U32 DiagRWAddressLow; /* 0x14 */
133 U32 DiagRWAddressHigh; /* 0x18 */
134 U32 Reserved2[5]; /* 0x1C */
135 U32 HostInterruptStatus; /* 0x30 */
136 U32 HostInterruptMask; /* 0x34 */
137 U32 DCRData; /* 0x38 */
138 U32 DCRAddress; /* 0x3C */
139 U32 Reserved3[2]; /* 0x40 */
140 U32 ReplyFreeHostIndex; /* 0x48 */
141 U32 Reserved4[8]; /* 0x4C */
142 U32 ReplyPostHostIndex; /* 0x6C */
143 U32 Reserved5; /* 0x70 */
144 U32 HCBSize; /* 0x74 */
145 U32 HCBAddressLow; /* 0x78 */
146 U32 HCBAddressHigh; /* 0x7C */
147 U32 Reserved6[16]; /* 0x80 */
148 U32 RequestDescriptorPostLow; /* 0xC0 */
149 U32 RequestDescriptorPostHigh; /* 0xC4 */
150 U32 Reserved7[14]; /* 0xC8 */
151} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
152 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
153
154/*
155 * Defines for working with the Doorbell register.
156 */
157#define MPI2_DOORBELL_OFFSET (0x00000000)
158
159/* IOC --> System values */
160#define MPI2_DOORBELL_USED (0x08000000)
161#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
162#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
163#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
164#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
165
166/* System --> IOC values */
167#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
168#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
169#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
170#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
171
172
173/*
174 * Defines for the WriteSequence register
175 */
176#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
177#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
178#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
179#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
180#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
181#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
182#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
183#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
184#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
185
186/*
187 * Defines for the HostDiagnostic register
188 */
189#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
190
191#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
192#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
193#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
194
195#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
196#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
197#define MPI2_DIAG_HCB_MODE (0x00000100)
198#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
199#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
200#define MPI2_DIAG_RESET_HISTORY (0x00000020)
201#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
202#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
203#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
204
205/*
206 * Offsets for DiagRWData and address
207 */
208#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
209#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
210#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
211
212/*
213 * Defines for the HostInterruptStatus register
214 */
215#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
216#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
217#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
218#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
219#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
220#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
221#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
222
223/*
224 * Defines for the HostInterruptMask register
225 */
226#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
227#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
228#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
229#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
230#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
231#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
232
233/*
234 * Offsets for DCRData and address
235 */
236#define MPI2_DCR_DATA_OFFSET (0x00000038)
237#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
238
239/*
240 * Offset for the Reply Free Queue
241 */
242#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
243
244/*
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]245 * Defines for the Reply Descriptor Post Queue
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]246 */
247#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]248#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
249#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
250#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]251
252/*
253 * Defines for the HCBSize and address
254 */
255#define MPI2_HCB_SIZE_OFFSET (0x00000074)
256#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
257#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
258
259#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
260#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
261
262/*
263 * Offsets for the Request Queue
264 */
265#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
266#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
267
268
269/*****************************************************************************
270*
271* Message Descriptors
272*
273*****************************************************************************/
274
275/* Request Descriptors */
276
277/* Default Request Descriptor */
278typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
279{
280 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]281 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]282 U16 SMID; /* 0x02 */
283 U16 LMID; /* 0x04 */
284 U16 DescriptorTypeDependent; /* 0x06 */
285} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
286 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
287 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
288
289/* defines for the RequestFlags field */
290#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
291#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
292#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
293#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
294#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]295#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]296
297#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
298
299
300/* High Priority Request Descriptor */
301typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
302{
303 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]304 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]305 U16 SMID; /* 0x02 */
306 U16 LMID; /* 0x04 */
307 U16 Reserved1; /* 0x06 */
308} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
309 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
310 Mpi2HighPriorityRequestDescriptor_t,
311 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
312
313
314/* SCSI IO Request Descriptor */
315typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
316{
317 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]318 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]319 U16 SMID; /* 0x02 */
320 U16 LMID; /* 0x04 */
321 U16 DevHandle; /* 0x06 */
322} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
323 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
324 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
325
326
327/* SCSI Target Request Descriptor */
328typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
329{
330 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]331 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]332 U16 SMID; /* 0x02 */
333 U16 LMID; /* 0x04 */
334 U16 IoIndex; /* 0x06 */
335} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
336 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
337 Mpi2SCSITargetRequestDescriptor_t,
338 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
339
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]340
341/* RAID Accelerator Request Descriptor */
342typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
343 U8 RequestFlags; /* 0x00 */
344 U8 MSIxIndex; /* 0x01 */
345 U16 SMID; /* 0x02 */
346 U16 LMID; /* 0x04 */
347 U16 Reserved; /* 0x06 */
348} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
349 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
350 Mpi2RAIDAcceleratorRequestDescriptor_t,
351 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
352
353
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]354/* union of Request Descriptors */
355typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
356{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]357 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
358 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
359 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
360 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
361 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
362 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]363} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
364 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
365
366
367/* Reply Descriptors */
368
369/* Default Reply Descriptor */
370typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
371{
372 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]373 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]374 U16 DescriptorTypeDependent1; /* 0x02 */
375 U32 DescriptorTypeDependent2; /* 0x04 */
376} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
377 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
378
379/* defines for the ReplyFlags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]380#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
381#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
382#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
383#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
384#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
385#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
386#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]387
388/* values for marking a reply descriptor as unused */
389#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
390#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
391
392/* Address Reply Descriptor */
393typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
394{
395 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]396 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]397 U16 SMID; /* 0x02 */
398 U32 ReplyFrameAddress; /* 0x04 */
399} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
400 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
401
402#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
403
404
405/* SCSI IO Success Reply Descriptor */
406typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
407{
408 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]409 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]410 U16 SMID; /* 0x02 */
411 U16 TaskTag; /* 0x04 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]412 U16 Reserved1; /* 0x06 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]413} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
414 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
415 Mpi2SCSIIOSuccessReplyDescriptor_t,
416 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
417
418
419/* TargetAssist Success Reply Descriptor */
420typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
421{
422 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]423 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]424 U16 SMID; /* 0x02 */
425 U8 SequenceNumber; /* 0x04 */
426 U8 Reserved1; /* 0x05 */
427 U16 IoIndex; /* 0x06 */
428} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
429 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
430 Mpi2TargetAssistSuccessReplyDescriptor_t,
431 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
432
433
434/* Target Command Buffer Reply Descriptor */
435typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
436{
437 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]438 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]439 U8 VP_ID; /* 0x02 */
440 U8 Flags; /* 0x03 */
441 U16 InitiatorDevHandle; /* 0x04 */
442 U16 IoIndex; /* 0x06 */
443} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
444 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
445 Mpi2TargetCommandBufferReplyDescriptor_t,
446 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
447
448/* defines for Flags field */
449#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
450
451
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]452/* RAID Accelerator Success Reply Descriptor */
453typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
454 U8 ReplyFlags; /* 0x00 */
455 U8 MSIxIndex; /* 0x01 */
456 U16 SMID; /* 0x02 */
457 U32 Reserved; /* 0x04 */
458} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
459 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
460 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
461 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
462
463
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]464/* union of Reply Descriptors */
465typedef union _MPI2_REPLY_DESCRIPTORS_UNION
466{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]467 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
468 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
469 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
470 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
471 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
472 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
473 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]474} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
475 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
476
477
478
479/*****************************************************************************
480*
481* Message Functions
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]482*
483*****************************************************************************/
484
485#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
486#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
487#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
488#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
489#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
490#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
491#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
492#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
493#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
494#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
495#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
496#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
497#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
498#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
499#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
500#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
501#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
502#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
503#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
504#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
505#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
506#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
507#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
508#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
509#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]510#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]511/* Host Based Discovery Action */
512#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]513/* Power Management Control */
514#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
515/* beginning of product-specific range */
516#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
517/* end of product-specific range */
518#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
519
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]520
521
522
523/* Doorbell functions */
524#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]525#define MPI2_FUNCTION_HANDSHAKE (0x42)
526
527
528/*****************************************************************************
529*
530* IOC Status Values
531*
532*****************************************************************************/
533
534/* mask for IOCStatus status value */
535#define MPI2_IOCSTATUS_MASK (0x7FFF)
536
537/****************************************************************************
538* Common IOCStatus values for all replies
539****************************************************************************/
540
541#define MPI2_IOCSTATUS_SUCCESS (0x0000)
542#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
543#define MPI2_IOCSTATUS_BUSY (0x0002)
544#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
545#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
546#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
547#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
548#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
549#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
550#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
551
552/****************************************************************************
553* Config IOCStatus values
554****************************************************************************/
555
556#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
557#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
558#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
559#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
560#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
561#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
562
563/****************************************************************************
564* SCSI IO Reply
565****************************************************************************/
566
567#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
568#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
569#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
570#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
571#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
572#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
573#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
574#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
575#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
576#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
577#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
578#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
579
580/****************************************************************************
581* For use by SCSI Initiator and SCSI Target end-to-end data protection
582****************************************************************************/
583
584#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
585#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
586#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
587
588/****************************************************************************
589* SCSI Target values
590****************************************************************************/
591
592#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
593#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
594#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
595#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
596#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
597#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
598#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
599#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
600#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
601#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
602
603/****************************************************************************
604* Serial Attached SCSI values
605****************************************************************************/
606
607#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
608#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
609
610/****************************************************************************
611* Diagnostic Buffer Post / Diagnostic Release values
612****************************************************************************/
613
614#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
615
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]616/****************************************************************************
617* RAID Accelerator values
618****************************************************************************/
619
620#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]621
622/****************************************************************************
623* IOCStatus flag to indicate that log info is available
624****************************************************************************/
625
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]626#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]627
628/****************************************************************************
629* IOCLogInfo Types
630****************************************************************************/
631
632#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
633#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
634#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
635#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
636#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
637#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
638#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
639#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
640
641
642/*****************************************************************************
643*
644* Standard Message Structures
645*
646*****************************************************************************/
647
648/****************************************************************************
649* Request Message Header for all request messages
650****************************************************************************/
651
652typedef struct _MPI2_REQUEST_HEADER
653{
654 U16 FunctionDependent1; /* 0x00 */
655 U8 ChainOffset; /* 0x02 */
656 U8 Function; /* 0x03 */
657 U16 FunctionDependent2; /* 0x04 */
658 U8 FunctionDependent3; /* 0x06 */
659 U8 MsgFlags; /* 0x07 */
660 U8 VP_ID; /* 0x08 */
661 U8 VF_ID; /* 0x09 */
662 U16 Reserved1; /* 0x0A */
663} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
664 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
665
666
667/****************************************************************************
668* Default Reply
669****************************************************************************/
670
671typedef struct _MPI2_DEFAULT_REPLY
672{
673 U16 FunctionDependent1; /* 0x00 */
674 U8 MsgLength; /* 0x02 */
675 U8 Function; /* 0x03 */
676 U16 FunctionDependent2; /* 0x04 */
677 U8 FunctionDependent3; /* 0x06 */
678 U8 MsgFlags; /* 0x07 */
679 U8 VP_ID; /* 0x08 */
680 U8 VF_ID; /* 0x09 */
681 U16 Reserved1; /* 0x0A */
682 U16 FunctionDependent5; /* 0x0C */
683 U16 IOCStatus; /* 0x0E */
684 U32 IOCLogInfo; /* 0x10 */
685} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
686 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
687
688
689/* common version structure/union used in messages and configuration pages */
690
691typedef struct _MPI2_VERSION_STRUCT
692{
693 U8 Dev; /* 0x00 */
694 U8 Unit; /* 0x01 */
695 U8 Minor; /* 0x02 */
696 U8 Major; /* 0x03 */
697} MPI2_VERSION_STRUCT;
698
699typedef union _MPI2_VERSION_UNION
700{
701 MPI2_VERSION_STRUCT Struct;
702 U32 Word;
703} MPI2_VERSION_UNION;
704
705
706/* LUN field defines, common to many structures */
707#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
708#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
709#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
710#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
711#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
712#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
713
714
715/*****************************************************************************
716*
717* Fusion-MPT MPI Scatter Gather Elements
718*
719*****************************************************************************/
720
721/****************************************************************************
722* MPI Simple Element structures
723****************************************************************************/
724
725typedef struct _MPI2_SGE_SIMPLE32
726{
727 U32 FlagsLength;
728 U32 Address;
729} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
730 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
731
732typedef struct _MPI2_SGE_SIMPLE64
733{
734 U32 FlagsLength;
735 U64 Address;
736} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
737 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
738
739typedef struct _MPI2_SGE_SIMPLE_UNION
740{
741 U32 FlagsLength;
742 union
743 {
744 U32 Address32;
745 U64 Address64;
746 } u;
747} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
748 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
749
750
751/****************************************************************************
752* MPI Chain Element structures
753****************************************************************************/
754
755typedef struct _MPI2_SGE_CHAIN32
756{
757 U16 Length;
758 U8 NextChainOffset;
759 U8 Flags;
760 U32 Address;
761} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
762 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
763
764typedef struct _MPI2_SGE_CHAIN64
765{
766 U16 Length;
767 U8 NextChainOffset;
768 U8 Flags;
769 U64 Address;
770} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
771 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
772
773typedef struct _MPI2_SGE_CHAIN_UNION
774{
775 U16 Length;
776 U8 NextChainOffset;
777 U8 Flags;
778 union
779 {
780 U32 Address32;
781 U64 Address64;
782 } u;
783} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
784 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
785
786
787/****************************************************************************
788* MPI Transaction Context Element structures
789****************************************************************************/
790
791typedef struct _MPI2_SGE_TRANSACTION32
792{
793 U8 Reserved;
794 U8 ContextSize;
795 U8 DetailsLength;
796 U8 Flags;
797 U32 TransactionContext[1];
798 U32 TransactionDetails[1];
799} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
800 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
801
802typedef struct _MPI2_SGE_TRANSACTION64
803{
804 U8 Reserved;
805 U8 ContextSize;
806 U8 DetailsLength;
807 U8 Flags;
808 U32 TransactionContext[2];
809 U32 TransactionDetails[1];
810} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
811 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
812
813typedef struct _MPI2_SGE_TRANSACTION96
814{
815 U8 Reserved;
816 U8 ContextSize;
817 U8 DetailsLength;
818 U8 Flags;
819 U32 TransactionContext[3];
820 U32 TransactionDetails[1];
821} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
822 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
823
824typedef struct _MPI2_SGE_TRANSACTION128
825{
826 U8 Reserved;
827 U8 ContextSize;
828 U8 DetailsLength;
829 U8 Flags;
830 U32 TransactionContext[4];
831 U32 TransactionDetails[1];
832} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
833 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
834
835typedef struct _MPI2_SGE_TRANSACTION_UNION
836{
837 U8 Reserved;
838 U8 ContextSize;
839 U8 DetailsLength;
840 U8 Flags;
841 union
842 {
843 U32 TransactionContext32[1];
844 U32 TransactionContext64[2];
845 U32 TransactionContext96[3];
846 U32 TransactionContext128[4];
847 } u;
848 U32 TransactionDetails[1];
849} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
850 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
851
852
853/****************************************************************************
854* MPI SGE union for IO SGL's
855****************************************************************************/
856
857typedef struct _MPI2_MPI_SGE_IO_UNION
858{
859 union
860 {
861 MPI2_SGE_SIMPLE_UNION Simple;
862 MPI2_SGE_CHAIN_UNION Chain;
863 } u;
864} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
865 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
866
867
868/****************************************************************************
869* MPI SGE union for SGL's with Simple and Transaction elements
870****************************************************************************/
871
872typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
873{
874 union
875 {
876 MPI2_SGE_SIMPLE_UNION Simple;
877 MPI2_SGE_TRANSACTION_UNION Transaction;
878 } u;
879} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
880 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
881
882
883/****************************************************************************
884* All MPI SGE types union
885****************************************************************************/
886
887typedef struct _MPI2_MPI_SGE_UNION
888{
889 union
890 {
891 MPI2_SGE_SIMPLE_UNION Simple;
892 MPI2_SGE_CHAIN_UNION Chain;
893 MPI2_SGE_TRANSACTION_UNION Transaction;
894 } u;
895} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
896 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
897
898
899/****************************************************************************
900* MPI SGE field definition and masks
901****************************************************************************/
902
903/* Flags field bit definitions */
904
905#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
906#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
907#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
908#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
909#define MPI2_SGE_FLAGS_DIRECTION (0x04)
910#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
911#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
912
913#define MPI2_SGE_FLAGS_SHIFT (24)
914
915#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
916#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
917
918/* Element Type */
919
920#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
921#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
922#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
923#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
924
925/* Address location */
926
927#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
928
929/* Direction */
930
931#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
932#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
933
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame^]934#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
935#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
936
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]937/* Address Size */
938
939#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
940#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
941
942/* Context Size */
943
944#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
945#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
946#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
947#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
948
949#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
950#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
951
952/****************************************************************************
953* MPI SGE operation Macros
954****************************************************************************/
955
956/* SIMPLE FlagsLength manipulations... */
957#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
958#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
959#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
960#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
961
962#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
963
964#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
965#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
966#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
967
968/* CAUTION - The following are READ-MODIFY-WRITE! */
969#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
970#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
971
972#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
973
974
975/*****************************************************************************
976*
977* Fusion-MPT IEEE Scatter Gather Elements
978*
979*****************************************************************************/
980
981/****************************************************************************
982* IEEE Simple Element structures
983****************************************************************************/
984
985typedef struct _MPI2_IEEE_SGE_SIMPLE32
986{
987 U32 Address;
988 U32 FlagsLength;
989} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
990 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
991
992typedef struct _MPI2_IEEE_SGE_SIMPLE64
993{
994 U64 Address;
995 U32 Length;
996 U16 Reserved1;
997 U8 Reserved2;
998 U8 Flags;
999} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1000 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1001
1002typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1003{
1004 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1005 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1006} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1007 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1008
1009
1010/****************************************************************************
1011* IEEE Chain Element structures
1012****************************************************************************/
1013
1014typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1015
1016typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1017
1018typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1019{
1020 MPI2_IEEE_SGE_CHAIN32 Chain32;
1021 MPI2_IEEE_SGE_CHAIN64 Chain64;
1022} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1023 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1024
1025
1026/****************************************************************************
1027* All IEEE SGE types union
1028****************************************************************************/
1029
1030typedef struct _MPI2_IEEE_SGE_UNION
1031{
1032 union
1033 {
1034 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1035 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1036 } u;
1037} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1038 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1039
1040
1041/****************************************************************************
1042* IEEE SGE field definitions and masks
1043****************************************************************************/
1044
1045/* Flags field bit definitions */
1046
1047#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1048
1049#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1050
1051#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1052
1053/* Element Type */
1054
1055#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1056#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1057
1058/* Data Location Address Space */
1059
1060#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1061#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1062#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1063#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1064#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1065
1066
1067/****************************************************************************
1068* IEEE SGE operation Macros
1069****************************************************************************/
1070
1071/* SIMPLE FlagsLength manipulations... */
1072#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1073#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1074#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1075
1076#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1077
1078#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1079#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1080#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1081
1082/* CAUTION - The following are READ-MODIFY-WRITE! */
1083#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1084#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1085
1086
1087
1088
1089/*****************************************************************************
1090*
1091* Fusion-MPT MPI/IEEE Scatter Gather Unions
1092*
1093*****************************************************************************/
1094
1095typedef union _MPI2_SIMPLE_SGE_UNION
1096{
1097 MPI2_SGE_SIMPLE_UNION MpiSimple;
1098 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1099} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1100 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1101
1102
1103typedef union _MPI2_SGE_IO_UNION
1104{
1105 MPI2_SGE_SIMPLE_UNION MpiSimple;
1106 MPI2_SGE_CHAIN_UNION MpiChain;
1107 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1108 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1109} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1110 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1111
1112
1113/****************************************************************************
1114*
1115* Values for SGLFlags field, used in many request messages with an SGL
1116*
1117****************************************************************************/
1118
1119/* values for MPI SGL Data Location Address Space subfield */
1120#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1121#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1122#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1123#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1124#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1125/* values for SGL Type subfield */
1126#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1127#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1128#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1129#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1130
1131
1132#endif
1133