blob: 6e2fe28dde4e7d68f260871c9377b96f30e8e644 [file] [log] [blame]
David Howellsb920de12008-02-08 04:19:31 -08001/* MN10300 cache management registers
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11
12#ifndef _ASM_CACHE_H
13#define _ASM_CACHE_H
14
15#include <asm/cpu-regs.h>
David Howells2f2a2132009-04-10 14:33:48 +010016#include <proc/cache.h>
David Howellsb920de12008-02-08 04:19:31 -080017
18#ifndef __ASSEMBLY__
19#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES)
20#else
21#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES
22#endif
23
FUJITA Tomonori6cdafaa2010-05-24 14:32:58 -070024#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
25
David Howellsb920de12008-02-08 04:19:31 -080026/* data cache purge registers
27 * - read from the register to unconditionally purge that cache line
28 * - write address & 0xffffff00 to conditionally purge that cache line
29 * - clear LSB to request invalidation as well
30 */
31#define DCACHE_PURGE(WAY, ENTRY) \
32 __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
33 (ENTRY) * L1_CACHE_BYTES, u32)
34
35#define DCACHE_PURGE_WAY0(ENTRY) \
36 __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
37#define DCACHE_PURGE_WAY1(ENTRY) \
38 __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
39#define DCACHE_PURGE_WAY2(ENTRY) \
40 __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
41#define DCACHE_PURGE_WAY3(ENTRY) \
42 __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
43
44/* instruction cache access registers */
45#define ICACHE_DATA(WAY, ENTRY, OFF) \
46 __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
47#define ICACHE_TAG(WAY, ENTRY) \
48 __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
49
50/* instruction cache access registers */
51#define DCACHE_DATA(WAY, ENTRY, OFF) \
52 __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
53#define DCACHE_TAG(WAY, ENTRY) \
54 __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
55
56#endif /* _ASM_CACHE_H */